1 /* IEEE754 floating point arithmetic 2 * single precision 3 */ 4 /* 5 * MIPS floating point support 6 * Copyright (C) 1994-2000 Algorithmics Ltd. 7 * 8 * This program is free software; you can distribute it and/or modify it 9 * under the terms of the GNU General Public License (Version 2) as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #include "ieee754sp.h" 23 24 union ieee754sp ieee754sp_sub(union ieee754sp x, union ieee754sp y) 25 { 26 int s; 27 28 COMPXSP; 29 COMPYSP; 30 31 EXPLODEXSP; 32 EXPLODEYSP; 33 34 ieee754_clearcx(); 35 36 FLUSHXSP; 37 FLUSHYSP; 38 39 switch (CLPAIR(xc, yc)) { 40 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): 41 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): 42 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): 43 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): 44 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): 45 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): 46 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): 47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): 48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): 49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): 50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): 51 ieee754_setcx(IEEE754_INVALID_OPERATION); 52 return ieee754sp_nanxcpt(ieee754sp_indef()); 53 54 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): 55 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): 56 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN): 57 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): 58 return y; 59 60 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): 61 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): 62 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): 63 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): 64 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF): 65 return x; 66 67 68 /* 69 * Infinity handling 70 */ 71 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): 72 if (xs != ys) 73 return x; 74 ieee754_setcx(IEEE754_INVALID_OPERATION); 75 return ieee754sp_indef(); 76 77 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): 78 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF): 79 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF): 80 return ieee754sp_inf(ys ^ 1); 81 82 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): 83 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM): 84 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): 85 return x; 86 87 /* 88 * Zero handling 89 */ 90 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): 91 if (xs != ys) 92 return x; 93 else 94 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); 95 96 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): 97 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): 98 return x; 99 100 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM): 101 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM): 102 /* quick fix up */ 103 SPSIGN(y) ^= 1; 104 return y; 105 106 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): 107 SPDNORMX; 108 109 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): 110 SPDNORMY; 111 break; 112 113 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM): 114 SPDNORMX; 115 break; 116 117 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): 118 break; 119 } 120 /* flip sign of y and handle as add */ 121 ys ^= 1; 122 123 assert(xm & SP_HIDDEN_BIT); 124 assert(ym & SP_HIDDEN_BIT); 125 126 127 /* provide guard,round and stick bit space */ 128 xm <<= 3; 129 ym <<= 3; 130 131 if (xe > ye) { 132 /* 133 * have to shift y fraction right to align 134 */ 135 s = xe - ye; 136 SPXSRSYn(s); 137 } else if (ye > xe) { 138 /* 139 * have to shift x fraction right to align 140 */ 141 s = ye - xe; 142 SPXSRSXn(s); 143 } 144 assert(xe == ye); 145 assert(xe <= SP_EMAX); 146 147 if (xs == ys) { 148 /* generate 28 bit result of adding two 27 bit numbers 149 */ 150 xm = xm + ym; 151 152 if (xm >> (SP_FBITS + 1 + 3)) { /* carry out */ 153 SPXSRSX1(); /* shift preserving sticky */ 154 } 155 } else { 156 if (xm >= ym) { 157 xm = xm - ym; 158 } else { 159 xm = ym - xm; 160 xs = ys; 161 } 162 if (xm == 0) { 163 if (ieee754_csr.rm == FPU_CSR_RD) 164 return ieee754sp_zero(1); /* round negative inf. => sign = -1 */ 165 else 166 return ieee754sp_zero(0); /* other round modes => sign = 1 */ 167 } 168 /* normalize to rounding precision 169 */ 170 while ((xm >> (SP_FBITS + 3)) == 0) { 171 xm <<= 1; 172 xe--; 173 } 174 } 175 176 return ieee754sp_format(xs, xe, xm); 177 } 178