1 /* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 22 * 23 * A complete emulator for MIPS coprocessor 1 instructions. This is 24 * required for #float(switch) or #float(trap), where it catches all 25 * COP1 instructions via the "CoProcessor Unusable" exception. 26 * 27 * More surprisingly it is also required for #float(ieee), to help out 28 * the hardware FPU at the boundaries of the IEEE-754 representation 29 * (denormalised values, infinities, underflow, etc). It is made 30 * quite nasty because emulation of some non-COP1 instructions is 31 * required, e.g. in branch delay slots. 32 * 33 * Note if you know that you won't have an FPU, then you'll get much 34 * better performance by compiling with -msoft-float! 35 */ 36 #include <linux/sched.h> 37 #include <linux/debugfs.h> 38 #include <linux/kconfig.h> 39 #include <linux/percpu-defs.h> 40 #include <linux/perf_event.h> 41 42 #include <asm/branch.h> 43 #include <asm/inst.h> 44 #include <asm/ptrace.h> 45 #include <asm/signal.h> 46 #include <asm/uaccess.h> 47 48 #include <asm/processor.h> 49 #include <asm/fpu_emulator.h> 50 #include <asm/fpu.h> 51 52 #include "ieee754.h" 53 54 /* Function which emulates a floating point instruction. */ 55 56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 57 mips_instruction); 58 59 static int fpux_emu(struct pt_regs *, 60 struct mips_fpu_struct *, mips_instruction, void *__user *); 61 62 /* Control registers */ 63 64 #define FPCREG_RID 0 /* $0 = revision id */ 65 #define FPCREG_CSR 31 /* $31 = csr */ 66 67 /* Determine rounding mode from the RM bits of the FCSR */ 68 #define modeindex(v) ((v) & FPU_CSR_RM) 69 70 /* convert condition code register number to csr bit */ 71 static const unsigned int fpucondbit[8] = { 72 FPU_CSR_COND0, 73 FPU_CSR_COND1, 74 FPU_CSR_COND2, 75 FPU_CSR_COND3, 76 FPU_CSR_COND4, 77 FPU_CSR_COND5, 78 FPU_CSR_COND6, 79 FPU_CSR_COND7 80 }; 81 82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 83 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 84 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 85 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 86 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 87 88 /* 89 * This functions translates a 32-bit microMIPS instruction 90 * into a 32-bit MIPS32 instruction. Returns 0 on success 91 * and SIGILL otherwise. 92 */ 93 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 94 { 95 union mips_instruction insn = *insn_ptr; 96 union mips_instruction mips32_insn = insn; 97 int func, fmt, op; 98 99 switch (insn.mm_i_format.opcode) { 100 case mm_ldc132_op: 101 mips32_insn.mm_i_format.opcode = ldc1_op; 102 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 103 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 104 break; 105 case mm_lwc132_op: 106 mips32_insn.mm_i_format.opcode = lwc1_op; 107 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 108 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 109 break; 110 case mm_sdc132_op: 111 mips32_insn.mm_i_format.opcode = sdc1_op; 112 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 113 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 114 break; 115 case mm_swc132_op: 116 mips32_insn.mm_i_format.opcode = swc1_op; 117 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 118 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 119 break; 120 case mm_pool32i_op: 121 /* NOTE: offset is << by 1 if in microMIPS mode. */ 122 if ((insn.mm_i_format.rt == mm_bc1f_op) || 123 (insn.mm_i_format.rt == mm_bc1t_op)) { 124 mips32_insn.fb_format.opcode = cop1_op; 125 mips32_insn.fb_format.bc = bc_op; 126 mips32_insn.fb_format.flag = 127 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 128 } else 129 return SIGILL; 130 break; 131 case mm_pool32f_op: 132 switch (insn.mm_fp0_format.func) { 133 case mm_32f_01_op: 134 case mm_32f_11_op: 135 case mm_32f_02_op: 136 case mm_32f_12_op: 137 case mm_32f_41_op: 138 case mm_32f_51_op: 139 case mm_32f_42_op: 140 case mm_32f_52_op: 141 op = insn.mm_fp0_format.func; 142 if (op == mm_32f_01_op) 143 func = madd_s_op; 144 else if (op == mm_32f_11_op) 145 func = madd_d_op; 146 else if (op == mm_32f_02_op) 147 func = nmadd_s_op; 148 else if (op == mm_32f_12_op) 149 func = nmadd_d_op; 150 else if (op == mm_32f_41_op) 151 func = msub_s_op; 152 else if (op == mm_32f_51_op) 153 func = msub_d_op; 154 else if (op == mm_32f_42_op) 155 func = nmsub_s_op; 156 else 157 func = nmsub_d_op; 158 mips32_insn.fp6_format.opcode = cop1x_op; 159 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 160 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 161 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 162 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 163 mips32_insn.fp6_format.func = func; 164 break; 165 case mm_32f_10_op: 166 func = -1; /* Invalid */ 167 op = insn.mm_fp5_format.op & 0x7; 168 if (op == mm_ldxc1_op) 169 func = ldxc1_op; 170 else if (op == mm_sdxc1_op) 171 func = sdxc1_op; 172 else if (op == mm_lwxc1_op) 173 func = lwxc1_op; 174 else if (op == mm_swxc1_op) 175 func = swxc1_op; 176 177 if (func != -1) { 178 mips32_insn.r_format.opcode = cop1x_op; 179 mips32_insn.r_format.rs = 180 insn.mm_fp5_format.base; 181 mips32_insn.r_format.rt = 182 insn.mm_fp5_format.index; 183 mips32_insn.r_format.rd = 0; 184 mips32_insn.r_format.re = insn.mm_fp5_format.fd; 185 mips32_insn.r_format.func = func; 186 } else 187 return SIGILL; 188 break; 189 case mm_32f_40_op: 190 op = -1; /* Invalid */ 191 if (insn.mm_fp2_format.op == mm_fmovt_op) 192 op = 1; 193 else if (insn.mm_fp2_format.op == mm_fmovf_op) 194 op = 0; 195 if (op != -1) { 196 mips32_insn.fp0_format.opcode = cop1_op; 197 mips32_insn.fp0_format.fmt = 198 sdps_format[insn.mm_fp2_format.fmt]; 199 mips32_insn.fp0_format.ft = 200 (insn.mm_fp2_format.cc<<2) + op; 201 mips32_insn.fp0_format.fs = 202 insn.mm_fp2_format.fs; 203 mips32_insn.fp0_format.fd = 204 insn.mm_fp2_format.fd; 205 mips32_insn.fp0_format.func = fmovc_op; 206 } else 207 return SIGILL; 208 break; 209 case mm_32f_60_op: 210 func = -1; /* Invalid */ 211 if (insn.mm_fp0_format.op == mm_fadd_op) 212 func = fadd_op; 213 else if (insn.mm_fp0_format.op == mm_fsub_op) 214 func = fsub_op; 215 else if (insn.mm_fp0_format.op == mm_fmul_op) 216 func = fmul_op; 217 else if (insn.mm_fp0_format.op == mm_fdiv_op) 218 func = fdiv_op; 219 if (func != -1) { 220 mips32_insn.fp0_format.opcode = cop1_op; 221 mips32_insn.fp0_format.fmt = 222 sdps_format[insn.mm_fp0_format.fmt]; 223 mips32_insn.fp0_format.ft = 224 insn.mm_fp0_format.ft; 225 mips32_insn.fp0_format.fs = 226 insn.mm_fp0_format.fs; 227 mips32_insn.fp0_format.fd = 228 insn.mm_fp0_format.fd; 229 mips32_insn.fp0_format.func = func; 230 } else 231 return SIGILL; 232 break; 233 case mm_32f_70_op: 234 func = -1; /* Invalid */ 235 if (insn.mm_fp0_format.op == mm_fmovn_op) 236 func = fmovn_op; 237 else if (insn.mm_fp0_format.op == mm_fmovz_op) 238 func = fmovz_op; 239 if (func != -1) { 240 mips32_insn.fp0_format.opcode = cop1_op; 241 mips32_insn.fp0_format.fmt = 242 sdps_format[insn.mm_fp0_format.fmt]; 243 mips32_insn.fp0_format.ft = 244 insn.mm_fp0_format.ft; 245 mips32_insn.fp0_format.fs = 246 insn.mm_fp0_format.fs; 247 mips32_insn.fp0_format.fd = 248 insn.mm_fp0_format.fd; 249 mips32_insn.fp0_format.func = func; 250 } else 251 return SIGILL; 252 break; 253 case mm_32f_73_op: /* POOL32FXF */ 254 switch (insn.mm_fp1_format.op) { 255 case mm_movf0_op: 256 case mm_movf1_op: 257 case mm_movt0_op: 258 case mm_movt1_op: 259 if ((insn.mm_fp1_format.op & 0x7f) == 260 mm_movf0_op) 261 op = 0; 262 else 263 op = 1; 264 mips32_insn.r_format.opcode = spec_op; 265 mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 266 mips32_insn.r_format.rt = 267 (insn.mm_fp4_format.cc << 2) + op; 268 mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 269 mips32_insn.r_format.re = 0; 270 mips32_insn.r_format.func = movc_op; 271 break; 272 case mm_fcvtd0_op: 273 case mm_fcvtd1_op: 274 case mm_fcvts0_op: 275 case mm_fcvts1_op: 276 if ((insn.mm_fp1_format.op & 0x7f) == 277 mm_fcvtd0_op) { 278 func = fcvtd_op; 279 fmt = swl_format[insn.mm_fp3_format.fmt]; 280 } else { 281 func = fcvts_op; 282 fmt = dwl_format[insn.mm_fp3_format.fmt]; 283 } 284 mips32_insn.fp0_format.opcode = cop1_op; 285 mips32_insn.fp0_format.fmt = fmt; 286 mips32_insn.fp0_format.ft = 0; 287 mips32_insn.fp0_format.fs = 288 insn.mm_fp3_format.fs; 289 mips32_insn.fp0_format.fd = 290 insn.mm_fp3_format.rt; 291 mips32_insn.fp0_format.func = func; 292 break; 293 case mm_fmov0_op: 294 case mm_fmov1_op: 295 case mm_fabs0_op: 296 case mm_fabs1_op: 297 case mm_fneg0_op: 298 case mm_fneg1_op: 299 if ((insn.mm_fp1_format.op & 0x7f) == 300 mm_fmov0_op) 301 func = fmov_op; 302 else if ((insn.mm_fp1_format.op & 0x7f) == 303 mm_fabs0_op) 304 func = fabs_op; 305 else 306 func = fneg_op; 307 mips32_insn.fp0_format.opcode = cop1_op; 308 mips32_insn.fp0_format.fmt = 309 sdps_format[insn.mm_fp3_format.fmt]; 310 mips32_insn.fp0_format.ft = 0; 311 mips32_insn.fp0_format.fs = 312 insn.mm_fp3_format.fs; 313 mips32_insn.fp0_format.fd = 314 insn.mm_fp3_format.rt; 315 mips32_insn.fp0_format.func = func; 316 break; 317 case mm_ffloorl_op: 318 case mm_ffloorw_op: 319 case mm_fceill_op: 320 case mm_fceilw_op: 321 case mm_ftruncl_op: 322 case mm_ftruncw_op: 323 case mm_froundl_op: 324 case mm_froundw_op: 325 case mm_fcvtl_op: 326 case mm_fcvtw_op: 327 if (insn.mm_fp1_format.op == mm_ffloorl_op) 328 func = ffloorl_op; 329 else if (insn.mm_fp1_format.op == mm_ffloorw_op) 330 func = ffloor_op; 331 else if (insn.mm_fp1_format.op == mm_fceill_op) 332 func = fceill_op; 333 else if (insn.mm_fp1_format.op == mm_fceilw_op) 334 func = fceil_op; 335 else if (insn.mm_fp1_format.op == mm_ftruncl_op) 336 func = ftruncl_op; 337 else if (insn.mm_fp1_format.op == mm_ftruncw_op) 338 func = ftrunc_op; 339 else if (insn.mm_fp1_format.op == mm_froundl_op) 340 func = froundl_op; 341 else if (insn.mm_fp1_format.op == mm_froundw_op) 342 func = fround_op; 343 else if (insn.mm_fp1_format.op == mm_fcvtl_op) 344 func = fcvtl_op; 345 else 346 func = fcvtw_op; 347 mips32_insn.fp0_format.opcode = cop1_op; 348 mips32_insn.fp0_format.fmt = 349 sd_format[insn.mm_fp1_format.fmt]; 350 mips32_insn.fp0_format.ft = 0; 351 mips32_insn.fp0_format.fs = 352 insn.mm_fp1_format.fs; 353 mips32_insn.fp0_format.fd = 354 insn.mm_fp1_format.rt; 355 mips32_insn.fp0_format.func = func; 356 break; 357 case mm_frsqrt_op: 358 case mm_fsqrt_op: 359 case mm_frecip_op: 360 if (insn.mm_fp1_format.op == mm_frsqrt_op) 361 func = frsqrt_op; 362 else if (insn.mm_fp1_format.op == mm_fsqrt_op) 363 func = fsqrt_op; 364 else 365 func = frecip_op; 366 mips32_insn.fp0_format.opcode = cop1_op; 367 mips32_insn.fp0_format.fmt = 368 sdps_format[insn.mm_fp1_format.fmt]; 369 mips32_insn.fp0_format.ft = 0; 370 mips32_insn.fp0_format.fs = 371 insn.mm_fp1_format.fs; 372 mips32_insn.fp0_format.fd = 373 insn.mm_fp1_format.rt; 374 mips32_insn.fp0_format.func = func; 375 break; 376 case mm_mfc1_op: 377 case mm_mtc1_op: 378 case mm_cfc1_op: 379 case mm_ctc1_op: 380 case mm_mfhc1_op: 381 case mm_mthc1_op: 382 if (insn.mm_fp1_format.op == mm_mfc1_op) 383 op = mfc_op; 384 else if (insn.mm_fp1_format.op == mm_mtc1_op) 385 op = mtc_op; 386 else if (insn.mm_fp1_format.op == mm_cfc1_op) 387 op = cfc_op; 388 else if (insn.mm_fp1_format.op == mm_ctc1_op) 389 op = ctc_op; 390 else if (insn.mm_fp1_format.op == mm_mfhc1_op) 391 op = mfhc_op; 392 else 393 op = mthc_op; 394 mips32_insn.fp1_format.opcode = cop1_op; 395 mips32_insn.fp1_format.op = op; 396 mips32_insn.fp1_format.rt = 397 insn.mm_fp1_format.rt; 398 mips32_insn.fp1_format.fs = 399 insn.mm_fp1_format.fs; 400 mips32_insn.fp1_format.fd = 0; 401 mips32_insn.fp1_format.func = 0; 402 break; 403 default: 404 return SIGILL; 405 } 406 break; 407 case mm_32f_74_op: /* c.cond.fmt */ 408 mips32_insn.fp0_format.opcode = cop1_op; 409 mips32_insn.fp0_format.fmt = 410 sdps_format[insn.mm_fp4_format.fmt]; 411 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 412 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 413 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 414 mips32_insn.fp0_format.func = 415 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 416 break; 417 default: 418 return SIGILL; 419 } 420 break; 421 default: 422 return SIGILL; 423 } 424 425 *insn_ptr = mips32_insn; 426 return 0; 427 } 428 429 /* 430 * Redundant with logic already in kernel/branch.c, 431 * embedded in compute_return_epc. At some point, 432 * a single subroutine should be used across both 433 * modules. 434 */ 435 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 436 unsigned long *contpc) 437 { 438 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 439 unsigned int fcr31; 440 unsigned int bit = 0; 441 442 switch (insn.i_format.opcode) { 443 case spec_op: 444 switch (insn.r_format.func) { 445 case jalr_op: 446 regs->regs[insn.r_format.rd] = 447 regs->cp0_epc + dec_insn.pc_inc + 448 dec_insn.next_pc_inc; 449 /* Fall through */ 450 case jr_op: 451 *contpc = regs->regs[insn.r_format.rs]; 452 return 1; 453 } 454 break; 455 case bcond_op: 456 switch (insn.i_format.rt) { 457 case bltzal_op: 458 case bltzall_op: 459 regs->regs[31] = regs->cp0_epc + 460 dec_insn.pc_inc + 461 dec_insn.next_pc_inc; 462 /* Fall through */ 463 case bltz_op: 464 case bltzl_op: 465 if ((long)regs->regs[insn.i_format.rs] < 0) 466 *contpc = regs->cp0_epc + 467 dec_insn.pc_inc + 468 (insn.i_format.simmediate << 2); 469 else 470 *contpc = regs->cp0_epc + 471 dec_insn.pc_inc + 472 dec_insn.next_pc_inc; 473 return 1; 474 case bgezal_op: 475 case bgezall_op: 476 regs->regs[31] = regs->cp0_epc + 477 dec_insn.pc_inc + 478 dec_insn.next_pc_inc; 479 /* Fall through */ 480 case bgez_op: 481 case bgezl_op: 482 if ((long)regs->regs[insn.i_format.rs] >= 0) 483 *contpc = regs->cp0_epc + 484 dec_insn.pc_inc + 485 (insn.i_format.simmediate << 2); 486 else 487 *contpc = regs->cp0_epc + 488 dec_insn.pc_inc + 489 dec_insn.next_pc_inc; 490 return 1; 491 } 492 break; 493 case jalx_op: 494 set_isa16_mode(bit); 495 case jal_op: 496 regs->regs[31] = regs->cp0_epc + 497 dec_insn.pc_inc + 498 dec_insn.next_pc_inc; 499 /* Fall through */ 500 case j_op: 501 *contpc = regs->cp0_epc + dec_insn.pc_inc; 502 *contpc >>= 28; 503 *contpc <<= 28; 504 *contpc |= (insn.j_format.target << 2); 505 /* Set microMIPS mode bit: XOR for jalx. */ 506 *contpc ^= bit; 507 return 1; 508 case beq_op: 509 case beql_op: 510 if (regs->regs[insn.i_format.rs] == 511 regs->regs[insn.i_format.rt]) 512 *contpc = regs->cp0_epc + 513 dec_insn.pc_inc + 514 (insn.i_format.simmediate << 2); 515 else 516 *contpc = regs->cp0_epc + 517 dec_insn.pc_inc + 518 dec_insn.next_pc_inc; 519 return 1; 520 case bne_op: 521 case bnel_op: 522 if (regs->regs[insn.i_format.rs] != 523 regs->regs[insn.i_format.rt]) 524 *contpc = regs->cp0_epc + 525 dec_insn.pc_inc + 526 (insn.i_format.simmediate << 2); 527 else 528 *contpc = regs->cp0_epc + 529 dec_insn.pc_inc + 530 dec_insn.next_pc_inc; 531 return 1; 532 case blez_op: 533 case blezl_op: 534 if ((long)regs->regs[insn.i_format.rs] <= 0) 535 *contpc = regs->cp0_epc + 536 dec_insn.pc_inc + 537 (insn.i_format.simmediate << 2); 538 else 539 *contpc = regs->cp0_epc + 540 dec_insn.pc_inc + 541 dec_insn.next_pc_inc; 542 return 1; 543 case bgtz_op: 544 case bgtzl_op: 545 if ((long)regs->regs[insn.i_format.rs] > 0) 546 *contpc = regs->cp0_epc + 547 dec_insn.pc_inc + 548 (insn.i_format.simmediate << 2); 549 else 550 *contpc = regs->cp0_epc + 551 dec_insn.pc_inc + 552 dec_insn.next_pc_inc; 553 return 1; 554 #ifdef CONFIG_CPU_CAVIUM_OCTEON 555 case lwc2_op: /* This is bbit0 on Octeon */ 556 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 557 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 558 else 559 *contpc = regs->cp0_epc + 8; 560 return 1; 561 case ldc2_op: /* This is bbit032 on Octeon */ 562 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 563 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 564 else 565 *contpc = regs->cp0_epc + 8; 566 return 1; 567 case swc2_op: /* This is bbit1 on Octeon */ 568 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 569 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 570 else 571 *contpc = regs->cp0_epc + 8; 572 return 1; 573 case sdc2_op: /* This is bbit132 on Octeon */ 574 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 575 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 576 else 577 *contpc = regs->cp0_epc + 8; 578 return 1; 579 #endif 580 case cop0_op: 581 case cop1_op: 582 case cop2_op: 583 case cop1x_op: 584 if (insn.i_format.rs == bc_op) { 585 preempt_disable(); 586 if (is_fpu_owner()) 587 fcr31 = read_32bit_cp1_register(CP1_STATUS); 588 else 589 fcr31 = current->thread.fpu.fcr31; 590 preempt_enable(); 591 592 bit = (insn.i_format.rt >> 2); 593 bit += (bit != 0); 594 bit += 23; 595 switch (insn.i_format.rt & 3) { 596 case 0: /* bc1f */ 597 case 2: /* bc1fl */ 598 if (~fcr31 & (1 << bit)) 599 *contpc = regs->cp0_epc + 600 dec_insn.pc_inc + 601 (insn.i_format.simmediate << 2); 602 else 603 *contpc = regs->cp0_epc + 604 dec_insn.pc_inc + 605 dec_insn.next_pc_inc; 606 return 1; 607 case 1: /* bc1t */ 608 case 3: /* bc1tl */ 609 if (fcr31 & (1 << bit)) 610 *contpc = regs->cp0_epc + 611 dec_insn.pc_inc + 612 (insn.i_format.simmediate << 2); 613 else 614 *contpc = regs->cp0_epc + 615 dec_insn.pc_inc + 616 dec_insn.next_pc_inc; 617 return 1; 618 } 619 } 620 break; 621 } 622 return 0; 623 } 624 625 /* 626 * In the Linux kernel, we support selection of FPR format on the 627 * basis of the Status.FR bit. If an FPU is not present, the FR bit 628 * is hardwired to zero, which would imply a 32-bit FPU even for 629 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 630 * FPU emu is slow and bulky and optimizing this function offers fairly 631 * sizeable benefits so we try to be clever and make this function return 632 * a constant whenever possible, that is on 64-bit kernels without O32 633 * compatibility enabled and on 32-bit without 64-bit FPU support. 634 */ 635 static inline int cop1_64bit(struct pt_regs *xcp) 636 { 637 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) 638 return 1; 639 else if (config_enabled(CONFIG_32BIT) && 640 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 641 return 0; 642 643 return !test_thread_flag(TIF_32BIT_FPREGS); 644 } 645 646 static inline bool hybrid_fprs(void) 647 { 648 return test_thread_flag(TIF_HYBRID_FPREGS); 649 } 650 651 #define SIFROMREG(si, x) \ 652 do { \ 653 if (cop1_64bit(xcp) && !hybrid_fprs()) \ 654 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ 655 else \ 656 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 657 } while (0) 658 659 #define SITOREG(si, x) \ 660 do { \ 661 if (cop1_64bit(xcp) && !hybrid_fprs()) { \ 662 unsigned i; \ 663 set_fpr32(&ctx->fpr[x], 0, si); \ 664 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 665 set_fpr32(&ctx->fpr[x], i, 0); \ 666 } else { \ 667 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 668 } \ 669 } while (0) 670 671 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) 672 673 #define SITOHREG(si, x) \ 674 do { \ 675 unsigned i; \ 676 set_fpr32(&ctx->fpr[x], 1, si); \ 677 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 678 set_fpr32(&ctx->fpr[x], i, 0); \ 679 } while (0) 680 681 #define DIFROMREG(di, x) \ 682 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) 683 684 #define DITOREG(di, x) \ 685 do { \ 686 unsigned fpr, i; \ 687 fpr = (x) & ~(cop1_64bit(xcp) == 0); \ 688 set_fpr64(&ctx->fpr[fpr], 0, di); \ 689 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 690 set_fpr64(&ctx->fpr[fpr], i, 0); \ 691 } while (0) 692 693 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 694 #define SPTOREG(sp, x) SITOREG((sp).bits, x) 695 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 696 #define DPTOREG(dp, x) DITOREG((dp).bits, x) 697 698 /* 699 * Emulate the single floating point instruction pointed at by EPC. 700 * Two instructions if the instruction is in a branch delay slot. 701 */ 702 703 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 704 struct mm_decoded_insn dec_insn, void *__user *fault_addr) 705 { 706 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 707 unsigned int cond, cbit; 708 mips_instruction ir; 709 int likely, pc_inc; 710 u32 __user *wva; 711 u64 __user *dva; 712 u32 value; 713 u32 wval; 714 u64 dval; 715 int sig; 716 717 /* 718 * These are giving gcc a gentle hint about what to expect in 719 * dec_inst in order to do better optimization. 720 */ 721 if (!cpu_has_mmips && dec_insn.micro_mips_mode) 722 unreachable(); 723 724 /* XXX NEC Vr54xx bug workaround */ 725 if (delay_slot(xcp)) { 726 if (dec_insn.micro_mips_mode) { 727 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 728 clear_delay_slot(xcp); 729 } else { 730 if (!isBranchInstr(xcp, dec_insn, &contpc)) 731 clear_delay_slot(xcp); 732 } 733 } 734 735 if (delay_slot(xcp)) { 736 /* 737 * The instruction to be emulated is in a branch delay slot 738 * which means that we have to emulate the branch instruction 739 * BEFORE we do the cop1 instruction. 740 * 741 * This branch could be a COP1 branch, but in that case we 742 * would have had a trap for that instruction, and would not 743 * come through this route. 744 * 745 * Linux MIPS branch emulator operates on context, updating the 746 * cp0_epc. 747 */ 748 ir = dec_insn.next_insn; /* process delay slot instr */ 749 pc_inc = dec_insn.next_pc_inc; 750 } else { 751 ir = dec_insn.insn; /* process current instr */ 752 pc_inc = dec_insn.pc_inc; 753 } 754 755 /* 756 * Since microMIPS FPU instructios are a subset of MIPS32 FPU 757 * instructions, we want to convert microMIPS FPU instructions 758 * into MIPS32 instructions so that we could reuse all of the 759 * FPU emulation code. 760 * 761 * NOTE: We cannot do this for branch instructions since they 762 * are not a subset. Example: Cannot emulate a 16-bit 763 * aligned target address with a MIPS32 instruction. 764 */ 765 if (dec_insn.micro_mips_mode) { 766 /* 767 * If next instruction is a 16-bit instruction, then it 768 * it cannot be a FPU instruction. This could happen 769 * since we can be called for non-FPU instructions. 770 */ 771 if ((pc_inc == 2) || 772 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 773 == SIGILL)) 774 return SIGILL; 775 } 776 777 emul: 778 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 779 MIPS_FPU_EMU_INC_STATS(emulated); 780 switch (MIPSInst_OPCODE(ir)) { 781 case ldc1_op: 782 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 783 MIPSInst_SIMM(ir)); 784 MIPS_FPU_EMU_INC_STATS(loads); 785 786 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { 787 MIPS_FPU_EMU_INC_STATS(errors); 788 *fault_addr = dva; 789 return SIGBUS; 790 } 791 if (__get_user(dval, dva)) { 792 MIPS_FPU_EMU_INC_STATS(errors); 793 *fault_addr = dva; 794 return SIGSEGV; 795 } 796 DITOREG(dval, MIPSInst_RT(ir)); 797 break; 798 799 case sdc1_op: 800 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 801 MIPSInst_SIMM(ir)); 802 MIPS_FPU_EMU_INC_STATS(stores); 803 DIFROMREG(dval, MIPSInst_RT(ir)); 804 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { 805 MIPS_FPU_EMU_INC_STATS(errors); 806 *fault_addr = dva; 807 return SIGBUS; 808 } 809 if (__put_user(dval, dva)) { 810 MIPS_FPU_EMU_INC_STATS(errors); 811 *fault_addr = dva; 812 return SIGSEGV; 813 } 814 break; 815 816 case lwc1_op: 817 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 818 MIPSInst_SIMM(ir)); 819 MIPS_FPU_EMU_INC_STATS(loads); 820 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { 821 MIPS_FPU_EMU_INC_STATS(errors); 822 *fault_addr = wva; 823 return SIGBUS; 824 } 825 if (__get_user(wval, wva)) { 826 MIPS_FPU_EMU_INC_STATS(errors); 827 *fault_addr = wva; 828 return SIGSEGV; 829 } 830 SITOREG(wval, MIPSInst_RT(ir)); 831 break; 832 833 case swc1_op: 834 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 835 MIPSInst_SIMM(ir)); 836 MIPS_FPU_EMU_INC_STATS(stores); 837 SIFROMREG(wval, MIPSInst_RT(ir)); 838 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { 839 MIPS_FPU_EMU_INC_STATS(errors); 840 *fault_addr = wva; 841 return SIGBUS; 842 } 843 if (__put_user(wval, wva)) { 844 MIPS_FPU_EMU_INC_STATS(errors); 845 *fault_addr = wva; 846 return SIGSEGV; 847 } 848 break; 849 850 case cop1_op: 851 switch (MIPSInst_RS(ir)) { 852 case dmfc_op: 853 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 854 return SIGILL; 855 856 /* copregister fs -> gpr[rt] */ 857 if (MIPSInst_RT(ir) != 0) { 858 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 859 MIPSInst_RD(ir)); 860 } 861 break; 862 863 case dmtc_op: 864 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 865 return SIGILL; 866 867 /* copregister fs <- rt */ 868 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 869 break; 870 871 case mfhc_op: 872 if (!cpu_has_mips_r2) 873 goto sigill; 874 875 /* copregister rd -> gpr[rt] */ 876 if (MIPSInst_RT(ir) != 0) { 877 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 878 MIPSInst_RD(ir)); 879 } 880 break; 881 882 case mthc_op: 883 if (!cpu_has_mips_r2) 884 goto sigill; 885 886 /* copregister rd <- gpr[rt] */ 887 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 888 break; 889 890 case mfc_op: 891 /* copregister rd -> gpr[rt] */ 892 if (MIPSInst_RT(ir) != 0) { 893 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 894 MIPSInst_RD(ir)); 895 } 896 break; 897 898 case mtc_op: 899 /* copregister rd <- rt */ 900 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 901 break; 902 903 case cfc_op: 904 /* cop control register rd -> gpr[rt] */ 905 if (MIPSInst_RD(ir) == FPCREG_CSR) { 906 value = ctx->fcr31; 907 value = (value & ~FPU_CSR_RM) | modeindex(value); 908 pr_debug("%p gpr[%d]<-csr=%08x\n", 909 (void *) (xcp->cp0_epc), 910 MIPSInst_RT(ir), value); 911 } 912 else if (MIPSInst_RD(ir) == FPCREG_RID) 913 value = 0; 914 else 915 value = 0; 916 if (MIPSInst_RT(ir)) 917 xcp->regs[MIPSInst_RT(ir)] = value; 918 break; 919 920 case ctc_op: 921 /* copregister rd <- rt */ 922 if (MIPSInst_RT(ir) == 0) 923 value = 0; 924 else 925 value = xcp->regs[MIPSInst_RT(ir)]; 926 927 /* we only have one writable control reg 928 */ 929 if (MIPSInst_RD(ir) == FPCREG_CSR) { 930 pr_debug("%p gpr[%d]->csr=%08x\n", 931 (void *) (xcp->cp0_epc), 932 MIPSInst_RT(ir), value); 933 934 /* 935 * Don't write reserved bits, 936 * and convert to ieee library modes 937 */ 938 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) | 939 modeindex(value); 940 } 941 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 942 return SIGFPE; 943 } 944 break; 945 946 case bc_op: 947 if (delay_slot(xcp)) 948 return SIGILL; 949 950 if (cpu_has_mips_4_5_r) 951 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 952 else 953 cbit = FPU_CSR_COND; 954 cond = ctx->fcr31 & cbit; 955 956 likely = 0; 957 switch (MIPSInst_RT(ir) & 3) { 958 case bcfl_op: 959 likely = 1; 960 case bcf_op: 961 cond = !cond; 962 break; 963 case bctl_op: 964 likely = 1; 965 case bct_op: 966 break; 967 default: 968 /* thats an illegal instruction */ 969 return SIGILL; 970 } 971 972 set_delay_slot(xcp); 973 if (cond) { 974 /* 975 * Branch taken: emulate dslot instruction 976 */ 977 xcp->cp0_epc += dec_insn.pc_inc; 978 979 contpc = MIPSInst_SIMM(ir); 980 ir = dec_insn.next_insn; 981 if (dec_insn.micro_mips_mode) { 982 contpc = (xcp->cp0_epc + (contpc << 1)); 983 984 /* If 16-bit instruction, not FPU. */ 985 if ((dec_insn.next_pc_inc == 2) || 986 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 987 988 /* 989 * Since this instruction will 990 * be put on the stack with 991 * 32-bit words, get around 992 * this problem by putting a 993 * NOP16 as the second one. 994 */ 995 if (dec_insn.next_pc_inc == 2) 996 ir = (ir & (~0xffff)) | MM_NOP16; 997 998 /* 999 * Single step the non-CP1 1000 * instruction in the dslot. 1001 */ 1002 return mips_dsemul(xcp, ir, contpc); 1003 } 1004 } else 1005 contpc = (xcp->cp0_epc + (contpc << 2)); 1006 1007 switch (MIPSInst_OPCODE(ir)) { 1008 case lwc1_op: 1009 goto emul; 1010 1011 case swc1_op: 1012 goto emul; 1013 1014 case ldc1_op: 1015 case sdc1_op: 1016 if (cpu_has_mips_2_3_4_5 || 1017 cpu_has_mips64) 1018 goto emul; 1019 1020 return SIGILL; 1021 goto emul; 1022 1023 case cop1_op: 1024 goto emul; 1025 1026 case cop1x_op: 1027 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2) 1028 /* its one of ours */ 1029 goto emul; 1030 1031 return SIGILL; 1032 1033 case spec_op: 1034 if (!cpu_has_mips_4_5_r) 1035 return SIGILL; 1036 1037 if (MIPSInst_FUNC(ir) == movc_op) 1038 goto emul; 1039 break; 1040 } 1041 1042 /* 1043 * Single step the non-cp1 1044 * instruction in the dslot 1045 */ 1046 return mips_dsemul(xcp, ir, contpc); 1047 } else if (likely) { /* branch not taken */ 1048 /* 1049 * branch likely nullifies 1050 * dslot if not taken 1051 */ 1052 xcp->cp0_epc += dec_insn.pc_inc; 1053 contpc += dec_insn.pc_inc; 1054 /* 1055 * else continue & execute 1056 * dslot as normal insn 1057 */ 1058 } 1059 break; 1060 1061 default: 1062 if (!(MIPSInst_RS(ir) & 0x10)) 1063 return SIGILL; 1064 1065 /* a real fpu computation instruction */ 1066 if ((sig = fpu_emu(xcp, ctx, ir))) 1067 return sig; 1068 } 1069 break; 1070 1071 case cop1x_op: 1072 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2) 1073 return SIGILL; 1074 1075 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1076 if (sig) 1077 return sig; 1078 break; 1079 1080 case spec_op: 1081 if (!cpu_has_mips_4_5_r) 1082 return SIGILL; 1083 1084 if (MIPSInst_FUNC(ir) != movc_op) 1085 return SIGILL; 1086 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 1087 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 1088 xcp->regs[MIPSInst_RD(ir)] = 1089 xcp->regs[MIPSInst_RS(ir)]; 1090 break; 1091 default: 1092 sigill: 1093 return SIGILL; 1094 } 1095 1096 /* we did it !! */ 1097 xcp->cp0_epc = contpc; 1098 clear_delay_slot(xcp); 1099 1100 return 0; 1101 } 1102 1103 /* 1104 * Conversion table from MIPS compare ops 48-63 1105 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 1106 */ 1107 static const unsigned char cmptab[8] = { 1108 0, /* cmp_0 (sig) cmp_sf */ 1109 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 1110 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 1111 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 1112 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 1113 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 1114 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 1115 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 1116 }; 1117 1118 1119 /* 1120 * Additional MIPS4 instructions 1121 */ 1122 1123 #define DEF3OP(name, p, f1, f2, f3) \ 1124 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ 1125 union ieee754##p s, union ieee754##p t) \ 1126 { \ 1127 struct _ieee754_csr ieee754_csr_save; \ 1128 s = f1(s, t); \ 1129 ieee754_csr_save = ieee754_csr; \ 1130 s = f2(s, r); \ 1131 ieee754_csr_save.cx |= ieee754_csr.cx; \ 1132 ieee754_csr_save.sx |= ieee754_csr.sx; \ 1133 s = f3(s); \ 1134 ieee754_csr.cx |= ieee754_csr_save.cx; \ 1135 ieee754_csr.sx |= ieee754_csr_save.sx; \ 1136 return s; \ 1137 } 1138 1139 static union ieee754dp fpemu_dp_recip(union ieee754dp d) 1140 { 1141 return ieee754dp_div(ieee754dp_one(0), d); 1142 } 1143 1144 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 1145 { 1146 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 1147 } 1148 1149 static union ieee754sp fpemu_sp_recip(union ieee754sp s) 1150 { 1151 return ieee754sp_div(ieee754sp_one(0), s); 1152 } 1153 1154 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 1155 { 1156 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 1157 } 1158 1159 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 1160 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 1161 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 1162 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 1163 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 1164 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 1165 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 1166 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 1167 1168 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1169 mips_instruction ir, void *__user *fault_addr) 1170 { 1171 unsigned rcsr = 0; /* resulting csr */ 1172 1173 MIPS_FPU_EMU_INC_STATS(cp1xops); 1174 1175 switch (MIPSInst_FMA_FFMT(ir)) { 1176 case s_fmt:{ /* 0 */ 1177 1178 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 1179 union ieee754sp fd, fr, fs, ft; 1180 u32 __user *va; 1181 u32 val; 1182 1183 switch (MIPSInst_FUNC(ir)) { 1184 case lwxc1_op: 1185 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1186 xcp->regs[MIPSInst_FT(ir)]); 1187 1188 MIPS_FPU_EMU_INC_STATS(loads); 1189 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1190 MIPS_FPU_EMU_INC_STATS(errors); 1191 *fault_addr = va; 1192 return SIGBUS; 1193 } 1194 if (__get_user(val, va)) { 1195 MIPS_FPU_EMU_INC_STATS(errors); 1196 *fault_addr = va; 1197 return SIGSEGV; 1198 } 1199 SITOREG(val, MIPSInst_FD(ir)); 1200 break; 1201 1202 case swxc1_op: 1203 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1204 xcp->regs[MIPSInst_FT(ir)]); 1205 1206 MIPS_FPU_EMU_INC_STATS(stores); 1207 1208 SIFROMREG(val, MIPSInst_FS(ir)); 1209 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1210 MIPS_FPU_EMU_INC_STATS(errors); 1211 *fault_addr = va; 1212 return SIGBUS; 1213 } 1214 if (put_user(val, va)) { 1215 MIPS_FPU_EMU_INC_STATS(errors); 1216 *fault_addr = va; 1217 return SIGSEGV; 1218 } 1219 break; 1220 1221 case madd_s_op: 1222 handler = fpemu_sp_madd; 1223 goto scoptop; 1224 case msub_s_op: 1225 handler = fpemu_sp_msub; 1226 goto scoptop; 1227 case nmadd_s_op: 1228 handler = fpemu_sp_nmadd; 1229 goto scoptop; 1230 case nmsub_s_op: 1231 handler = fpemu_sp_nmsub; 1232 goto scoptop; 1233 1234 scoptop: 1235 SPFROMREG(fr, MIPSInst_FR(ir)); 1236 SPFROMREG(fs, MIPSInst_FS(ir)); 1237 SPFROMREG(ft, MIPSInst_FT(ir)); 1238 fd = (*handler) (fr, fs, ft); 1239 SPTOREG(fd, MIPSInst_FD(ir)); 1240 1241 copcsr: 1242 if (ieee754_cxtest(IEEE754_INEXACT)) { 1243 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1244 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1245 } 1246 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1247 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1248 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1249 } 1250 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1251 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1252 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1253 } 1254 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1255 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1256 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1257 } 1258 1259 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1260 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1261 /*printk ("SIGFPE: FPU csr = %08x\n", 1262 ctx->fcr31); */ 1263 return SIGFPE; 1264 } 1265 1266 break; 1267 1268 default: 1269 return SIGILL; 1270 } 1271 break; 1272 } 1273 1274 case d_fmt:{ /* 1 */ 1275 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 1276 union ieee754dp fd, fr, fs, ft; 1277 u64 __user *va; 1278 u64 val; 1279 1280 switch (MIPSInst_FUNC(ir)) { 1281 case ldxc1_op: 1282 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1283 xcp->regs[MIPSInst_FT(ir)]); 1284 1285 MIPS_FPU_EMU_INC_STATS(loads); 1286 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1287 MIPS_FPU_EMU_INC_STATS(errors); 1288 *fault_addr = va; 1289 return SIGBUS; 1290 } 1291 if (__get_user(val, va)) { 1292 MIPS_FPU_EMU_INC_STATS(errors); 1293 *fault_addr = va; 1294 return SIGSEGV; 1295 } 1296 DITOREG(val, MIPSInst_FD(ir)); 1297 break; 1298 1299 case sdxc1_op: 1300 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1301 xcp->regs[MIPSInst_FT(ir)]); 1302 1303 MIPS_FPU_EMU_INC_STATS(stores); 1304 DIFROMREG(val, MIPSInst_FS(ir)); 1305 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1306 MIPS_FPU_EMU_INC_STATS(errors); 1307 *fault_addr = va; 1308 return SIGBUS; 1309 } 1310 if (__put_user(val, va)) { 1311 MIPS_FPU_EMU_INC_STATS(errors); 1312 *fault_addr = va; 1313 return SIGSEGV; 1314 } 1315 break; 1316 1317 case madd_d_op: 1318 handler = fpemu_dp_madd; 1319 goto dcoptop; 1320 case msub_d_op: 1321 handler = fpemu_dp_msub; 1322 goto dcoptop; 1323 case nmadd_d_op: 1324 handler = fpemu_dp_nmadd; 1325 goto dcoptop; 1326 case nmsub_d_op: 1327 handler = fpemu_dp_nmsub; 1328 goto dcoptop; 1329 1330 dcoptop: 1331 DPFROMREG(fr, MIPSInst_FR(ir)); 1332 DPFROMREG(fs, MIPSInst_FS(ir)); 1333 DPFROMREG(ft, MIPSInst_FT(ir)); 1334 fd = (*handler) (fr, fs, ft); 1335 DPTOREG(fd, MIPSInst_FD(ir)); 1336 goto copcsr; 1337 1338 default: 1339 return SIGILL; 1340 } 1341 break; 1342 } 1343 1344 case 0x3: 1345 if (MIPSInst_FUNC(ir) != pfetch_op) 1346 return SIGILL; 1347 1348 /* ignore prefx operation */ 1349 break; 1350 1351 default: 1352 return SIGILL; 1353 } 1354 1355 return 0; 1356 } 1357 1358 1359 1360 /* 1361 * Emulate a single COP1 arithmetic instruction. 1362 */ 1363 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1364 mips_instruction ir) 1365 { 1366 int rfmt; /* resulting format */ 1367 unsigned rcsr = 0; /* resulting csr */ 1368 unsigned int oldrm; 1369 unsigned int cbit; 1370 unsigned cond; 1371 union { 1372 union ieee754dp d; 1373 union ieee754sp s; 1374 int w; 1375 s64 l; 1376 } rv; /* resulting value */ 1377 u64 bits; 1378 1379 MIPS_FPU_EMU_INC_STATS(cp1ops); 1380 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 1381 case s_fmt: { /* 0 */ 1382 union { 1383 union ieee754sp(*b) (union ieee754sp, union ieee754sp); 1384 union ieee754sp(*u) (union ieee754sp); 1385 } handler; 1386 union ieee754sp fs, ft; 1387 1388 switch (MIPSInst_FUNC(ir)) { 1389 /* binary ops */ 1390 case fadd_op: 1391 handler.b = ieee754sp_add; 1392 goto scopbop; 1393 case fsub_op: 1394 handler.b = ieee754sp_sub; 1395 goto scopbop; 1396 case fmul_op: 1397 handler.b = ieee754sp_mul; 1398 goto scopbop; 1399 case fdiv_op: 1400 handler.b = ieee754sp_div; 1401 goto scopbop; 1402 1403 /* unary ops */ 1404 case fsqrt_op: 1405 if (!cpu_has_mips_4_5_r) 1406 return SIGILL; 1407 1408 handler.u = ieee754sp_sqrt; 1409 goto scopuop; 1410 1411 /* 1412 * Note that on some MIPS IV implementations such as the 1413 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1414 * achieve full IEEE-754 accuracy - however this emulator does. 1415 */ 1416 case frsqrt_op: 1417 if (!cpu_has_mips_4_5_r2) 1418 return SIGILL; 1419 1420 handler.u = fpemu_sp_rsqrt; 1421 goto scopuop; 1422 1423 case frecip_op: 1424 if (!cpu_has_mips_4_5_r2) 1425 return SIGILL; 1426 1427 handler.u = fpemu_sp_recip; 1428 goto scopuop; 1429 1430 case fmovc_op: 1431 if (!cpu_has_mips_4_5_r) 1432 return SIGILL; 1433 1434 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1435 if (((ctx->fcr31 & cond) != 0) != 1436 ((MIPSInst_FT(ir) & 1) != 0)) 1437 return 0; 1438 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1439 break; 1440 1441 case fmovz_op: 1442 if (!cpu_has_mips_4_5_r) 1443 return SIGILL; 1444 1445 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1446 return 0; 1447 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1448 break; 1449 1450 case fmovn_op: 1451 if (!cpu_has_mips_4_5_r) 1452 return SIGILL; 1453 1454 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1455 return 0; 1456 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1457 break; 1458 1459 case fabs_op: 1460 handler.u = ieee754sp_abs; 1461 goto scopuop; 1462 1463 case fneg_op: 1464 handler.u = ieee754sp_neg; 1465 goto scopuop; 1466 1467 case fmov_op: 1468 /* an easy one */ 1469 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1470 goto copcsr; 1471 1472 /* binary op on handler */ 1473 scopbop: 1474 SPFROMREG(fs, MIPSInst_FS(ir)); 1475 SPFROMREG(ft, MIPSInst_FT(ir)); 1476 1477 rv.s = (*handler.b) (fs, ft); 1478 goto copcsr; 1479 scopuop: 1480 SPFROMREG(fs, MIPSInst_FS(ir)); 1481 rv.s = (*handler.u) (fs); 1482 goto copcsr; 1483 copcsr: 1484 if (ieee754_cxtest(IEEE754_INEXACT)) { 1485 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1486 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1487 } 1488 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1489 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1490 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1491 } 1492 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1493 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1494 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1495 } 1496 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { 1497 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); 1498 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1499 } 1500 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1501 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1502 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1503 } 1504 break; 1505 1506 /* unary conv ops */ 1507 case fcvts_op: 1508 return SIGILL; /* not defined */ 1509 1510 case fcvtd_op: 1511 SPFROMREG(fs, MIPSInst_FS(ir)); 1512 rv.d = ieee754dp_fsp(fs); 1513 rfmt = d_fmt; 1514 goto copcsr; 1515 1516 case fcvtw_op: 1517 SPFROMREG(fs, MIPSInst_FS(ir)); 1518 rv.w = ieee754sp_tint(fs); 1519 rfmt = w_fmt; 1520 goto copcsr; 1521 1522 case fround_op: 1523 case ftrunc_op: 1524 case fceil_op: 1525 case ffloor_op: 1526 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) 1527 return SIGILL; 1528 1529 oldrm = ieee754_csr.rm; 1530 SPFROMREG(fs, MIPSInst_FS(ir)); 1531 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1532 rv.w = ieee754sp_tint(fs); 1533 ieee754_csr.rm = oldrm; 1534 rfmt = w_fmt; 1535 goto copcsr; 1536 1537 case fcvtl_op: 1538 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1539 return SIGILL; 1540 1541 SPFROMREG(fs, MIPSInst_FS(ir)); 1542 rv.l = ieee754sp_tlong(fs); 1543 rfmt = l_fmt; 1544 goto copcsr; 1545 1546 case froundl_op: 1547 case ftruncl_op: 1548 case fceill_op: 1549 case ffloorl_op: 1550 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1551 return SIGILL; 1552 1553 oldrm = ieee754_csr.rm; 1554 SPFROMREG(fs, MIPSInst_FS(ir)); 1555 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1556 rv.l = ieee754sp_tlong(fs); 1557 ieee754_csr.rm = oldrm; 1558 rfmt = l_fmt; 1559 goto copcsr; 1560 1561 default: 1562 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1563 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1564 union ieee754sp fs, ft; 1565 1566 SPFROMREG(fs, MIPSInst_FS(ir)); 1567 SPFROMREG(ft, MIPSInst_FT(ir)); 1568 rv.w = ieee754sp_cmp(fs, ft, 1569 cmptab[cmpop & 0x7], cmpop & 0x8); 1570 rfmt = -1; 1571 if ((cmpop & 0x8) && ieee754_cxtest 1572 (IEEE754_INVALID_OPERATION)) 1573 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1574 else 1575 goto copcsr; 1576 1577 } else 1578 return SIGILL; 1579 break; 1580 } 1581 break; 1582 } 1583 1584 case d_fmt: { 1585 union ieee754dp fs, ft; 1586 union { 1587 union ieee754dp(*b) (union ieee754dp, union ieee754dp); 1588 union ieee754dp(*u) (union ieee754dp); 1589 } handler; 1590 1591 switch (MIPSInst_FUNC(ir)) { 1592 /* binary ops */ 1593 case fadd_op: 1594 handler.b = ieee754dp_add; 1595 goto dcopbop; 1596 case fsub_op: 1597 handler.b = ieee754dp_sub; 1598 goto dcopbop; 1599 case fmul_op: 1600 handler.b = ieee754dp_mul; 1601 goto dcopbop; 1602 case fdiv_op: 1603 handler.b = ieee754dp_div; 1604 goto dcopbop; 1605 1606 /* unary ops */ 1607 case fsqrt_op: 1608 if (!cpu_has_mips_2_3_4_5_r) 1609 return SIGILL; 1610 1611 handler.u = ieee754dp_sqrt; 1612 goto dcopuop; 1613 /* 1614 * Note that on some MIPS IV implementations such as the 1615 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1616 * achieve full IEEE-754 accuracy - however this emulator does. 1617 */ 1618 case frsqrt_op: 1619 if (!cpu_has_mips_4_5_r2) 1620 return SIGILL; 1621 1622 handler.u = fpemu_dp_rsqrt; 1623 goto dcopuop; 1624 case frecip_op: 1625 if (!cpu_has_mips_4_5_r2) 1626 return SIGILL; 1627 1628 handler.u = fpemu_dp_recip; 1629 goto dcopuop; 1630 case fmovc_op: 1631 if (!cpu_has_mips_4_5_r) 1632 return SIGILL; 1633 1634 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1635 if (((ctx->fcr31 & cond) != 0) != 1636 ((MIPSInst_FT(ir) & 1) != 0)) 1637 return 0; 1638 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1639 break; 1640 case fmovz_op: 1641 if (!cpu_has_mips_4_5_r) 1642 return SIGILL; 1643 1644 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1645 return 0; 1646 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1647 break; 1648 case fmovn_op: 1649 if (!cpu_has_mips_4_5_r) 1650 return SIGILL; 1651 1652 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1653 return 0; 1654 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1655 break; 1656 case fabs_op: 1657 handler.u = ieee754dp_abs; 1658 goto dcopuop; 1659 1660 case fneg_op: 1661 handler.u = ieee754dp_neg; 1662 goto dcopuop; 1663 1664 case fmov_op: 1665 /* an easy one */ 1666 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1667 goto copcsr; 1668 1669 /* binary op on handler */ 1670 dcopbop: 1671 DPFROMREG(fs, MIPSInst_FS(ir)); 1672 DPFROMREG(ft, MIPSInst_FT(ir)); 1673 1674 rv.d = (*handler.b) (fs, ft); 1675 goto copcsr; 1676 dcopuop: 1677 DPFROMREG(fs, MIPSInst_FS(ir)); 1678 rv.d = (*handler.u) (fs); 1679 goto copcsr; 1680 1681 /* 1682 * unary conv ops 1683 */ 1684 case fcvts_op: 1685 DPFROMREG(fs, MIPSInst_FS(ir)); 1686 rv.s = ieee754sp_fdp(fs); 1687 rfmt = s_fmt; 1688 goto copcsr; 1689 1690 case fcvtd_op: 1691 return SIGILL; /* not defined */ 1692 1693 case fcvtw_op: 1694 DPFROMREG(fs, MIPSInst_FS(ir)); 1695 rv.w = ieee754dp_tint(fs); /* wrong */ 1696 rfmt = w_fmt; 1697 goto copcsr; 1698 1699 case fround_op: 1700 case ftrunc_op: 1701 case fceil_op: 1702 case ffloor_op: 1703 if (!cpu_has_mips_2_3_4_5_r) 1704 return SIGILL; 1705 1706 oldrm = ieee754_csr.rm; 1707 DPFROMREG(fs, MIPSInst_FS(ir)); 1708 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1709 rv.w = ieee754dp_tint(fs); 1710 ieee754_csr.rm = oldrm; 1711 rfmt = w_fmt; 1712 goto copcsr; 1713 1714 case fcvtl_op: 1715 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1716 return SIGILL; 1717 1718 DPFROMREG(fs, MIPSInst_FS(ir)); 1719 rv.l = ieee754dp_tlong(fs); 1720 rfmt = l_fmt; 1721 goto copcsr; 1722 1723 case froundl_op: 1724 case ftruncl_op: 1725 case fceill_op: 1726 case ffloorl_op: 1727 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1728 return SIGILL; 1729 1730 oldrm = ieee754_csr.rm; 1731 DPFROMREG(fs, MIPSInst_FS(ir)); 1732 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1733 rv.l = ieee754dp_tlong(fs); 1734 ieee754_csr.rm = oldrm; 1735 rfmt = l_fmt; 1736 goto copcsr; 1737 1738 default: 1739 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1740 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1741 union ieee754dp fs, ft; 1742 1743 DPFROMREG(fs, MIPSInst_FS(ir)); 1744 DPFROMREG(ft, MIPSInst_FT(ir)); 1745 rv.w = ieee754dp_cmp(fs, ft, 1746 cmptab[cmpop & 0x7], cmpop & 0x8); 1747 rfmt = -1; 1748 if ((cmpop & 0x8) 1749 && 1750 ieee754_cxtest 1751 (IEEE754_INVALID_OPERATION)) 1752 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1753 else 1754 goto copcsr; 1755 1756 } 1757 else { 1758 return SIGILL; 1759 } 1760 break; 1761 } 1762 break; 1763 1764 case w_fmt: 1765 switch (MIPSInst_FUNC(ir)) { 1766 case fcvts_op: 1767 /* convert word to single precision real */ 1768 SPFROMREG(fs, MIPSInst_FS(ir)); 1769 rv.s = ieee754sp_fint(fs.bits); 1770 rfmt = s_fmt; 1771 goto copcsr; 1772 case fcvtd_op: 1773 /* convert word to double precision real */ 1774 SPFROMREG(fs, MIPSInst_FS(ir)); 1775 rv.d = ieee754dp_fint(fs.bits); 1776 rfmt = d_fmt; 1777 goto copcsr; 1778 default: 1779 return SIGILL; 1780 } 1781 break; 1782 } 1783 1784 case l_fmt: 1785 1786 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1787 return SIGILL; 1788 1789 DIFROMREG(bits, MIPSInst_FS(ir)); 1790 1791 switch (MIPSInst_FUNC(ir)) { 1792 case fcvts_op: 1793 /* convert long to single precision real */ 1794 rv.s = ieee754sp_flong(bits); 1795 rfmt = s_fmt; 1796 goto copcsr; 1797 case fcvtd_op: 1798 /* convert long to double precision real */ 1799 rv.d = ieee754dp_flong(bits); 1800 rfmt = d_fmt; 1801 goto copcsr; 1802 default: 1803 return SIGILL; 1804 } 1805 break; 1806 1807 default: 1808 return SIGILL; 1809 } 1810 1811 /* 1812 * Update the fpu CSR register for this operation. 1813 * If an exception is required, generate a tidy SIGFPE exception, 1814 * without updating the result register. 1815 * Note: cause exception bits do not accumulate, they are rewritten 1816 * for each op; only the flag/sticky bits accumulate. 1817 */ 1818 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1819 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1820 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ 1821 return SIGFPE; 1822 } 1823 1824 /* 1825 * Now we can safely write the result back to the register file. 1826 */ 1827 switch (rfmt) { 1828 case -1: 1829 1830 if (cpu_has_mips_4_5_r) 1831 cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; 1832 else 1833 cbit = FPU_CSR_COND; 1834 if (rv.w) 1835 ctx->fcr31 |= cbit; 1836 else 1837 ctx->fcr31 &= ~cbit; 1838 break; 1839 1840 case d_fmt: 1841 DPTOREG(rv.d, MIPSInst_FD(ir)); 1842 break; 1843 case s_fmt: 1844 SPTOREG(rv.s, MIPSInst_FD(ir)); 1845 break; 1846 case w_fmt: 1847 SITOREG(rv.w, MIPSInst_FD(ir)); 1848 break; 1849 case l_fmt: 1850 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1851 return SIGILL; 1852 1853 DITOREG(rv.l, MIPSInst_FD(ir)); 1854 break; 1855 default: 1856 return SIGILL; 1857 } 1858 1859 return 0; 1860 } 1861 1862 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1863 int has_fpu, void *__user *fault_addr) 1864 { 1865 unsigned long oldepc, prevepc; 1866 struct mm_decoded_insn dec_insn; 1867 u16 instr[4]; 1868 u16 *instr_ptr; 1869 int sig = 0; 1870 1871 oldepc = xcp->cp0_epc; 1872 do { 1873 prevepc = xcp->cp0_epc; 1874 1875 if (get_isa16_mode(prevepc) && cpu_has_mmips) { 1876 /* 1877 * Get next 2 microMIPS instructions and convert them 1878 * into 32-bit instructions. 1879 */ 1880 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 1881 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 1882 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 1883 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 1884 MIPS_FPU_EMU_INC_STATS(errors); 1885 return SIGBUS; 1886 } 1887 instr_ptr = instr; 1888 1889 /* Get first instruction. */ 1890 if (mm_insn_16bit(*instr_ptr)) { 1891 /* Duplicate the half-word. */ 1892 dec_insn.insn = (*instr_ptr << 16) | 1893 (*instr_ptr); 1894 /* 16-bit instruction. */ 1895 dec_insn.pc_inc = 2; 1896 instr_ptr += 1; 1897 } else { 1898 dec_insn.insn = (*instr_ptr << 16) | 1899 *(instr_ptr+1); 1900 /* 32-bit instruction. */ 1901 dec_insn.pc_inc = 4; 1902 instr_ptr += 2; 1903 } 1904 /* Get second instruction. */ 1905 if (mm_insn_16bit(*instr_ptr)) { 1906 /* Duplicate the half-word. */ 1907 dec_insn.next_insn = (*instr_ptr << 16) | 1908 (*instr_ptr); 1909 /* 16-bit instruction. */ 1910 dec_insn.next_pc_inc = 2; 1911 } else { 1912 dec_insn.next_insn = (*instr_ptr << 16) | 1913 *(instr_ptr+1); 1914 /* 32-bit instruction. */ 1915 dec_insn.next_pc_inc = 4; 1916 } 1917 dec_insn.micro_mips_mode = 1; 1918 } else { 1919 if ((get_user(dec_insn.insn, 1920 (mips_instruction __user *) xcp->cp0_epc)) || 1921 (get_user(dec_insn.next_insn, 1922 (mips_instruction __user *)(xcp->cp0_epc+4)))) { 1923 MIPS_FPU_EMU_INC_STATS(errors); 1924 return SIGBUS; 1925 } 1926 dec_insn.pc_inc = 4; 1927 dec_insn.next_pc_inc = 4; 1928 dec_insn.micro_mips_mode = 0; 1929 } 1930 1931 if ((dec_insn.insn == 0) || 1932 ((dec_insn.pc_inc == 2) && 1933 ((dec_insn.insn & 0xffff) == MM_NOP16))) 1934 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 1935 else { 1936 /* 1937 * The 'ieee754_csr' is an alias of 1938 * ctx->fcr31. No need to copy ctx->fcr31 to 1939 * ieee754_csr. But ieee754_csr.rm is ieee 1940 * library modes. (not mips rounding mode) 1941 */ 1942 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 1943 } 1944 1945 if (has_fpu) 1946 break; 1947 if (sig) 1948 break; 1949 1950 cond_resched(); 1951 } while (xcp->cp0_epc > prevepc); 1952 1953 /* SIGILL indicates a non-fpu instruction */ 1954 if (sig == SIGILL && xcp->cp0_epc != oldepc) 1955 /* but if EPC has advanced, then ignore it */ 1956 sig = 0; 1957 1958 return sig; 1959 } 1960