1 /* 2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 22 * 23 * A complete emulator for MIPS coprocessor 1 instructions. This is 24 * required for #float(switch) or #float(trap), where it catches all 25 * COP1 instructions via the "CoProcessor Unusable" exception. 26 * 27 * More surprisingly it is also required for #float(ieee), to help out 28 * the hardware fpu at the boundaries of the IEEE-754 representation 29 * (denormalised values, infinities, underflow, etc). It is made 30 * quite nasty because emulation of some non-COP1 instructions is 31 * required, e.g. in branch delay slots. 32 * 33 * Note if you know that you won't have an fpu, then you'll get much 34 * better performance by compiling with -msoft-float! 35 */ 36 #include <linux/sched.h> 37 #include <linux/module.h> 38 #include <linux/debugfs.h> 39 #include <linux/perf_event.h> 40 41 #include <asm/inst.h> 42 #include <asm/bootinfo.h> 43 #include <asm/processor.h> 44 #include <asm/ptrace.h> 45 #include <asm/signal.h> 46 #include <asm/mipsregs.h> 47 #include <asm/fpu_emulator.h> 48 #include <asm/fpu.h> 49 #include <asm/uaccess.h> 50 #include <asm/branch.h> 51 52 #include "ieee754.h" 53 54 /* Strap kernel emulator for full MIPS IV emulation */ 55 56 #ifdef __mips 57 #undef __mips 58 #endif 59 #define __mips 4 60 61 /* Function which emulates a floating point instruction. */ 62 63 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 64 mips_instruction); 65 66 #if __mips >= 4 && __mips != 32 67 static int fpux_emu(struct pt_regs *, 68 struct mips_fpu_struct *, mips_instruction, void *__user *); 69 #endif 70 71 /* Further private data for which no space exists in mips_fpu_struct */ 72 73 #ifdef CONFIG_DEBUG_FS 74 DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); 75 #endif 76 77 /* Control registers */ 78 79 #define FPCREG_RID 0 /* $0 = revision id */ 80 #define FPCREG_CSR 31 /* $31 = csr */ 81 82 /* Determine rounding mode from the RM bits of the FCSR */ 83 #define modeindex(v) ((v) & FPU_CSR_RM) 84 85 /* microMIPS bitfields */ 86 #define MM_POOL32A_MINOR_MASK 0x3f 87 #define MM_POOL32A_MINOR_SHIFT 0x6 88 #define MM_MIPS32_COND_FC 0x30 89 90 /* Convert Mips rounding mode (0..3) to IEEE library modes. */ 91 static const unsigned char ieee_rm[4] = { 92 [FPU_CSR_RN] = IEEE754_RN, 93 [FPU_CSR_RZ] = IEEE754_RZ, 94 [FPU_CSR_RU] = IEEE754_RU, 95 [FPU_CSR_RD] = IEEE754_RD, 96 }; 97 /* Convert IEEE library modes to Mips rounding mode (0..3). */ 98 static const unsigned char mips_rm[4] = { 99 [IEEE754_RN] = FPU_CSR_RN, 100 [IEEE754_RZ] = FPU_CSR_RZ, 101 [IEEE754_RD] = FPU_CSR_RD, 102 [IEEE754_RU] = FPU_CSR_RU, 103 }; 104 105 #if __mips >= 4 106 /* convert condition code register number to csr bit */ 107 static const unsigned int fpucondbit[8] = { 108 FPU_CSR_COND0, 109 FPU_CSR_COND1, 110 FPU_CSR_COND2, 111 FPU_CSR_COND3, 112 FPU_CSR_COND4, 113 FPU_CSR_COND5, 114 FPU_CSR_COND6, 115 FPU_CSR_COND7 116 }; 117 #endif 118 119 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */ 120 static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7}; 121 122 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 123 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 124 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 125 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 126 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 127 128 /* 129 * This functions translates a 32-bit microMIPS instruction 130 * into a 32-bit MIPS32 instruction. Returns 0 on success 131 * and SIGILL otherwise. 132 */ 133 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 134 { 135 union mips_instruction insn = *insn_ptr; 136 union mips_instruction mips32_insn = insn; 137 int func, fmt, op; 138 139 switch (insn.mm_i_format.opcode) { 140 case mm_ldc132_op: 141 mips32_insn.mm_i_format.opcode = ldc1_op; 142 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 143 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 144 break; 145 case mm_lwc132_op: 146 mips32_insn.mm_i_format.opcode = lwc1_op; 147 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 148 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 149 break; 150 case mm_sdc132_op: 151 mips32_insn.mm_i_format.opcode = sdc1_op; 152 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 153 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 154 break; 155 case mm_swc132_op: 156 mips32_insn.mm_i_format.opcode = swc1_op; 157 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 158 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 159 break; 160 case mm_pool32i_op: 161 /* NOTE: offset is << by 1 if in microMIPS mode. */ 162 if ((insn.mm_i_format.rt == mm_bc1f_op) || 163 (insn.mm_i_format.rt == mm_bc1t_op)) { 164 mips32_insn.fb_format.opcode = cop1_op; 165 mips32_insn.fb_format.bc = bc_op; 166 mips32_insn.fb_format.flag = 167 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 168 } else 169 return SIGILL; 170 break; 171 case mm_pool32f_op: 172 switch (insn.mm_fp0_format.func) { 173 case mm_32f_01_op: 174 case mm_32f_11_op: 175 case mm_32f_02_op: 176 case mm_32f_12_op: 177 case mm_32f_41_op: 178 case mm_32f_51_op: 179 case mm_32f_42_op: 180 case mm_32f_52_op: 181 op = insn.mm_fp0_format.func; 182 if (op == mm_32f_01_op) 183 func = madd_s_op; 184 else if (op == mm_32f_11_op) 185 func = madd_d_op; 186 else if (op == mm_32f_02_op) 187 func = nmadd_s_op; 188 else if (op == mm_32f_12_op) 189 func = nmadd_d_op; 190 else if (op == mm_32f_41_op) 191 func = msub_s_op; 192 else if (op == mm_32f_51_op) 193 func = msub_d_op; 194 else if (op == mm_32f_42_op) 195 func = nmsub_s_op; 196 else 197 func = nmsub_d_op; 198 mips32_insn.fp6_format.opcode = cop1x_op; 199 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 200 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 201 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 202 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 203 mips32_insn.fp6_format.func = func; 204 break; 205 case mm_32f_10_op: 206 func = -1; /* Invalid */ 207 op = insn.mm_fp5_format.op & 0x7; 208 if (op == mm_ldxc1_op) 209 func = ldxc1_op; 210 else if (op == mm_sdxc1_op) 211 func = sdxc1_op; 212 else if (op == mm_lwxc1_op) 213 func = lwxc1_op; 214 else if (op == mm_swxc1_op) 215 func = swxc1_op; 216 217 if (func != -1) { 218 mips32_insn.r_format.opcode = cop1x_op; 219 mips32_insn.r_format.rs = 220 insn.mm_fp5_format.base; 221 mips32_insn.r_format.rt = 222 insn.mm_fp5_format.index; 223 mips32_insn.r_format.rd = 0; 224 mips32_insn.r_format.re = insn.mm_fp5_format.fd; 225 mips32_insn.r_format.func = func; 226 } else 227 return SIGILL; 228 break; 229 case mm_32f_40_op: 230 op = -1; /* Invalid */ 231 if (insn.mm_fp2_format.op == mm_fmovt_op) 232 op = 1; 233 else if (insn.mm_fp2_format.op == mm_fmovf_op) 234 op = 0; 235 if (op != -1) { 236 mips32_insn.fp0_format.opcode = cop1_op; 237 mips32_insn.fp0_format.fmt = 238 sdps_format[insn.mm_fp2_format.fmt]; 239 mips32_insn.fp0_format.ft = 240 (insn.mm_fp2_format.cc<<2) + op; 241 mips32_insn.fp0_format.fs = 242 insn.mm_fp2_format.fs; 243 mips32_insn.fp0_format.fd = 244 insn.mm_fp2_format.fd; 245 mips32_insn.fp0_format.func = fmovc_op; 246 } else 247 return SIGILL; 248 break; 249 case mm_32f_60_op: 250 func = -1; /* Invalid */ 251 if (insn.mm_fp0_format.op == mm_fadd_op) 252 func = fadd_op; 253 else if (insn.mm_fp0_format.op == mm_fsub_op) 254 func = fsub_op; 255 else if (insn.mm_fp0_format.op == mm_fmul_op) 256 func = fmul_op; 257 else if (insn.mm_fp0_format.op == mm_fdiv_op) 258 func = fdiv_op; 259 if (func != -1) { 260 mips32_insn.fp0_format.opcode = cop1_op; 261 mips32_insn.fp0_format.fmt = 262 sdps_format[insn.mm_fp0_format.fmt]; 263 mips32_insn.fp0_format.ft = 264 insn.mm_fp0_format.ft; 265 mips32_insn.fp0_format.fs = 266 insn.mm_fp0_format.fs; 267 mips32_insn.fp0_format.fd = 268 insn.mm_fp0_format.fd; 269 mips32_insn.fp0_format.func = func; 270 } else 271 return SIGILL; 272 break; 273 case mm_32f_70_op: 274 func = -1; /* Invalid */ 275 if (insn.mm_fp0_format.op == mm_fmovn_op) 276 func = fmovn_op; 277 else if (insn.mm_fp0_format.op == mm_fmovz_op) 278 func = fmovz_op; 279 if (func != -1) { 280 mips32_insn.fp0_format.opcode = cop1_op; 281 mips32_insn.fp0_format.fmt = 282 sdps_format[insn.mm_fp0_format.fmt]; 283 mips32_insn.fp0_format.ft = 284 insn.mm_fp0_format.ft; 285 mips32_insn.fp0_format.fs = 286 insn.mm_fp0_format.fs; 287 mips32_insn.fp0_format.fd = 288 insn.mm_fp0_format.fd; 289 mips32_insn.fp0_format.func = func; 290 } else 291 return SIGILL; 292 break; 293 case mm_32f_73_op: /* POOL32FXF */ 294 switch (insn.mm_fp1_format.op) { 295 case mm_movf0_op: 296 case mm_movf1_op: 297 case mm_movt0_op: 298 case mm_movt1_op: 299 if ((insn.mm_fp1_format.op & 0x7f) == 300 mm_movf0_op) 301 op = 0; 302 else 303 op = 1; 304 mips32_insn.r_format.opcode = spec_op; 305 mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 306 mips32_insn.r_format.rt = 307 (insn.mm_fp4_format.cc << 2) + op; 308 mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 309 mips32_insn.r_format.re = 0; 310 mips32_insn.r_format.func = movc_op; 311 break; 312 case mm_fcvtd0_op: 313 case mm_fcvtd1_op: 314 case mm_fcvts0_op: 315 case mm_fcvts1_op: 316 if ((insn.mm_fp1_format.op & 0x7f) == 317 mm_fcvtd0_op) { 318 func = fcvtd_op; 319 fmt = swl_format[insn.mm_fp3_format.fmt]; 320 } else { 321 func = fcvts_op; 322 fmt = dwl_format[insn.mm_fp3_format.fmt]; 323 } 324 mips32_insn.fp0_format.opcode = cop1_op; 325 mips32_insn.fp0_format.fmt = fmt; 326 mips32_insn.fp0_format.ft = 0; 327 mips32_insn.fp0_format.fs = 328 insn.mm_fp3_format.fs; 329 mips32_insn.fp0_format.fd = 330 insn.mm_fp3_format.rt; 331 mips32_insn.fp0_format.func = func; 332 break; 333 case mm_fmov0_op: 334 case mm_fmov1_op: 335 case mm_fabs0_op: 336 case mm_fabs1_op: 337 case mm_fneg0_op: 338 case mm_fneg1_op: 339 if ((insn.mm_fp1_format.op & 0x7f) == 340 mm_fmov0_op) 341 func = fmov_op; 342 else if ((insn.mm_fp1_format.op & 0x7f) == 343 mm_fabs0_op) 344 func = fabs_op; 345 else 346 func = fneg_op; 347 mips32_insn.fp0_format.opcode = cop1_op; 348 mips32_insn.fp0_format.fmt = 349 sdps_format[insn.mm_fp3_format.fmt]; 350 mips32_insn.fp0_format.ft = 0; 351 mips32_insn.fp0_format.fs = 352 insn.mm_fp3_format.fs; 353 mips32_insn.fp0_format.fd = 354 insn.mm_fp3_format.rt; 355 mips32_insn.fp0_format.func = func; 356 break; 357 case mm_ffloorl_op: 358 case mm_ffloorw_op: 359 case mm_fceill_op: 360 case mm_fceilw_op: 361 case mm_ftruncl_op: 362 case mm_ftruncw_op: 363 case mm_froundl_op: 364 case mm_froundw_op: 365 case mm_fcvtl_op: 366 case mm_fcvtw_op: 367 if (insn.mm_fp1_format.op == mm_ffloorl_op) 368 func = ffloorl_op; 369 else if (insn.mm_fp1_format.op == mm_ffloorw_op) 370 func = ffloor_op; 371 else if (insn.mm_fp1_format.op == mm_fceill_op) 372 func = fceill_op; 373 else if (insn.mm_fp1_format.op == mm_fceilw_op) 374 func = fceil_op; 375 else if (insn.mm_fp1_format.op == mm_ftruncl_op) 376 func = ftruncl_op; 377 else if (insn.mm_fp1_format.op == mm_ftruncw_op) 378 func = ftrunc_op; 379 else if (insn.mm_fp1_format.op == mm_froundl_op) 380 func = froundl_op; 381 else if (insn.mm_fp1_format.op == mm_froundw_op) 382 func = fround_op; 383 else if (insn.mm_fp1_format.op == mm_fcvtl_op) 384 func = fcvtl_op; 385 else 386 func = fcvtw_op; 387 mips32_insn.fp0_format.opcode = cop1_op; 388 mips32_insn.fp0_format.fmt = 389 sd_format[insn.mm_fp1_format.fmt]; 390 mips32_insn.fp0_format.ft = 0; 391 mips32_insn.fp0_format.fs = 392 insn.mm_fp1_format.fs; 393 mips32_insn.fp0_format.fd = 394 insn.mm_fp1_format.rt; 395 mips32_insn.fp0_format.func = func; 396 break; 397 case mm_frsqrt_op: 398 case mm_fsqrt_op: 399 case mm_frecip_op: 400 if (insn.mm_fp1_format.op == mm_frsqrt_op) 401 func = frsqrt_op; 402 else if (insn.mm_fp1_format.op == mm_fsqrt_op) 403 func = fsqrt_op; 404 else 405 func = frecip_op; 406 mips32_insn.fp0_format.opcode = cop1_op; 407 mips32_insn.fp0_format.fmt = 408 sdps_format[insn.mm_fp1_format.fmt]; 409 mips32_insn.fp0_format.ft = 0; 410 mips32_insn.fp0_format.fs = 411 insn.mm_fp1_format.fs; 412 mips32_insn.fp0_format.fd = 413 insn.mm_fp1_format.rt; 414 mips32_insn.fp0_format.func = func; 415 break; 416 case mm_mfc1_op: 417 case mm_mtc1_op: 418 case mm_cfc1_op: 419 case mm_ctc1_op: 420 if (insn.mm_fp1_format.op == mm_mfc1_op) 421 op = mfc_op; 422 else if (insn.mm_fp1_format.op == mm_mtc1_op) 423 op = mtc_op; 424 else if (insn.mm_fp1_format.op == mm_cfc1_op) 425 op = cfc_op; 426 else 427 op = ctc_op; 428 mips32_insn.fp1_format.opcode = cop1_op; 429 mips32_insn.fp1_format.op = op; 430 mips32_insn.fp1_format.rt = 431 insn.mm_fp1_format.rt; 432 mips32_insn.fp1_format.fs = 433 insn.mm_fp1_format.fs; 434 mips32_insn.fp1_format.fd = 0; 435 mips32_insn.fp1_format.func = 0; 436 break; 437 default: 438 return SIGILL; 439 break; 440 } 441 break; 442 case mm_32f_74_op: /* c.cond.fmt */ 443 mips32_insn.fp0_format.opcode = cop1_op; 444 mips32_insn.fp0_format.fmt = 445 sdps_format[insn.mm_fp4_format.fmt]; 446 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 447 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 448 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 449 mips32_insn.fp0_format.func = 450 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 451 break; 452 default: 453 return SIGILL; 454 break; 455 } 456 break; 457 default: 458 return SIGILL; 459 break; 460 } 461 462 *insn_ptr = mips32_insn; 463 return 0; 464 } 465 466 int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 467 unsigned long *contpc) 468 { 469 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 470 int bc_false = 0; 471 unsigned int fcr31; 472 unsigned int bit; 473 474 switch (insn.mm_i_format.opcode) { 475 case mm_pool32a_op: 476 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) == 477 mm_pool32axf_op) { 478 switch (insn.mm_i_format.simmediate >> 479 MM_POOL32A_MINOR_SHIFT) { 480 case mm_jalr_op: 481 case mm_jalrhb_op: 482 case mm_jalrs_op: 483 case mm_jalrshb_op: 484 if (insn.mm_i_format.rt != 0) /* Not mm_jr */ 485 regs->regs[insn.mm_i_format.rt] = 486 regs->cp0_epc + 487 dec_insn.pc_inc + 488 dec_insn.next_pc_inc; 489 *contpc = regs->regs[insn.mm_i_format.rs]; 490 return 1; 491 break; 492 } 493 } 494 break; 495 case mm_pool32i_op: 496 switch (insn.mm_i_format.rt) { 497 case mm_bltzals_op: 498 case mm_bltzal_op: 499 regs->regs[31] = regs->cp0_epc + 500 dec_insn.pc_inc + 501 dec_insn.next_pc_inc; 502 /* Fall through */ 503 case mm_bltz_op: 504 if ((long)regs->regs[insn.mm_i_format.rs] < 0) 505 *contpc = regs->cp0_epc + 506 dec_insn.pc_inc + 507 (insn.mm_i_format.simmediate << 1); 508 else 509 *contpc = regs->cp0_epc + 510 dec_insn.pc_inc + 511 dec_insn.next_pc_inc; 512 return 1; 513 break; 514 case mm_bgezals_op: 515 case mm_bgezal_op: 516 regs->regs[31] = regs->cp0_epc + 517 dec_insn.pc_inc + 518 dec_insn.next_pc_inc; 519 /* Fall through */ 520 case mm_bgez_op: 521 if ((long)regs->regs[insn.mm_i_format.rs] >= 0) 522 *contpc = regs->cp0_epc + 523 dec_insn.pc_inc + 524 (insn.mm_i_format.simmediate << 1); 525 else 526 *contpc = regs->cp0_epc + 527 dec_insn.pc_inc + 528 dec_insn.next_pc_inc; 529 return 1; 530 break; 531 case mm_blez_op: 532 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 533 *contpc = regs->cp0_epc + 534 dec_insn.pc_inc + 535 (insn.mm_i_format.simmediate << 1); 536 else 537 *contpc = regs->cp0_epc + 538 dec_insn.pc_inc + 539 dec_insn.next_pc_inc; 540 return 1; 541 break; 542 case mm_bgtz_op: 543 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 544 *contpc = regs->cp0_epc + 545 dec_insn.pc_inc + 546 (insn.mm_i_format.simmediate << 1); 547 else 548 *contpc = regs->cp0_epc + 549 dec_insn.pc_inc + 550 dec_insn.next_pc_inc; 551 return 1; 552 break; 553 case mm_bc2f_op: 554 case mm_bc1f_op: 555 bc_false = 1; 556 /* Fall through */ 557 case mm_bc2t_op: 558 case mm_bc1t_op: 559 preempt_disable(); 560 if (is_fpu_owner()) 561 asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 562 else 563 fcr31 = current->thread.fpu.fcr31; 564 preempt_enable(); 565 566 if (bc_false) 567 fcr31 = ~fcr31; 568 569 bit = (insn.mm_i_format.rs >> 2); 570 bit += (bit != 0); 571 bit += 23; 572 if (fcr31 & (1 << bit)) 573 *contpc = regs->cp0_epc + 574 dec_insn.pc_inc + 575 (insn.mm_i_format.simmediate << 1); 576 else 577 *contpc = regs->cp0_epc + 578 dec_insn.pc_inc + dec_insn.next_pc_inc; 579 return 1; 580 break; 581 } 582 break; 583 case mm_pool16c_op: 584 switch (insn.mm_i_format.rt) { 585 case mm_jalr16_op: 586 case mm_jalrs16_op: 587 regs->regs[31] = regs->cp0_epc + 588 dec_insn.pc_inc + dec_insn.next_pc_inc; 589 /* Fall through */ 590 case mm_jr16_op: 591 *contpc = regs->regs[insn.mm_i_format.rs]; 592 return 1; 593 break; 594 } 595 break; 596 case mm_beqz16_op: 597 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0) 598 *contpc = regs->cp0_epc + 599 dec_insn.pc_inc + 600 (insn.mm_b1_format.simmediate << 1); 601 else 602 *contpc = regs->cp0_epc + 603 dec_insn.pc_inc + dec_insn.next_pc_inc; 604 return 1; 605 break; 606 case mm_bnez16_op: 607 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) 608 *contpc = regs->cp0_epc + 609 dec_insn.pc_inc + 610 (insn.mm_b1_format.simmediate << 1); 611 else 612 *contpc = regs->cp0_epc + 613 dec_insn.pc_inc + dec_insn.next_pc_inc; 614 return 1; 615 break; 616 case mm_b16_op: 617 *contpc = regs->cp0_epc + dec_insn.pc_inc + 618 (insn.mm_b0_format.simmediate << 1); 619 return 1; 620 break; 621 case mm_beq32_op: 622 if (regs->regs[insn.mm_i_format.rs] == 623 regs->regs[insn.mm_i_format.rt]) 624 *contpc = regs->cp0_epc + 625 dec_insn.pc_inc + 626 (insn.mm_i_format.simmediate << 1); 627 else 628 *contpc = regs->cp0_epc + 629 dec_insn.pc_inc + 630 dec_insn.next_pc_inc; 631 return 1; 632 break; 633 case mm_bne32_op: 634 if (regs->regs[insn.mm_i_format.rs] != 635 regs->regs[insn.mm_i_format.rt]) 636 *contpc = regs->cp0_epc + 637 dec_insn.pc_inc + 638 (insn.mm_i_format.simmediate << 1); 639 else 640 *contpc = regs->cp0_epc + 641 dec_insn.pc_inc + dec_insn.next_pc_inc; 642 return 1; 643 break; 644 case mm_jalx32_op: 645 regs->regs[31] = regs->cp0_epc + 646 dec_insn.pc_inc + dec_insn.next_pc_inc; 647 *contpc = regs->cp0_epc + dec_insn.pc_inc; 648 *contpc >>= 28; 649 *contpc <<= 28; 650 *contpc |= (insn.j_format.target << 2); 651 return 1; 652 break; 653 case mm_jals32_op: 654 case mm_jal32_op: 655 regs->regs[31] = regs->cp0_epc + 656 dec_insn.pc_inc + dec_insn.next_pc_inc; 657 /* Fall through */ 658 case mm_j32_op: 659 *contpc = regs->cp0_epc + dec_insn.pc_inc; 660 *contpc >>= 27; 661 *contpc <<= 27; 662 *contpc |= (insn.j_format.target << 1); 663 set_isa16_mode(*contpc); 664 return 1; 665 break; 666 } 667 return 0; 668 } 669 670 /* 671 * Redundant with logic already in kernel/branch.c, 672 * embedded in compute_return_epc. At some point, 673 * a single subroutine should be used across both 674 * modules. 675 */ 676 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 677 unsigned long *contpc) 678 { 679 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 680 unsigned int fcr31; 681 unsigned int bit = 0; 682 683 switch (insn.i_format.opcode) { 684 case spec_op: 685 switch (insn.r_format.func) { 686 case jalr_op: 687 regs->regs[insn.r_format.rd] = 688 regs->cp0_epc + dec_insn.pc_inc + 689 dec_insn.next_pc_inc; 690 /* Fall through */ 691 case jr_op: 692 *contpc = regs->regs[insn.r_format.rs]; 693 return 1; 694 break; 695 } 696 break; 697 case bcond_op: 698 switch (insn.i_format.rt) { 699 case bltzal_op: 700 case bltzall_op: 701 regs->regs[31] = regs->cp0_epc + 702 dec_insn.pc_inc + 703 dec_insn.next_pc_inc; 704 /* Fall through */ 705 case bltz_op: 706 case bltzl_op: 707 if ((long)regs->regs[insn.i_format.rs] < 0) 708 *contpc = regs->cp0_epc + 709 dec_insn.pc_inc + 710 (insn.i_format.simmediate << 2); 711 else 712 *contpc = regs->cp0_epc + 713 dec_insn.pc_inc + 714 dec_insn.next_pc_inc; 715 return 1; 716 break; 717 case bgezal_op: 718 case bgezall_op: 719 regs->regs[31] = regs->cp0_epc + 720 dec_insn.pc_inc + 721 dec_insn.next_pc_inc; 722 /* Fall through */ 723 case bgez_op: 724 case bgezl_op: 725 if ((long)regs->regs[insn.i_format.rs] >= 0) 726 *contpc = regs->cp0_epc + 727 dec_insn.pc_inc + 728 (insn.i_format.simmediate << 2); 729 else 730 *contpc = regs->cp0_epc + 731 dec_insn.pc_inc + 732 dec_insn.next_pc_inc; 733 return 1; 734 break; 735 } 736 break; 737 case jalx_op: 738 set_isa16_mode(bit); 739 case jal_op: 740 regs->regs[31] = regs->cp0_epc + 741 dec_insn.pc_inc + 742 dec_insn.next_pc_inc; 743 /* Fall through */ 744 case j_op: 745 *contpc = regs->cp0_epc + dec_insn.pc_inc; 746 *contpc >>= 28; 747 *contpc <<= 28; 748 *contpc |= (insn.j_format.target << 2); 749 /* Set microMIPS mode bit: XOR for jalx. */ 750 *contpc ^= bit; 751 return 1; 752 break; 753 case beq_op: 754 case beql_op: 755 if (regs->regs[insn.i_format.rs] == 756 regs->regs[insn.i_format.rt]) 757 *contpc = regs->cp0_epc + 758 dec_insn.pc_inc + 759 (insn.i_format.simmediate << 2); 760 else 761 *contpc = regs->cp0_epc + 762 dec_insn.pc_inc + 763 dec_insn.next_pc_inc; 764 return 1; 765 break; 766 case bne_op: 767 case bnel_op: 768 if (regs->regs[insn.i_format.rs] != 769 regs->regs[insn.i_format.rt]) 770 *contpc = regs->cp0_epc + 771 dec_insn.pc_inc + 772 (insn.i_format.simmediate << 2); 773 else 774 *contpc = regs->cp0_epc + 775 dec_insn.pc_inc + 776 dec_insn.next_pc_inc; 777 return 1; 778 break; 779 case blez_op: 780 case blezl_op: 781 if ((long)regs->regs[insn.i_format.rs] <= 0) 782 *contpc = regs->cp0_epc + 783 dec_insn.pc_inc + 784 (insn.i_format.simmediate << 2); 785 else 786 *contpc = regs->cp0_epc + 787 dec_insn.pc_inc + 788 dec_insn.next_pc_inc; 789 return 1; 790 break; 791 case bgtz_op: 792 case bgtzl_op: 793 if ((long)regs->regs[insn.i_format.rs] > 0) 794 *contpc = regs->cp0_epc + 795 dec_insn.pc_inc + 796 (insn.i_format.simmediate << 2); 797 else 798 *contpc = regs->cp0_epc + 799 dec_insn.pc_inc + 800 dec_insn.next_pc_inc; 801 return 1; 802 break; 803 case cop0_op: 804 case cop1_op: 805 case cop2_op: 806 case cop1x_op: 807 if (insn.i_format.rs == bc_op) { 808 preempt_disable(); 809 if (is_fpu_owner()) 810 asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 811 else 812 fcr31 = current->thread.fpu.fcr31; 813 preempt_enable(); 814 815 bit = (insn.i_format.rt >> 2); 816 bit += (bit != 0); 817 bit += 23; 818 switch (insn.i_format.rt & 3) { 819 case 0: /* bc1f */ 820 case 2: /* bc1fl */ 821 if (~fcr31 & (1 << bit)) 822 *contpc = regs->cp0_epc + 823 dec_insn.pc_inc + 824 (insn.i_format.simmediate << 2); 825 else 826 *contpc = regs->cp0_epc + 827 dec_insn.pc_inc + 828 dec_insn.next_pc_inc; 829 return 1; 830 break; 831 case 1: /* bc1t */ 832 case 3: /* bc1tl */ 833 if (fcr31 & (1 << bit)) 834 *contpc = regs->cp0_epc + 835 dec_insn.pc_inc + 836 (insn.i_format.simmediate << 2); 837 else 838 *contpc = regs->cp0_epc + 839 dec_insn.pc_inc + 840 dec_insn.next_pc_inc; 841 return 1; 842 break; 843 } 844 } 845 break; 846 } 847 return 0; 848 } 849 850 /* 851 * In the Linux kernel, we support selection of FPR format on the 852 * basis of the Status.FR bit. If an FPU is not present, the FR bit 853 * is hardwired to zero, which would imply a 32-bit FPU even for 854 * 64-bit CPUs so we rather look at TIF_32BIT_REGS. 855 * FPU emu is slow and bulky and optimizing this function offers fairly 856 * sizeable benefits so we try to be clever and make this function return 857 * a constant whenever possible, that is on 64-bit kernels without O32 858 * compatibility enabled and on 32-bit kernels. 859 */ 860 static inline int cop1_64bit(struct pt_regs *xcp) 861 { 862 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32) 863 return 1; 864 #elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32) 865 return !test_thread_flag(TIF_32BIT_REGS); 866 #else 867 return 0; 868 #endif 869 } 870 871 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \ 872 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32)) 873 874 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \ 875 cop1_64bit(xcp) || !(x & 1) ? \ 876 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ 877 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) 878 879 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)]) 880 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di)) 881 882 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 883 #define SPTOREG(sp, x) SITOREG((sp).bits, x) 884 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 885 #define DPTOREG(dp, x) DITOREG((dp).bits, x) 886 887 /* 888 * Emulate the single floating point instruction pointed at by EPC. 889 * Two instructions if the instruction is in a branch delay slot. 890 */ 891 892 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 893 struct mm_decoded_insn dec_insn, void *__user *fault_addr) 894 { 895 mips_instruction ir; 896 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 897 unsigned int cond; 898 int pc_inc; 899 900 /* XXX NEC Vr54xx bug workaround */ 901 if (xcp->cp0_cause & CAUSEF_BD) { 902 if (dec_insn.micro_mips_mode) { 903 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 904 xcp->cp0_cause &= ~CAUSEF_BD; 905 } else { 906 if (!isBranchInstr(xcp, dec_insn, &contpc)) 907 xcp->cp0_cause &= ~CAUSEF_BD; 908 } 909 } 910 911 if (xcp->cp0_cause & CAUSEF_BD) { 912 /* 913 * The instruction to be emulated is in a branch delay slot 914 * which means that we have to emulate the branch instruction 915 * BEFORE we do the cop1 instruction. 916 * 917 * This branch could be a COP1 branch, but in that case we 918 * would have had a trap for that instruction, and would not 919 * come through this route. 920 * 921 * Linux MIPS branch emulator operates on context, updating the 922 * cp0_epc. 923 */ 924 ir = dec_insn.next_insn; /* process delay slot instr */ 925 pc_inc = dec_insn.next_pc_inc; 926 } else { 927 ir = dec_insn.insn; /* process current instr */ 928 pc_inc = dec_insn.pc_inc; 929 } 930 931 /* 932 * Since microMIPS FPU instructios are a subset of MIPS32 FPU 933 * instructions, we want to convert microMIPS FPU instructions 934 * into MIPS32 instructions so that we could reuse all of the 935 * FPU emulation code. 936 * 937 * NOTE: We cannot do this for branch instructions since they 938 * are not a subset. Example: Cannot emulate a 16-bit 939 * aligned target address with a MIPS32 instruction. 940 */ 941 if (dec_insn.micro_mips_mode) { 942 /* 943 * If next instruction is a 16-bit instruction, then it 944 * it cannot be a FPU instruction. This could happen 945 * since we can be called for non-FPU instructions. 946 */ 947 if ((pc_inc == 2) || 948 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 949 == SIGILL)) 950 return SIGILL; 951 } 952 953 emul: 954 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 955 MIPS_FPU_EMU_INC_STATS(emulated); 956 switch (MIPSInst_OPCODE(ir)) { 957 case ldc1_op:{ 958 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 959 MIPSInst_SIMM(ir)); 960 u64 val; 961 962 MIPS_FPU_EMU_INC_STATS(loads); 963 964 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 965 MIPS_FPU_EMU_INC_STATS(errors); 966 *fault_addr = va; 967 return SIGBUS; 968 } 969 if (__get_user(val, va)) { 970 MIPS_FPU_EMU_INC_STATS(errors); 971 *fault_addr = va; 972 return SIGSEGV; 973 } 974 DITOREG(val, MIPSInst_RT(ir)); 975 break; 976 } 977 978 case sdc1_op:{ 979 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 980 MIPSInst_SIMM(ir)); 981 u64 val; 982 983 MIPS_FPU_EMU_INC_STATS(stores); 984 DIFROMREG(val, MIPSInst_RT(ir)); 985 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 986 MIPS_FPU_EMU_INC_STATS(errors); 987 *fault_addr = va; 988 return SIGBUS; 989 } 990 if (__put_user(val, va)) { 991 MIPS_FPU_EMU_INC_STATS(errors); 992 *fault_addr = va; 993 return SIGSEGV; 994 } 995 break; 996 } 997 998 case lwc1_op:{ 999 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1000 MIPSInst_SIMM(ir)); 1001 u32 val; 1002 1003 MIPS_FPU_EMU_INC_STATS(loads); 1004 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1005 MIPS_FPU_EMU_INC_STATS(errors); 1006 *fault_addr = va; 1007 return SIGBUS; 1008 } 1009 if (__get_user(val, va)) { 1010 MIPS_FPU_EMU_INC_STATS(errors); 1011 *fault_addr = va; 1012 return SIGSEGV; 1013 } 1014 SITOREG(val, MIPSInst_RT(ir)); 1015 break; 1016 } 1017 1018 case swc1_op:{ 1019 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1020 MIPSInst_SIMM(ir)); 1021 u32 val; 1022 1023 MIPS_FPU_EMU_INC_STATS(stores); 1024 SIFROMREG(val, MIPSInst_RT(ir)); 1025 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1026 MIPS_FPU_EMU_INC_STATS(errors); 1027 *fault_addr = va; 1028 return SIGBUS; 1029 } 1030 if (__put_user(val, va)) { 1031 MIPS_FPU_EMU_INC_STATS(errors); 1032 *fault_addr = va; 1033 return SIGSEGV; 1034 } 1035 break; 1036 } 1037 1038 case cop1_op: 1039 switch (MIPSInst_RS(ir)) { 1040 1041 #if defined(__mips64) 1042 case dmfc_op: 1043 /* copregister fs -> gpr[rt] */ 1044 if (MIPSInst_RT(ir) != 0) { 1045 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1046 MIPSInst_RD(ir)); 1047 } 1048 break; 1049 1050 case dmtc_op: 1051 /* copregister fs <- rt */ 1052 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1053 break; 1054 #endif 1055 1056 case mfc_op: 1057 /* copregister rd -> gpr[rt] */ 1058 if (MIPSInst_RT(ir) != 0) { 1059 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1060 MIPSInst_RD(ir)); 1061 } 1062 break; 1063 1064 case mtc_op: 1065 /* copregister rd <- rt */ 1066 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1067 break; 1068 1069 case cfc_op:{ 1070 /* cop control register rd -> gpr[rt] */ 1071 u32 value; 1072 1073 if (MIPSInst_RD(ir) == FPCREG_CSR) { 1074 value = ctx->fcr31; 1075 value = (value & ~FPU_CSR_RM) | 1076 mips_rm[modeindex(value)]; 1077 #ifdef CSRTRACE 1078 printk("%p gpr[%d]<-csr=%08x\n", 1079 (void *) (xcp->cp0_epc), 1080 MIPSInst_RT(ir), value); 1081 #endif 1082 } 1083 else if (MIPSInst_RD(ir) == FPCREG_RID) 1084 value = 0; 1085 else 1086 value = 0; 1087 if (MIPSInst_RT(ir)) 1088 xcp->regs[MIPSInst_RT(ir)] = value; 1089 break; 1090 } 1091 1092 case ctc_op:{ 1093 /* copregister rd <- rt */ 1094 u32 value; 1095 1096 if (MIPSInst_RT(ir) == 0) 1097 value = 0; 1098 else 1099 value = xcp->regs[MIPSInst_RT(ir)]; 1100 1101 /* we only have one writable control reg 1102 */ 1103 if (MIPSInst_RD(ir) == FPCREG_CSR) { 1104 #ifdef CSRTRACE 1105 printk("%p gpr[%d]->csr=%08x\n", 1106 (void *) (xcp->cp0_epc), 1107 MIPSInst_RT(ir), value); 1108 #endif 1109 1110 /* 1111 * Don't write reserved bits, 1112 * and convert to ieee library modes 1113 */ 1114 ctx->fcr31 = (value & 1115 ~(FPU_CSR_RSVD | FPU_CSR_RM)) | 1116 ieee_rm[modeindex(value)]; 1117 } 1118 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1119 return SIGFPE; 1120 } 1121 break; 1122 } 1123 1124 case bc_op:{ 1125 int likely = 0; 1126 1127 if (xcp->cp0_cause & CAUSEF_BD) 1128 return SIGILL; 1129 1130 #if __mips >= 4 1131 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2]; 1132 #else 1133 cond = ctx->fcr31 & FPU_CSR_COND; 1134 #endif 1135 switch (MIPSInst_RT(ir) & 3) { 1136 case bcfl_op: 1137 likely = 1; 1138 case bcf_op: 1139 cond = !cond; 1140 break; 1141 case bctl_op: 1142 likely = 1; 1143 case bct_op: 1144 break; 1145 default: 1146 /* thats an illegal instruction */ 1147 return SIGILL; 1148 } 1149 1150 xcp->cp0_cause |= CAUSEF_BD; 1151 if (cond) { 1152 /* branch taken: emulate dslot 1153 * instruction 1154 */ 1155 xcp->cp0_epc += dec_insn.pc_inc; 1156 1157 contpc = MIPSInst_SIMM(ir); 1158 ir = dec_insn.next_insn; 1159 if (dec_insn.micro_mips_mode) { 1160 contpc = (xcp->cp0_epc + (contpc << 1)); 1161 1162 /* If 16-bit instruction, not FPU. */ 1163 if ((dec_insn.next_pc_inc == 2) || 1164 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 1165 1166 /* 1167 * Since this instruction will 1168 * be put on the stack with 1169 * 32-bit words, get around 1170 * this problem by putting a 1171 * NOP16 as the second one. 1172 */ 1173 if (dec_insn.next_pc_inc == 2) 1174 ir = (ir & (~0xffff)) | MM_NOP16; 1175 1176 /* 1177 * Single step the non-CP1 1178 * instruction in the dslot. 1179 */ 1180 return mips_dsemul(xcp, ir, contpc); 1181 } 1182 } else 1183 contpc = (xcp->cp0_epc + (contpc << 2)); 1184 1185 switch (MIPSInst_OPCODE(ir)) { 1186 case lwc1_op: 1187 case swc1_op: 1188 #if (__mips >= 2 || defined(__mips64)) 1189 case ldc1_op: 1190 case sdc1_op: 1191 #endif 1192 case cop1_op: 1193 #if __mips >= 4 && __mips != 32 1194 case cop1x_op: 1195 #endif 1196 /* its one of ours */ 1197 goto emul; 1198 #if __mips >= 4 1199 case spec_op: 1200 if (MIPSInst_FUNC(ir) == movc_op) 1201 goto emul; 1202 break; 1203 #endif 1204 } 1205 1206 /* 1207 * Single step the non-cp1 1208 * instruction in the dslot 1209 */ 1210 return mips_dsemul(xcp, ir, contpc); 1211 } 1212 else { 1213 /* branch not taken */ 1214 if (likely) { 1215 /* 1216 * branch likely nullifies 1217 * dslot if not taken 1218 */ 1219 xcp->cp0_epc += dec_insn.pc_inc; 1220 contpc += dec_insn.pc_inc; 1221 /* 1222 * else continue & execute 1223 * dslot as normal insn 1224 */ 1225 } 1226 } 1227 break; 1228 } 1229 1230 default: 1231 if (!(MIPSInst_RS(ir) & 0x10)) 1232 return SIGILL; 1233 { 1234 int sig; 1235 1236 /* a real fpu computation instruction */ 1237 if ((sig = fpu_emu(xcp, ctx, ir))) 1238 return sig; 1239 } 1240 } 1241 break; 1242 1243 #if __mips >= 4 && __mips != 32 1244 case cop1x_op:{ 1245 int sig = fpux_emu(xcp, ctx, ir, fault_addr); 1246 if (sig) 1247 return sig; 1248 break; 1249 } 1250 #endif 1251 1252 #if __mips >= 4 1253 case spec_op: 1254 if (MIPSInst_FUNC(ir) != movc_op) 1255 return SIGILL; 1256 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 1257 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 1258 xcp->regs[MIPSInst_RD(ir)] = 1259 xcp->regs[MIPSInst_RS(ir)]; 1260 break; 1261 #endif 1262 1263 default: 1264 return SIGILL; 1265 } 1266 1267 /* we did it !! */ 1268 xcp->cp0_epc = contpc; 1269 xcp->cp0_cause &= ~CAUSEF_BD; 1270 1271 return 0; 1272 } 1273 1274 /* 1275 * Conversion table from MIPS compare ops 48-63 1276 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 1277 */ 1278 static const unsigned char cmptab[8] = { 1279 0, /* cmp_0 (sig) cmp_sf */ 1280 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 1281 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 1282 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 1283 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 1284 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 1285 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 1286 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 1287 }; 1288 1289 1290 #if __mips >= 4 && __mips != 32 1291 1292 /* 1293 * Additional MIPS4 instructions 1294 */ 1295 1296 #define DEF3OP(name, p, f1, f2, f3) \ 1297 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \ 1298 ieee754##p t) \ 1299 { \ 1300 struct _ieee754_csr ieee754_csr_save; \ 1301 s = f1(s, t); \ 1302 ieee754_csr_save = ieee754_csr; \ 1303 s = f2(s, r); \ 1304 ieee754_csr_save.cx |= ieee754_csr.cx; \ 1305 ieee754_csr_save.sx |= ieee754_csr.sx; \ 1306 s = f3(s); \ 1307 ieee754_csr.cx |= ieee754_csr_save.cx; \ 1308 ieee754_csr.sx |= ieee754_csr_save.sx; \ 1309 return s; \ 1310 } 1311 1312 static ieee754dp fpemu_dp_recip(ieee754dp d) 1313 { 1314 return ieee754dp_div(ieee754dp_one(0), d); 1315 } 1316 1317 static ieee754dp fpemu_dp_rsqrt(ieee754dp d) 1318 { 1319 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 1320 } 1321 1322 static ieee754sp fpemu_sp_recip(ieee754sp s) 1323 { 1324 return ieee754sp_div(ieee754sp_one(0), s); 1325 } 1326 1327 static ieee754sp fpemu_sp_rsqrt(ieee754sp s) 1328 { 1329 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 1330 } 1331 1332 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 1333 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 1334 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 1335 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 1336 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 1337 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 1338 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 1339 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 1340 1341 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1342 mips_instruction ir, void *__user *fault_addr) 1343 { 1344 unsigned rcsr = 0; /* resulting csr */ 1345 1346 MIPS_FPU_EMU_INC_STATS(cp1xops); 1347 1348 switch (MIPSInst_FMA_FFMT(ir)) { 1349 case s_fmt:{ /* 0 */ 1350 1351 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp); 1352 ieee754sp fd, fr, fs, ft; 1353 u32 __user *va; 1354 u32 val; 1355 1356 switch (MIPSInst_FUNC(ir)) { 1357 case lwxc1_op: 1358 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1359 xcp->regs[MIPSInst_FT(ir)]); 1360 1361 MIPS_FPU_EMU_INC_STATS(loads); 1362 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1363 MIPS_FPU_EMU_INC_STATS(errors); 1364 *fault_addr = va; 1365 return SIGBUS; 1366 } 1367 if (__get_user(val, va)) { 1368 MIPS_FPU_EMU_INC_STATS(errors); 1369 *fault_addr = va; 1370 return SIGSEGV; 1371 } 1372 SITOREG(val, MIPSInst_FD(ir)); 1373 break; 1374 1375 case swxc1_op: 1376 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1377 xcp->regs[MIPSInst_FT(ir)]); 1378 1379 MIPS_FPU_EMU_INC_STATS(stores); 1380 1381 SIFROMREG(val, MIPSInst_FS(ir)); 1382 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1383 MIPS_FPU_EMU_INC_STATS(errors); 1384 *fault_addr = va; 1385 return SIGBUS; 1386 } 1387 if (put_user(val, va)) { 1388 MIPS_FPU_EMU_INC_STATS(errors); 1389 *fault_addr = va; 1390 return SIGSEGV; 1391 } 1392 break; 1393 1394 case madd_s_op: 1395 handler = fpemu_sp_madd; 1396 goto scoptop; 1397 case msub_s_op: 1398 handler = fpemu_sp_msub; 1399 goto scoptop; 1400 case nmadd_s_op: 1401 handler = fpemu_sp_nmadd; 1402 goto scoptop; 1403 case nmsub_s_op: 1404 handler = fpemu_sp_nmsub; 1405 goto scoptop; 1406 1407 scoptop: 1408 SPFROMREG(fr, MIPSInst_FR(ir)); 1409 SPFROMREG(fs, MIPSInst_FS(ir)); 1410 SPFROMREG(ft, MIPSInst_FT(ir)); 1411 fd = (*handler) (fr, fs, ft); 1412 SPTOREG(fd, MIPSInst_FD(ir)); 1413 1414 copcsr: 1415 if (ieee754_cxtest(IEEE754_INEXACT)) 1416 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1417 if (ieee754_cxtest(IEEE754_UNDERFLOW)) 1418 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1419 if (ieee754_cxtest(IEEE754_OVERFLOW)) 1420 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1421 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 1422 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1423 1424 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1425 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1426 /*printk ("SIGFPE: fpu csr = %08x\n", 1427 ctx->fcr31); */ 1428 return SIGFPE; 1429 } 1430 1431 break; 1432 1433 default: 1434 return SIGILL; 1435 } 1436 break; 1437 } 1438 1439 case d_fmt:{ /* 1 */ 1440 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp); 1441 ieee754dp fd, fr, fs, ft; 1442 u64 __user *va; 1443 u64 val; 1444 1445 switch (MIPSInst_FUNC(ir)) { 1446 case ldxc1_op: 1447 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1448 xcp->regs[MIPSInst_FT(ir)]); 1449 1450 MIPS_FPU_EMU_INC_STATS(loads); 1451 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1452 MIPS_FPU_EMU_INC_STATS(errors); 1453 *fault_addr = va; 1454 return SIGBUS; 1455 } 1456 if (__get_user(val, va)) { 1457 MIPS_FPU_EMU_INC_STATS(errors); 1458 *fault_addr = va; 1459 return SIGSEGV; 1460 } 1461 DITOREG(val, MIPSInst_FD(ir)); 1462 break; 1463 1464 case sdxc1_op: 1465 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1466 xcp->regs[MIPSInst_FT(ir)]); 1467 1468 MIPS_FPU_EMU_INC_STATS(stores); 1469 DIFROMREG(val, MIPSInst_FS(ir)); 1470 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1471 MIPS_FPU_EMU_INC_STATS(errors); 1472 *fault_addr = va; 1473 return SIGBUS; 1474 } 1475 if (__put_user(val, va)) { 1476 MIPS_FPU_EMU_INC_STATS(errors); 1477 *fault_addr = va; 1478 return SIGSEGV; 1479 } 1480 break; 1481 1482 case madd_d_op: 1483 handler = fpemu_dp_madd; 1484 goto dcoptop; 1485 case msub_d_op: 1486 handler = fpemu_dp_msub; 1487 goto dcoptop; 1488 case nmadd_d_op: 1489 handler = fpemu_dp_nmadd; 1490 goto dcoptop; 1491 case nmsub_d_op: 1492 handler = fpemu_dp_nmsub; 1493 goto dcoptop; 1494 1495 dcoptop: 1496 DPFROMREG(fr, MIPSInst_FR(ir)); 1497 DPFROMREG(fs, MIPSInst_FS(ir)); 1498 DPFROMREG(ft, MIPSInst_FT(ir)); 1499 fd = (*handler) (fr, fs, ft); 1500 DPTOREG(fd, MIPSInst_FD(ir)); 1501 goto copcsr; 1502 1503 default: 1504 return SIGILL; 1505 } 1506 break; 1507 } 1508 1509 case 0x7: /* 7 */ 1510 if (MIPSInst_FUNC(ir) != pfetch_op) { 1511 return SIGILL; 1512 } 1513 /* ignore prefx operation */ 1514 break; 1515 1516 default: 1517 return SIGILL; 1518 } 1519 1520 return 0; 1521 } 1522 #endif 1523 1524 1525 1526 /* 1527 * Emulate a single COP1 arithmetic instruction. 1528 */ 1529 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1530 mips_instruction ir) 1531 { 1532 int rfmt; /* resulting format */ 1533 unsigned rcsr = 0; /* resulting csr */ 1534 unsigned cond; 1535 union { 1536 ieee754dp d; 1537 ieee754sp s; 1538 int w; 1539 #ifdef __mips64 1540 s64 l; 1541 #endif 1542 } rv; /* resulting value */ 1543 1544 MIPS_FPU_EMU_INC_STATS(cp1ops); 1545 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 1546 case s_fmt:{ /* 0 */ 1547 union { 1548 ieee754sp(*b) (ieee754sp, ieee754sp); 1549 ieee754sp(*u) (ieee754sp); 1550 } handler; 1551 1552 switch (MIPSInst_FUNC(ir)) { 1553 /* binary ops */ 1554 case fadd_op: 1555 handler.b = ieee754sp_add; 1556 goto scopbop; 1557 case fsub_op: 1558 handler.b = ieee754sp_sub; 1559 goto scopbop; 1560 case fmul_op: 1561 handler.b = ieee754sp_mul; 1562 goto scopbop; 1563 case fdiv_op: 1564 handler.b = ieee754sp_div; 1565 goto scopbop; 1566 1567 /* unary ops */ 1568 #if __mips >= 2 || defined(__mips64) 1569 case fsqrt_op: 1570 handler.u = ieee754sp_sqrt; 1571 goto scopuop; 1572 #endif 1573 #if __mips >= 4 && __mips != 32 1574 case frsqrt_op: 1575 handler.u = fpemu_sp_rsqrt; 1576 goto scopuop; 1577 case frecip_op: 1578 handler.u = fpemu_sp_recip; 1579 goto scopuop; 1580 #endif 1581 #if __mips >= 4 1582 case fmovc_op: 1583 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1584 if (((ctx->fcr31 & cond) != 0) != 1585 ((MIPSInst_FT(ir) & 1) != 0)) 1586 return 0; 1587 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1588 break; 1589 case fmovz_op: 1590 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1591 return 0; 1592 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1593 break; 1594 case fmovn_op: 1595 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1596 return 0; 1597 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1598 break; 1599 #endif 1600 case fabs_op: 1601 handler.u = ieee754sp_abs; 1602 goto scopuop; 1603 case fneg_op: 1604 handler.u = ieee754sp_neg; 1605 goto scopuop; 1606 case fmov_op: 1607 /* an easy one */ 1608 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1609 goto copcsr; 1610 1611 /* binary op on handler */ 1612 scopbop: 1613 { 1614 ieee754sp fs, ft; 1615 1616 SPFROMREG(fs, MIPSInst_FS(ir)); 1617 SPFROMREG(ft, MIPSInst_FT(ir)); 1618 1619 rv.s = (*handler.b) (fs, ft); 1620 goto copcsr; 1621 } 1622 scopuop: 1623 { 1624 ieee754sp fs; 1625 1626 SPFROMREG(fs, MIPSInst_FS(ir)); 1627 rv.s = (*handler.u) (fs); 1628 goto copcsr; 1629 } 1630 copcsr: 1631 if (ieee754_cxtest(IEEE754_INEXACT)) 1632 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1633 if (ieee754_cxtest(IEEE754_UNDERFLOW)) 1634 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1635 if (ieee754_cxtest(IEEE754_OVERFLOW)) 1636 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1637 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) 1638 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1639 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 1640 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1641 break; 1642 1643 /* unary conv ops */ 1644 case fcvts_op: 1645 return SIGILL; /* not defined */ 1646 case fcvtd_op:{ 1647 ieee754sp fs; 1648 1649 SPFROMREG(fs, MIPSInst_FS(ir)); 1650 rv.d = ieee754dp_fsp(fs); 1651 rfmt = d_fmt; 1652 goto copcsr; 1653 } 1654 case fcvtw_op:{ 1655 ieee754sp fs; 1656 1657 SPFROMREG(fs, MIPSInst_FS(ir)); 1658 rv.w = ieee754sp_tint(fs); 1659 rfmt = w_fmt; 1660 goto copcsr; 1661 } 1662 1663 #if __mips >= 2 || defined(__mips64) 1664 case fround_op: 1665 case ftrunc_op: 1666 case fceil_op: 1667 case ffloor_op:{ 1668 unsigned int oldrm = ieee754_csr.rm; 1669 ieee754sp fs; 1670 1671 SPFROMREG(fs, MIPSInst_FS(ir)); 1672 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1673 rv.w = ieee754sp_tint(fs); 1674 ieee754_csr.rm = oldrm; 1675 rfmt = w_fmt; 1676 goto copcsr; 1677 } 1678 #endif /* __mips >= 2 */ 1679 1680 #if defined(__mips64) 1681 case fcvtl_op:{ 1682 ieee754sp fs; 1683 1684 SPFROMREG(fs, MIPSInst_FS(ir)); 1685 rv.l = ieee754sp_tlong(fs); 1686 rfmt = l_fmt; 1687 goto copcsr; 1688 } 1689 1690 case froundl_op: 1691 case ftruncl_op: 1692 case fceill_op: 1693 case ffloorl_op:{ 1694 unsigned int oldrm = ieee754_csr.rm; 1695 ieee754sp fs; 1696 1697 SPFROMREG(fs, MIPSInst_FS(ir)); 1698 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1699 rv.l = ieee754sp_tlong(fs); 1700 ieee754_csr.rm = oldrm; 1701 rfmt = l_fmt; 1702 goto copcsr; 1703 } 1704 #endif /* defined(__mips64) */ 1705 1706 default: 1707 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1708 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1709 ieee754sp fs, ft; 1710 1711 SPFROMREG(fs, MIPSInst_FS(ir)); 1712 SPFROMREG(ft, MIPSInst_FT(ir)); 1713 rv.w = ieee754sp_cmp(fs, ft, 1714 cmptab[cmpop & 0x7], cmpop & 0x8); 1715 rfmt = -1; 1716 if ((cmpop & 0x8) && ieee754_cxtest 1717 (IEEE754_INVALID_OPERATION)) 1718 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1719 else 1720 goto copcsr; 1721 1722 } 1723 else { 1724 return SIGILL; 1725 } 1726 break; 1727 } 1728 break; 1729 } 1730 1731 case d_fmt:{ 1732 union { 1733 ieee754dp(*b) (ieee754dp, ieee754dp); 1734 ieee754dp(*u) (ieee754dp); 1735 } handler; 1736 1737 switch (MIPSInst_FUNC(ir)) { 1738 /* binary ops */ 1739 case fadd_op: 1740 handler.b = ieee754dp_add; 1741 goto dcopbop; 1742 case fsub_op: 1743 handler.b = ieee754dp_sub; 1744 goto dcopbop; 1745 case fmul_op: 1746 handler.b = ieee754dp_mul; 1747 goto dcopbop; 1748 case fdiv_op: 1749 handler.b = ieee754dp_div; 1750 goto dcopbop; 1751 1752 /* unary ops */ 1753 #if __mips >= 2 || defined(__mips64) 1754 case fsqrt_op: 1755 handler.u = ieee754dp_sqrt; 1756 goto dcopuop; 1757 #endif 1758 #if __mips >= 4 && __mips != 32 1759 case frsqrt_op: 1760 handler.u = fpemu_dp_rsqrt; 1761 goto dcopuop; 1762 case frecip_op: 1763 handler.u = fpemu_dp_recip; 1764 goto dcopuop; 1765 #endif 1766 #if __mips >= 4 1767 case fmovc_op: 1768 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1769 if (((ctx->fcr31 & cond) != 0) != 1770 ((MIPSInst_FT(ir) & 1) != 0)) 1771 return 0; 1772 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1773 break; 1774 case fmovz_op: 1775 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1776 return 0; 1777 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1778 break; 1779 case fmovn_op: 1780 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1781 return 0; 1782 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1783 break; 1784 #endif 1785 case fabs_op: 1786 handler.u = ieee754dp_abs; 1787 goto dcopuop; 1788 1789 case fneg_op: 1790 handler.u = ieee754dp_neg; 1791 goto dcopuop; 1792 1793 case fmov_op: 1794 /* an easy one */ 1795 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1796 goto copcsr; 1797 1798 /* binary op on handler */ 1799 dcopbop:{ 1800 ieee754dp fs, ft; 1801 1802 DPFROMREG(fs, MIPSInst_FS(ir)); 1803 DPFROMREG(ft, MIPSInst_FT(ir)); 1804 1805 rv.d = (*handler.b) (fs, ft); 1806 goto copcsr; 1807 } 1808 dcopuop:{ 1809 ieee754dp fs; 1810 1811 DPFROMREG(fs, MIPSInst_FS(ir)); 1812 rv.d = (*handler.u) (fs); 1813 goto copcsr; 1814 } 1815 1816 /* unary conv ops */ 1817 case fcvts_op:{ 1818 ieee754dp fs; 1819 1820 DPFROMREG(fs, MIPSInst_FS(ir)); 1821 rv.s = ieee754sp_fdp(fs); 1822 rfmt = s_fmt; 1823 goto copcsr; 1824 } 1825 case fcvtd_op: 1826 return SIGILL; /* not defined */ 1827 1828 case fcvtw_op:{ 1829 ieee754dp fs; 1830 1831 DPFROMREG(fs, MIPSInst_FS(ir)); 1832 rv.w = ieee754dp_tint(fs); /* wrong */ 1833 rfmt = w_fmt; 1834 goto copcsr; 1835 } 1836 1837 #if __mips >= 2 || defined(__mips64) 1838 case fround_op: 1839 case ftrunc_op: 1840 case fceil_op: 1841 case ffloor_op:{ 1842 unsigned int oldrm = ieee754_csr.rm; 1843 ieee754dp fs; 1844 1845 DPFROMREG(fs, MIPSInst_FS(ir)); 1846 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1847 rv.w = ieee754dp_tint(fs); 1848 ieee754_csr.rm = oldrm; 1849 rfmt = w_fmt; 1850 goto copcsr; 1851 } 1852 #endif 1853 1854 #if defined(__mips64) 1855 case fcvtl_op:{ 1856 ieee754dp fs; 1857 1858 DPFROMREG(fs, MIPSInst_FS(ir)); 1859 rv.l = ieee754dp_tlong(fs); 1860 rfmt = l_fmt; 1861 goto copcsr; 1862 } 1863 1864 case froundl_op: 1865 case ftruncl_op: 1866 case fceill_op: 1867 case ffloorl_op:{ 1868 unsigned int oldrm = ieee754_csr.rm; 1869 ieee754dp fs; 1870 1871 DPFROMREG(fs, MIPSInst_FS(ir)); 1872 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1873 rv.l = ieee754dp_tlong(fs); 1874 ieee754_csr.rm = oldrm; 1875 rfmt = l_fmt; 1876 goto copcsr; 1877 } 1878 #endif /* __mips >= 3 */ 1879 1880 default: 1881 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1882 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1883 ieee754dp fs, ft; 1884 1885 DPFROMREG(fs, MIPSInst_FS(ir)); 1886 DPFROMREG(ft, MIPSInst_FT(ir)); 1887 rv.w = ieee754dp_cmp(fs, ft, 1888 cmptab[cmpop & 0x7], cmpop & 0x8); 1889 rfmt = -1; 1890 if ((cmpop & 0x8) 1891 && 1892 ieee754_cxtest 1893 (IEEE754_INVALID_OPERATION)) 1894 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1895 else 1896 goto copcsr; 1897 1898 } 1899 else { 1900 return SIGILL; 1901 } 1902 break; 1903 } 1904 break; 1905 } 1906 1907 case w_fmt:{ 1908 ieee754sp fs; 1909 1910 switch (MIPSInst_FUNC(ir)) { 1911 case fcvts_op: 1912 /* convert word to single precision real */ 1913 SPFROMREG(fs, MIPSInst_FS(ir)); 1914 rv.s = ieee754sp_fint(fs.bits); 1915 rfmt = s_fmt; 1916 goto copcsr; 1917 case fcvtd_op: 1918 /* convert word to double precision real */ 1919 SPFROMREG(fs, MIPSInst_FS(ir)); 1920 rv.d = ieee754dp_fint(fs.bits); 1921 rfmt = d_fmt; 1922 goto copcsr; 1923 default: 1924 return SIGILL; 1925 } 1926 break; 1927 } 1928 1929 #if defined(__mips64) 1930 case l_fmt:{ 1931 switch (MIPSInst_FUNC(ir)) { 1932 case fcvts_op: 1933 /* convert long to single precision real */ 1934 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]); 1935 rfmt = s_fmt; 1936 goto copcsr; 1937 case fcvtd_op: 1938 /* convert long to double precision real */ 1939 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]); 1940 rfmt = d_fmt; 1941 goto copcsr; 1942 default: 1943 return SIGILL; 1944 } 1945 break; 1946 } 1947 #endif 1948 1949 default: 1950 return SIGILL; 1951 } 1952 1953 /* 1954 * Update the fpu CSR register for this operation. 1955 * If an exception is required, generate a tidy SIGFPE exception, 1956 * without updating the result register. 1957 * Note: cause exception bits do not accumulate, they are rewritten 1958 * for each op; only the flag/sticky bits accumulate. 1959 */ 1960 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1961 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1962 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */ 1963 return SIGFPE; 1964 } 1965 1966 /* 1967 * Now we can safely write the result back to the register file. 1968 */ 1969 switch (rfmt) { 1970 case -1:{ 1971 #if __mips >= 4 1972 cond = fpucondbit[MIPSInst_FD(ir) >> 2]; 1973 #else 1974 cond = FPU_CSR_COND; 1975 #endif 1976 if (rv.w) 1977 ctx->fcr31 |= cond; 1978 else 1979 ctx->fcr31 &= ~cond; 1980 break; 1981 } 1982 case d_fmt: 1983 DPTOREG(rv.d, MIPSInst_FD(ir)); 1984 break; 1985 case s_fmt: 1986 SPTOREG(rv.s, MIPSInst_FD(ir)); 1987 break; 1988 case w_fmt: 1989 SITOREG(rv.w, MIPSInst_FD(ir)); 1990 break; 1991 #if defined(__mips64) 1992 case l_fmt: 1993 DITOREG(rv.l, MIPSInst_FD(ir)); 1994 break; 1995 #endif 1996 default: 1997 return SIGILL; 1998 } 1999 2000 return 0; 2001 } 2002 2003 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 2004 int has_fpu, void *__user *fault_addr) 2005 { 2006 unsigned long oldepc, prevepc; 2007 struct mm_decoded_insn dec_insn; 2008 u16 instr[4]; 2009 u16 *instr_ptr; 2010 int sig = 0; 2011 2012 oldepc = xcp->cp0_epc; 2013 do { 2014 prevepc = xcp->cp0_epc; 2015 2016 if (get_isa16_mode(prevepc) && cpu_has_mmips) { 2017 /* 2018 * Get next 2 microMIPS instructions and convert them 2019 * into 32-bit instructions. 2020 */ 2021 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 2022 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 2023 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 2024 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 2025 MIPS_FPU_EMU_INC_STATS(errors); 2026 return SIGBUS; 2027 } 2028 instr_ptr = instr; 2029 2030 /* Get first instruction. */ 2031 if (mm_insn_16bit(*instr_ptr)) { 2032 /* Duplicate the half-word. */ 2033 dec_insn.insn = (*instr_ptr << 16) | 2034 (*instr_ptr); 2035 /* 16-bit instruction. */ 2036 dec_insn.pc_inc = 2; 2037 instr_ptr += 1; 2038 } else { 2039 dec_insn.insn = (*instr_ptr << 16) | 2040 *(instr_ptr+1); 2041 /* 32-bit instruction. */ 2042 dec_insn.pc_inc = 4; 2043 instr_ptr += 2; 2044 } 2045 /* Get second instruction. */ 2046 if (mm_insn_16bit(*instr_ptr)) { 2047 /* Duplicate the half-word. */ 2048 dec_insn.next_insn = (*instr_ptr << 16) | 2049 (*instr_ptr); 2050 /* 16-bit instruction. */ 2051 dec_insn.next_pc_inc = 2; 2052 } else { 2053 dec_insn.next_insn = (*instr_ptr << 16) | 2054 *(instr_ptr+1); 2055 /* 32-bit instruction. */ 2056 dec_insn.next_pc_inc = 4; 2057 } 2058 dec_insn.micro_mips_mode = 1; 2059 } else { 2060 if ((get_user(dec_insn.insn, 2061 (mips_instruction __user *) xcp->cp0_epc)) || 2062 (get_user(dec_insn.next_insn, 2063 (mips_instruction __user *)(xcp->cp0_epc+4)))) { 2064 MIPS_FPU_EMU_INC_STATS(errors); 2065 return SIGBUS; 2066 } 2067 dec_insn.pc_inc = 4; 2068 dec_insn.next_pc_inc = 4; 2069 dec_insn.micro_mips_mode = 0; 2070 } 2071 2072 if ((dec_insn.insn == 0) || 2073 ((dec_insn.pc_inc == 2) && 2074 ((dec_insn.insn & 0xffff) == MM_NOP16))) 2075 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 2076 else { 2077 /* 2078 * The 'ieee754_csr' is an alias of 2079 * ctx->fcr31. No need to copy ctx->fcr31 to 2080 * ieee754_csr. But ieee754_csr.rm is ieee 2081 * library modes. (not mips rounding mode) 2082 */ 2083 /* convert to ieee library modes */ 2084 ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; 2085 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 2086 /* revert to mips rounding mode */ 2087 ieee754_csr.rm = mips_rm[ieee754_csr.rm]; 2088 } 2089 2090 if (has_fpu) 2091 break; 2092 if (sig) 2093 break; 2094 2095 cond_resched(); 2096 } while (xcp->cp0_epc > prevepc); 2097 2098 /* SIGILL indicates a non-fpu instruction */ 2099 if (sig == SIGILL && xcp->cp0_epc != oldepc) 2100 /* but if epc has advanced, then ignore it */ 2101 sig = 0; 2102 2103 return sig; 2104 } 2105 2106 #ifdef CONFIG_DEBUG_FS 2107 2108 static int fpuemu_stat_get(void *data, u64 *val) 2109 { 2110 int cpu; 2111 unsigned long sum = 0; 2112 for_each_online_cpu(cpu) { 2113 struct mips_fpu_emulator_stats *ps; 2114 local_t *pv; 2115 ps = &per_cpu(fpuemustats, cpu); 2116 pv = (void *)ps + (unsigned long)data; 2117 sum += local_read(pv); 2118 } 2119 *val = sum; 2120 return 0; 2121 } 2122 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n"); 2123 2124 extern struct dentry *mips_debugfs_dir; 2125 static int __init debugfs_fpuemu(void) 2126 { 2127 struct dentry *d, *dir; 2128 2129 if (!mips_debugfs_dir) 2130 return -ENODEV; 2131 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); 2132 if (!dir) 2133 return -ENOMEM; 2134 2135 #define FPU_STAT_CREATE(M) \ 2136 do { \ 2137 d = debugfs_create_file(#M , S_IRUGO, dir, \ 2138 (void *)offsetof(struct mips_fpu_emulator_stats, M), \ 2139 &fops_fpuemu_stat); \ 2140 if (!d) \ 2141 return -ENOMEM; \ 2142 } while (0) 2143 2144 FPU_STAT_CREATE(emulated); 2145 FPU_STAT_CREATE(loads); 2146 FPU_STAT_CREATE(stores); 2147 FPU_STAT_CREATE(cp1ops); 2148 FPU_STAT_CREATE(cp1xops); 2149 FPU_STAT_CREATE(errors); 2150 2151 return 0; 2152 } 2153 __initcall(debugfs_fpuemu); 2154 #endif 2155