1 /* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 22 * 23 * A complete emulator for MIPS coprocessor 1 instructions. This is 24 * required for #float(switch) or #float(trap), where it catches all 25 * COP1 instructions via the "CoProcessor Unusable" exception. 26 * 27 * More surprisingly it is also required for #float(ieee), to help out 28 * the hardware FPU at the boundaries of the IEEE-754 representation 29 * (denormalised values, infinities, underflow, etc). It is made 30 * quite nasty because emulation of some non-COP1 instructions is 31 * required, e.g. in branch delay slots. 32 * 33 * Note if you know that you won't have an FPU, then you'll get much 34 * better performance by compiling with -msoft-float! 35 */ 36 #include <linux/sched.h> 37 #include <linux/debugfs.h> 38 #include <linux/percpu-defs.h> 39 #include <linux/perf_event.h> 40 41 #include <asm/branch.h> 42 #include <asm/inst.h> 43 #include <asm/ptrace.h> 44 #include <asm/signal.h> 45 #include <linux/uaccess.h> 46 47 #include <asm/cpu-info.h> 48 #include <asm/processor.h> 49 #include <asm/fpu_emulator.h> 50 #include <asm/fpu.h> 51 #include <asm/mips-r2-to-r6-emul.h> 52 53 #include "ieee754.h" 54 55 /* Function which emulates a floating point instruction. */ 56 57 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 58 mips_instruction); 59 60 static int fpux_emu(struct pt_regs *, 61 struct mips_fpu_struct *, mips_instruction, void __user **); 62 63 /* Control registers */ 64 65 #define FPCREG_RID 0 /* $0 = revision id */ 66 #define FPCREG_FCCR 25 /* $25 = fccr */ 67 #define FPCREG_FEXR 26 /* $26 = fexr */ 68 #define FPCREG_FENR 28 /* $28 = fenr */ 69 #define FPCREG_CSR 31 /* $31 = csr */ 70 71 /* convert condition code register number to csr bit */ 72 const unsigned int fpucondbit[8] = { 73 FPU_CSR_COND, 74 FPU_CSR_COND1, 75 FPU_CSR_COND2, 76 FPU_CSR_COND3, 77 FPU_CSR_COND4, 78 FPU_CSR_COND5, 79 FPU_CSR_COND6, 80 FPU_CSR_COND7 81 }; 82 83 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 84 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 85 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 86 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 87 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 88 89 /* 90 * This functions translates a 32-bit microMIPS instruction 91 * into a 32-bit MIPS32 instruction. Returns 0 on success 92 * and SIGILL otherwise. 93 */ 94 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 95 { 96 union mips_instruction insn = *insn_ptr; 97 union mips_instruction mips32_insn = insn; 98 int func, fmt, op; 99 100 switch (insn.mm_i_format.opcode) { 101 case mm_ldc132_op: 102 mips32_insn.mm_i_format.opcode = ldc1_op; 103 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 104 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 105 break; 106 case mm_lwc132_op: 107 mips32_insn.mm_i_format.opcode = lwc1_op; 108 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 109 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 110 break; 111 case mm_sdc132_op: 112 mips32_insn.mm_i_format.opcode = sdc1_op; 113 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 114 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 115 break; 116 case mm_swc132_op: 117 mips32_insn.mm_i_format.opcode = swc1_op; 118 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 119 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 120 break; 121 case mm_pool32i_op: 122 /* NOTE: offset is << by 1 if in microMIPS mode. */ 123 if ((insn.mm_i_format.rt == mm_bc1f_op) || 124 (insn.mm_i_format.rt == mm_bc1t_op)) { 125 mips32_insn.fb_format.opcode = cop1_op; 126 mips32_insn.fb_format.bc = bc_op; 127 mips32_insn.fb_format.flag = 128 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 129 } else 130 return SIGILL; 131 break; 132 case mm_pool32f_op: 133 switch (insn.mm_fp0_format.func) { 134 case mm_32f_01_op: 135 case mm_32f_11_op: 136 case mm_32f_02_op: 137 case mm_32f_12_op: 138 case mm_32f_41_op: 139 case mm_32f_51_op: 140 case mm_32f_42_op: 141 case mm_32f_52_op: 142 op = insn.mm_fp0_format.func; 143 if (op == mm_32f_01_op) 144 func = madd_s_op; 145 else if (op == mm_32f_11_op) 146 func = madd_d_op; 147 else if (op == mm_32f_02_op) 148 func = nmadd_s_op; 149 else if (op == mm_32f_12_op) 150 func = nmadd_d_op; 151 else if (op == mm_32f_41_op) 152 func = msub_s_op; 153 else if (op == mm_32f_51_op) 154 func = msub_d_op; 155 else if (op == mm_32f_42_op) 156 func = nmsub_s_op; 157 else 158 func = nmsub_d_op; 159 mips32_insn.fp6_format.opcode = cop1x_op; 160 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 161 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 162 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 163 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 164 mips32_insn.fp6_format.func = func; 165 break; 166 case mm_32f_10_op: 167 func = -1; /* Invalid */ 168 op = insn.mm_fp5_format.op & 0x7; 169 if (op == mm_ldxc1_op) 170 func = ldxc1_op; 171 else if (op == mm_sdxc1_op) 172 func = sdxc1_op; 173 else if (op == mm_lwxc1_op) 174 func = lwxc1_op; 175 else if (op == mm_swxc1_op) 176 func = swxc1_op; 177 178 if (func != -1) { 179 mips32_insn.r_format.opcode = cop1x_op; 180 mips32_insn.r_format.rs = 181 insn.mm_fp5_format.base; 182 mips32_insn.r_format.rt = 183 insn.mm_fp5_format.index; 184 mips32_insn.r_format.rd = 0; 185 mips32_insn.r_format.re = insn.mm_fp5_format.fd; 186 mips32_insn.r_format.func = func; 187 } else 188 return SIGILL; 189 break; 190 case mm_32f_40_op: 191 op = -1; /* Invalid */ 192 if (insn.mm_fp2_format.op == mm_fmovt_op) 193 op = 1; 194 else if (insn.mm_fp2_format.op == mm_fmovf_op) 195 op = 0; 196 if (op != -1) { 197 mips32_insn.fp0_format.opcode = cop1_op; 198 mips32_insn.fp0_format.fmt = 199 sdps_format[insn.mm_fp2_format.fmt]; 200 mips32_insn.fp0_format.ft = 201 (insn.mm_fp2_format.cc<<2) + op; 202 mips32_insn.fp0_format.fs = 203 insn.mm_fp2_format.fs; 204 mips32_insn.fp0_format.fd = 205 insn.mm_fp2_format.fd; 206 mips32_insn.fp0_format.func = fmovc_op; 207 } else 208 return SIGILL; 209 break; 210 case mm_32f_60_op: 211 func = -1; /* Invalid */ 212 if (insn.mm_fp0_format.op == mm_fadd_op) 213 func = fadd_op; 214 else if (insn.mm_fp0_format.op == mm_fsub_op) 215 func = fsub_op; 216 else if (insn.mm_fp0_format.op == mm_fmul_op) 217 func = fmul_op; 218 else if (insn.mm_fp0_format.op == mm_fdiv_op) 219 func = fdiv_op; 220 if (func != -1) { 221 mips32_insn.fp0_format.opcode = cop1_op; 222 mips32_insn.fp0_format.fmt = 223 sdps_format[insn.mm_fp0_format.fmt]; 224 mips32_insn.fp0_format.ft = 225 insn.mm_fp0_format.ft; 226 mips32_insn.fp0_format.fs = 227 insn.mm_fp0_format.fs; 228 mips32_insn.fp0_format.fd = 229 insn.mm_fp0_format.fd; 230 mips32_insn.fp0_format.func = func; 231 } else 232 return SIGILL; 233 break; 234 case mm_32f_70_op: 235 func = -1; /* Invalid */ 236 if (insn.mm_fp0_format.op == mm_fmovn_op) 237 func = fmovn_op; 238 else if (insn.mm_fp0_format.op == mm_fmovz_op) 239 func = fmovz_op; 240 if (func != -1) { 241 mips32_insn.fp0_format.opcode = cop1_op; 242 mips32_insn.fp0_format.fmt = 243 sdps_format[insn.mm_fp0_format.fmt]; 244 mips32_insn.fp0_format.ft = 245 insn.mm_fp0_format.ft; 246 mips32_insn.fp0_format.fs = 247 insn.mm_fp0_format.fs; 248 mips32_insn.fp0_format.fd = 249 insn.mm_fp0_format.fd; 250 mips32_insn.fp0_format.func = func; 251 } else 252 return SIGILL; 253 break; 254 case mm_32f_73_op: /* POOL32FXF */ 255 switch (insn.mm_fp1_format.op) { 256 case mm_movf0_op: 257 case mm_movf1_op: 258 case mm_movt0_op: 259 case mm_movt1_op: 260 if ((insn.mm_fp1_format.op & 0x7f) == 261 mm_movf0_op) 262 op = 0; 263 else 264 op = 1; 265 mips32_insn.r_format.opcode = spec_op; 266 mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 267 mips32_insn.r_format.rt = 268 (insn.mm_fp4_format.cc << 2) + op; 269 mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 270 mips32_insn.r_format.re = 0; 271 mips32_insn.r_format.func = movc_op; 272 break; 273 case mm_fcvtd0_op: 274 case mm_fcvtd1_op: 275 case mm_fcvts0_op: 276 case mm_fcvts1_op: 277 if ((insn.mm_fp1_format.op & 0x7f) == 278 mm_fcvtd0_op) { 279 func = fcvtd_op; 280 fmt = swl_format[insn.mm_fp3_format.fmt]; 281 } else { 282 func = fcvts_op; 283 fmt = dwl_format[insn.mm_fp3_format.fmt]; 284 } 285 mips32_insn.fp0_format.opcode = cop1_op; 286 mips32_insn.fp0_format.fmt = fmt; 287 mips32_insn.fp0_format.ft = 0; 288 mips32_insn.fp0_format.fs = 289 insn.mm_fp3_format.fs; 290 mips32_insn.fp0_format.fd = 291 insn.mm_fp3_format.rt; 292 mips32_insn.fp0_format.func = func; 293 break; 294 case mm_fmov0_op: 295 case mm_fmov1_op: 296 case mm_fabs0_op: 297 case mm_fabs1_op: 298 case mm_fneg0_op: 299 case mm_fneg1_op: 300 if ((insn.mm_fp1_format.op & 0x7f) == 301 mm_fmov0_op) 302 func = fmov_op; 303 else if ((insn.mm_fp1_format.op & 0x7f) == 304 mm_fabs0_op) 305 func = fabs_op; 306 else 307 func = fneg_op; 308 mips32_insn.fp0_format.opcode = cop1_op; 309 mips32_insn.fp0_format.fmt = 310 sdps_format[insn.mm_fp3_format.fmt]; 311 mips32_insn.fp0_format.ft = 0; 312 mips32_insn.fp0_format.fs = 313 insn.mm_fp3_format.fs; 314 mips32_insn.fp0_format.fd = 315 insn.mm_fp3_format.rt; 316 mips32_insn.fp0_format.func = func; 317 break; 318 case mm_ffloorl_op: 319 case mm_ffloorw_op: 320 case mm_fceill_op: 321 case mm_fceilw_op: 322 case mm_ftruncl_op: 323 case mm_ftruncw_op: 324 case mm_froundl_op: 325 case mm_froundw_op: 326 case mm_fcvtl_op: 327 case mm_fcvtw_op: 328 if (insn.mm_fp1_format.op == mm_ffloorl_op) 329 func = ffloorl_op; 330 else if (insn.mm_fp1_format.op == mm_ffloorw_op) 331 func = ffloor_op; 332 else if (insn.mm_fp1_format.op == mm_fceill_op) 333 func = fceill_op; 334 else if (insn.mm_fp1_format.op == mm_fceilw_op) 335 func = fceil_op; 336 else if (insn.mm_fp1_format.op == mm_ftruncl_op) 337 func = ftruncl_op; 338 else if (insn.mm_fp1_format.op == mm_ftruncw_op) 339 func = ftrunc_op; 340 else if (insn.mm_fp1_format.op == mm_froundl_op) 341 func = froundl_op; 342 else if (insn.mm_fp1_format.op == mm_froundw_op) 343 func = fround_op; 344 else if (insn.mm_fp1_format.op == mm_fcvtl_op) 345 func = fcvtl_op; 346 else 347 func = fcvtw_op; 348 mips32_insn.fp0_format.opcode = cop1_op; 349 mips32_insn.fp0_format.fmt = 350 sd_format[insn.mm_fp1_format.fmt]; 351 mips32_insn.fp0_format.ft = 0; 352 mips32_insn.fp0_format.fs = 353 insn.mm_fp1_format.fs; 354 mips32_insn.fp0_format.fd = 355 insn.mm_fp1_format.rt; 356 mips32_insn.fp0_format.func = func; 357 break; 358 case mm_frsqrt_op: 359 case mm_fsqrt_op: 360 case mm_frecip_op: 361 if (insn.mm_fp1_format.op == mm_frsqrt_op) 362 func = frsqrt_op; 363 else if (insn.mm_fp1_format.op == mm_fsqrt_op) 364 func = fsqrt_op; 365 else 366 func = frecip_op; 367 mips32_insn.fp0_format.opcode = cop1_op; 368 mips32_insn.fp0_format.fmt = 369 sdps_format[insn.mm_fp1_format.fmt]; 370 mips32_insn.fp0_format.ft = 0; 371 mips32_insn.fp0_format.fs = 372 insn.mm_fp1_format.fs; 373 mips32_insn.fp0_format.fd = 374 insn.mm_fp1_format.rt; 375 mips32_insn.fp0_format.func = func; 376 break; 377 case mm_mfc1_op: 378 case mm_mtc1_op: 379 case mm_cfc1_op: 380 case mm_ctc1_op: 381 case mm_mfhc1_op: 382 case mm_mthc1_op: 383 if (insn.mm_fp1_format.op == mm_mfc1_op) 384 op = mfc_op; 385 else if (insn.mm_fp1_format.op == mm_mtc1_op) 386 op = mtc_op; 387 else if (insn.mm_fp1_format.op == mm_cfc1_op) 388 op = cfc_op; 389 else if (insn.mm_fp1_format.op == mm_ctc1_op) 390 op = ctc_op; 391 else if (insn.mm_fp1_format.op == mm_mfhc1_op) 392 op = mfhc_op; 393 else 394 op = mthc_op; 395 mips32_insn.fp1_format.opcode = cop1_op; 396 mips32_insn.fp1_format.op = op; 397 mips32_insn.fp1_format.rt = 398 insn.mm_fp1_format.rt; 399 mips32_insn.fp1_format.fs = 400 insn.mm_fp1_format.fs; 401 mips32_insn.fp1_format.fd = 0; 402 mips32_insn.fp1_format.func = 0; 403 break; 404 default: 405 return SIGILL; 406 } 407 break; 408 case mm_32f_74_op: /* c.cond.fmt */ 409 mips32_insn.fp0_format.opcode = cop1_op; 410 mips32_insn.fp0_format.fmt = 411 sdps_format[insn.mm_fp4_format.fmt]; 412 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 413 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 414 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 415 mips32_insn.fp0_format.func = 416 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 417 break; 418 default: 419 return SIGILL; 420 } 421 break; 422 default: 423 return SIGILL; 424 } 425 426 *insn_ptr = mips32_insn; 427 return 0; 428 } 429 430 /* 431 * Redundant with logic already in kernel/branch.c, 432 * embedded in compute_return_epc. At some point, 433 * a single subroutine should be used across both 434 * modules. 435 */ 436 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 437 unsigned long *contpc) 438 { 439 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 440 unsigned int fcr31; 441 unsigned int bit = 0; 442 unsigned int bit0; 443 union fpureg *fpr; 444 445 switch (insn.i_format.opcode) { 446 case spec_op: 447 switch (insn.r_format.func) { 448 case jalr_op: 449 if (insn.r_format.rd != 0) { 450 regs->regs[insn.r_format.rd] = 451 regs->cp0_epc + dec_insn.pc_inc + 452 dec_insn.next_pc_inc; 453 } 454 /* fall through */ 455 case jr_op: 456 /* For R6, JR already emulated in jalr_op */ 457 if (NO_R6EMU && insn.r_format.func == jr_op) 458 break; 459 *contpc = regs->regs[insn.r_format.rs]; 460 return 1; 461 } 462 break; 463 case bcond_op: 464 switch (insn.i_format.rt) { 465 case bltzal_op: 466 case bltzall_op: 467 if (NO_R6EMU && (insn.i_format.rs || 468 insn.i_format.rt == bltzall_op)) 469 break; 470 471 regs->regs[31] = regs->cp0_epc + 472 dec_insn.pc_inc + 473 dec_insn.next_pc_inc; 474 /* fall through */ 475 case bltzl_op: 476 if (NO_R6EMU) 477 break; 478 /* fall through */ 479 case bltz_op: 480 if ((long)regs->regs[insn.i_format.rs] < 0) 481 *contpc = regs->cp0_epc + 482 dec_insn.pc_inc + 483 (insn.i_format.simmediate << 2); 484 else 485 *contpc = regs->cp0_epc + 486 dec_insn.pc_inc + 487 dec_insn.next_pc_inc; 488 return 1; 489 case bgezal_op: 490 case bgezall_op: 491 if (NO_R6EMU && (insn.i_format.rs || 492 insn.i_format.rt == bgezall_op)) 493 break; 494 495 regs->regs[31] = regs->cp0_epc + 496 dec_insn.pc_inc + 497 dec_insn.next_pc_inc; 498 /* fall through */ 499 case bgezl_op: 500 if (NO_R6EMU) 501 break; 502 /* fall through */ 503 case bgez_op: 504 if ((long)regs->regs[insn.i_format.rs] >= 0) 505 *contpc = regs->cp0_epc + 506 dec_insn.pc_inc + 507 (insn.i_format.simmediate << 2); 508 else 509 *contpc = regs->cp0_epc + 510 dec_insn.pc_inc + 511 dec_insn.next_pc_inc; 512 return 1; 513 } 514 break; 515 case jalx_op: 516 set_isa16_mode(bit); 517 /* fall through */ 518 case jal_op: 519 regs->regs[31] = regs->cp0_epc + 520 dec_insn.pc_inc + 521 dec_insn.next_pc_inc; 522 /* fall through */ 523 case j_op: 524 *contpc = regs->cp0_epc + dec_insn.pc_inc; 525 *contpc >>= 28; 526 *contpc <<= 28; 527 *contpc |= (insn.j_format.target << 2); 528 /* Set microMIPS mode bit: XOR for jalx. */ 529 *contpc ^= bit; 530 return 1; 531 case beql_op: 532 if (NO_R6EMU) 533 break; 534 /* fall through */ 535 case beq_op: 536 if (regs->regs[insn.i_format.rs] == 537 regs->regs[insn.i_format.rt]) 538 *contpc = regs->cp0_epc + 539 dec_insn.pc_inc + 540 (insn.i_format.simmediate << 2); 541 else 542 *contpc = regs->cp0_epc + 543 dec_insn.pc_inc + 544 dec_insn.next_pc_inc; 545 return 1; 546 case bnel_op: 547 if (NO_R6EMU) 548 break; 549 /* fall through */ 550 case bne_op: 551 if (regs->regs[insn.i_format.rs] != 552 regs->regs[insn.i_format.rt]) 553 *contpc = regs->cp0_epc + 554 dec_insn.pc_inc + 555 (insn.i_format.simmediate << 2); 556 else 557 *contpc = regs->cp0_epc + 558 dec_insn.pc_inc + 559 dec_insn.next_pc_inc; 560 return 1; 561 case blezl_op: 562 if (!insn.i_format.rt && NO_R6EMU) 563 break; 564 /* fall through */ 565 case blez_op: 566 567 /* 568 * Compact branches for R6 for the 569 * blez and blezl opcodes. 570 * BLEZ | rs = 0 | rt != 0 == BLEZALC 571 * BLEZ | rs = rt != 0 == BGEZALC 572 * BLEZ | rs != 0 | rt != 0 == BGEUC 573 * BLEZL | rs = 0 | rt != 0 == BLEZC 574 * BLEZL | rs = rt != 0 == BGEZC 575 * BLEZL | rs != 0 | rt != 0 == BGEC 576 * 577 * For real BLEZ{,L}, rt is always 0. 578 */ 579 if (cpu_has_mips_r6 && insn.i_format.rt) { 580 if ((insn.i_format.opcode == blez_op) && 581 ((!insn.i_format.rs && insn.i_format.rt) || 582 (insn.i_format.rs == insn.i_format.rt))) 583 regs->regs[31] = regs->cp0_epc + 584 dec_insn.pc_inc; 585 *contpc = regs->cp0_epc + dec_insn.pc_inc + 586 dec_insn.next_pc_inc; 587 588 return 1; 589 } 590 if ((long)regs->regs[insn.i_format.rs] <= 0) 591 *contpc = regs->cp0_epc + 592 dec_insn.pc_inc + 593 (insn.i_format.simmediate << 2); 594 else 595 *contpc = regs->cp0_epc + 596 dec_insn.pc_inc + 597 dec_insn.next_pc_inc; 598 return 1; 599 case bgtzl_op: 600 if (!insn.i_format.rt && NO_R6EMU) 601 break; 602 /* fall through */ 603 case bgtz_op: 604 /* 605 * Compact branches for R6 for the 606 * bgtz and bgtzl opcodes. 607 * BGTZ | rs = 0 | rt != 0 == BGTZALC 608 * BGTZ | rs = rt != 0 == BLTZALC 609 * BGTZ | rs != 0 | rt != 0 == BLTUC 610 * BGTZL | rs = 0 | rt != 0 == BGTZC 611 * BGTZL | rs = rt != 0 == BLTZC 612 * BGTZL | rs != 0 | rt != 0 == BLTC 613 * 614 * *ZALC varint for BGTZ &&& rt != 0 615 * For real GTZ{,L}, rt is always 0. 616 */ 617 if (cpu_has_mips_r6 && insn.i_format.rt) { 618 if ((insn.i_format.opcode == blez_op) && 619 ((!insn.i_format.rs && insn.i_format.rt) || 620 (insn.i_format.rs == insn.i_format.rt))) 621 regs->regs[31] = regs->cp0_epc + 622 dec_insn.pc_inc; 623 *contpc = regs->cp0_epc + dec_insn.pc_inc + 624 dec_insn.next_pc_inc; 625 626 return 1; 627 } 628 629 if ((long)regs->regs[insn.i_format.rs] > 0) 630 *contpc = regs->cp0_epc + 631 dec_insn.pc_inc + 632 (insn.i_format.simmediate << 2); 633 else 634 *contpc = regs->cp0_epc + 635 dec_insn.pc_inc + 636 dec_insn.next_pc_inc; 637 return 1; 638 case pop10_op: 639 case pop30_op: 640 if (!cpu_has_mips_r6) 641 break; 642 if (insn.i_format.rt && !insn.i_format.rs) 643 regs->regs[31] = regs->cp0_epc + 4; 644 *contpc = regs->cp0_epc + dec_insn.pc_inc + 645 dec_insn.next_pc_inc; 646 647 return 1; 648 #ifdef CONFIG_CPU_CAVIUM_OCTEON 649 case lwc2_op: /* This is bbit0 on Octeon */ 650 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 651 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 652 else 653 *contpc = regs->cp0_epc + 8; 654 return 1; 655 case ldc2_op: /* This is bbit032 on Octeon */ 656 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 657 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 658 else 659 *contpc = regs->cp0_epc + 8; 660 return 1; 661 case swc2_op: /* This is bbit1 on Octeon */ 662 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 663 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 664 else 665 *contpc = regs->cp0_epc + 8; 666 return 1; 667 case sdc2_op: /* This is bbit132 on Octeon */ 668 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 669 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 670 else 671 *contpc = regs->cp0_epc + 8; 672 return 1; 673 #else 674 case bc6_op: 675 /* 676 * Only valid for MIPS R6 but we can still end up 677 * here from a broken userland so just tell emulator 678 * this is not a branch and let it break later on. 679 */ 680 if (!cpu_has_mips_r6) 681 break; 682 *contpc = regs->cp0_epc + dec_insn.pc_inc + 683 dec_insn.next_pc_inc; 684 685 return 1; 686 case balc6_op: 687 if (!cpu_has_mips_r6) 688 break; 689 regs->regs[31] = regs->cp0_epc + 4; 690 *contpc = regs->cp0_epc + dec_insn.pc_inc + 691 dec_insn.next_pc_inc; 692 693 return 1; 694 case pop66_op: 695 if (!cpu_has_mips_r6) 696 break; 697 *contpc = regs->cp0_epc + dec_insn.pc_inc + 698 dec_insn.next_pc_inc; 699 700 return 1; 701 case pop76_op: 702 if (!cpu_has_mips_r6) 703 break; 704 if (!insn.i_format.rs) 705 regs->regs[31] = regs->cp0_epc + 4; 706 *contpc = regs->cp0_epc + dec_insn.pc_inc + 707 dec_insn.next_pc_inc; 708 709 return 1; 710 #endif 711 case cop0_op: 712 case cop1_op: 713 /* Need to check for R6 bc1nez and bc1eqz branches */ 714 if (cpu_has_mips_r6 && 715 ((insn.i_format.rs == bc1eqz_op) || 716 (insn.i_format.rs == bc1nez_op))) { 717 bit = 0; 718 fpr = ¤t->thread.fpu.fpr[insn.i_format.rt]; 719 bit0 = get_fpr32(fpr, 0) & 0x1; 720 switch (insn.i_format.rs) { 721 case bc1eqz_op: 722 bit = bit0 == 0; 723 break; 724 case bc1nez_op: 725 bit = bit0 != 0; 726 break; 727 } 728 if (bit) 729 *contpc = regs->cp0_epc + 730 dec_insn.pc_inc + 731 (insn.i_format.simmediate << 2); 732 else 733 *contpc = regs->cp0_epc + 734 dec_insn.pc_inc + 735 dec_insn.next_pc_inc; 736 737 return 1; 738 } 739 /* R2/R6 compatible cop1 instruction */ 740 /* fall through */ 741 case cop2_op: 742 case cop1x_op: 743 if (insn.i_format.rs == bc_op) { 744 preempt_disable(); 745 if (is_fpu_owner()) 746 fcr31 = read_32bit_cp1_register(CP1_STATUS); 747 else 748 fcr31 = current->thread.fpu.fcr31; 749 preempt_enable(); 750 751 bit = (insn.i_format.rt >> 2); 752 bit += (bit != 0); 753 bit += 23; 754 switch (insn.i_format.rt & 3) { 755 case 0: /* bc1f */ 756 case 2: /* bc1fl */ 757 if (~fcr31 & (1 << bit)) 758 *contpc = regs->cp0_epc + 759 dec_insn.pc_inc + 760 (insn.i_format.simmediate << 2); 761 else 762 *contpc = regs->cp0_epc + 763 dec_insn.pc_inc + 764 dec_insn.next_pc_inc; 765 return 1; 766 case 1: /* bc1t */ 767 case 3: /* bc1tl */ 768 if (fcr31 & (1 << bit)) 769 *contpc = regs->cp0_epc + 770 dec_insn.pc_inc + 771 (insn.i_format.simmediate << 2); 772 else 773 *contpc = regs->cp0_epc + 774 dec_insn.pc_inc + 775 dec_insn.next_pc_inc; 776 return 1; 777 } 778 } 779 break; 780 } 781 return 0; 782 } 783 784 /* 785 * In the Linux kernel, we support selection of FPR format on the 786 * basis of the Status.FR bit. If an FPU is not present, the FR bit 787 * is hardwired to zero, which would imply a 32-bit FPU even for 788 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 789 * FPU emu is slow and bulky and optimizing this function offers fairly 790 * sizeable benefits so we try to be clever and make this function return 791 * a constant whenever possible, that is on 64-bit kernels without O32 792 * compatibility enabled and on 32-bit without 64-bit FPU support. 793 */ 794 static inline int cop1_64bit(struct pt_regs *xcp) 795 { 796 if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32)) 797 return 1; 798 else if (IS_ENABLED(CONFIG_32BIT) && 799 !IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT)) 800 return 0; 801 802 return !test_thread_flag(TIF_32BIT_FPREGS); 803 } 804 805 static inline bool hybrid_fprs(void) 806 { 807 return test_thread_flag(TIF_HYBRID_FPREGS); 808 } 809 810 #define SIFROMREG(si, x) \ 811 do { \ 812 if (cop1_64bit(xcp) && !hybrid_fprs()) \ 813 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ 814 else \ 815 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 816 } while (0) 817 818 #define SITOREG(si, x) \ 819 do { \ 820 if (cop1_64bit(xcp) && !hybrid_fprs()) { \ 821 unsigned int i; \ 822 set_fpr32(&ctx->fpr[x], 0, si); \ 823 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 824 set_fpr32(&ctx->fpr[x], i, 0); \ 825 } else { \ 826 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 827 } \ 828 } while (0) 829 830 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) 831 832 #define SITOHREG(si, x) \ 833 do { \ 834 unsigned int i; \ 835 set_fpr32(&ctx->fpr[x], 1, si); \ 836 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 837 set_fpr32(&ctx->fpr[x], i, 0); \ 838 } while (0) 839 840 #define DIFROMREG(di, x) \ 841 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) ^ 1)], 0)) 842 843 #define DITOREG(di, x) \ 844 do { \ 845 unsigned int fpr, i; \ 846 fpr = (x) & ~(cop1_64bit(xcp) ^ 1); \ 847 set_fpr64(&ctx->fpr[fpr], 0, di); \ 848 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 849 set_fpr64(&ctx->fpr[fpr], i, 0); \ 850 } while (0) 851 852 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 853 #define SPTOREG(sp, x) SITOREG((sp).bits, x) 854 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 855 #define DPTOREG(dp, x) DITOREG((dp).bits, x) 856 857 /* 858 * Emulate a CFC1 instruction. 859 */ 860 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 861 mips_instruction ir) 862 { 863 u32 fcr31 = ctx->fcr31; 864 u32 value = 0; 865 866 switch (MIPSInst_RD(ir)) { 867 case FPCREG_CSR: 868 value = fcr31; 869 pr_debug("%p gpr[%d]<-csr=%08x\n", 870 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 871 break; 872 873 case FPCREG_FENR: 874 if (!cpu_has_mips_r) 875 break; 876 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 877 MIPS_FENR_FS; 878 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM); 879 pr_debug("%p gpr[%d]<-enr=%08x\n", 880 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 881 break; 882 883 case FPCREG_FEXR: 884 if (!cpu_has_mips_r) 885 break; 886 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 887 pr_debug("%p gpr[%d]<-exr=%08x\n", 888 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 889 break; 890 891 case FPCREG_FCCR: 892 if (!cpu_has_mips_r) 893 break; 894 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 895 MIPS_FCCR_COND0; 896 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 897 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0); 898 pr_debug("%p gpr[%d]<-ccr=%08x\n", 899 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 900 break; 901 902 case FPCREG_RID: 903 value = boot_cpu_data.fpu_id; 904 break; 905 906 default: 907 break; 908 } 909 910 if (MIPSInst_RT(ir)) 911 xcp->regs[MIPSInst_RT(ir)] = value; 912 } 913 914 /* 915 * Emulate a CTC1 instruction. 916 */ 917 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 918 mips_instruction ir) 919 { 920 u32 fcr31 = ctx->fcr31; 921 u32 value; 922 u32 mask; 923 924 if (MIPSInst_RT(ir) == 0) 925 value = 0; 926 else 927 value = xcp->regs[MIPSInst_RT(ir)]; 928 929 switch (MIPSInst_RD(ir)) { 930 case FPCREG_CSR: 931 pr_debug("%p gpr[%d]->csr=%08x\n", 932 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 933 934 /* Preserve read-only bits. */ 935 mask = boot_cpu_data.fpu_msk31; 936 fcr31 = (value & ~mask) | (fcr31 & mask); 937 break; 938 939 case FPCREG_FENR: 940 if (!cpu_has_mips_r) 941 break; 942 pr_debug("%p gpr[%d]->enr=%08x\n", 943 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 944 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM); 945 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 946 FPU_CSR_FS; 947 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM); 948 break; 949 950 case FPCREG_FEXR: 951 if (!cpu_has_mips_r) 952 break; 953 pr_debug("%p gpr[%d]->exr=%08x\n", 954 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 955 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S); 956 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 957 break; 958 959 case FPCREG_FCCR: 960 if (!cpu_has_mips_r) 961 break; 962 pr_debug("%p gpr[%d]->ccr=%08x\n", 963 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 964 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND); 965 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 966 FPU_CSR_COND; 967 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 968 FPU_CSR_CONDX; 969 break; 970 971 default: 972 break; 973 } 974 975 ctx->fcr31 = fcr31; 976 } 977 978 /* 979 * Emulate the single floating point instruction pointed at by EPC. 980 * Two instructions if the instruction is in a branch delay slot. 981 */ 982 983 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 984 struct mm_decoded_insn dec_insn, void __user **fault_addr) 985 { 986 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 987 unsigned int cond, cbit, bit0; 988 mips_instruction ir; 989 int likely, pc_inc; 990 union fpureg *fpr; 991 u32 __user *wva; 992 u64 __user *dva; 993 u32 wval; 994 u64 dval; 995 int sig; 996 997 /* 998 * These are giving gcc a gentle hint about what to expect in 999 * dec_inst in order to do better optimization. 1000 */ 1001 if (!cpu_has_mmips && dec_insn.micro_mips_mode) 1002 unreachable(); 1003 1004 /* XXX NEC Vr54xx bug workaround */ 1005 if (delay_slot(xcp)) { 1006 if (dec_insn.micro_mips_mode) { 1007 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 1008 clear_delay_slot(xcp); 1009 } else { 1010 if (!isBranchInstr(xcp, dec_insn, &contpc)) 1011 clear_delay_slot(xcp); 1012 } 1013 } 1014 1015 if (delay_slot(xcp)) { 1016 /* 1017 * The instruction to be emulated is in a branch delay slot 1018 * which means that we have to emulate the branch instruction 1019 * BEFORE we do the cop1 instruction. 1020 * 1021 * This branch could be a COP1 branch, but in that case we 1022 * would have had a trap for that instruction, and would not 1023 * come through this route. 1024 * 1025 * Linux MIPS branch emulator operates on context, updating the 1026 * cp0_epc. 1027 */ 1028 ir = dec_insn.next_insn; /* process delay slot instr */ 1029 pc_inc = dec_insn.next_pc_inc; 1030 } else { 1031 ir = dec_insn.insn; /* process current instr */ 1032 pc_inc = dec_insn.pc_inc; 1033 } 1034 1035 /* 1036 * Since microMIPS FPU instructios are a subset of MIPS32 FPU 1037 * instructions, we want to convert microMIPS FPU instructions 1038 * into MIPS32 instructions so that we could reuse all of the 1039 * FPU emulation code. 1040 * 1041 * NOTE: We cannot do this for branch instructions since they 1042 * are not a subset. Example: Cannot emulate a 16-bit 1043 * aligned target address with a MIPS32 instruction. 1044 */ 1045 if (dec_insn.micro_mips_mode) { 1046 /* 1047 * If next instruction is a 16-bit instruction, then it 1048 * it cannot be a FPU instruction. This could happen 1049 * since we can be called for non-FPU instructions. 1050 */ 1051 if ((pc_inc == 2) || 1052 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 1053 == SIGILL)) 1054 return SIGILL; 1055 } 1056 1057 emul: 1058 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 1059 MIPS_FPU_EMU_INC_STATS(emulated); 1060 switch (MIPSInst_OPCODE(ir)) { 1061 case ldc1_op: 1062 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1063 MIPSInst_SIMM(ir)); 1064 MIPS_FPU_EMU_INC_STATS(loads); 1065 1066 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { 1067 MIPS_FPU_EMU_INC_STATS(errors); 1068 *fault_addr = dva; 1069 return SIGBUS; 1070 } 1071 if (__get_user(dval, dva)) { 1072 MIPS_FPU_EMU_INC_STATS(errors); 1073 *fault_addr = dva; 1074 return SIGSEGV; 1075 } 1076 DITOREG(dval, MIPSInst_RT(ir)); 1077 break; 1078 1079 case sdc1_op: 1080 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1081 MIPSInst_SIMM(ir)); 1082 MIPS_FPU_EMU_INC_STATS(stores); 1083 DIFROMREG(dval, MIPSInst_RT(ir)); 1084 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { 1085 MIPS_FPU_EMU_INC_STATS(errors); 1086 *fault_addr = dva; 1087 return SIGBUS; 1088 } 1089 if (__put_user(dval, dva)) { 1090 MIPS_FPU_EMU_INC_STATS(errors); 1091 *fault_addr = dva; 1092 return SIGSEGV; 1093 } 1094 break; 1095 1096 case lwc1_op: 1097 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1098 MIPSInst_SIMM(ir)); 1099 MIPS_FPU_EMU_INC_STATS(loads); 1100 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { 1101 MIPS_FPU_EMU_INC_STATS(errors); 1102 *fault_addr = wva; 1103 return SIGBUS; 1104 } 1105 if (__get_user(wval, wva)) { 1106 MIPS_FPU_EMU_INC_STATS(errors); 1107 *fault_addr = wva; 1108 return SIGSEGV; 1109 } 1110 SITOREG(wval, MIPSInst_RT(ir)); 1111 break; 1112 1113 case swc1_op: 1114 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1115 MIPSInst_SIMM(ir)); 1116 MIPS_FPU_EMU_INC_STATS(stores); 1117 SIFROMREG(wval, MIPSInst_RT(ir)); 1118 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { 1119 MIPS_FPU_EMU_INC_STATS(errors); 1120 *fault_addr = wva; 1121 return SIGBUS; 1122 } 1123 if (__put_user(wval, wva)) { 1124 MIPS_FPU_EMU_INC_STATS(errors); 1125 *fault_addr = wva; 1126 return SIGSEGV; 1127 } 1128 break; 1129 1130 case cop1_op: 1131 switch (MIPSInst_RS(ir)) { 1132 case dmfc_op: 1133 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1134 return SIGILL; 1135 1136 /* copregister fs -> gpr[rt] */ 1137 if (MIPSInst_RT(ir) != 0) { 1138 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1139 MIPSInst_RD(ir)); 1140 } 1141 break; 1142 1143 case dmtc_op: 1144 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1145 return SIGILL; 1146 1147 /* copregister fs <- rt */ 1148 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1149 break; 1150 1151 case mfhc_op: 1152 if (!cpu_has_mips_r2_r6) 1153 return SIGILL; 1154 1155 /* copregister rd -> gpr[rt] */ 1156 if (MIPSInst_RT(ir) != 0) { 1157 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 1158 MIPSInst_RD(ir)); 1159 } 1160 break; 1161 1162 case mthc_op: 1163 if (!cpu_has_mips_r2_r6) 1164 return SIGILL; 1165 1166 /* copregister rd <- gpr[rt] */ 1167 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1168 break; 1169 1170 case mfc_op: 1171 /* copregister rd -> gpr[rt] */ 1172 if (MIPSInst_RT(ir) != 0) { 1173 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1174 MIPSInst_RD(ir)); 1175 } 1176 break; 1177 1178 case mtc_op: 1179 /* copregister rd <- rt */ 1180 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1181 break; 1182 1183 case cfc_op: 1184 /* cop control register rd -> gpr[rt] */ 1185 cop1_cfc(xcp, ctx, ir); 1186 break; 1187 1188 case ctc_op: 1189 /* copregister rd <- rt */ 1190 cop1_ctc(xcp, ctx, ir); 1191 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1192 return SIGFPE; 1193 } 1194 break; 1195 1196 case bc1eqz_op: 1197 case bc1nez_op: 1198 if (!cpu_has_mips_r6 || delay_slot(xcp)) 1199 return SIGILL; 1200 1201 likely = 0; 1202 cond = 0; 1203 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)]; 1204 bit0 = get_fpr32(fpr, 0) & 0x1; 1205 switch (MIPSInst_RS(ir)) { 1206 case bc1eqz_op: 1207 MIPS_FPU_EMU_INC_STATS(bc1eqz); 1208 cond = bit0 == 0; 1209 break; 1210 case bc1nez_op: 1211 MIPS_FPU_EMU_INC_STATS(bc1nez); 1212 cond = bit0 != 0; 1213 break; 1214 } 1215 goto branch_common; 1216 1217 case bc_op: 1218 if (delay_slot(xcp)) 1219 return SIGILL; 1220 1221 if (cpu_has_mips_4_5_r) 1222 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 1223 else 1224 cbit = FPU_CSR_COND; 1225 cond = ctx->fcr31 & cbit; 1226 1227 likely = 0; 1228 switch (MIPSInst_RT(ir) & 3) { 1229 case bcfl_op: 1230 if (cpu_has_mips_2_3_4_5_r) 1231 likely = 1; 1232 /* fall through */ 1233 case bcf_op: 1234 cond = !cond; 1235 break; 1236 case bctl_op: 1237 if (cpu_has_mips_2_3_4_5_r) 1238 likely = 1; 1239 /* fall through */ 1240 case bct_op: 1241 break; 1242 } 1243 branch_common: 1244 MIPS_FPU_EMU_INC_STATS(branches); 1245 set_delay_slot(xcp); 1246 if (cond) { 1247 /* 1248 * Branch taken: emulate dslot instruction 1249 */ 1250 unsigned long bcpc; 1251 1252 /* 1253 * Remember EPC at the branch to point back 1254 * at so that any delay-slot instruction 1255 * signal is not silently ignored. 1256 */ 1257 bcpc = xcp->cp0_epc; 1258 xcp->cp0_epc += dec_insn.pc_inc; 1259 1260 contpc = MIPSInst_SIMM(ir); 1261 ir = dec_insn.next_insn; 1262 if (dec_insn.micro_mips_mode) { 1263 contpc = (xcp->cp0_epc + (contpc << 1)); 1264 1265 /* If 16-bit instruction, not FPU. */ 1266 if ((dec_insn.next_pc_inc == 2) || 1267 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 1268 1269 /* 1270 * Since this instruction will 1271 * be put on the stack with 1272 * 32-bit words, get around 1273 * this problem by putting a 1274 * NOP16 as the second one. 1275 */ 1276 if (dec_insn.next_pc_inc == 2) 1277 ir = (ir & (~0xffff)) | MM_NOP16; 1278 1279 /* 1280 * Single step the non-CP1 1281 * instruction in the dslot. 1282 */ 1283 sig = mips_dsemul(xcp, ir, 1284 bcpc, contpc); 1285 if (sig < 0) 1286 break; 1287 if (sig) 1288 xcp->cp0_epc = bcpc; 1289 /* 1290 * SIGILL forces out of 1291 * the emulation loop. 1292 */ 1293 return sig ? sig : SIGILL; 1294 } 1295 } else 1296 contpc = (xcp->cp0_epc + (contpc << 2)); 1297 1298 switch (MIPSInst_OPCODE(ir)) { 1299 case lwc1_op: 1300 case swc1_op: 1301 goto emul; 1302 1303 case ldc1_op: 1304 case sdc1_op: 1305 if (cpu_has_mips_2_3_4_5_r) 1306 goto emul; 1307 1308 goto bc_sigill; 1309 1310 case cop1_op: 1311 goto emul; 1312 1313 case cop1x_op: 1314 if (cpu_has_mips_4_5_64_r2_r6) 1315 /* its one of ours */ 1316 goto emul; 1317 1318 goto bc_sigill; 1319 1320 case spec_op: 1321 switch (MIPSInst_FUNC(ir)) { 1322 case movc_op: 1323 if (cpu_has_mips_4_5_r) 1324 goto emul; 1325 1326 goto bc_sigill; 1327 } 1328 break; 1329 1330 bc_sigill: 1331 xcp->cp0_epc = bcpc; 1332 return SIGILL; 1333 } 1334 1335 /* 1336 * Single step the non-cp1 1337 * instruction in the dslot 1338 */ 1339 sig = mips_dsemul(xcp, ir, bcpc, contpc); 1340 if (sig < 0) 1341 break; 1342 if (sig) 1343 xcp->cp0_epc = bcpc; 1344 /* SIGILL forces out of the emulation loop. */ 1345 return sig ? sig : SIGILL; 1346 } else if (likely) { /* branch not taken */ 1347 /* 1348 * branch likely nullifies 1349 * dslot if not taken 1350 */ 1351 xcp->cp0_epc += dec_insn.pc_inc; 1352 contpc += dec_insn.pc_inc; 1353 /* 1354 * else continue & execute 1355 * dslot as normal insn 1356 */ 1357 } 1358 break; 1359 1360 default: 1361 if (!(MIPSInst_RS(ir) & 0x10)) 1362 return SIGILL; 1363 1364 /* a real fpu computation instruction */ 1365 sig = fpu_emu(xcp, ctx, ir); 1366 if (sig) 1367 return sig; 1368 } 1369 break; 1370 1371 case cop1x_op: 1372 if (!cpu_has_mips_4_5_64_r2_r6) 1373 return SIGILL; 1374 1375 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1376 if (sig) 1377 return sig; 1378 break; 1379 1380 case spec_op: 1381 if (!cpu_has_mips_4_5_r) 1382 return SIGILL; 1383 1384 if (MIPSInst_FUNC(ir) != movc_op) 1385 return SIGILL; 1386 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 1387 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 1388 xcp->regs[MIPSInst_RD(ir)] = 1389 xcp->regs[MIPSInst_RS(ir)]; 1390 break; 1391 default: 1392 return SIGILL; 1393 } 1394 1395 /* we did it !! */ 1396 xcp->cp0_epc = contpc; 1397 clear_delay_slot(xcp); 1398 1399 return 0; 1400 } 1401 1402 /* 1403 * Conversion table from MIPS compare ops 48-63 1404 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 1405 */ 1406 static const unsigned char cmptab[8] = { 1407 0, /* cmp_0 (sig) cmp_sf */ 1408 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 1409 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 1410 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 1411 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 1412 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 1413 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 1414 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 1415 }; 1416 1417 static const unsigned char negative_cmptab[8] = { 1418 0, /* Reserved */ 1419 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ, 1420 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 1421 IEEE754_CLT | IEEE754_CGT, 1422 /* Reserved */ 1423 }; 1424 1425 1426 /* 1427 * Additional MIPS4 instructions 1428 */ 1429 1430 #define DEF3OP(name, p, f1, f2, f3) \ 1431 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ 1432 union ieee754##p s, union ieee754##p t) \ 1433 { \ 1434 struct _ieee754_csr ieee754_csr_save; \ 1435 s = f1(s, t); \ 1436 ieee754_csr_save = ieee754_csr; \ 1437 s = f2(s, r); \ 1438 ieee754_csr_save.cx |= ieee754_csr.cx; \ 1439 ieee754_csr_save.sx |= ieee754_csr.sx; \ 1440 s = f3(s); \ 1441 ieee754_csr.cx |= ieee754_csr_save.cx; \ 1442 ieee754_csr.sx |= ieee754_csr_save.sx; \ 1443 return s; \ 1444 } 1445 1446 static union ieee754dp fpemu_dp_recip(union ieee754dp d) 1447 { 1448 return ieee754dp_div(ieee754dp_one(0), d); 1449 } 1450 1451 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 1452 { 1453 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 1454 } 1455 1456 static union ieee754sp fpemu_sp_recip(union ieee754sp s) 1457 { 1458 return ieee754sp_div(ieee754sp_one(0), s); 1459 } 1460 1461 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 1462 { 1463 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 1464 } 1465 1466 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 1467 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 1468 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 1469 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 1470 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 1471 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 1472 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 1473 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 1474 1475 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1476 mips_instruction ir, void __user **fault_addr) 1477 { 1478 unsigned int rcsr = 0; /* resulting csr */ 1479 1480 MIPS_FPU_EMU_INC_STATS(cp1xops); 1481 1482 switch (MIPSInst_FMA_FFMT(ir)) { 1483 case s_fmt:{ /* 0 */ 1484 1485 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 1486 union ieee754sp fd, fr, fs, ft; 1487 u32 __user *va; 1488 u32 val; 1489 1490 switch (MIPSInst_FUNC(ir)) { 1491 case lwxc1_op: 1492 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1493 xcp->regs[MIPSInst_FT(ir)]); 1494 1495 MIPS_FPU_EMU_INC_STATS(loads); 1496 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1497 MIPS_FPU_EMU_INC_STATS(errors); 1498 *fault_addr = va; 1499 return SIGBUS; 1500 } 1501 if (__get_user(val, va)) { 1502 MIPS_FPU_EMU_INC_STATS(errors); 1503 *fault_addr = va; 1504 return SIGSEGV; 1505 } 1506 SITOREG(val, MIPSInst_FD(ir)); 1507 break; 1508 1509 case swxc1_op: 1510 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1511 xcp->regs[MIPSInst_FT(ir)]); 1512 1513 MIPS_FPU_EMU_INC_STATS(stores); 1514 1515 SIFROMREG(val, MIPSInst_FS(ir)); 1516 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1517 MIPS_FPU_EMU_INC_STATS(errors); 1518 *fault_addr = va; 1519 return SIGBUS; 1520 } 1521 if (put_user(val, va)) { 1522 MIPS_FPU_EMU_INC_STATS(errors); 1523 *fault_addr = va; 1524 return SIGSEGV; 1525 } 1526 break; 1527 1528 case madd_s_op: 1529 handler = fpemu_sp_madd; 1530 goto scoptop; 1531 case msub_s_op: 1532 handler = fpemu_sp_msub; 1533 goto scoptop; 1534 case nmadd_s_op: 1535 handler = fpemu_sp_nmadd; 1536 goto scoptop; 1537 case nmsub_s_op: 1538 handler = fpemu_sp_nmsub; 1539 goto scoptop; 1540 1541 scoptop: 1542 SPFROMREG(fr, MIPSInst_FR(ir)); 1543 SPFROMREG(fs, MIPSInst_FS(ir)); 1544 SPFROMREG(ft, MIPSInst_FT(ir)); 1545 fd = (*handler) (fr, fs, ft); 1546 SPTOREG(fd, MIPSInst_FD(ir)); 1547 1548 copcsr: 1549 if (ieee754_cxtest(IEEE754_INEXACT)) { 1550 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1551 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1552 } 1553 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1554 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1555 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1556 } 1557 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1558 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1559 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1560 } 1561 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1562 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1563 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1564 } 1565 1566 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1567 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1568 /*printk ("SIGFPE: FPU csr = %08x\n", 1569 ctx->fcr31); */ 1570 return SIGFPE; 1571 } 1572 1573 break; 1574 1575 default: 1576 return SIGILL; 1577 } 1578 break; 1579 } 1580 1581 case d_fmt:{ /* 1 */ 1582 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 1583 union ieee754dp fd, fr, fs, ft; 1584 u64 __user *va; 1585 u64 val; 1586 1587 switch (MIPSInst_FUNC(ir)) { 1588 case ldxc1_op: 1589 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1590 xcp->regs[MIPSInst_FT(ir)]); 1591 1592 MIPS_FPU_EMU_INC_STATS(loads); 1593 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1594 MIPS_FPU_EMU_INC_STATS(errors); 1595 *fault_addr = va; 1596 return SIGBUS; 1597 } 1598 if (__get_user(val, va)) { 1599 MIPS_FPU_EMU_INC_STATS(errors); 1600 *fault_addr = va; 1601 return SIGSEGV; 1602 } 1603 DITOREG(val, MIPSInst_FD(ir)); 1604 break; 1605 1606 case sdxc1_op: 1607 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1608 xcp->regs[MIPSInst_FT(ir)]); 1609 1610 MIPS_FPU_EMU_INC_STATS(stores); 1611 DIFROMREG(val, MIPSInst_FS(ir)); 1612 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1613 MIPS_FPU_EMU_INC_STATS(errors); 1614 *fault_addr = va; 1615 return SIGBUS; 1616 } 1617 if (__put_user(val, va)) { 1618 MIPS_FPU_EMU_INC_STATS(errors); 1619 *fault_addr = va; 1620 return SIGSEGV; 1621 } 1622 break; 1623 1624 case madd_d_op: 1625 handler = fpemu_dp_madd; 1626 goto dcoptop; 1627 case msub_d_op: 1628 handler = fpemu_dp_msub; 1629 goto dcoptop; 1630 case nmadd_d_op: 1631 handler = fpemu_dp_nmadd; 1632 goto dcoptop; 1633 case nmsub_d_op: 1634 handler = fpemu_dp_nmsub; 1635 goto dcoptop; 1636 1637 dcoptop: 1638 DPFROMREG(fr, MIPSInst_FR(ir)); 1639 DPFROMREG(fs, MIPSInst_FS(ir)); 1640 DPFROMREG(ft, MIPSInst_FT(ir)); 1641 fd = (*handler) (fr, fs, ft); 1642 DPTOREG(fd, MIPSInst_FD(ir)); 1643 goto copcsr; 1644 1645 default: 1646 return SIGILL; 1647 } 1648 break; 1649 } 1650 1651 case 0x3: 1652 if (MIPSInst_FUNC(ir) != pfetch_op) 1653 return SIGILL; 1654 1655 /* ignore prefx operation */ 1656 break; 1657 1658 default: 1659 return SIGILL; 1660 } 1661 1662 return 0; 1663 } 1664 1665 1666 1667 /* 1668 * Emulate a single COP1 arithmetic instruction. 1669 */ 1670 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1671 mips_instruction ir) 1672 { 1673 int rfmt; /* resulting format */ 1674 unsigned int rcsr = 0; /* resulting csr */ 1675 unsigned int oldrm; 1676 unsigned int cbit; 1677 unsigned int cond; 1678 union { 1679 union ieee754dp d; 1680 union ieee754sp s; 1681 int w; 1682 s64 l; 1683 } rv; /* resulting value */ 1684 u64 bits; 1685 1686 MIPS_FPU_EMU_INC_STATS(cp1ops); 1687 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 1688 case s_fmt: { /* 0 */ 1689 union { 1690 union ieee754sp(*b) (union ieee754sp, union ieee754sp); 1691 union ieee754sp(*u) (union ieee754sp); 1692 } handler; 1693 union ieee754sp fd, fs, ft; 1694 1695 switch (MIPSInst_FUNC(ir)) { 1696 /* binary ops */ 1697 case fadd_op: 1698 MIPS_FPU_EMU_INC_STATS(add_s); 1699 handler.b = ieee754sp_add; 1700 goto scopbop; 1701 case fsub_op: 1702 MIPS_FPU_EMU_INC_STATS(sub_s); 1703 handler.b = ieee754sp_sub; 1704 goto scopbop; 1705 case fmul_op: 1706 MIPS_FPU_EMU_INC_STATS(mul_s); 1707 handler.b = ieee754sp_mul; 1708 goto scopbop; 1709 case fdiv_op: 1710 MIPS_FPU_EMU_INC_STATS(div_s); 1711 handler.b = ieee754sp_div; 1712 goto scopbop; 1713 1714 /* unary ops */ 1715 case fsqrt_op: 1716 if (!cpu_has_mips_2_3_4_5_r) 1717 return SIGILL; 1718 1719 MIPS_FPU_EMU_INC_STATS(sqrt_s); 1720 handler.u = ieee754sp_sqrt; 1721 goto scopuop; 1722 1723 /* 1724 * Note that on some MIPS IV implementations such as the 1725 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1726 * achieve full IEEE-754 accuracy - however this emulator does. 1727 */ 1728 case frsqrt_op: 1729 if (!cpu_has_mips_4_5_64_r2_r6) 1730 return SIGILL; 1731 1732 MIPS_FPU_EMU_INC_STATS(rsqrt_s); 1733 handler.u = fpemu_sp_rsqrt; 1734 goto scopuop; 1735 1736 case frecip_op: 1737 if (!cpu_has_mips_4_5_64_r2_r6) 1738 return SIGILL; 1739 1740 MIPS_FPU_EMU_INC_STATS(recip_s); 1741 handler.u = fpemu_sp_recip; 1742 goto scopuop; 1743 1744 case fmovc_op: 1745 if (!cpu_has_mips_4_5_r) 1746 return SIGILL; 1747 1748 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1749 if (((ctx->fcr31 & cond) != 0) != 1750 ((MIPSInst_FT(ir) & 1) != 0)) 1751 return 0; 1752 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1753 break; 1754 1755 case fmovz_op: 1756 if (!cpu_has_mips_4_5_r) 1757 return SIGILL; 1758 1759 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1760 return 0; 1761 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1762 break; 1763 1764 case fmovn_op: 1765 if (!cpu_has_mips_4_5_r) 1766 return SIGILL; 1767 1768 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1769 return 0; 1770 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1771 break; 1772 1773 case fseleqz_op: 1774 if (!cpu_has_mips_r6) 1775 return SIGILL; 1776 1777 MIPS_FPU_EMU_INC_STATS(seleqz_s); 1778 SPFROMREG(rv.s, MIPSInst_FT(ir)); 1779 if (rv.w & 0x1) 1780 rv.w = 0; 1781 else 1782 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1783 break; 1784 1785 case fselnez_op: 1786 if (!cpu_has_mips_r6) 1787 return SIGILL; 1788 1789 MIPS_FPU_EMU_INC_STATS(selnez_s); 1790 SPFROMREG(rv.s, MIPSInst_FT(ir)); 1791 if (rv.w & 0x1) 1792 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1793 else 1794 rv.w = 0; 1795 break; 1796 1797 case fmaddf_op: { 1798 union ieee754sp ft, fs, fd; 1799 1800 if (!cpu_has_mips_r6) 1801 return SIGILL; 1802 1803 MIPS_FPU_EMU_INC_STATS(maddf_s); 1804 SPFROMREG(ft, MIPSInst_FT(ir)); 1805 SPFROMREG(fs, MIPSInst_FS(ir)); 1806 SPFROMREG(fd, MIPSInst_FD(ir)); 1807 rv.s = ieee754sp_maddf(fd, fs, ft); 1808 goto copcsr; 1809 } 1810 1811 case fmsubf_op: { 1812 union ieee754sp ft, fs, fd; 1813 1814 if (!cpu_has_mips_r6) 1815 return SIGILL; 1816 1817 MIPS_FPU_EMU_INC_STATS(msubf_s); 1818 SPFROMREG(ft, MIPSInst_FT(ir)); 1819 SPFROMREG(fs, MIPSInst_FS(ir)); 1820 SPFROMREG(fd, MIPSInst_FD(ir)); 1821 rv.s = ieee754sp_msubf(fd, fs, ft); 1822 goto copcsr; 1823 } 1824 1825 case frint_op: { 1826 union ieee754sp fs; 1827 1828 if (!cpu_has_mips_r6) 1829 return SIGILL; 1830 1831 MIPS_FPU_EMU_INC_STATS(rint_s); 1832 SPFROMREG(fs, MIPSInst_FS(ir)); 1833 rv.s = ieee754sp_rint(fs); 1834 goto copcsr; 1835 } 1836 1837 case fclass_op: { 1838 union ieee754sp fs; 1839 1840 if (!cpu_has_mips_r6) 1841 return SIGILL; 1842 1843 MIPS_FPU_EMU_INC_STATS(class_s); 1844 SPFROMREG(fs, MIPSInst_FS(ir)); 1845 rv.w = ieee754sp_2008class(fs); 1846 rfmt = w_fmt; 1847 goto copcsr; 1848 } 1849 1850 case fmin_op: { 1851 union ieee754sp fs, ft; 1852 1853 if (!cpu_has_mips_r6) 1854 return SIGILL; 1855 1856 MIPS_FPU_EMU_INC_STATS(min_s); 1857 SPFROMREG(ft, MIPSInst_FT(ir)); 1858 SPFROMREG(fs, MIPSInst_FS(ir)); 1859 rv.s = ieee754sp_fmin(fs, ft); 1860 goto copcsr; 1861 } 1862 1863 case fmina_op: { 1864 union ieee754sp fs, ft; 1865 1866 if (!cpu_has_mips_r6) 1867 return SIGILL; 1868 1869 MIPS_FPU_EMU_INC_STATS(mina_s); 1870 SPFROMREG(ft, MIPSInst_FT(ir)); 1871 SPFROMREG(fs, MIPSInst_FS(ir)); 1872 rv.s = ieee754sp_fmina(fs, ft); 1873 goto copcsr; 1874 } 1875 1876 case fmax_op: { 1877 union ieee754sp fs, ft; 1878 1879 if (!cpu_has_mips_r6) 1880 return SIGILL; 1881 1882 MIPS_FPU_EMU_INC_STATS(max_s); 1883 SPFROMREG(ft, MIPSInst_FT(ir)); 1884 SPFROMREG(fs, MIPSInst_FS(ir)); 1885 rv.s = ieee754sp_fmax(fs, ft); 1886 goto copcsr; 1887 } 1888 1889 case fmaxa_op: { 1890 union ieee754sp fs, ft; 1891 1892 if (!cpu_has_mips_r6) 1893 return SIGILL; 1894 1895 MIPS_FPU_EMU_INC_STATS(maxa_s); 1896 SPFROMREG(ft, MIPSInst_FT(ir)); 1897 SPFROMREG(fs, MIPSInst_FS(ir)); 1898 rv.s = ieee754sp_fmaxa(fs, ft); 1899 goto copcsr; 1900 } 1901 1902 case fabs_op: 1903 MIPS_FPU_EMU_INC_STATS(abs_s); 1904 handler.u = ieee754sp_abs; 1905 goto scopuop; 1906 1907 case fneg_op: 1908 MIPS_FPU_EMU_INC_STATS(neg_s); 1909 handler.u = ieee754sp_neg; 1910 goto scopuop; 1911 1912 case fmov_op: 1913 /* an easy one */ 1914 MIPS_FPU_EMU_INC_STATS(mov_s); 1915 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1916 goto copcsr; 1917 1918 /* binary op on handler */ 1919 scopbop: 1920 SPFROMREG(fs, MIPSInst_FS(ir)); 1921 SPFROMREG(ft, MIPSInst_FT(ir)); 1922 1923 rv.s = (*handler.b) (fs, ft); 1924 goto copcsr; 1925 scopuop: 1926 SPFROMREG(fs, MIPSInst_FS(ir)); 1927 rv.s = (*handler.u) (fs); 1928 goto copcsr; 1929 copcsr: 1930 if (ieee754_cxtest(IEEE754_INEXACT)) { 1931 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1932 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1933 } 1934 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1935 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1936 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1937 } 1938 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1939 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1940 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1941 } 1942 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { 1943 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); 1944 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1945 } 1946 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1947 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1948 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1949 } 1950 break; 1951 1952 /* unary conv ops */ 1953 case fcvts_op: 1954 return SIGILL; /* not defined */ 1955 1956 case fcvtd_op: 1957 MIPS_FPU_EMU_INC_STATS(cvt_d_s); 1958 SPFROMREG(fs, MIPSInst_FS(ir)); 1959 rv.d = ieee754dp_fsp(fs); 1960 rfmt = d_fmt; 1961 goto copcsr; 1962 1963 case fcvtw_op: 1964 MIPS_FPU_EMU_INC_STATS(cvt_w_s); 1965 SPFROMREG(fs, MIPSInst_FS(ir)); 1966 rv.w = ieee754sp_tint(fs); 1967 rfmt = w_fmt; 1968 goto copcsr; 1969 1970 case fround_op: 1971 case ftrunc_op: 1972 case fceil_op: 1973 case ffloor_op: 1974 if (!cpu_has_mips_2_3_4_5_r) 1975 return SIGILL; 1976 1977 if (MIPSInst_FUNC(ir) == fceil_op) 1978 MIPS_FPU_EMU_INC_STATS(ceil_w_s); 1979 if (MIPSInst_FUNC(ir) == ffloor_op) 1980 MIPS_FPU_EMU_INC_STATS(floor_w_s); 1981 if (MIPSInst_FUNC(ir) == fround_op) 1982 MIPS_FPU_EMU_INC_STATS(round_w_s); 1983 if (MIPSInst_FUNC(ir) == ftrunc_op) 1984 MIPS_FPU_EMU_INC_STATS(trunc_w_s); 1985 1986 oldrm = ieee754_csr.rm; 1987 SPFROMREG(fs, MIPSInst_FS(ir)); 1988 ieee754_csr.rm = MIPSInst_FUNC(ir); 1989 rv.w = ieee754sp_tint(fs); 1990 ieee754_csr.rm = oldrm; 1991 rfmt = w_fmt; 1992 goto copcsr; 1993 1994 case fsel_op: 1995 if (!cpu_has_mips_r6) 1996 return SIGILL; 1997 1998 MIPS_FPU_EMU_INC_STATS(sel_s); 1999 SPFROMREG(fd, MIPSInst_FD(ir)); 2000 if (fd.bits & 0x1) 2001 SPFROMREG(rv.s, MIPSInst_FT(ir)); 2002 else 2003 SPFROMREG(rv.s, MIPSInst_FS(ir)); 2004 break; 2005 2006 case fcvtl_op: 2007 if (!cpu_has_mips_3_4_5_64_r2_r6) 2008 return SIGILL; 2009 2010 MIPS_FPU_EMU_INC_STATS(cvt_l_s); 2011 SPFROMREG(fs, MIPSInst_FS(ir)); 2012 rv.l = ieee754sp_tlong(fs); 2013 rfmt = l_fmt; 2014 goto copcsr; 2015 2016 case froundl_op: 2017 case ftruncl_op: 2018 case fceill_op: 2019 case ffloorl_op: 2020 if (!cpu_has_mips_3_4_5_64_r2_r6) 2021 return SIGILL; 2022 2023 if (MIPSInst_FUNC(ir) == fceill_op) 2024 MIPS_FPU_EMU_INC_STATS(ceil_l_s); 2025 if (MIPSInst_FUNC(ir) == ffloorl_op) 2026 MIPS_FPU_EMU_INC_STATS(floor_l_s); 2027 if (MIPSInst_FUNC(ir) == froundl_op) 2028 MIPS_FPU_EMU_INC_STATS(round_l_s); 2029 if (MIPSInst_FUNC(ir) == ftruncl_op) 2030 MIPS_FPU_EMU_INC_STATS(trunc_l_s); 2031 2032 oldrm = ieee754_csr.rm; 2033 SPFROMREG(fs, MIPSInst_FS(ir)); 2034 ieee754_csr.rm = MIPSInst_FUNC(ir); 2035 rv.l = ieee754sp_tlong(fs); 2036 ieee754_csr.rm = oldrm; 2037 rfmt = l_fmt; 2038 goto copcsr; 2039 2040 default: 2041 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { 2042 unsigned int cmpop; 2043 union ieee754sp fs, ft; 2044 2045 cmpop = MIPSInst_FUNC(ir) - fcmp_op; 2046 SPFROMREG(fs, MIPSInst_FS(ir)); 2047 SPFROMREG(ft, MIPSInst_FT(ir)); 2048 rv.w = ieee754sp_cmp(fs, ft, 2049 cmptab[cmpop & 0x7], cmpop & 0x8); 2050 rfmt = -1; 2051 if ((cmpop & 0x8) && ieee754_cxtest 2052 (IEEE754_INVALID_OPERATION)) 2053 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2054 else 2055 goto copcsr; 2056 2057 } else 2058 return SIGILL; 2059 break; 2060 } 2061 break; 2062 } 2063 2064 case d_fmt: { 2065 union ieee754dp fd, fs, ft; 2066 union { 2067 union ieee754dp(*b) (union ieee754dp, union ieee754dp); 2068 union ieee754dp(*u) (union ieee754dp); 2069 } handler; 2070 2071 switch (MIPSInst_FUNC(ir)) { 2072 /* binary ops */ 2073 case fadd_op: 2074 MIPS_FPU_EMU_INC_STATS(add_d); 2075 handler.b = ieee754dp_add; 2076 goto dcopbop; 2077 case fsub_op: 2078 MIPS_FPU_EMU_INC_STATS(sub_d); 2079 handler.b = ieee754dp_sub; 2080 goto dcopbop; 2081 case fmul_op: 2082 MIPS_FPU_EMU_INC_STATS(mul_d); 2083 handler.b = ieee754dp_mul; 2084 goto dcopbop; 2085 case fdiv_op: 2086 MIPS_FPU_EMU_INC_STATS(div_d); 2087 handler.b = ieee754dp_div; 2088 goto dcopbop; 2089 2090 /* unary ops */ 2091 case fsqrt_op: 2092 if (!cpu_has_mips_2_3_4_5_r) 2093 return SIGILL; 2094 2095 MIPS_FPU_EMU_INC_STATS(sqrt_d); 2096 handler.u = ieee754dp_sqrt; 2097 goto dcopuop; 2098 /* 2099 * Note that on some MIPS IV implementations such as the 2100 * R5000 and R8000 the FSQRT and FRECIP instructions do not 2101 * achieve full IEEE-754 accuracy - however this emulator does. 2102 */ 2103 case frsqrt_op: 2104 if (!cpu_has_mips_4_5_64_r2_r6) 2105 return SIGILL; 2106 2107 MIPS_FPU_EMU_INC_STATS(rsqrt_d); 2108 handler.u = fpemu_dp_rsqrt; 2109 goto dcopuop; 2110 case frecip_op: 2111 if (!cpu_has_mips_4_5_64_r2_r6) 2112 return SIGILL; 2113 2114 MIPS_FPU_EMU_INC_STATS(recip_d); 2115 handler.u = fpemu_dp_recip; 2116 goto dcopuop; 2117 case fmovc_op: 2118 if (!cpu_has_mips_4_5_r) 2119 return SIGILL; 2120 2121 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 2122 if (((ctx->fcr31 & cond) != 0) != 2123 ((MIPSInst_FT(ir) & 1) != 0)) 2124 return 0; 2125 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2126 break; 2127 case fmovz_op: 2128 if (!cpu_has_mips_4_5_r) 2129 return SIGILL; 2130 2131 if (xcp->regs[MIPSInst_FT(ir)] != 0) 2132 return 0; 2133 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2134 break; 2135 case fmovn_op: 2136 if (!cpu_has_mips_4_5_r) 2137 return SIGILL; 2138 2139 if (xcp->regs[MIPSInst_FT(ir)] == 0) 2140 return 0; 2141 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2142 break; 2143 2144 case fseleqz_op: 2145 if (!cpu_has_mips_r6) 2146 return SIGILL; 2147 2148 MIPS_FPU_EMU_INC_STATS(seleqz_d); 2149 DPFROMREG(rv.d, MIPSInst_FT(ir)); 2150 if (rv.l & 0x1) 2151 rv.l = 0; 2152 else 2153 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2154 break; 2155 2156 case fselnez_op: 2157 if (!cpu_has_mips_r6) 2158 return SIGILL; 2159 2160 MIPS_FPU_EMU_INC_STATS(selnez_d); 2161 DPFROMREG(rv.d, MIPSInst_FT(ir)); 2162 if (rv.l & 0x1) 2163 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2164 else 2165 rv.l = 0; 2166 break; 2167 2168 case fmaddf_op: { 2169 union ieee754dp ft, fs, fd; 2170 2171 if (!cpu_has_mips_r6) 2172 return SIGILL; 2173 2174 MIPS_FPU_EMU_INC_STATS(maddf_d); 2175 DPFROMREG(ft, MIPSInst_FT(ir)); 2176 DPFROMREG(fs, MIPSInst_FS(ir)); 2177 DPFROMREG(fd, MIPSInst_FD(ir)); 2178 rv.d = ieee754dp_maddf(fd, fs, ft); 2179 goto copcsr; 2180 } 2181 2182 case fmsubf_op: { 2183 union ieee754dp ft, fs, fd; 2184 2185 if (!cpu_has_mips_r6) 2186 return SIGILL; 2187 2188 MIPS_FPU_EMU_INC_STATS(msubf_d); 2189 DPFROMREG(ft, MIPSInst_FT(ir)); 2190 DPFROMREG(fs, MIPSInst_FS(ir)); 2191 DPFROMREG(fd, MIPSInst_FD(ir)); 2192 rv.d = ieee754dp_msubf(fd, fs, ft); 2193 goto copcsr; 2194 } 2195 2196 case frint_op: { 2197 union ieee754dp fs; 2198 2199 if (!cpu_has_mips_r6) 2200 return SIGILL; 2201 2202 MIPS_FPU_EMU_INC_STATS(rint_d); 2203 DPFROMREG(fs, MIPSInst_FS(ir)); 2204 rv.d = ieee754dp_rint(fs); 2205 goto copcsr; 2206 } 2207 2208 case fclass_op: { 2209 union ieee754dp fs; 2210 2211 if (!cpu_has_mips_r6) 2212 return SIGILL; 2213 2214 MIPS_FPU_EMU_INC_STATS(class_d); 2215 DPFROMREG(fs, MIPSInst_FS(ir)); 2216 rv.l = ieee754dp_2008class(fs); 2217 rfmt = l_fmt; 2218 goto copcsr; 2219 } 2220 2221 case fmin_op: { 2222 union ieee754dp fs, ft; 2223 2224 if (!cpu_has_mips_r6) 2225 return SIGILL; 2226 2227 MIPS_FPU_EMU_INC_STATS(min_d); 2228 DPFROMREG(ft, MIPSInst_FT(ir)); 2229 DPFROMREG(fs, MIPSInst_FS(ir)); 2230 rv.d = ieee754dp_fmin(fs, ft); 2231 goto copcsr; 2232 } 2233 2234 case fmina_op: { 2235 union ieee754dp fs, ft; 2236 2237 if (!cpu_has_mips_r6) 2238 return SIGILL; 2239 2240 MIPS_FPU_EMU_INC_STATS(mina_d); 2241 DPFROMREG(ft, MIPSInst_FT(ir)); 2242 DPFROMREG(fs, MIPSInst_FS(ir)); 2243 rv.d = ieee754dp_fmina(fs, ft); 2244 goto copcsr; 2245 } 2246 2247 case fmax_op: { 2248 union ieee754dp fs, ft; 2249 2250 if (!cpu_has_mips_r6) 2251 return SIGILL; 2252 2253 MIPS_FPU_EMU_INC_STATS(max_d); 2254 DPFROMREG(ft, MIPSInst_FT(ir)); 2255 DPFROMREG(fs, MIPSInst_FS(ir)); 2256 rv.d = ieee754dp_fmax(fs, ft); 2257 goto copcsr; 2258 } 2259 2260 case fmaxa_op: { 2261 union ieee754dp fs, ft; 2262 2263 if (!cpu_has_mips_r6) 2264 return SIGILL; 2265 2266 MIPS_FPU_EMU_INC_STATS(maxa_d); 2267 DPFROMREG(ft, MIPSInst_FT(ir)); 2268 DPFROMREG(fs, MIPSInst_FS(ir)); 2269 rv.d = ieee754dp_fmaxa(fs, ft); 2270 goto copcsr; 2271 } 2272 2273 case fabs_op: 2274 MIPS_FPU_EMU_INC_STATS(abs_d); 2275 handler.u = ieee754dp_abs; 2276 goto dcopuop; 2277 2278 case fneg_op: 2279 MIPS_FPU_EMU_INC_STATS(neg_d); 2280 handler.u = ieee754dp_neg; 2281 goto dcopuop; 2282 2283 case fmov_op: 2284 /* an easy one */ 2285 MIPS_FPU_EMU_INC_STATS(mov_d); 2286 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2287 goto copcsr; 2288 2289 /* binary op on handler */ 2290 dcopbop: 2291 DPFROMREG(fs, MIPSInst_FS(ir)); 2292 DPFROMREG(ft, MIPSInst_FT(ir)); 2293 2294 rv.d = (*handler.b) (fs, ft); 2295 goto copcsr; 2296 dcopuop: 2297 DPFROMREG(fs, MIPSInst_FS(ir)); 2298 rv.d = (*handler.u) (fs); 2299 goto copcsr; 2300 2301 /* 2302 * unary conv ops 2303 */ 2304 case fcvts_op: 2305 MIPS_FPU_EMU_INC_STATS(cvt_s_d); 2306 DPFROMREG(fs, MIPSInst_FS(ir)); 2307 rv.s = ieee754sp_fdp(fs); 2308 rfmt = s_fmt; 2309 goto copcsr; 2310 2311 case fcvtd_op: 2312 return SIGILL; /* not defined */ 2313 2314 case fcvtw_op: 2315 MIPS_FPU_EMU_INC_STATS(cvt_w_d); 2316 DPFROMREG(fs, MIPSInst_FS(ir)); 2317 rv.w = ieee754dp_tint(fs); /* wrong */ 2318 rfmt = w_fmt; 2319 goto copcsr; 2320 2321 case fround_op: 2322 case ftrunc_op: 2323 case fceil_op: 2324 case ffloor_op: 2325 if (!cpu_has_mips_2_3_4_5_r) 2326 return SIGILL; 2327 2328 if (MIPSInst_FUNC(ir) == fceil_op) 2329 MIPS_FPU_EMU_INC_STATS(ceil_w_d); 2330 if (MIPSInst_FUNC(ir) == ffloor_op) 2331 MIPS_FPU_EMU_INC_STATS(floor_w_d); 2332 if (MIPSInst_FUNC(ir) == fround_op) 2333 MIPS_FPU_EMU_INC_STATS(round_w_d); 2334 if (MIPSInst_FUNC(ir) == ftrunc_op) 2335 MIPS_FPU_EMU_INC_STATS(trunc_w_d); 2336 2337 oldrm = ieee754_csr.rm; 2338 DPFROMREG(fs, MIPSInst_FS(ir)); 2339 ieee754_csr.rm = MIPSInst_FUNC(ir); 2340 rv.w = ieee754dp_tint(fs); 2341 ieee754_csr.rm = oldrm; 2342 rfmt = w_fmt; 2343 goto copcsr; 2344 2345 case fsel_op: 2346 if (!cpu_has_mips_r6) 2347 return SIGILL; 2348 2349 MIPS_FPU_EMU_INC_STATS(sel_d); 2350 DPFROMREG(fd, MIPSInst_FD(ir)); 2351 if (fd.bits & 0x1) 2352 DPFROMREG(rv.d, MIPSInst_FT(ir)); 2353 else 2354 DPFROMREG(rv.d, MIPSInst_FS(ir)); 2355 break; 2356 2357 case fcvtl_op: 2358 if (!cpu_has_mips_3_4_5_64_r2_r6) 2359 return SIGILL; 2360 2361 MIPS_FPU_EMU_INC_STATS(cvt_l_d); 2362 DPFROMREG(fs, MIPSInst_FS(ir)); 2363 rv.l = ieee754dp_tlong(fs); 2364 rfmt = l_fmt; 2365 goto copcsr; 2366 2367 case froundl_op: 2368 case ftruncl_op: 2369 case fceill_op: 2370 case ffloorl_op: 2371 if (!cpu_has_mips_3_4_5_64_r2_r6) 2372 return SIGILL; 2373 2374 if (MIPSInst_FUNC(ir) == fceill_op) 2375 MIPS_FPU_EMU_INC_STATS(ceil_l_d); 2376 if (MIPSInst_FUNC(ir) == ffloorl_op) 2377 MIPS_FPU_EMU_INC_STATS(floor_l_d); 2378 if (MIPSInst_FUNC(ir) == froundl_op) 2379 MIPS_FPU_EMU_INC_STATS(round_l_d); 2380 if (MIPSInst_FUNC(ir) == ftruncl_op) 2381 MIPS_FPU_EMU_INC_STATS(trunc_l_d); 2382 2383 oldrm = ieee754_csr.rm; 2384 DPFROMREG(fs, MIPSInst_FS(ir)); 2385 ieee754_csr.rm = MIPSInst_FUNC(ir); 2386 rv.l = ieee754dp_tlong(fs); 2387 ieee754_csr.rm = oldrm; 2388 rfmt = l_fmt; 2389 goto copcsr; 2390 2391 default: 2392 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { 2393 unsigned int cmpop; 2394 union ieee754dp fs, ft; 2395 2396 cmpop = MIPSInst_FUNC(ir) - fcmp_op; 2397 DPFROMREG(fs, MIPSInst_FS(ir)); 2398 DPFROMREG(ft, MIPSInst_FT(ir)); 2399 rv.w = ieee754dp_cmp(fs, ft, 2400 cmptab[cmpop & 0x7], cmpop & 0x8); 2401 rfmt = -1; 2402 if ((cmpop & 0x8) 2403 && 2404 ieee754_cxtest 2405 (IEEE754_INVALID_OPERATION)) 2406 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2407 else 2408 goto copcsr; 2409 2410 } 2411 else { 2412 return SIGILL; 2413 } 2414 break; 2415 } 2416 break; 2417 } 2418 2419 case w_fmt: { 2420 union ieee754dp fs; 2421 2422 switch (MIPSInst_FUNC(ir)) { 2423 case fcvts_op: 2424 /* convert word to single precision real */ 2425 MIPS_FPU_EMU_INC_STATS(cvt_s_w); 2426 SPFROMREG(fs, MIPSInst_FS(ir)); 2427 rv.s = ieee754sp_fint(fs.bits); 2428 rfmt = s_fmt; 2429 goto copcsr; 2430 case fcvtd_op: 2431 /* convert word to double precision real */ 2432 MIPS_FPU_EMU_INC_STATS(cvt_d_w); 2433 SPFROMREG(fs, MIPSInst_FS(ir)); 2434 rv.d = ieee754dp_fint(fs.bits); 2435 rfmt = d_fmt; 2436 goto copcsr; 2437 default: { 2438 /* Emulating the new CMP.condn.fmt R6 instruction */ 2439 #define CMPOP_MASK 0x7 2440 #define SIGN_BIT (0x1 << 3) 2441 #define PREDICATE_BIT (0x1 << 4) 2442 2443 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; 2444 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; 2445 union ieee754sp fs, ft; 2446 2447 /* This is an R6 only instruction */ 2448 if (!cpu_has_mips_r6 || 2449 (MIPSInst_FUNC(ir) & 0x20)) 2450 return SIGILL; 2451 2452 if (!sig) { 2453 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2454 switch (cmpop) { 2455 case 0: 2456 MIPS_FPU_EMU_INC_STATS(cmp_af_s); 2457 break; 2458 case 1: 2459 MIPS_FPU_EMU_INC_STATS(cmp_un_s); 2460 break; 2461 case 2: 2462 MIPS_FPU_EMU_INC_STATS(cmp_eq_s); 2463 break; 2464 case 3: 2465 MIPS_FPU_EMU_INC_STATS(cmp_ueq_s); 2466 break; 2467 case 4: 2468 MIPS_FPU_EMU_INC_STATS(cmp_lt_s); 2469 break; 2470 case 5: 2471 MIPS_FPU_EMU_INC_STATS(cmp_ult_s); 2472 break; 2473 case 6: 2474 MIPS_FPU_EMU_INC_STATS(cmp_le_s); 2475 break; 2476 case 7: 2477 MIPS_FPU_EMU_INC_STATS(cmp_ule_s); 2478 break; 2479 } 2480 } else { 2481 switch (cmpop) { 2482 case 1: 2483 MIPS_FPU_EMU_INC_STATS(cmp_or_s); 2484 break; 2485 case 2: 2486 MIPS_FPU_EMU_INC_STATS(cmp_une_s); 2487 break; 2488 case 3: 2489 MIPS_FPU_EMU_INC_STATS(cmp_ne_s); 2490 break; 2491 } 2492 } 2493 } else { 2494 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2495 switch (cmpop) { 2496 case 0: 2497 MIPS_FPU_EMU_INC_STATS(cmp_saf_s); 2498 break; 2499 case 1: 2500 MIPS_FPU_EMU_INC_STATS(cmp_sun_s); 2501 break; 2502 case 2: 2503 MIPS_FPU_EMU_INC_STATS(cmp_seq_s); 2504 break; 2505 case 3: 2506 MIPS_FPU_EMU_INC_STATS(cmp_sueq_s); 2507 break; 2508 case 4: 2509 MIPS_FPU_EMU_INC_STATS(cmp_slt_s); 2510 break; 2511 case 5: 2512 MIPS_FPU_EMU_INC_STATS(cmp_sult_s); 2513 break; 2514 case 6: 2515 MIPS_FPU_EMU_INC_STATS(cmp_sle_s); 2516 break; 2517 case 7: 2518 MIPS_FPU_EMU_INC_STATS(cmp_sule_s); 2519 break; 2520 } 2521 } else { 2522 switch (cmpop) { 2523 case 1: 2524 MIPS_FPU_EMU_INC_STATS(cmp_sor_s); 2525 break; 2526 case 2: 2527 MIPS_FPU_EMU_INC_STATS(cmp_sune_s); 2528 break; 2529 case 3: 2530 MIPS_FPU_EMU_INC_STATS(cmp_sne_s); 2531 break; 2532 } 2533 } 2534 } 2535 2536 /* fmt is w_fmt for single precision so fix it */ 2537 rfmt = s_fmt; 2538 /* default to false */ 2539 rv.w = 0; 2540 2541 /* CMP.condn.S */ 2542 SPFROMREG(fs, MIPSInst_FS(ir)); 2543 SPFROMREG(ft, MIPSInst_FT(ir)); 2544 2545 /* positive predicates */ 2546 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2547 if (ieee754sp_cmp(fs, ft, cmptab[cmpop], 2548 sig)) 2549 rv.w = -1; /* true, all 1s */ 2550 if ((sig) && 2551 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2552 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2553 else 2554 goto copcsr; 2555 } else { 2556 /* negative predicates */ 2557 switch (cmpop) { 2558 case 1: 2559 case 2: 2560 case 3: 2561 if (ieee754sp_cmp(fs, ft, 2562 negative_cmptab[cmpop], 2563 sig)) 2564 rv.w = -1; /* true, all 1s */ 2565 if (sig && 2566 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2567 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2568 else 2569 goto copcsr; 2570 break; 2571 default: 2572 /* Reserved R6 ops */ 2573 return SIGILL; 2574 } 2575 } 2576 break; 2577 } 2578 } 2579 break; 2580 } 2581 2582 case l_fmt: 2583 2584 if (!cpu_has_mips_3_4_5_64_r2_r6) 2585 return SIGILL; 2586 2587 DIFROMREG(bits, MIPSInst_FS(ir)); 2588 2589 switch (MIPSInst_FUNC(ir)) { 2590 case fcvts_op: 2591 /* convert long to single precision real */ 2592 MIPS_FPU_EMU_INC_STATS(cvt_s_l); 2593 rv.s = ieee754sp_flong(bits); 2594 rfmt = s_fmt; 2595 goto copcsr; 2596 case fcvtd_op: 2597 /* convert long to double precision real */ 2598 MIPS_FPU_EMU_INC_STATS(cvt_d_l); 2599 rv.d = ieee754dp_flong(bits); 2600 rfmt = d_fmt; 2601 goto copcsr; 2602 default: { 2603 /* Emulating the new CMP.condn.fmt R6 instruction */ 2604 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; 2605 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; 2606 union ieee754dp fs, ft; 2607 2608 if (!cpu_has_mips_r6 || 2609 (MIPSInst_FUNC(ir) & 0x20)) 2610 return SIGILL; 2611 2612 if (!sig) { 2613 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2614 switch (cmpop) { 2615 case 0: 2616 MIPS_FPU_EMU_INC_STATS(cmp_af_d); 2617 break; 2618 case 1: 2619 MIPS_FPU_EMU_INC_STATS(cmp_un_d); 2620 break; 2621 case 2: 2622 MIPS_FPU_EMU_INC_STATS(cmp_eq_d); 2623 break; 2624 case 3: 2625 MIPS_FPU_EMU_INC_STATS(cmp_ueq_d); 2626 break; 2627 case 4: 2628 MIPS_FPU_EMU_INC_STATS(cmp_lt_d); 2629 break; 2630 case 5: 2631 MIPS_FPU_EMU_INC_STATS(cmp_ult_d); 2632 break; 2633 case 6: 2634 MIPS_FPU_EMU_INC_STATS(cmp_le_d); 2635 break; 2636 case 7: 2637 MIPS_FPU_EMU_INC_STATS(cmp_ule_d); 2638 break; 2639 } 2640 } else { 2641 switch (cmpop) { 2642 case 1: 2643 MIPS_FPU_EMU_INC_STATS(cmp_or_d); 2644 break; 2645 case 2: 2646 MIPS_FPU_EMU_INC_STATS(cmp_une_d); 2647 break; 2648 case 3: 2649 MIPS_FPU_EMU_INC_STATS(cmp_ne_d); 2650 break; 2651 } 2652 } 2653 } else { 2654 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2655 switch (cmpop) { 2656 case 0: 2657 MIPS_FPU_EMU_INC_STATS(cmp_saf_d); 2658 break; 2659 case 1: 2660 MIPS_FPU_EMU_INC_STATS(cmp_sun_d); 2661 break; 2662 case 2: 2663 MIPS_FPU_EMU_INC_STATS(cmp_seq_d); 2664 break; 2665 case 3: 2666 MIPS_FPU_EMU_INC_STATS(cmp_sueq_d); 2667 break; 2668 case 4: 2669 MIPS_FPU_EMU_INC_STATS(cmp_slt_d); 2670 break; 2671 case 5: 2672 MIPS_FPU_EMU_INC_STATS(cmp_sult_d); 2673 break; 2674 case 6: 2675 MIPS_FPU_EMU_INC_STATS(cmp_sle_d); 2676 break; 2677 case 7: 2678 MIPS_FPU_EMU_INC_STATS(cmp_sule_d); 2679 break; 2680 } 2681 } else { 2682 switch (cmpop) { 2683 case 1: 2684 MIPS_FPU_EMU_INC_STATS(cmp_sor_d); 2685 break; 2686 case 2: 2687 MIPS_FPU_EMU_INC_STATS(cmp_sune_d); 2688 break; 2689 case 3: 2690 MIPS_FPU_EMU_INC_STATS(cmp_sne_d); 2691 break; 2692 } 2693 } 2694 } 2695 2696 /* fmt is l_fmt for double precision so fix it */ 2697 rfmt = d_fmt; 2698 /* default to false */ 2699 rv.l = 0; 2700 2701 /* CMP.condn.D */ 2702 DPFROMREG(fs, MIPSInst_FS(ir)); 2703 DPFROMREG(ft, MIPSInst_FT(ir)); 2704 2705 /* positive predicates */ 2706 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { 2707 if (ieee754dp_cmp(fs, ft, 2708 cmptab[cmpop], sig)) 2709 rv.l = -1LL; /* true, all 1s */ 2710 if (sig && 2711 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2712 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2713 else 2714 goto copcsr; 2715 } else { 2716 /* negative predicates */ 2717 switch (cmpop) { 2718 case 1: 2719 case 2: 2720 case 3: 2721 if (ieee754dp_cmp(fs, ft, 2722 negative_cmptab[cmpop], 2723 sig)) 2724 rv.l = -1LL; /* true, all 1s */ 2725 if (sig && 2726 ieee754_cxtest(IEEE754_INVALID_OPERATION)) 2727 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2728 else 2729 goto copcsr; 2730 break; 2731 default: 2732 /* Reserved R6 ops */ 2733 return SIGILL; 2734 } 2735 } 2736 break; 2737 } 2738 } 2739 break; 2740 2741 default: 2742 return SIGILL; 2743 } 2744 2745 /* 2746 * Update the fpu CSR register for this operation. 2747 * If an exception is required, generate a tidy SIGFPE exception, 2748 * without updating the result register. 2749 * Note: cause exception bits do not accumulate, they are rewritten 2750 * for each op; only the flag/sticky bits accumulate. 2751 */ 2752 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 2753 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 2754 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ 2755 return SIGFPE; 2756 } 2757 2758 /* 2759 * Now we can safely write the result back to the register file. 2760 */ 2761 switch (rfmt) { 2762 case -1: 2763 2764 if (cpu_has_mips_4_5_r) 2765 cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; 2766 else 2767 cbit = FPU_CSR_COND; 2768 if (rv.w) 2769 ctx->fcr31 |= cbit; 2770 else 2771 ctx->fcr31 &= ~cbit; 2772 break; 2773 2774 case d_fmt: 2775 DPTOREG(rv.d, MIPSInst_FD(ir)); 2776 break; 2777 case s_fmt: 2778 SPTOREG(rv.s, MIPSInst_FD(ir)); 2779 break; 2780 case w_fmt: 2781 SITOREG(rv.w, MIPSInst_FD(ir)); 2782 break; 2783 case l_fmt: 2784 if (!cpu_has_mips_3_4_5_64_r2_r6) 2785 return SIGILL; 2786 2787 DITOREG(rv.l, MIPSInst_FD(ir)); 2788 break; 2789 default: 2790 return SIGILL; 2791 } 2792 2793 return 0; 2794 } 2795 2796 /* 2797 * Emulate FPU instructions. 2798 * 2799 * If we use FPU hardware, then we have been typically called to handle 2800 * an unimplemented operation, such as where an operand is a NaN or 2801 * denormalized. In that case exit the emulation loop after a single 2802 * iteration so as to let hardware execute any subsequent instructions. 2803 * 2804 * If we have no FPU hardware or it has been disabled, then continue 2805 * emulating floating-point instructions until one of these conditions 2806 * has occurred: 2807 * 2808 * - a non-FPU instruction has been encountered, 2809 * 2810 * - an attempt to emulate has ended with a signal, 2811 * 2812 * - the ISA mode has been switched. 2813 * 2814 * We need to terminate the emulation loop if we got switched to the 2815 * MIPS16 mode, whether supported or not, so that we do not attempt 2816 * to emulate a MIPS16 instruction as a regular MIPS FPU instruction. 2817 * Similarly if we got switched to the microMIPS mode and only the 2818 * regular MIPS mode is supported, so that we do not attempt to emulate 2819 * a microMIPS instruction as a regular MIPS FPU instruction. Or if 2820 * we got switched to the regular MIPS mode and only the microMIPS mode 2821 * is supported, so that we do not attempt to emulate a regular MIPS 2822 * instruction that should cause an Address Error exception instead. 2823 * For simplicity we always terminate upon an ISA mode switch. 2824 */ 2825 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 2826 int has_fpu, void __user **fault_addr) 2827 { 2828 unsigned long oldepc, prevepc; 2829 struct mm_decoded_insn dec_insn; 2830 u16 instr[4]; 2831 u16 *instr_ptr; 2832 int sig = 0; 2833 2834 oldepc = xcp->cp0_epc; 2835 do { 2836 prevepc = xcp->cp0_epc; 2837 2838 if (get_isa16_mode(prevepc) && cpu_has_mmips) { 2839 /* 2840 * Get next 2 microMIPS instructions and convert them 2841 * into 32-bit instructions. 2842 */ 2843 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 2844 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 2845 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 2846 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 2847 MIPS_FPU_EMU_INC_STATS(errors); 2848 return SIGBUS; 2849 } 2850 instr_ptr = instr; 2851 2852 /* Get first instruction. */ 2853 if (mm_insn_16bit(*instr_ptr)) { 2854 /* Duplicate the half-word. */ 2855 dec_insn.insn = (*instr_ptr << 16) | 2856 (*instr_ptr); 2857 /* 16-bit instruction. */ 2858 dec_insn.pc_inc = 2; 2859 instr_ptr += 1; 2860 } else { 2861 dec_insn.insn = (*instr_ptr << 16) | 2862 *(instr_ptr+1); 2863 /* 32-bit instruction. */ 2864 dec_insn.pc_inc = 4; 2865 instr_ptr += 2; 2866 } 2867 /* Get second instruction. */ 2868 if (mm_insn_16bit(*instr_ptr)) { 2869 /* Duplicate the half-word. */ 2870 dec_insn.next_insn = (*instr_ptr << 16) | 2871 (*instr_ptr); 2872 /* 16-bit instruction. */ 2873 dec_insn.next_pc_inc = 2; 2874 } else { 2875 dec_insn.next_insn = (*instr_ptr << 16) | 2876 *(instr_ptr+1); 2877 /* 32-bit instruction. */ 2878 dec_insn.next_pc_inc = 4; 2879 } 2880 dec_insn.micro_mips_mode = 1; 2881 } else { 2882 if ((get_user(dec_insn.insn, 2883 (mips_instruction __user *) xcp->cp0_epc)) || 2884 (get_user(dec_insn.next_insn, 2885 (mips_instruction __user *)(xcp->cp0_epc+4)))) { 2886 MIPS_FPU_EMU_INC_STATS(errors); 2887 return SIGBUS; 2888 } 2889 dec_insn.pc_inc = 4; 2890 dec_insn.next_pc_inc = 4; 2891 dec_insn.micro_mips_mode = 0; 2892 } 2893 2894 if ((dec_insn.insn == 0) || 2895 ((dec_insn.pc_inc == 2) && 2896 ((dec_insn.insn & 0xffff) == MM_NOP16))) 2897 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 2898 else { 2899 /* 2900 * The 'ieee754_csr' is an alias of ctx->fcr31. 2901 * No need to copy ctx->fcr31 to ieee754_csr. 2902 */ 2903 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 2904 } 2905 2906 if (has_fpu) 2907 break; 2908 if (sig) 2909 break; 2910 /* 2911 * We have to check for the ISA bit explicitly here, 2912 * because `get_isa16_mode' may return 0 if support 2913 * for code compression has been globally disabled, 2914 * or otherwise we may produce the wrong signal or 2915 * even proceed successfully where we must not. 2916 */ 2917 if ((xcp->cp0_epc ^ prevepc) & 0x1) 2918 break; 2919 2920 cond_resched(); 2921 } while (xcp->cp0_epc > prevepc); 2922 2923 /* SIGILL indicates a non-fpu instruction */ 2924 if (sig == SIGILL && xcp->cp0_epc != oldepc) 2925 /* but if EPC has advanced, then ignore it */ 2926 sig = 0; 2927 2928 return sig; 2929 } 2930