11da177e4SLinus Torvalds /* 23f7cac41SRalf Baechle * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * MIPS floating point support 51da177e4SLinus Torvalds * Copyright (C) 1994-2000 Algorithmics Ltd. 61da177e4SLinus Torvalds * 71da177e4SLinus Torvalds * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 81da177e4SLinus Torvalds * Copyright (C) 2000 MIPS Technologies, Inc. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * This program is free software; you can distribute it and/or modify it 111da177e4SLinus Torvalds * under the terms of the GNU General Public License (Version 2) as 121da177e4SLinus Torvalds * published by the Free Software Foundation. 131da177e4SLinus Torvalds * 141da177e4SLinus Torvalds * This program is distributed in the hope it will be useful, but WITHOUT 151da177e4SLinus Torvalds * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 161da177e4SLinus Torvalds * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 171da177e4SLinus Torvalds * for more details. 181da177e4SLinus Torvalds * 191da177e4SLinus Torvalds * You should have received a copy of the GNU General Public License along 201da177e4SLinus Torvalds * with this program; if not, write to the Free Software Foundation, Inc., 213f7cac41SRalf Baechle * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 221da177e4SLinus Torvalds * 231da177e4SLinus Torvalds * A complete emulator for MIPS coprocessor 1 instructions. This is 241da177e4SLinus Torvalds * required for #float(switch) or #float(trap), where it catches all 251da177e4SLinus Torvalds * COP1 instructions via the "CoProcessor Unusable" exception. 261da177e4SLinus Torvalds * 271da177e4SLinus Torvalds * More surprisingly it is also required for #float(ieee), to help out 283f7cac41SRalf Baechle * the hardware FPU at the boundaries of the IEEE-754 representation 291da177e4SLinus Torvalds * (denormalised values, infinities, underflow, etc). It is made 301da177e4SLinus Torvalds * quite nasty because emulation of some non-COP1 instructions is 311da177e4SLinus Torvalds * required, e.g. in branch delay slots. 321da177e4SLinus Torvalds * 333f7cac41SRalf Baechle * Note if you know that you won't have an FPU, then you'll get much 341da177e4SLinus Torvalds * better performance by compiling with -msoft-float! 351da177e4SLinus Torvalds */ 361da177e4SLinus Torvalds #include <linux/sched.h> 3783fd38caSAtsushi Nemoto #include <linux/debugfs.h> 3808a07904SRalf Baechle #include <linux/kconfig.h> 3985c51c51SRalf Baechle #include <linux/percpu-defs.h> 407f788d2dSDeng-Cheng Zhu #include <linux/perf_event.h> 411da177e4SLinus Torvalds 42cd8ee345SRalf Baechle #include <asm/branch.h> 431da177e4SLinus Torvalds #include <asm/inst.h> 441da177e4SLinus Torvalds #include <asm/ptrace.h> 451da177e4SLinus Torvalds #include <asm/signal.h> 46cd8ee345SRalf Baechle #include <asm/uaccess.h> 47cd8ee345SRalf Baechle 48cd8ee345SRalf Baechle #include <asm/processor.h> 491da177e4SLinus Torvalds #include <asm/fpu_emulator.h> 50102cedc3SLeonid Yegoshin #include <asm/fpu.h> 511da177e4SLinus Torvalds 521da177e4SLinus Torvalds #include "ieee754.h" 531da177e4SLinus Torvalds 541da177e4SLinus Torvalds /* Function which emulates a floating point instruction. */ 551da177e4SLinus Torvalds 56eae89076SAtsushi Nemoto static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 571da177e4SLinus Torvalds mips_instruction); 581da177e4SLinus Torvalds 591da177e4SLinus Torvalds static int fpux_emu(struct pt_regs *, 60515b029dSDavid Daney struct mips_fpu_struct *, mips_instruction, void *__user *); 611da177e4SLinus Torvalds 621da177e4SLinus Torvalds /* Control registers */ 631da177e4SLinus Torvalds 641da177e4SLinus Torvalds #define FPCREG_RID 0 /* $0 = revision id */ 651da177e4SLinus Torvalds #define FPCREG_CSR 31 /* $31 = csr */ 661da177e4SLinus Torvalds 6795e8f634SShane McDonald /* Determine rounding mode from the RM bits of the FCSR */ 6895e8f634SShane McDonald #define modeindex(v) ((v) & FPU_CSR_RM) 6995e8f634SShane McDonald 701da177e4SLinus Torvalds /* convert condition code register number to csr bit */ 711da177e4SLinus Torvalds static const unsigned int fpucondbit[8] = { 721da177e4SLinus Torvalds FPU_CSR_COND0, 731da177e4SLinus Torvalds FPU_CSR_COND1, 741da177e4SLinus Torvalds FPU_CSR_COND2, 751da177e4SLinus Torvalds FPU_CSR_COND3, 761da177e4SLinus Torvalds FPU_CSR_COND4, 771da177e4SLinus Torvalds FPU_CSR_COND5, 781da177e4SLinus Torvalds FPU_CSR_COND6, 791da177e4SLinus Torvalds FPU_CSR_COND7 801da177e4SLinus Torvalds }; 811da177e4SLinus Torvalds 82102cedc3SLeonid Yegoshin /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 83102cedc3SLeonid Yegoshin static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 84102cedc3SLeonid Yegoshin static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 85102cedc3SLeonid Yegoshin static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 86102cedc3SLeonid Yegoshin static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 87102cedc3SLeonid Yegoshin 88102cedc3SLeonid Yegoshin /* 89102cedc3SLeonid Yegoshin * This functions translates a 32-bit microMIPS instruction 90102cedc3SLeonid Yegoshin * into a 32-bit MIPS32 instruction. Returns 0 on success 91102cedc3SLeonid Yegoshin * and SIGILL otherwise. 92102cedc3SLeonid Yegoshin */ 93102cedc3SLeonid Yegoshin static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 94102cedc3SLeonid Yegoshin { 95102cedc3SLeonid Yegoshin union mips_instruction insn = *insn_ptr; 96102cedc3SLeonid Yegoshin union mips_instruction mips32_insn = insn; 97102cedc3SLeonid Yegoshin int func, fmt, op; 98102cedc3SLeonid Yegoshin 99102cedc3SLeonid Yegoshin switch (insn.mm_i_format.opcode) { 100102cedc3SLeonid Yegoshin case mm_ldc132_op: 101102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = ldc1_op; 102102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 103102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 104102cedc3SLeonid Yegoshin break; 105102cedc3SLeonid Yegoshin case mm_lwc132_op: 106102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = lwc1_op; 107102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 108102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 109102cedc3SLeonid Yegoshin break; 110102cedc3SLeonid Yegoshin case mm_sdc132_op: 111102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = sdc1_op; 112102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 113102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 114102cedc3SLeonid Yegoshin break; 115102cedc3SLeonid Yegoshin case mm_swc132_op: 116102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.opcode = swc1_op; 117102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 118102cedc3SLeonid Yegoshin mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 119102cedc3SLeonid Yegoshin break; 120102cedc3SLeonid Yegoshin case mm_pool32i_op: 121102cedc3SLeonid Yegoshin /* NOTE: offset is << by 1 if in microMIPS mode. */ 122102cedc3SLeonid Yegoshin if ((insn.mm_i_format.rt == mm_bc1f_op) || 123102cedc3SLeonid Yegoshin (insn.mm_i_format.rt == mm_bc1t_op)) { 124102cedc3SLeonid Yegoshin mips32_insn.fb_format.opcode = cop1_op; 125102cedc3SLeonid Yegoshin mips32_insn.fb_format.bc = bc_op; 126102cedc3SLeonid Yegoshin mips32_insn.fb_format.flag = 127102cedc3SLeonid Yegoshin (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 128102cedc3SLeonid Yegoshin } else 129102cedc3SLeonid Yegoshin return SIGILL; 130102cedc3SLeonid Yegoshin break; 131102cedc3SLeonid Yegoshin case mm_pool32f_op: 132102cedc3SLeonid Yegoshin switch (insn.mm_fp0_format.func) { 133102cedc3SLeonid Yegoshin case mm_32f_01_op: 134102cedc3SLeonid Yegoshin case mm_32f_11_op: 135102cedc3SLeonid Yegoshin case mm_32f_02_op: 136102cedc3SLeonid Yegoshin case mm_32f_12_op: 137102cedc3SLeonid Yegoshin case mm_32f_41_op: 138102cedc3SLeonid Yegoshin case mm_32f_51_op: 139102cedc3SLeonid Yegoshin case mm_32f_42_op: 140102cedc3SLeonid Yegoshin case mm_32f_52_op: 141102cedc3SLeonid Yegoshin op = insn.mm_fp0_format.func; 142102cedc3SLeonid Yegoshin if (op == mm_32f_01_op) 143102cedc3SLeonid Yegoshin func = madd_s_op; 144102cedc3SLeonid Yegoshin else if (op == mm_32f_11_op) 145102cedc3SLeonid Yegoshin func = madd_d_op; 146102cedc3SLeonid Yegoshin else if (op == mm_32f_02_op) 147102cedc3SLeonid Yegoshin func = nmadd_s_op; 148102cedc3SLeonid Yegoshin else if (op == mm_32f_12_op) 149102cedc3SLeonid Yegoshin func = nmadd_d_op; 150102cedc3SLeonid Yegoshin else if (op == mm_32f_41_op) 151102cedc3SLeonid Yegoshin func = msub_s_op; 152102cedc3SLeonid Yegoshin else if (op == mm_32f_51_op) 153102cedc3SLeonid Yegoshin func = msub_d_op; 154102cedc3SLeonid Yegoshin else if (op == mm_32f_42_op) 155102cedc3SLeonid Yegoshin func = nmsub_s_op; 156102cedc3SLeonid Yegoshin else 157102cedc3SLeonid Yegoshin func = nmsub_d_op; 158102cedc3SLeonid Yegoshin mips32_insn.fp6_format.opcode = cop1x_op; 159102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 160102cedc3SLeonid Yegoshin mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 161102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 162102cedc3SLeonid Yegoshin mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 163102cedc3SLeonid Yegoshin mips32_insn.fp6_format.func = func; 164102cedc3SLeonid Yegoshin break; 165102cedc3SLeonid Yegoshin case mm_32f_10_op: 166102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 167102cedc3SLeonid Yegoshin op = insn.mm_fp5_format.op & 0x7; 168102cedc3SLeonid Yegoshin if (op == mm_ldxc1_op) 169102cedc3SLeonid Yegoshin func = ldxc1_op; 170102cedc3SLeonid Yegoshin else if (op == mm_sdxc1_op) 171102cedc3SLeonid Yegoshin func = sdxc1_op; 172102cedc3SLeonid Yegoshin else if (op == mm_lwxc1_op) 173102cedc3SLeonid Yegoshin func = lwxc1_op; 174102cedc3SLeonid Yegoshin else if (op == mm_swxc1_op) 175102cedc3SLeonid Yegoshin func = swxc1_op; 176102cedc3SLeonid Yegoshin 177102cedc3SLeonid Yegoshin if (func != -1) { 178102cedc3SLeonid Yegoshin mips32_insn.r_format.opcode = cop1x_op; 179102cedc3SLeonid Yegoshin mips32_insn.r_format.rs = 180102cedc3SLeonid Yegoshin insn.mm_fp5_format.base; 181102cedc3SLeonid Yegoshin mips32_insn.r_format.rt = 182102cedc3SLeonid Yegoshin insn.mm_fp5_format.index; 183102cedc3SLeonid Yegoshin mips32_insn.r_format.rd = 0; 184102cedc3SLeonid Yegoshin mips32_insn.r_format.re = insn.mm_fp5_format.fd; 185102cedc3SLeonid Yegoshin mips32_insn.r_format.func = func; 186102cedc3SLeonid Yegoshin } else 187102cedc3SLeonid Yegoshin return SIGILL; 188102cedc3SLeonid Yegoshin break; 189102cedc3SLeonid Yegoshin case mm_32f_40_op: 190102cedc3SLeonid Yegoshin op = -1; /* Invalid */ 191102cedc3SLeonid Yegoshin if (insn.mm_fp2_format.op == mm_fmovt_op) 192102cedc3SLeonid Yegoshin op = 1; 193102cedc3SLeonid Yegoshin else if (insn.mm_fp2_format.op == mm_fmovf_op) 194102cedc3SLeonid Yegoshin op = 0; 195102cedc3SLeonid Yegoshin if (op != -1) { 196102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 197102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 198102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp2_format.fmt]; 199102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 200102cedc3SLeonid Yegoshin (insn.mm_fp2_format.cc<<2) + op; 201102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 202102cedc3SLeonid Yegoshin insn.mm_fp2_format.fs; 203102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 204102cedc3SLeonid Yegoshin insn.mm_fp2_format.fd; 205102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = fmovc_op; 206102cedc3SLeonid Yegoshin } else 207102cedc3SLeonid Yegoshin return SIGILL; 208102cedc3SLeonid Yegoshin break; 209102cedc3SLeonid Yegoshin case mm_32f_60_op: 210102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 211102cedc3SLeonid Yegoshin if (insn.mm_fp0_format.op == mm_fadd_op) 212102cedc3SLeonid Yegoshin func = fadd_op; 213102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fsub_op) 214102cedc3SLeonid Yegoshin func = fsub_op; 215102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fmul_op) 216102cedc3SLeonid Yegoshin func = fmul_op; 217102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fdiv_op) 218102cedc3SLeonid Yegoshin func = fdiv_op; 219102cedc3SLeonid Yegoshin if (func != -1) { 220102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 221102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 222102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp0_format.fmt]; 223102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 224102cedc3SLeonid Yegoshin insn.mm_fp0_format.ft; 225102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 226102cedc3SLeonid Yegoshin insn.mm_fp0_format.fs; 227102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 228102cedc3SLeonid Yegoshin insn.mm_fp0_format.fd; 229102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 230102cedc3SLeonid Yegoshin } else 231102cedc3SLeonid Yegoshin return SIGILL; 232102cedc3SLeonid Yegoshin break; 233102cedc3SLeonid Yegoshin case mm_32f_70_op: 234102cedc3SLeonid Yegoshin func = -1; /* Invalid */ 235102cedc3SLeonid Yegoshin if (insn.mm_fp0_format.op == mm_fmovn_op) 236102cedc3SLeonid Yegoshin func = fmovn_op; 237102cedc3SLeonid Yegoshin else if (insn.mm_fp0_format.op == mm_fmovz_op) 238102cedc3SLeonid Yegoshin func = fmovz_op; 239102cedc3SLeonid Yegoshin if (func != -1) { 240102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 241102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 242102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp0_format.fmt]; 243102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 244102cedc3SLeonid Yegoshin insn.mm_fp0_format.ft; 245102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 246102cedc3SLeonid Yegoshin insn.mm_fp0_format.fs; 247102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 248102cedc3SLeonid Yegoshin insn.mm_fp0_format.fd; 249102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 250102cedc3SLeonid Yegoshin } else 251102cedc3SLeonid Yegoshin return SIGILL; 252102cedc3SLeonid Yegoshin break; 253102cedc3SLeonid Yegoshin case mm_32f_73_op: /* POOL32FXF */ 254102cedc3SLeonid Yegoshin switch (insn.mm_fp1_format.op) { 255102cedc3SLeonid Yegoshin case mm_movf0_op: 256102cedc3SLeonid Yegoshin case mm_movf1_op: 257102cedc3SLeonid Yegoshin case mm_movt0_op: 258102cedc3SLeonid Yegoshin case mm_movt1_op: 259102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 260102cedc3SLeonid Yegoshin mm_movf0_op) 261102cedc3SLeonid Yegoshin op = 0; 262102cedc3SLeonid Yegoshin else 263102cedc3SLeonid Yegoshin op = 1; 264102cedc3SLeonid Yegoshin mips32_insn.r_format.opcode = spec_op; 265102cedc3SLeonid Yegoshin mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 266102cedc3SLeonid Yegoshin mips32_insn.r_format.rt = 267102cedc3SLeonid Yegoshin (insn.mm_fp4_format.cc << 2) + op; 268102cedc3SLeonid Yegoshin mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 269102cedc3SLeonid Yegoshin mips32_insn.r_format.re = 0; 270102cedc3SLeonid Yegoshin mips32_insn.r_format.func = movc_op; 271102cedc3SLeonid Yegoshin break; 272102cedc3SLeonid Yegoshin case mm_fcvtd0_op: 273102cedc3SLeonid Yegoshin case mm_fcvtd1_op: 274102cedc3SLeonid Yegoshin case mm_fcvts0_op: 275102cedc3SLeonid Yegoshin case mm_fcvts1_op: 276102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 277102cedc3SLeonid Yegoshin mm_fcvtd0_op) { 278102cedc3SLeonid Yegoshin func = fcvtd_op; 279102cedc3SLeonid Yegoshin fmt = swl_format[insn.mm_fp3_format.fmt]; 280102cedc3SLeonid Yegoshin } else { 281102cedc3SLeonid Yegoshin func = fcvts_op; 282102cedc3SLeonid Yegoshin fmt = dwl_format[insn.mm_fp3_format.fmt]; 283102cedc3SLeonid Yegoshin } 284102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 285102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = fmt; 286102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 287102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 288102cedc3SLeonid Yegoshin insn.mm_fp3_format.fs; 289102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 290102cedc3SLeonid Yegoshin insn.mm_fp3_format.rt; 291102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 292102cedc3SLeonid Yegoshin break; 293102cedc3SLeonid Yegoshin case mm_fmov0_op: 294102cedc3SLeonid Yegoshin case mm_fmov1_op: 295102cedc3SLeonid Yegoshin case mm_fabs0_op: 296102cedc3SLeonid Yegoshin case mm_fabs1_op: 297102cedc3SLeonid Yegoshin case mm_fneg0_op: 298102cedc3SLeonid Yegoshin case mm_fneg1_op: 299102cedc3SLeonid Yegoshin if ((insn.mm_fp1_format.op & 0x7f) == 300102cedc3SLeonid Yegoshin mm_fmov0_op) 301102cedc3SLeonid Yegoshin func = fmov_op; 302102cedc3SLeonid Yegoshin else if ((insn.mm_fp1_format.op & 0x7f) == 303102cedc3SLeonid Yegoshin mm_fabs0_op) 304102cedc3SLeonid Yegoshin func = fabs_op; 305102cedc3SLeonid Yegoshin else 306102cedc3SLeonid Yegoshin func = fneg_op; 307102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 308102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 309102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp3_format.fmt]; 310102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 311102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 312102cedc3SLeonid Yegoshin insn.mm_fp3_format.fs; 313102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 314102cedc3SLeonid Yegoshin insn.mm_fp3_format.rt; 315102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 316102cedc3SLeonid Yegoshin break; 317102cedc3SLeonid Yegoshin case mm_ffloorl_op: 318102cedc3SLeonid Yegoshin case mm_ffloorw_op: 319102cedc3SLeonid Yegoshin case mm_fceill_op: 320102cedc3SLeonid Yegoshin case mm_fceilw_op: 321102cedc3SLeonid Yegoshin case mm_ftruncl_op: 322102cedc3SLeonid Yegoshin case mm_ftruncw_op: 323102cedc3SLeonid Yegoshin case mm_froundl_op: 324102cedc3SLeonid Yegoshin case mm_froundw_op: 325102cedc3SLeonid Yegoshin case mm_fcvtl_op: 326102cedc3SLeonid Yegoshin case mm_fcvtw_op: 327102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_ffloorl_op) 328102cedc3SLeonid Yegoshin func = ffloorl_op; 329102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ffloorw_op) 330102cedc3SLeonid Yegoshin func = ffloor_op; 331102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fceill_op) 332102cedc3SLeonid Yegoshin func = fceill_op; 333102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fceilw_op) 334102cedc3SLeonid Yegoshin func = fceil_op; 335102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ftruncl_op) 336102cedc3SLeonid Yegoshin func = ftruncl_op; 337102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_ftruncw_op) 338102cedc3SLeonid Yegoshin func = ftrunc_op; 339102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_froundl_op) 340102cedc3SLeonid Yegoshin func = froundl_op; 341102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_froundw_op) 342102cedc3SLeonid Yegoshin func = fround_op; 343102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fcvtl_op) 344102cedc3SLeonid Yegoshin func = fcvtl_op; 345102cedc3SLeonid Yegoshin else 346102cedc3SLeonid Yegoshin func = fcvtw_op; 347102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 348102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 349102cedc3SLeonid Yegoshin sd_format[insn.mm_fp1_format.fmt]; 350102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 351102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 352102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 353102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 354102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 355102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 356102cedc3SLeonid Yegoshin break; 357102cedc3SLeonid Yegoshin case mm_frsqrt_op: 358102cedc3SLeonid Yegoshin case mm_fsqrt_op: 359102cedc3SLeonid Yegoshin case mm_frecip_op: 360102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_frsqrt_op) 361102cedc3SLeonid Yegoshin func = frsqrt_op; 362102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_fsqrt_op) 363102cedc3SLeonid Yegoshin func = fsqrt_op; 364102cedc3SLeonid Yegoshin else 365102cedc3SLeonid Yegoshin func = frecip_op; 366102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 367102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 368102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp1_format.fmt]; 369102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = 0; 370102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = 371102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 372102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = 373102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 374102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = func; 375102cedc3SLeonid Yegoshin break; 376102cedc3SLeonid Yegoshin case mm_mfc1_op: 377102cedc3SLeonid Yegoshin case mm_mtc1_op: 378102cedc3SLeonid Yegoshin case mm_cfc1_op: 379102cedc3SLeonid Yegoshin case mm_ctc1_op: 3809355e59cSSteven J. Hill case mm_mfhc1_op: 3819355e59cSSteven J. Hill case mm_mthc1_op: 382102cedc3SLeonid Yegoshin if (insn.mm_fp1_format.op == mm_mfc1_op) 383102cedc3SLeonid Yegoshin op = mfc_op; 384102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_mtc1_op) 385102cedc3SLeonid Yegoshin op = mtc_op; 386102cedc3SLeonid Yegoshin else if (insn.mm_fp1_format.op == mm_cfc1_op) 387102cedc3SLeonid Yegoshin op = cfc_op; 3889355e59cSSteven J. Hill else if (insn.mm_fp1_format.op == mm_ctc1_op) 389102cedc3SLeonid Yegoshin op = ctc_op; 3909355e59cSSteven J. Hill else if (insn.mm_fp1_format.op == mm_mfhc1_op) 3919355e59cSSteven J. Hill op = mfhc_op; 3929355e59cSSteven J. Hill else 3939355e59cSSteven J. Hill op = mthc_op; 394102cedc3SLeonid Yegoshin mips32_insn.fp1_format.opcode = cop1_op; 395102cedc3SLeonid Yegoshin mips32_insn.fp1_format.op = op; 396102cedc3SLeonid Yegoshin mips32_insn.fp1_format.rt = 397102cedc3SLeonid Yegoshin insn.mm_fp1_format.rt; 398102cedc3SLeonid Yegoshin mips32_insn.fp1_format.fs = 399102cedc3SLeonid Yegoshin insn.mm_fp1_format.fs; 400102cedc3SLeonid Yegoshin mips32_insn.fp1_format.fd = 0; 401102cedc3SLeonid Yegoshin mips32_insn.fp1_format.func = 0; 402102cedc3SLeonid Yegoshin break; 403102cedc3SLeonid Yegoshin default: 404102cedc3SLeonid Yegoshin return SIGILL; 405102cedc3SLeonid Yegoshin } 406102cedc3SLeonid Yegoshin break; 407102cedc3SLeonid Yegoshin case mm_32f_74_op: /* c.cond.fmt */ 408102cedc3SLeonid Yegoshin mips32_insn.fp0_format.opcode = cop1_op; 409102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fmt = 410102cedc3SLeonid Yegoshin sdps_format[insn.mm_fp4_format.fmt]; 411102cedc3SLeonid Yegoshin mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 412102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 413102cedc3SLeonid Yegoshin mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 414102cedc3SLeonid Yegoshin mips32_insn.fp0_format.func = 415102cedc3SLeonid Yegoshin insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 416102cedc3SLeonid Yegoshin break; 417102cedc3SLeonid Yegoshin default: 418102cedc3SLeonid Yegoshin return SIGILL; 419102cedc3SLeonid Yegoshin } 420102cedc3SLeonid Yegoshin break; 421102cedc3SLeonid Yegoshin default: 422102cedc3SLeonid Yegoshin return SIGILL; 423102cedc3SLeonid Yegoshin } 424102cedc3SLeonid Yegoshin 425102cedc3SLeonid Yegoshin *insn_ptr = mips32_insn; 426102cedc3SLeonid Yegoshin return 0; 427102cedc3SLeonid Yegoshin } 428102cedc3SLeonid Yegoshin 4291da177e4SLinus Torvalds /* 4301da177e4SLinus Torvalds * Redundant with logic already in kernel/branch.c, 4311da177e4SLinus Torvalds * embedded in compute_return_epc. At some point, 4321da177e4SLinus Torvalds * a single subroutine should be used across both 4331da177e4SLinus Torvalds * modules. 4341da177e4SLinus Torvalds */ 435102cedc3SLeonid Yegoshin static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 436102cedc3SLeonid Yegoshin unsigned long *contpc) 4371da177e4SLinus Torvalds { 438102cedc3SLeonid Yegoshin union mips_instruction insn = (union mips_instruction)dec_insn.insn; 439102cedc3SLeonid Yegoshin unsigned int fcr31; 440102cedc3SLeonid Yegoshin unsigned int bit = 0; 441102cedc3SLeonid Yegoshin 442102cedc3SLeonid Yegoshin switch (insn.i_format.opcode) { 4431da177e4SLinus Torvalds case spec_op: 444102cedc3SLeonid Yegoshin switch (insn.r_format.func) { 4451da177e4SLinus Torvalds case jalr_op: 446102cedc3SLeonid Yegoshin regs->regs[insn.r_format.rd] = 447102cedc3SLeonid Yegoshin regs->cp0_epc + dec_insn.pc_inc + 448102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 449102cedc3SLeonid Yegoshin /* Fall through */ 4501da177e4SLinus Torvalds case jr_op: 451102cedc3SLeonid Yegoshin *contpc = regs->regs[insn.r_format.rs]; 4521da177e4SLinus Torvalds return 1; 4531da177e4SLinus Torvalds } 4541da177e4SLinus Torvalds break; 4551da177e4SLinus Torvalds case bcond_op: 456102cedc3SLeonid Yegoshin switch (insn.i_format.rt) { 4571da177e4SLinus Torvalds case bltzal_op: 4581da177e4SLinus Torvalds case bltzall_op: 459102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 460102cedc3SLeonid Yegoshin dec_insn.pc_inc + 461102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 462102cedc3SLeonid Yegoshin /* Fall through */ 463102cedc3SLeonid Yegoshin case bltz_op: 464102cedc3SLeonid Yegoshin case bltzl_op: 465102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] < 0) 466102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 467102cedc3SLeonid Yegoshin dec_insn.pc_inc + 468102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 469102cedc3SLeonid Yegoshin else 470102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 471102cedc3SLeonid Yegoshin dec_insn.pc_inc + 472102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 4731da177e4SLinus Torvalds return 1; 474102cedc3SLeonid Yegoshin case bgezal_op: 475102cedc3SLeonid Yegoshin case bgezall_op: 476102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 477102cedc3SLeonid Yegoshin dec_insn.pc_inc + 478102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 479102cedc3SLeonid Yegoshin /* Fall through */ 480102cedc3SLeonid Yegoshin case bgez_op: 481102cedc3SLeonid Yegoshin case bgezl_op: 482102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] >= 0) 483102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 484102cedc3SLeonid Yegoshin dec_insn.pc_inc + 485102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 486102cedc3SLeonid Yegoshin else 487102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 488102cedc3SLeonid Yegoshin dec_insn.pc_inc + 489102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 490102cedc3SLeonid Yegoshin return 1; 4911da177e4SLinus Torvalds } 4921da177e4SLinus Torvalds break; 4931da177e4SLinus Torvalds case jalx_op: 494102cedc3SLeonid Yegoshin set_isa16_mode(bit); 495102cedc3SLeonid Yegoshin case jal_op: 496102cedc3SLeonid Yegoshin regs->regs[31] = regs->cp0_epc + 497102cedc3SLeonid Yegoshin dec_insn.pc_inc + 498102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 499102cedc3SLeonid Yegoshin /* Fall through */ 500102cedc3SLeonid Yegoshin case j_op: 501102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + dec_insn.pc_inc; 502102cedc3SLeonid Yegoshin *contpc >>= 28; 503102cedc3SLeonid Yegoshin *contpc <<= 28; 504102cedc3SLeonid Yegoshin *contpc |= (insn.j_format.target << 2); 505102cedc3SLeonid Yegoshin /* Set microMIPS mode bit: XOR for jalx. */ 506102cedc3SLeonid Yegoshin *contpc ^= bit; 5071da177e4SLinus Torvalds return 1; 508102cedc3SLeonid Yegoshin case beq_op: 509102cedc3SLeonid Yegoshin case beql_op: 510102cedc3SLeonid Yegoshin if (regs->regs[insn.i_format.rs] == 511102cedc3SLeonid Yegoshin regs->regs[insn.i_format.rt]) 512102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 513102cedc3SLeonid Yegoshin dec_insn.pc_inc + 514102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 515102cedc3SLeonid Yegoshin else 516102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 517102cedc3SLeonid Yegoshin dec_insn.pc_inc + 518102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 519102cedc3SLeonid Yegoshin return 1; 520102cedc3SLeonid Yegoshin case bne_op: 521102cedc3SLeonid Yegoshin case bnel_op: 522102cedc3SLeonid Yegoshin if (regs->regs[insn.i_format.rs] != 523102cedc3SLeonid Yegoshin regs->regs[insn.i_format.rt]) 524102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 525102cedc3SLeonid Yegoshin dec_insn.pc_inc + 526102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 527102cedc3SLeonid Yegoshin else 528102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 529102cedc3SLeonid Yegoshin dec_insn.pc_inc + 530102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 531102cedc3SLeonid Yegoshin return 1; 532102cedc3SLeonid Yegoshin case blez_op: 533102cedc3SLeonid Yegoshin case blezl_op: 534102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] <= 0) 535102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 536102cedc3SLeonid Yegoshin dec_insn.pc_inc + 537102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 538102cedc3SLeonid Yegoshin else 539102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 540102cedc3SLeonid Yegoshin dec_insn.pc_inc + 541102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 542102cedc3SLeonid Yegoshin return 1; 543102cedc3SLeonid Yegoshin case bgtz_op: 544102cedc3SLeonid Yegoshin case bgtzl_op: 545102cedc3SLeonid Yegoshin if ((long)regs->regs[insn.i_format.rs] > 0) 546102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 547102cedc3SLeonid Yegoshin dec_insn.pc_inc + 548102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 549102cedc3SLeonid Yegoshin else 550102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 551102cedc3SLeonid Yegoshin dec_insn.pc_inc + 552102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 553102cedc3SLeonid Yegoshin return 1; 554c26d4219SDavid Daney #ifdef CONFIG_CPU_CAVIUM_OCTEON 555c26d4219SDavid Daney case lwc2_op: /* This is bbit0 on Octeon */ 556c26d4219SDavid Daney if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 557c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 558c26d4219SDavid Daney else 559c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 560c26d4219SDavid Daney return 1; 561c26d4219SDavid Daney case ldc2_op: /* This is bbit032 on Octeon */ 562c26d4219SDavid Daney if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 563c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 564c26d4219SDavid Daney else 565c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 566c26d4219SDavid Daney return 1; 567c26d4219SDavid Daney case swc2_op: /* This is bbit1 on Octeon */ 568c26d4219SDavid Daney if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 569c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 570c26d4219SDavid Daney else 571c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 572c26d4219SDavid Daney return 1; 573c26d4219SDavid Daney case sdc2_op: /* This is bbit132 on Octeon */ 574c26d4219SDavid Daney if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 575c26d4219SDavid Daney *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 576c26d4219SDavid Daney else 577c26d4219SDavid Daney *contpc = regs->cp0_epc + 8; 578c26d4219SDavid Daney return 1; 579c26d4219SDavid Daney #endif 5801da177e4SLinus Torvalds case cop0_op: 5811da177e4SLinus Torvalds case cop1_op: 5821da177e4SLinus Torvalds case cop2_op: 5831da177e4SLinus Torvalds case cop1x_op: 584102cedc3SLeonid Yegoshin if (insn.i_format.rs == bc_op) { 585102cedc3SLeonid Yegoshin preempt_disable(); 586102cedc3SLeonid Yegoshin if (is_fpu_owner()) 587102cedc3SLeonid Yegoshin asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 588102cedc3SLeonid Yegoshin else 589102cedc3SLeonid Yegoshin fcr31 = current->thread.fpu.fcr31; 590102cedc3SLeonid Yegoshin preempt_enable(); 591102cedc3SLeonid Yegoshin 592102cedc3SLeonid Yegoshin bit = (insn.i_format.rt >> 2); 593102cedc3SLeonid Yegoshin bit += (bit != 0); 594102cedc3SLeonid Yegoshin bit += 23; 595102cedc3SLeonid Yegoshin switch (insn.i_format.rt & 3) { 596102cedc3SLeonid Yegoshin case 0: /* bc1f */ 597102cedc3SLeonid Yegoshin case 2: /* bc1fl */ 598102cedc3SLeonid Yegoshin if (~fcr31 & (1 << bit)) 599102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 600102cedc3SLeonid Yegoshin dec_insn.pc_inc + 601102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 602102cedc3SLeonid Yegoshin else 603102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 604102cedc3SLeonid Yegoshin dec_insn.pc_inc + 605102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 606102cedc3SLeonid Yegoshin return 1; 607102cedc3SLeonid Yegoshin case 1: /* bc1t */ 608102cedc3SLeonid Yegoshin case 3: /* bc1tl */ 609102cedc3SLeonid Yegoshin if (fcr31 & (1 << bit)) 610102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 611102cedc3SLeonid Yegoshin dec_insn.pc_inc + 612102cedc3SLeonid Yegoshin (insn.i_format.simmediate << 2); 613102cedc3SLeonid Yegoshin else 614102cedc3SLeonid Yegoshin *contpc = regs->cp0_epc + 615102cedc3SLeonid Yegoshin dec_insn.pc_inc + 616102cedc3SLeonid Yegoshin dec_insn.next_pc_inc; 6171da177e4SLinus Torvalds return 1; 6181da177e4SLinus Torvalds } 619102cedc3SLeonid Yegoshin } 620102cedc3SLeonid Yegoshin break; 621102cedc3SLeonid Yegoshin } 6221da177e4SLinus Torvalds return 0; 6231da177e4SLinus Torvalds } 6241da177e4SLinus Torvalds 6251da177e4SLinus Torvalds /* 6261da177e4SLinus Torvalds * In the Linux kernel, we support selection of FPR format on the 627da0bac33SDavid Daney * basis of the Status.FR bit. If an FPU is not present, the FR bit 628da0bac33SDavid Daney * is hardwired to zero, which would imply a 32-bit FPU even for 629597ce172SPaul Burton * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 63051d943f0SRalf Baechle * FPU emu is slow and bulky and optimizing this function offers fairly 63151d943f0SRalf Baechle * sizeable benefits so we try to be clever and make this function return 63251d943f0SRalf Baechle * a constant whenever possible, that is on 64-bit kernels without O32 633597ce172SPaul Burton * compatibility enabled and on 32-bit without 64-bit FPU support. 6341da177e4SLinus Torvalds */ 635da0bac33SDavid Daney static inline int cop1_64bit(struct pt_regs *xcp) 636da0bac33SDavid Daney { 63708a07904SRalf Baechle if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) 63851d943f0SRalf Baechle return 1; 63908a07904SRalf Baechle else if (config_enabled(CONFIG_32BIT) && 64008a07904SRalf Baechle !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 641da0bac33SDavid Daney return 0; 64208a07904SRalf Baechle 643597ce172SPaul Burton return !test_thread_flag(TIF_32BIT_FPREGS); 644da0bac33SDavid Daney } 6451da177e4SLinus Torvalds 64647fa0c02SRalf Baechle #define SIFROMREG(si, x) \ 64747fa0c02SRalf Baechle do { \ 648bbd426f5SPaul Burton if (cop1_64bit(xcp)) \ 649bbd426f5SPaul Burton (si) = get_fpr32(&ctx->fpr[x], 0); \ 650bbd426f5SPaul Burton else \ 651bbd426f5SPaul Burton (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 652bbd426f5SPaul Burton } while (0) 653da0bac33SDavid Daney 65447fa0c02SRalf Baechle #define SITOREG(si, x) \ 65547fa0c02SRalf Baechle do { \ 656ef1c47afSPaul Burton if (cop1_64bit(xcp)) { \ 657ef1c47afSPaul Burton unsigned i; \ 658bbd426f5SPaul Burton set_fpr32(&ctx->fpr[x], 0, si); \ 659ef1c47afSPaul Burton for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 660ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], i, 0); \ 661ef1c47afSPaul Burton } else { \ 662bbd426f5SPaul Burton set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 663ef1c47afSPaul Burton } \ 664bbd426f5SPaul Burton } while (0) 6651da177e4SLinus Torvalds 666bbd426f5SPaul Burton #define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1)) 667ef1c47afSPaul Burton 66847fa0c02SRalf Baechle #define SITOHREG(si, x) \ 66947fa0c02SRalf Baechle do { \ 670ef1c47afSPaul Burton unsigned i; \ 671ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], 1, si); \ 672ef1c47afSPaul Burton for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 673ef1c47afSPaul Burton set_fpr32(&ctx->fpr[x], i, 0); \ 674ef1c47afSPaul Burton } while (0) 6751ac94400SLeonid Yegoshin 676bbd426f5SPaul Burton #define DIFROMREG(di, x) \ 677bbd426f5SPaul Burton ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) 678bbd426f5SPaul Burton 67947fa0c02SRalf Baechle #define DITOREG(di, x) \ 68047fa0c02SRalf Baechle do { \ 681ef1c47afSPaul Burton unsigned fpr, i; \ 682ef1c47afSPaul Burton fpr = (x) & ~(cop1_64bit(xcp) == 0); \ 683ef1c47afSPaul Burton set_fpr64(&ctx->fpr[fpr], 0, di); \ 684ef1c47afSPaul Burton for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 685ef1c47afSPaul Burton set_fpr64(&ctx->fpr[fpr], i, 0); \ 686ef1c47afSPaul Burton } while (0) 6871da177e4SLinus Torvalds 6881da177e4SLinus Torvalds #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 6891da177e4SLinus Torvalds #define SPTOREG(sp, x) SITOREG((sp).bits, x) 6901da177e4SLinus Torvalds #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 6911da177e4SLinus Torvalds #define DPTOREG(dp, x) DITOREG((dp).bits, x) 6921da177e4SLinus Torvalds 6931da177e4SLinus Torvalds /* 6941da177e4SLinus Torvalds * Emulate the single floating point instruction pointed at by EPC. 6951da177e4SLinus Torvalds * Two instructions if the instruction is in a branch delay slot. 6961da177e4SLinus Torvalds */ 6971da177e4SLinus Torvalds 698515b029dSDavid Daney static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 699102cedc3SLeonid Yegoshin struct mm_decoded_insn dec_insn, void *__user *fault_addr) 7001da177e4SLinus Torvalds { 701102cedc3SLeonid Yegoshin unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 7023f7cac41SRalf Baechle unsigned int cond, cbit; 7033f7cac41SRalf Baechle mips_instruction ir; 7043f7cac41SRalf Baechle int likely, pc_inc; 7053f7cac41SRalf Baechle u32 __user *wva; 7063f7cac41SRalf Baechle u64 __user *dva; 7073f7cac41SRalf Baechle u32 value; 7083f7cac41SRalf Baechle u32 wval; 7093f7cac41SRalf Baechle u64 dval; 7103f7cac41SRalf Baechle int sig; 7111da177e4SLinus Torvalds 7121da177e4SLinus Torvalds /* XXX NEC Vr54xx bug workaround */ 713e7e9cae5SRalf Baechle if (delay_slot(xcp)) { 714102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 715102cedc3SLeonid Yegoshin if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 716e7e9cae5SRalf Baechle clear_delay_slot(xcp); 717102cedc3SLeonid Yegoshin } else { 718102cedc3SLeonid Yegoshin if (!isBranchInstr(xcp, dec_insn, &contpc)) 719e7e9cae5SRalf Baechle clear_delay_slot(xcp); 720102cedc3SLeonid Yegoshin } 721102cedc3SLeonid Yegoshin } 7221da177e4SLinus Torvalds 723e7e9cae5SRalf Baechle if (delay_slot(xcp)) { 7241da177e4SLinus Torvalds /* 7251da177e4SLinus Torvalds * The instruction to be emulated is in a branch delay slot 7261da177e4SLinus Torvalds * which means that we have to emulate the branch instruction 7271da177e4SLinus Torvalds * BEFORE we do the cop1 instruction. 7281da177e4SLinus Torvalds * 7291da177e4SLinus Torvalds * This branch could be a COP1 branch, but in that case we 7301da177e4SLinus Torvalds * would have had a trap for that instruction, and would not 7311da177e4SLinus Torvalds * come through this route. 7321da177e4SLinus Torvalds * 7331da177e4SLinus Torvalds * Linux MIPS branch emulator operates on context, updating the 7341da177e4SLinus Torvalds * cp0_epc. 7351da177e4SLinus Torvalds */ 736102cedc3SLeonid Yegoshin ir = dec_insn.next_insn; /* process delay slot instr */ 737102cedc3SLeonid Yegoshin pc_inc = dec_insn.next_pc_inc; 738333d1f67SRalf Baechle } else { 739102cedc3SLeonid Yegoshin ir = dec_insn.insn; /* process current instr */ 740102cedc3SLeonid Yegoshin pc_inc = dec_insn.pc_inc; 741102cedc3SLeonid Yegoshin } 742102cedc3SLeonid Yegoshin 743102cedc3SLeonid Yegoshin /* 744102cedc3SLeonid Yegoshin * Since microMIPS FPU instructios are a subset of MIPS32 FPU 745102cedc3SLeonid Yegoshin * instructions, we want to convert microMIPS FPU instructions 746102cedc3SLeonid Yegoshin * into MIPS32 instructions so that we could reuse all of the 747102cedc3SLeonid Yegoshin * FPU emulation code. 748102cedc3SLeonid Yegoshin * 749102cedc3SLeonid Yegoshin * NOTE: We cannot do this for branch instructions since they 750102cedc3SLeonid Yegoshin * are not a subset. Example: Cannot emulate a 16-bit 751102cedc3SLeonid Yegoshin * aligned target address with a MIPS32 instruction. 752102cedc3SLeonid Yegoshin */ 753102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 754102cedc3SLeonid Yegoshin /* 755102cedc3SLeonid Yegoshin * If next instruction is a 16-bit instruction, then it 756102cedc3SLeonid Yegoshin * it cannot be a FPU instruction. This could happen 757102cedc3SLeonid Yegoshin * since we can be called for non-FPU instructions. 758102cedc3SLeonid Yegoshin */ 759102cedc3SLeonid Yegoshin if ((pc_inc == 2) || 760102cedc3SLeonid Yegoshin (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 761102cedc3SLeonid Yegoshin == SIGILL)) 762102cedc3SLeonid Yegoshin return SIGILL; 7631da177e4SLinus Torvalds } 7641da177e4SLinus Torvalds 7651da177e4SLinus Torvalds emul: 766a8b0ca17SPeter Zijlstra perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 767b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(emulated); 7681da177e4SLinus Torvalds switch (MIPSInst_OPCODE(ir)) { 7693f7cac41SRalf Baechle case ldc1_op: 7703f7cac41SRalf Baechle dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 7711da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 772b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 773515b029dSDavid Daney 7743f7cac41SRalf Baechle if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { 775b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 7763f7cac41SRalf Baechle *fault_addr = dva; 7771da177e4SLinus Torvalds return SIGBUS; 7781da177e4SLinus Torvalds } 7793f7cac41SRalf Baechle if (__get_user(dval, dva)) { 780515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 7813f7cac41SRalf Baechle *fault_addr = dva; 782515b029dSDavid Daney return SIGSEGV; 783515b029dSDavid Daney } 7843f7cac41SRalf Baechle DITOREG(dval, MIPSInst_RT(ir)); 7851da177e4SLinus Torvalds break; 7861da177e4SLinus Torvalds 7873f7cac41SRalf Baechle case sdc1_op: 7883f7cac41SRalf Baechle dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 7891da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 790b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 7913f7cac41SRalf Baechle DIFROMREG(dval, MIPSInst_RT(ir)); 7923f7cac41SRalf Baechle if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { 793b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 7943f7cac41SRalf Baechle *fault_addr = dva; 7951da177e4SLinus Torvalds return SIGBUS; 7961da177e4SLinus Torvalds } 7973f7cac41SRalf Baechle if (__put_user(dval, dva)) { 798515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 7993f7cac41SRalf Baechle *fault_addr = dva; 800515b029dSDavid Daney return SIGSEGV; 801515b029dSDavid Daney } 8021da177e4SLinus Torvalds break; 8031da177e4SLinus Torvalds 8043f7cac41SRalf Baechle case lwc1_op: 8053f7cac41SRalf Baechle wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 8061da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 807b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 8083f7cac41SRalf Baechle if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { 809b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 8103f7cac41SRalf Baechle *fault_addr = wva; 8111da177e4SLinus Torvalds return SIGBUS; 8121da177e4SLinus Torvalds } 8133f7cac41SRalf Baechle if (__get_user(wval, wva)) { 814515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 8153f7cac41SRalf Baechle *fault_addr = wva; 816515b029dSDavid Daney return SIGSEGV; 817515b029dSDavid Daney } 8183f7cac41SRalf Baechle SITOREG(wval, MIPSInst_RT(ir)); 8191da177e4SLinus Torvalds break; 8201da177e4SLinus Torvalds 8213f7cac41SRalf Baechle case swc1_op: 8223f7cac41SRalf Baechle wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 8231da177e4SLinus Torvalds MIPSInst_SIMM(ir)); 824b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 8253f7cac41SRalf Baechle SIFROMREG(wval, MIPSInst_RT(ir)); 8263f7cac41SRalf Baechle if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { 827b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 8283f7cac41SRalf Baechle *fault_addr = wva; 8291da177e4SLinus Torvalds return SIGBUS; 8301da177e4SLinus Torvalds } 8313f7cac41SRalf Baechle if (__put_user(wval, wva)) { 832515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 8333f7cac41SRalf Baechle *fault_addr = wva; 834515b029dSDavid Daney return SIGSEGV; 835515b029dSDavid Daney } 8361da177e4SLinus Torvalds break; 8371da177e4SLinus Torvalds 8381da177e4SLinus Torvalds case cop1_op: 8391da177e4SLinus Torvalds switch (MIPSInst_RS(ir)) { 8401da177e4SLinus Torvalds case dmfc_op: 84108a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 84208a07904SRalf Baechle return SIGILL; 84308a07904SRalf Baechle 8441da177e4SLinus Torvalds /* copregister fs -> gpr[rt] */ 8451da177e4SLinus Torvalds if (MIPSInst_RT(ir) != 0) { 8461da177e4SLinus Torvalds DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 8471da177e4SLinus Torvalds MIPSInst_RD(ir)); 8481da177e4SLinus Torvalds } 8491da177e4SLinus Torvalds break; 8501da177e4SLinus Torvalds 8511da177e4SLinus Torvalds case dmtc_op: 85208a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 85308a07904SRalf Baechle return SIGILL; 85408a07904SRalf Baechle 8551da177e4SLinus Torvalds /* copregister fs <- rt */ 8561da177e4SLinus Torvalds DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 8571da177e4SLinus Torvalds break; 8581da177e4SLinus Torvalds 8591ac94400SLeonid Yegoshin case mfhc_op: 8601ac94400SLeonid Yegoshin if (!cpu_has_mips_r2) 8611ac94400SLeonid Yegoshin goto sigill; 8621ac94400SLeonid Yegoshin 8631ac94400SLeonid Yegoshin /* copregister rd -> gpr[rt] */ 8641ac94400SLeonid Yegoshin if (MIPSInst_RT(ir) != 0) { 8651ac94400SLeonid Yegoshin SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 8661ac94400SLeonid Yegoshin MIPSInst_RD(ir)); 8671ac94400SLeonid Yegoshin } 8681ac94400SLeonid Yegoshin break; 8691ac94400SLeonid Yegoshin 8701ac94400SLeonid Yegoshin case mthc_op: 8711ac94400SLeonid Yegoshin if (!cpu_has_mips_r2) 8721ac94400SLeonid Yegoshin goto sigill; 8731ac94400SLeonid Yegoshin 8741ac94400SLeonid Yegoshin /* copregister rd <- gpr[rt] */ 8751ac94400SLeonid Yegoshin SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 8761ac94400SLeonid Yegoshin break; 8771ac94400SLeonid Yegoshin 8781da177e4SLinus Torvalds case mfc_op: 8791da177e4SLinus Torvalds /* copregister rd -> gpr[rt] */ 8801da177e4SLinus Torvalds if (MIPSInst_RT(ir) != 0) { 8811da177e4SLinus Torvalds SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 8821da177e4SLinus Torvalds MIPSInst_RD(ir)); 8831da177e4SLinus Torvalds } 8841da177e4SLinus Torvalds break; 8851da177e4SLinus Torvalds 8861da177e4SLinus Torvalds case mtc_op: 8871da177e4SLinus Torvalds /* copregister rd <- rt */ 8881da177e4SLinus Torvalds SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 8891da177e4SLinus Torvalds break; 8901da177e4SLinus Torvalds 8913f7cac41SRalf Baechle case cfc_op: 8921da177e4SLinus Torvalds /* cop control register rd -> gpr[rt] */ 8931da177e4SLinus Torvalds if (MIPSInst_RD(ir) == FPCREG_CSR) { 8941da177e4SLinus Torvalds value = ctx->fcr31; 89556a64733SRalf Baechle value = (value & ~FPU_CSR_RM) | modeindex(value); 89692df0f8bSRalf Baechle pr_debug("%p gpr[%d]<-csr=%08x\n", 897333d1f67SRalf Baechle (void *) (xcp->cp0_epc), 8981da177e4SLinus Torvalds MIPSInst_RT(ir), value); 8991da177e4SLinus Torvalds } 9001da177e4SLinus Torvalds else if (MIPSInst_RD(ir) == FPCREG_RID) 9011da177e4SLinus Torvalds value = 0; 9021da177e4SLinus Torvalds else 9031da177e4SLinus Torvalds value = 0; 9041da177e4SLinus Torvalds if (MIPSInst_RT(ir)) 9051da177e4SLinus Torvalds xcp->regs[MIPSInst_RT(ir)] = value; 9061da177e4SLinus Torvalds break; 9071da177e4SLinus Torvalds 9083f7cac41SRalf Baechle case ctc_op: 9091da177e4SLinus Torvalds /* copregister rd <- rt */ 9101da177e4SLinus Torvalds if (MIPSInst_RT(ir) == 0) 9111da177e4SLinus Torvalds value = 0; 9121da177e4SLinus Torvalds else 9131da177e4SLinus Torvalds value = xcp->regs[MIPSInst_RT(ir)]; 9141da177e4SLinus Torvalds 9151da177e4SLinus Torvalds /* we only have one writable control reg 9161da177e4SLinus Torvalds */ 9171da177e4SLinus Torvalds if (MIPSInst_RD(ir) == FPCREG_CSR) { 91892df0f8bSRalf Baechle pr_debug("%p gpr[%d]->csr=%08x\n", 919333d1f67SRalf Baechle (void *) (xcp->cp0_epc), 9201da177e4SLinus Torvalds MIPSInst_RT(ir), value); 92195e8f634SShane McDonald 92295e8f634SShane McDonald /* 92395e8f634SShane McDonald * Don't write reserved bits, 92495e8f634SShane McDonald * and convert to ieee library modes 92595e8f634SShane McDonald */ 92656a64733SRalf Baechle ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) | 92756a64733SRalf Baechle modeindex(value); 9281da177e4SLinus Torvalds } 9291da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 9301da177e4SLinus Torvalds return SIGFPE; 9311da177e4SLinus Torvalds } 9321da177e4SLinus Torvalds break; 9331da177e4SLinus Torvalds 9343f7cac41SRalf Baechle case bc_op: 935e7e9cae5SRalf Baechle if (delay_slot(xcp)) 9361da177e4SLinus Torvalds return SIGILL; 9371da177e4SLinus Torvalds 93808a07904SRalf Baechle if (cpu_has_mips_4_5_r) 93908a07904SRalf Baechle cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 94008a07904SRalf Baechle else 94108a07904SRalf Baechle cbit = FPU_CSR_COND; 94208a07904SRalf Baechle cond = ctx->fcr31 & cbit; 94308a07904SRalf Baechle 9443f7cac41SRalf Baechle likely = 0; 9451da177e4SLinus Torvalds switch (MIPSInst_RT(ir) & 3) { 9461da177e4SLinus Torvalds case bcfl_op: 9471da177e4SLinus Torvalds likely = 1; 9481da177e4SLinus Torvalds case bcf_op: 9491da177e4SLinus Torvalds cond = !cond; 9501da177e4SLinus Torvalds break; 9511da177e4SLinus Torvalds case bctl_op: 9521da177e4SLinus Torvalds likely = 1; 9531da177e4SLinus Torvalds case bct_op: 9541da177e4SLinus Torvalds break; 9551da177e4SLinus Torvalds default: 9561da177e4SLinus Torvalds /* thats an illegal instruction */ 9571da177e4SLinus Torvalds return SIGILL; 9581da177e4SLinus Torvalds } 9591da177e4SLinus Torvalds 960e7e9cae5SRalf Baechle set_delay_slot(xcp); 9611da177e4SLinus Torvalds if (cond) { 9623f7cac41SRalf Baechle /* 9633f7cac41SRalf Baechle * Branch taken: emulate dslot instruction 9641da177e4SLinus Torvalds */ 965102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; 9661da177e4SLinus Torvalds 967102cedc3SLeonid Yegoshin contpc = MIPSInst_SIMM(ir); 968102cedc3SLeonid Yegoshin ir = dec_insn.next_insn; 969102cedc3SLeonid Yegoshin if (dec_insn.micro_mips_mode) { 970102cedc3SLeonid Yegoshin contpc = (xcp->cp0_epc + (contpc << 1)); 971102cedc3SLeonid Yegoshin 972102cedc3SLeonid Yegoshin /* If 16-bit instruction, not FPU. */ 973102cedc3SLeonid Yegoshin if ((dec_insn.next_pc_inc == 2) || 974102cedc3SLeonid Yegoshin (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 975102cedc3SLeonid Yegoshin 976102cedc3SLeonid Yegoshin /* 977102cedc3SLeonid Yegoshin * Since this instruction will 978102cedc3SLeonid Yegoshin * be put on the stack with 979102cedc3SLeonid Yegoshin * 32-bit words, get around 980102cedc3SLeonid Yegoshin * this problem by putting a 981102cedc3SLeonid Yegoshin * NOP16 as the second one. 982102cedc3SLeonid Yegoshin */ 983102cedc3SLeonid Yegoshin if (dec_insn.next_pc_inc == 2) 984102cedc3SLeonid Yegoshin ir = (ir & (~0xffff)) | MM_NOP16; 985102cedc3SLeonid Yegoshin 986102cedc3SLeonid Yegoshin /* 987102cedc3SLeonid Yegoshin * Single step the non-CP1 988102cedc3SLeonid Yegoshin * instruction in the dslot. 989102cedc3SLeonid Yegoshin */ 990102cedc3SLeonid Yegoshin return mips_dsemul(xcp, ir, contpc); 991515b029dSDavid Daney } 992102cedc3SLeonid Yegoshin } else 993102cedc3SLeonid Yegoshin contpc = (xcp->cp0_epc + (contpc << 2)); 9941da177e4SLinus Torvalds 9951da177e4SLinus Torvalds switch (MIPSInst_OPCODE(ir)) { 9961da177e4SLinus Torvalds case lwc1_op: 99708a07904SRalf Baechle goto emul; 9983f7cac41SRalf Baechle 9991da177e4SLinus Torvalds case swc1_op: 100008a07904SRalf Baechle goto emul; 10013f7cac41SRalf Baechle 10021da177e4SLinus Torvalds case ldc1_op: 10031da177e4SLinus Torvalds case sdc1_op: 100408a07904SRalf Baechle if (cpu_has_mips_2_3_4_5 || 100508a07904SRalf Baechle cpu_has_mips64) 100608a07904SRalf Baechle goto emul; 100708a07904SRalf Baechle 100808a07904SRalf Baechle return SIGILL; 100908a07904SRalf Baechle goto emul; 10103f7cac41SRalf Baechle 10111da177e4SLinus Torvalds case cop1_op: 101208a07904SRalf Baechle goto emul; 10133f7cac41SRalf Baechle 10141da177e4SLinus Torvalds case cop1x_op: 101508a07904SRalf Baechle if (cpu_has_mips_4_5 || cpu_has_mips64) 10161da177e4SLinus Torvalds /* its one of ours */ 10171da177e4SLinus Torvalds goto emul; 101808a07904SRalf Baechle 101908a07904SRalf Baechle return SIGILL; 10203f7cac41SRalf Baechle 10211da177e4SLinus Torvalds case spec_op: 102208a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 102308a07904SRalf Baechle return SIGILL; 102408a07904SRalf Baechle 10251da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) == movc_op) 10261da177e4SLinus Torvalds goto emul; 10271da177e4SLinus Torvalds break; 10281da177e4SLinus Torvalds } 10291da177e4SLinus Torvalds 10301da177e4SLinus Torvalds /* 10311da177e4SLinus Torvalds * Single step the non-cp1 10321da177e4SLinus Torvalds * instruction in the dslot 10331da177e4SLinus Torvalds */ 1034e70dfc10SAtsushi Nemoto return mips_dsemul(xcp, ir, contpc); 10353f7cac41SRalf Baechle } else if (likely) { /* branch not taken */ 10361da177e4SLinus Torvalds /* 10371da177e4SLinus Torvalds * branch likely nullifies 10381da177e4SLinus Torvalds * dslot if not taken 10391da177e4SLinus Torvalds */ 1040102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; 1041102cedc3SLeonid Yegoshin contpc += dec_insn.pc_inc; 10421da177e4SLinus Torvalds /* 10431da177e4SLinus Torvalds * else continue & execute 10441da177e4SLinus Torvalds * dslot as normal insn 10451da177e4SLinus Torvalds */ 10461da177e4SLinus Torvalds } 10471da177e4SLinus Torvalds break; 10481da177e4SLinus Torvalds 10491da177e4SLinus Torvalds default: 10501da177e4SLinus Torvalds if (!(MIPSInst_RS(ir) & 0x10)) 10511da177e4SLinus Torvalds return SIGILL; 10521da177e4SLinus Torvalds 10531da177e4SLinus Torvalds /* a real fpu computation instruction */ 10541da177e4SLinus Torvalds if ((sig = fpu_emu(xcp, ctx, ir))) 10551da177e4SLinus Torvalds return sig; 10561da177e4SLinus Torvalds } 10571da177e4SLinus Torvalds break; 10581da177e4SLinus Torvalds 10593f7cac41SRalf Baechle case cop1x_op: 106008a07904SRalf Baechle if (!cpu_has_mips_4_5 && !cpu_has_mips64) 106108a07904SRalf Baechle return SIGILL; 106208a07904SRalf Baechle 106308a07904SRalf Baechle sig = fpux_emu(xcp, ctx, ir, fault_addr); 1064515b029dSDavid Daney if (sig) 10651da177e4SLinus Torvalds return sig; 10661da177e4SLinus Torvalds break; 10671da177e4SLinus Torvalds 10681da177e4SLinus Torvalds case spec_op: 106908a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 107008a07904SRalf Baechle return SIGILL; 107108a07904SRalf Baechle 10721da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) != movc_op) 10731da177e4SLinus Torvalds return SIGILL; 10741da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 10751da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 10761da177e4SLinus Torvalds xcp->regs[MIPSInst_RD(ir)] = 10771da177e4SLinus Torvalds xcp->regs[MIPSInst_RS(ir)]; 10781da177e4SLinus Torvalds break; 10791da177e4SLinus Torvalds default: 10801ac94400SLeonid Yegoshin sigill: 10811da177e4SLinus Torvalds return SIGILL; 10821da177e4SLinus Torvalds } 10831da177e4SLinus Torvalds 10841da177e4SLinus Torvalds /* we did it !! */ 1085e70dfc10SAtsushi Nemoto xcp->cp0_epc = contpc; 1086e7e9cae5SRalf Baechle clear_delay_slot(xcp); 1087333d1f67SRalf Baechle 10881da177e4SLinus Torvalds return 0; 10891da177e4SLinus Torvalds } 10901da177e4SLinus Torvalds 10911da177e4SLinus Torvalds /* 10921da177e4SLinus Torvalds * Conversion table from MIPS compare ops 48-63 10931da177e4SLinus Torvalds * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 10941da177e4SLinus Torvalds */ 10951da177e4SLinus Torvalds static const unsigned char cmptab[8] = { 10961da177e4SLinus Torvalds 0, /* cmp_0 (sig) cmp_sf */ 10971da177e4SLinus Torvalds IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 10981da177e4SLinus Torvalds IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 10991da177e4SLinus Torvalds IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 11001da177e4SLinus Torvalds IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 11011da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 11021da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 11031da177e4SLinus Torvalds IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 11041da177e4SLinus Torvalds }; 11051da177e4SLinus Torvalds 11061da177e4SLinus Torvalds 11071da177e4SLinus Torvalds /* 11081da177e4SLinus Torvalds * Additional MIPS4 instructions 11091da177e4SLinus Torvalds */ 11101da177e4SLinus Torvalds 11111da177e4SLinus Torvalds #define DEF3OP(name, p, f1, f2, f3) \ 111247fa0c02SRalf Baechle static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ 111347fa0c02SRalf Baechle union ieee754##p s, union ieee754##p t) \ 11141da177e4SLinus Torvalds { \ 1115cd21dfcfSRalf Baechle struct _ieee754_csr ieee754_csr_save; \ 11161da177e4SLinus Torvalds s = f1(s, t); \ 11171da177e4SLinus Torvalds ieee754_csr_save = ieee754_csr; \ 11181da177e4SLinus Torvalds s = f2(s, r); \ 11191da177e4SLinus Torvalds ieee754_csr_save.cx |= ieee754_csr.cx; \ 11201da177e4SLinus Torvalds ieee754_csr_save.sx |= ieee754_csr.sx; \ 11211da177e4SLinus Torvalds s = f3(s); \ 11221da177e4SLinus Torvalds ieee754_csr.cx |= ieee754_csr_save.cx; \ 11231da177e4SLinus Torvalds ieee754_csr.sx |= ieee754_csr_save.sx; \ 11241da177e4SLinus Torvalds return s; \ 11251da177e4SLinus Torvalds } 11261da177e4SLinus Torvalds 11272209bcb1SRalf Baechle static union ieee754dp fpemu_dp_recip(union ieee754dp d) 11281da177e4SLinus Torvalds { 11291da177e4SLinus Torvalds return ieee754dp_div(ieee754dp_one(0), d); 11301da177e4SLinus Torvalds } 11311da177e4SLinus Torvalds 11322209bcb1SRalf Baechle static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 11331da177e4SLinus Torvalds { 11341da177e4SLinus Torvalds return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 11351da177e4SLinus Torvalds } 11361da177e4SLinus Torvalds 11372209bcb1SRalf Baechle static union ieee754sp fpemu_sp_recip(union ieee754sp s) 11381da177e4SLinus Torvalds { 11391da177e4SLinus Torvalds return ieee754sp_div(ieee754sp_one(0), s); 11401da177e4SLinus Torvalds } 11411da177e4SLinus Torvalds 11422209bcb1SRalf Baechle static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 11431da177e4SLinus Torvalds { 11441da177e4SLinus Torvalds return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 11451da177e4SLinus Torvalds } 11461da177e4SLinus Torvalds 11471da177e4SLinus Torvalds DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 11481da177e4SLinus Torvalds DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 11491da177e4SLinus Torvalds DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 11501da177e4SLinus Torvalds DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 11511da177e4SLinus Torvalds DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 11521da177e4SLinus Torvalds DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 11531da177e4SLinus Torvalds DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 11541da177e4SLinus Torvalds DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 11551da177e4SLinus Torvalds 1156eae89076SAtsushi Nemoto static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1157515b029dSDavid Daney mips_instruction ir, void *__user *fault_addr) 11581da177e4SLinus Torvalds { 11591da177e4SLinus Torvalds unsigned rcsr = 0; /* resulting csr */ 11601da177e4SLinus Torvalds 1161b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(cp1xops); 11621da177e4SLinus Torvalds 11631da177e4SLinus Torvalds switch (MIPSInst_FMA_FFMT(ir)) { 11641da177e4SLinus Torvalds case s_fmt:{ /* 0 */ 11651da177e4SLinus Torvalds 11662209bcb1SRalf Baechle union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 11672209bcb1SRalf Baechle union ieee754sp fd, fr, fs, ft; 11683fccc015SRalf Baechle u32 __user *va; 11691da177e4SLinus Torvalds u32 val; 11701da177e4SLinus Torvalds 11711da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 11721da177e4SLinus Torvalds case lwxc1_op: 11733fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 11741da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 11751da177e4SLinus Torvalds 1176b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 1177515b029dSDavid Daney if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1178b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1179515b029dSDavid Daney *fault_addr = va; 11801da177e4SLinus Torvalds return SIGBUS; 11811da177e4SLinus Torvalds } 1182515b029dSDavid Daney if (__get_user(val, va)) { 1183515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1184515b029dSDavid Daney *fault_addr = va; 1185515b029dSDavid Daney return SIGSEGV; 1186515b029dSDavid Daney } 11871da177e4SLinus Torvalds SITOREG(val, MIPSInst_FD(ir)); 11881da177e4SLinus Torvalds break; 11891da177e4SLinus Torvalds 11901da177e4SLinus Torvalds case swxc1_op: 11913fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 11921da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 11931da177e4SLinus Torvalds 1194b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 11951da177e4SLinus Torvalds 11961da177e4SLinus Torvalds SIFROMREG(val, MIPSInst_FS(ir)); 1197515b029dSDavid Daney if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1198515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1199515b029dSDavid Daney *fault_addr = va; 1200515b029dSDavid Daney return SIGBUS; 1201515b029dSDavid Daney } 12021da177e4SLinus Torvalds if (put_user(val, va)) { 1203b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1204515b029dSDavid Daney *fault_addr = va; 1205515b029dSDavid Daney return SIGSEGV; 12061da177e4SLinus Torvalds } 12071da177e4SLinus Torvalds break; 12081da177e4SLinus Torvalds 12091da177e4SLinus Torvalds case madd_s_op: 12101da177e4SLinus Torvalds handler = fpemu_sp_madd; 12111da177e4SLinus Torvalds goto scoptop; 12121da177e4SLinus Torvalds case msub_s_op: 12131da177e4SLinus Torvalds handler = fpemu_sp_msub; 12141da177e4SLinus Torvalds goto scoptop; 12151da177e4SLinus Torvalds case nmadd_s_op: 12161da177e4SLinus Torvalds handler = fpemu_sp_nmadd; 12171da177e4SLinus Torvalds goto scoptop; 12181da177e4SLinus Torvalds case nmsub_s_op: 12191da177e4SLinus Torvalds handler = fpemu_sp_nmsub; 12201da177e4SLinus Torvalds goto scoptop; 12211da177e4SLinus Torvalds 12221da177e4SLinus Torvalds scoptop: 12231da177e4SLinus Torvalds SPFROMREG(fr, MIPSInst_FR(ir)); 12241da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 12251da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 12261da177e4SLinus Torvalds fd = (*handler) (fr, fs, ft); 12271da177e4SLinus Torvalds SPTOREG(fd, MIPSInst_FD(ir)); 12281da177e4SLinus Torvalds 12291da177e4SLinus Torvalds copcsr: 12301da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INEXACT)) 12311da177e4SLinus Torvalds rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 12321da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_UNDERFLOW)) 12331da177e4SLinus Torvalds rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 12341da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_OVERFLOW)) 12351da177e4SLinus Torvalds rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 12361da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 12371da177e4SLinus Torvalds rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 12381da177e4SLinus Torvalds 12391da177e4SLinus Torvalds ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 12401da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 12413f7cac41SRalf Baechle /*printk ("SIGFPE: FPU csr = %08x\n", 12421da177e4SLinus Torvalds ctx->fcr31); */ 12431da177e4SLinus Torvalds return SIGFPE; 12441da177e4SLinus Torvalds } 12451da177e4SLinus Torvalds 12461da177e4SLinus Torvalds break; 12471da177e4SLinus Torvalds 12481da177e4SLinus Torvalds default: 12491da177e4SLinus Torvalds return SIGILL; 12501da177e4SLinus Torvalds } 12511da177e4SLinus Torvalds break; 12521da177e4SLinus Torvalds } 12531da177e4SLinus Torvalds 12541da177e4SLinus Torvalds case d_fmt:{ /* 1 */ 12552209bcb1SRalf Baechle union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 12562209bcb1SRalf Baechle union ieee754dp fd, fr, fs, ft; 12573fccc015SRalf Baechle u64 __user *va; 12581da177e4SLinus Torvalds u64 val; 12591da177e4SLinus Torvalds 12601da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 12611da177e4SLinus Torvalds case ldxc1_op: 12623fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 12631da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 12641da177e4SLinus Torvalds 1265b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(loads); 1266515b029dSDavid Daney if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1267b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1268515b029dSDavid Daney *fault_addr = va; 12691da177e4SLinus Torvalds return SIGBUS; 12701da177e4SLinus Torvalds } 1271515b029dSDavid Daney if (__get_user(val, va)) { 1272515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1273515b029dSDavid Daney *fault_addr = va; 1274515b029dSDavid Daney return SIGSEGV; 1275515b029dSDavid Daney } 12761da177e4SLinus Torvalds DITOREG(val, MIPSInst_FD(ir)); 12771da177e4SLinus Torvalds break; 12781da177e4SLinus Torvalds 12791da177e4SLinus Torvalds case sdxc1_op: 12803fccc015SRalf Baechle va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 12811da177e4SLinus Torvalds xcp->regs[MIPSInst_FT(ir)]); 12821da177e4SLinus Torvalds 1283b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(stores); 12841da177e4SLinus Torvalds DIFROMREG(val, MIPSInst_FS(ir)); 1285515b029dSDavid Daney if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1286b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1287515b029dSDavid Daney *fault_addr = va; 12881da177e4SLinus Torvalds return SIGBUS; 12891da177e4SLinus Torvalds } 1290515b029dSDavid Daney if (__put_user(val, va)) { 1291515b029dSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 1292515b029dSDavid Daney *fault_addr = va; 1293515b029dSDavid Daney return SIGSEGV; 1294515b029dSDavid Daney } 12951da177e4SLinus Torvalds break; 12961da177e4SLinus Torvalds 12971da177e4SLinus Torvalds case madd_d_op: 12981da177e4SLinus Torvalds handler = fpemu_dp_madd; 12991da177e4SLinus Torvalds goto dcoptop; 13001da177e4SLinus Torvalds case msub_d_op: 13011da177e4SLinus Torvalds handler = fpemu_dp_msub; 13021da177e4SLinus Torvalds goto dcoptop; 13031da177e4SLinus Torvalds case nmadd_d_op: 13041da177e4SLinus Torvalds handler = fpemu_dp_nmadd; 13051da177e4SLinus Torvalds goto dcoptop; 13061da177e4SLinus Torvalds case nmsub_d_op: 13071da177e4SLinus Torvalds handler = fpemu_dp_nmsub; 13081da177e4SLinus Torvalds goto dcoptop; 13091da177e4SLinus Torvalds 13101da177e4SLinus Torvalds dcoptop: 13111da177e4SLinus Torvalds DPFROMREG(fr, MIPSInst_FR(ir)); 13121da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 13131da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 13141da177e4SLinus Torvalds fd = (*handler) (fr, fs, ft); 13151da177e4SLinus Torvalds DPTOREG(fd, MIPSInst_FD(ir)); 13161da177e4SLinus Torvalds goto copcsr; 13171da177e4SLinus Torvalds 13181da177e4SLinus Torvalds default: 13191da177e4SLinus Torvalds return SIGILL; 13201da177e4SLinus Torvalds } 13211da177e4SLinus Torvalds break; 13221da177e4SLinus Torvalds } 13231da177e4SLinus Torvalds 132451061b88SDeng-Cheng Zhu case 0x3: 132551061b88SDeng-Cheng Zhu if (MIPSInst_FUNC(ir) != pfetch_op) 13261da177e4SLinus Torvalds return SIGILL; 132751061b88SDeng-Cheng Zhu 13281da177e4SLinus Torvalds /* ignore prefx operation */ 13291da177e4SLinus Torvalds break; 13301da177e4SLinus Torvalds 13311da177e4SLinus Torvalds default: 13321da177e4SLinus Torvalds return SIGILL; 13331da177e4SLinus Torvalds } 13341da177e4SLinus Torvalds 13351da177e4SLinus Torvalds return 0; 13361da177e4SLinus Torvalds } 13371da177e4SLinus Torvalds 13381da177e4SLinus Torvalds 13391da177e4SLinus Torvalds 13401da177e4SLinus Torvalds /* 13411da177e4SLinus Torvalds * Emulate a single COP1 arithmetic instruction. 13421da177e4SLinus Torvalds */ 1343eae89076SAtsushi Nemoto static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 13441da177e4SLinus Torvalds mips_instruction ir) 13451da177e4SLinus Torvalds { 13461da177e4SLinus Torvalds int rfmt; /* resulting format */ 13471da177e4SLinus Torvalds unsigned rcsr = 0; /* resulting csr */ 13483f7cac41SRalf Baechle unsigned int oldrm; 13493f7cac41SRalf Baechle unsigned int cbit; 13501da177e4SLinus Torvalds unsigned cond; 13511da177e4SLinus Torvalds union { 13522209bcb1SRalf Baechle union ieee754dp d; 13532209bcb1SRalf Baechle union ieee754sp s; 13541da177e4SLinus Torvalds int w; 13551da177e4SLinus Torvalds s64 l; 13561da177e4SLinus Torvalds } rv; /* resulting value */ 13573f7cac41SRalf Baechle u64 bits; 13581da177e4SLinus Torvalds 1359b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(cp1ops); 13601da177e4SLinus Torvalds switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 13611da177e4SLinus Torvalds case s_fmt: { /* 0 */ 13621da177e4SLinus Torvalds union { 13632209bcb1SRalf Baechle union ieee754sp(*b) (union ieee754sp, union ieee754sp); 13642209bcb1SRalf Baechle union ieee754sp(*u) (union ieee754sp); 13651da177e4SLinus Torvalds } handler; 13663f7cac41SRalf Baechle union ieee754sp fs, ft; 13671da177e4SLinus Torvalds 13681da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 13691da177e4SLinus Torvalds /* binary ops */ 13701da177e4SLinus Torvalds case fadd_op: 13711da177e4SLinus Torvalds handler.b = ieee754sp_add; 13721da177e4SLinus Torvalds goto scopbop; 13731da177e4SLinus Torvalds case fsub_op: 13741da177e4SLinus Torvalds handler.b = ieee754sp_sub; 13751da177e4SLinus Torvalds goto scopbop; 13761da177e4SLinus Torvalds case fmul_op: 13771da177e4SLinus Torvalds handler.b = ieee754sp_mul; 13781da177e4SLinus Torvalds goto scopbop; 13791da177e4SLinus Torvalds case fdiv_op: 13801da177e4SLinus Torvalds handler.b = ieee754sp_div; 13811da177e4SLinus Torvalds goto scopbop; 13821da177e4SLinus Torvalds 13831da177e4SLinus Torvalds /* unary ops */ 13841da177e4SLinus Torvalds case fsqrt_op: 138508a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 138608a07904SRalf Baechle return SIGILL; 138708a07904SRalf Baechle 13881da177e4SLinus Torvalds handler.u = ieee754sp_sqrt; 13891da177e4SLinus Torvalds goto scopuop; 13903f7cac41SRalf Baechle 139108a07904SRalf Baechle /* 139208a07904SRalf Baechle * Note that on some MIPS IV implementations such as the 139308a07904SRalf Baechle * R5000 and R8000 the FSQRT and FRECIP instructions do not 139408a07904SRalf Baechle * achieve full IEEE-754 accuracy - however this emulator does. 139508a07904SRalf Baechle */ 13961da177e4SLinus Torvalds case frsqrt_op: 139708a07904SRalf Baechle if (!cpu_has_mips_4_5_r2) 139808a07904SRalf Baechle return SIGILL; 139908a07904SRalf Baechle 14001da177e4SLinus Torvalds handler.u = fpemu_sp_rsqrt; 14011da177e4SLinus Torvalds goto scopuop; 14023f7cac41SRalf Baechle 14031da177e4SLinus Torvalds case frecip_op: 140408a07904SRalf Baechle if (!cpu_has_mips_4_5_r2) 140508a07904SRalf Baechle return SIGILL; 140608a07904SRalf Baechle 14071da177e4SLinus Torvalds handler.u = fpemu_sp_recip; 14081da177e4SLinus Torvalds goto scopuop; 140908a07904SRalf Baechle 14101da177e4SLinus Torvalds case fmovc_op: 141108a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 141208a07904SRalf Baechle return SIGILL; 141308a07904SRalf Baechle 14141da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 14151da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) != 14161da177e4SLinus Torvalds ((MIPSInst_FT(ir) & 1) != 0)) 14171da177e4SLinus Torvalds return 0; 14181da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 14191da177e4SLinus Torvalds break; 14203f7cac41SRalf Baechle 14211da177e4SLinus Torvalds case fmovz_op: 142208a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 142308a07904SRalf Baechle return SIGILL; 142408a07904SRalf Baechle 14251da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] != 0) 14261da177e4SLinus Torvalds return 0; 14271da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 14281da177e4SLinus Torvalds break; 14293f7cac41SRalf Baechle 14301da177e4SLinus Torvalds case fmovn_op: 143108a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 143208a07904SRalf Baechle return SIGILL; 143308a07904SRalf Baechle 14341da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] == 0) 14351da177e4SLinus Torvalds return 0; 14361da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 14371da177e4SLinus Torvalds break; 14383f7cac41SRalf Baechle 14391da177e4SLinus Torvalds case fabs_op: 14401da177e4SLinus Torvalds handler.u = ieee754sp_abs; 14411da177e4SLinus Torvalds goto scopuop; 14423f7cac41SRalf Baechle 14431da177e4SLinus Torvalds case fneg_op: 14441da177e4SLinus Torvalds handler.u = ieee754sp_neg; 14451da177e4SLinus Torvalds goto scopuop; 14463f7cac41SRalf Baechle 14471da177e4SLinus Torvalds case fmov_op: 14481da177e4SLinus Torvalds /* an easy one */ 14491da177e4SLinus Torvalds SPFROMREG(rv.s, MIPSInst_FS(ir)); 14501da177e4SLinus Torvalds goto copcsr; 14511da177e4SLinus Torvalds 14521da177e4SLinus Torvalds /* binary op on handler */ 14531da177e4SLinus Torvalds scopbop: 14541da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 14551da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 14561da177e4SLinus Torvalds 14571da177e4SLinus Torvalds rv.s = (*handler.b) (fs, ft); 14581da177e4SLinus Torvalds goto copcsr; 14591da177e4SLinus Torvalds scopuop: 14601da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 14611da177e4SLinus Torvalds rv.s = (*handler.u) (fs); 14621da177e4SLinus Torvalds goto copcsr; 14631da177e4SLinus Torvalds copcsr: 14641da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INEXACT)) 14651da177e4SLinus Torvalds rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 14661da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_UNDERFLOW)) 14671da177e4SLinus Torvalds rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 14681da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_OVERFLOW)) 14691da177e4SLinus Torvalds rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 14701da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) 14711da177e4SLinus Torvalds rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 14721da177e4SLinus Torvalds if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 14731da177e4SLinus Torvalds rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 14741da177e4SLinus Torvalds break; 14751da177e4SLinus Torvalds 14761da177e4SLinus Torvalds /* unary conv ops */ 14771da177e4SLinus Torvalds case fcvts_op: 14781da177e4SLinus Torvalds return SIGILL; /* not defined */ 14791da177e4SLinus Torvalds 14803f7cac41SRalf Baechle case fcvtd_op: 14811da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 14821da177e4SLinus Torvalds rv.d = ieee754dp_fsp(fs); 14831da177e4SLinus Torvalds rfmt = d_fmt; 14841da177e4SLinus Torvalds goto copcsr; 14851da177e4SLinus Torvalds 14863f7cac41SRalf Baechle case fcvtw_op: 14871da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 14881da177e4SLinus Torvalds rv.w = ieee754sp_tint(fs); 14891da177e4SLinus Torvalds rfmt = w_fmt; 14901da177e4SLinus Torvalds goto copcsr; 14911da177e4SLinus Torvalds 14921da177e4SLinus Torvalds case fround_op: 14931da177e4SLinus Torvalds case ftrunc_op: 14941da177e4SLinus Torvalds case fceil_op: 14953f7cac41SRalf Baechle case ffloor_op: 149608a07904SRalf Baechle if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) 149708a07904SRalf Baechle return SIGILL; 149808a07904SRalf Baechle 14993f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 15001da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 150156a64733SRalf Baechle ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 15021da177e4SLinus Torvalds rv.w = ieee754sp_tint(fs); 15031da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 15041da177e4SLinus Torvalds rfmt = w_fmt; 15051da177e4SLinus Torvalds goto copcsr; 15061da177e4SLinus Torvalds 15073f7cac41SRalf Baechle case fcvtl_op: 150808a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 150908a07904SRalf Baechle return SIGILL; 151008a07904SRalf Baechle 15111da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 15121da177e4SLinus Torvalds rv.l = ieee754sp_tlong(fs); 15131da177e4SLinus Torvalds rfmt = l_fmt; 15141da177e4SLinus Torvalds goto copcsr; 15151da177e4SLinus Torvalds 15161da177e4SLinus Torvalds case froundl_op: 15171da177e4SLinus Torvalds case ftruncl_op: 15181da177e4SLinus Torvalds case fceill_op: 15193f7cac41SRalf Baechle case ffloorl_op: 152008a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 152108a07904SRalf Baechle return SIGILL; 152208a07904SRalf Baechle 15233f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 15241da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 152556a64733SRalf Baechle ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 15261da177e4SLinus Torvalds rv.l = ieee754sp_tlong(fs); 15271da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 15281da177e4SLinus Torvalds rfmt = l_fmt; 15291da177e4SLinus Torvalds goto copcsr; 15301da177e4SLinus Torvalds 15311da177e4SLinus Torvalds default: 15321da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) >= fcmp_op) { 15331da177e4SLinus Torvalds unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 15342209bcb1SRalf Baechle union ieee754sp fs, ft; 15351da177e4SLinus Torvalds 15361da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 15371da177e4SLinus Torvalds SPFROMREG(ft, MIPSInst_FT(ir)); 15381da177e4SLinus Torvalds rv.w = ieee754sp_cmp(fs, ft, 15391da177e4SLinus Torvalds cmptab[cmpop & 0x7], cmpop & 0x8); 15401da177e4SLinus Torvalds rfmt = -1; 15411da177e4SLinus Torvalds if ((cmpop & 0x8) && ieee754_cxtest 15421da177e4SLinus Torvalds (IEEE754_INVALID_OPERATION)) 15431da177e4SLinus Torvalds rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 15441da177e4SLinus Torvalds else 15451da177e4SLinus Torvalds goto copcsr; 15461da177e4SLinus Torvalds 15473f7cac41SRalf Baechle } else 15481da177e4SLinus Torvalds return SIGILL; 15491da177e4SLinus Torvalds break; 15501da177e4SLinus Torvalds } 15511da177e4SLinus Torvalds break; 15521da177e4SLinus Torvalds } 15531da177e4SLinus Torvalds 15541da177e4SLinus Torvalds case d_fmt: { 15553f7cac41SRalf Baechle union ieee754dp fs, ft; 15561da177e4SLinus Torvalds union { 15572209bcb1SRalf Baechle union ieee754dp(*b) (union ieee754dp, union ieee754dp); 15582209bcb1SRalf Baechle union ieee754dp(*u) (union ieee754dp); 15591da177e4SLinus Torvalds } handler; 15601da177e4SLinus Torvalds 15611da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 15621da177e4SLinus Torvalds /* binary ops */ 15631da177e4SLinus Torvalds case fadd_op: 15641da177e4SLinus Torvalds handler.b = ieee754dp_add; 15651da177e4SLinus Torvalds goto dcopbop; 15661da177e4SLinus Torvalds case fsub_op: 15671da177e4SLinus Torvalds handler.b = ieee754dp_sub; 15681da177e4SLinus Torvalds goto dcopbop; 15691da177e4SLinus Torvalds case fmul_op: 15701da177e4SLinus Torvalds handler.b = ieee754dp_mul; 15711da177e4SLinus Torvalds goto dcopbop; 15721da177e4SLinus Torvalds case fdiv_op: 15731da177e4SLinus Torvalds handler.b = ieee754dp_div; 15741da177e4SLinus Torvalds goto dcopbop; 15751da177e4SLinus Torvalds 15761da177e4SLinus Torvalds /* unary ops */ 15771da177e4SLinus Torvalds case fsqrt_op: 157808a07904SRalf Baechle if (!cpu_has_mips_2_3_4_5_r) 157908a07904SRalf Baechle return SIGILL; 158008a07904SRalf Baechle 15811da177e4SLinus Torvalds handler.u = ieee754dp_sqrt; 15821da177e4SLinus Torvalds goto dcopuop; 158308a07904SRalf Baechle /* 158408a07904SRalf Baechle * Note that on some MIPS IV implementations such as the 158508a07904SRalf Baechle * R5000 and R8000 the FSQRT and FRECIP instructions do not 158608a07904SRalf Baechle * achieve full IEEE-754 accuracy - however this emulator does. 158708a07904SRalf Baechle */ 15881da177e4SLinus Torvalds case frsqrt_op: 158908a07904SRalf Baechle if (!cpu_has_mips_4_5_r2) 159008a07904SRalf Baechle return SIGILL; 159108a07904SRalf Baechle 15921da177e4SLinus Torvalds handler.u = fpemu_dp_rsqrt; 15931da177e4SLinus Torvalds goto dcopuop; 15941da177e4SLinus Torvalds case frecip_op: 159508a07904SRalf Baechle if (!cpu_has_mips_4_5_r2) 159608a07904SRalf Baechle return SIGILL; 159708a07904SRalf Baechle 15981da177e4SLinus Torvalds handler.u = fpemu_dp_recip; 15991da177e4SLinus Torvalds goto dcopuop; 16001da177e4SLinus Torvalds case fmovc_op: 160108a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 160208a07904SRalf Baechle return SIGILL; 160308a07904SRalf Baechle 16041da177e4SLinus Torvalds cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 16051da177e4SLinus Torvalds if (((ctx->fcr31 & cond) != 0) != 16061da177e4SLinus Torvalds ((MIPSInst_FT(ir) & 1) != 0)) 16071da177e4SLinus Torvalds return 0; 16081da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 16091da177e4SLinus Torvalds break; 16101da177e4SLinus Torvalds case fmovz_op: 161108a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 161208a07904SRalf Baechle return SIGILL; 161308a07904SRalf Baechle 16141da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] != 0) 16151da177e4SLinus Torvalds return 0; 16161da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 16171da177e4SLinus Torvalds break; 16181da177e4SLinus Torvalds case fmovn_op: 161908a07904SRalf Baechle if (!cpu_has_mips_4_5_r) 162008a07904SRalf Baechle return SIGILL; 162108a07904SRalf Baechle 16221da177e4SLinus Torvalds if (xcp->regs[MIPSInst_FT(ir)] == 0) 16231da177e4SLinus Torvalds return 0; 16241da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 16251da177e4SLinus Torvalds break; 16261da177e4SLinus Torvalds case fabs_op: 16271da177e4SLinus Torvalds handler.u = ieee754dp_abs; 16281da177e4SLinus Torvalds goto dcopuop; 16291da177e4SLinus Torvalds 16301da177e4SLinus Torvalds case fneg_op: 16311da177e4SLinus Torvalds handler.u = ieee754dp_neg; 16321da177e4SLinus Torvalds goto dcopuop; 16331da177e4SLinus Torvalds 16341da177e4SLinus Torvalds case fmov_op: 16351da177e4SLinus Torvalds /* an easy one */ 16361da177e4SLinus Torvalds DPFROMREG(rv.d, MIPSInst_FS(ir)); 16371da177e4SLinus Torvalds goto copcsr; 16381da177e4SLinus Torvalds 16391da177e4SLinus Torvalds /* binary op on handler */ 16403f7cac41SRalf Baechle dcopbop: 16411da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 16421da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 16431da177e4SLinus Torvalds 16441da177e4SLinus Torvalds rv.d = (*handler.b) (fs, ft); 16451da177e4SLinus Torvalds goto copcsr; 16463f7cac41SRalf Baechle dcopuop: 16471da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 16481da177e4SLinus Torvalds rv.d = (*handler.u) (fs); 16491da177e4SLinus Torvalds goto copcsr; 16501da177e4SLinus Torvalds 16513f7cac41SRalf Baechle /* 16523f7cac41SRalf Baechle * unary conv ops 16533f7cac41SRalf Baechle */ 16543f7cac41SRalf Baechle case fcvts_op: 16551da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 16561da177e4SLinus Torvalds rv.s = ieee754sp_fdp(fs); 16571da177e4SLinus Torvalds rfmt = s_fmt; 16581da177e4SLinus Torvalds goto copcsr; 16593f7cac41SRalf Baechle 16601da177e4SLinus Torvalds case fcvtd_op: 16611da177e4SLinus Torvalds return SIGILL; /* not defined */ 16621da177e4SLinus Torvalds 16633f7cac41SRalf Baechle case fcvtw_op: 16641da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 16651da177e4SLinus Torvalds rv.w = ieee754dp_tint(fs); /* wrong */ 16661da177e4SLinus Torvalds rfmt = w_fmt; 16671da177e4SLinus Torvalds goto copcsr; 16681da177e4SLinus Torvalds 16691da177e4SLinus Torvalds case fround_op: 16701da177e4SLinus Torvalds case ftrunc_op: 16711da177e4SLinus Torvalds case fceil_op: 16723f7cac41SRalf Baechle case ffloor_op: 167308a07904SRalf Baechle if (!cpu_has_mips_2_3_4_5_r) 167408a07904SRalf Baechle return SIGILL; 167508a07904SRalf Baechle 16763f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 16771da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 167856a64733SRalf Baechle ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 16791da177e4SLinus Torvalds rv.w = ieee754dp_tint(fs); 16801da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 16811da177e4SLinus Torvalds rfmt = w_fmt; 16821da177e4SLinus Torvalds goto copcsr; 16831da177e4SLinus Torvalds 16843f7cac41SRalf Baechle case fcvtl_op: 168508a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 168608a07904SRalf Baechle return SIGILL; 168708a07904SRalf Baechle 16881da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 16891da177e4SLinus Torvalds rv.l = ieee754dp_tlong(fs); 16901da177e4SLinus Torvalds rfmt = l_fmt; 16911da177e4SLinus Torvalds goto copcsr; 16921da177e4SLinus Torvalds 16931da177e4SLinus Torvalds case froundl_op: 16941da177e4SLinus Torvalds case ftruncl_op: 16951da177e4SLinus Torvalds case fceill_op: 16963f7cac41SRalf Baechle case ffloorl_op: 169708a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 169808a07904SRalf Baechle return SIGILL; 169908a07904SRalf Baechle 17003f7cac41SRalf Baechle oldrm = ieee754_csr.rm; 17011da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 170256a64733SRalf Baechle ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 17031da177e4SLinus Torvalds rv.l = ieee754dp_tlong(fs); 17041da177e4SLinus Torvalds ieee754_csr.rm = oldrm; 17051da177e4SLinus Torvalds rfmt = l_fmt; 17061da177e4SLinus Torvalds goto copcsr; 17071da177e4SLinus Torvalds 17081da177e4SLinus Torvalds default: 17091da177e4SLinus Torvalds if (MIPSInst_FUNC(ir) >= fcmp_op) { 17101da177e4SLinus Torvalds unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 17112209bcb1SRalf Baechle union ieee754dp fs, ft; 17121da177e4SLinus Torvalds 17131da177e4SLinus Torvalds DPFROMREG(fs, MIPSInst_FS(ir)); 17141da177e4SLinus Torvalds DPFROMREG(ft, MIPSInst_FT(ir)); 17151da177e4SLinus Torvalds rv.w = ieee754dp_cmp(fs, ft, 17161da177e4SLinus Torvalds cmptab[cmpop & 0x7], cmpop & 0x8); 17171da177e4SLinus Torvalds rfmt = -1; 17181da177e4SLinus Torvalds if ((cmpop & 0x8) 17191da177e4SLinus Torvalds && 17201da177e4SLinus Torvalds ieee754_cxtest 17211da177e4SLinus Torvalds (IEEE754_INVALID_OPERATION)) 17221da177e4SLinus Torvalds rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 17231da177e4SLinus Torvalds else 17241da177e4SLinus Torvalds goto copcsr; 17251da177e4SLinus Torvalds 17261da177e4SLinus Torvalds } 17271da177e4SLinus Torvalds else { 17281da177e4SLinus Torvalds return SIGILL; 17291da177e4SLinus Torvalds } 17301da177e4SLinus Torvalds break; 17311da177e4SLinus Torvalds } 17321da177e4SLinus Torvalds break; 17331da177e4SLinus Torvalds 17343f7cac41SRalf Baechle case w_fmt: 17351da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 17361da177e4SLinus Torvalds case fcvts_op: 17371da177e4SLinus Torvalds /* convert word to single precision real */ 17381da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17391da177e4SLinus Torvalds rv.s = ieee754sp_fint(fs.bits); 17401da177e4SLinus Torvalds rfmt = s_fmt; 17411da177e4SLinus Torvalds goto copcsr; 17421da177e4SLinus Torvalds case fcvtd_op: 17431da177e4SLinus Torvalds /* convert word to double precision real */ 17441da177e4SLinus Torvalds SPFROMREG(fs, MIPSInst_FS(ir)); 17451da177e4SLinus Torvalds rv.d = ieee754dp_fint(fs.bits); 17461da177e4SLinus Torvalds rfmt = d_fmt; 17471da177e4SLinus Torvalds goto copcsr; 17481da177e4SLinus Torvalds default: 17491da177e4SLinus Torvalds return SIGILL; 17501da177e4SLinus Torvalds } 17511da177e4SLinus Torvalds break; 17521da177e4SLinus Torvalds } 17531da177e4SLinus Torvalds 17543f7cac41SRalf Baechle case l_fmt: 175508a07904SRalf Baechle 175608a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 175708a07904SRalf Baechle return SIGILL; 175808a07904SRalf Baechle 1759bbd426f5SPaul Burton DIFROMREG(bits, MIPSInst_FS(ir)); 1760bbd426f5SPaul Burton 17611da177e4SLinus Torvalds switch (MIPSInst_FUNC(ir)) { 17621da177e4SLinus Torvalds case fcvts_op: 17631da177e4SLinus Torvalds /* convert long to single precision real */ 1764bbd426f5SPaul Burton rv.s = ieee754sp_flong(bits); 17651da177e4SLinus Torvalds rfmt = s_fmt; 17661da177e4SLinus Torvalds goto copcsr; 17671da177e4SLinus Torvalds case fcvtd_op: 17681da177e4SLinus Torvalds /* convert long to double precision real */ 1769bbd426f5SPaul Burton rv.d = ieee754dp_flong(bits); 17701da177e4SLinus Torvalds rfmt = d_fmt; 17711da177e4SLinus Torvalds goto copcsr; 17721da177e4SLinus Torvalds default: 17731da177e4SLinus Torvalds return SIGILL; 17741da177e4SLinus Torvalds } 17751da177e4SLinus Torvalds break; 17761da177e4SLinus Torvalds 17771da177e4SLinus Torvalds default: 17781da177e4SLinus Torvalds return SIGILL; 17791da177e4SLinus Torvalds } 17801da177e4SLinus Torvalds 17811da177e4SLinus Torvalds /* 17821da177e4SLinus Torvalds * Update the fpu CSR register for this operation. 17831da177e4SLinus Torvalds * If an exception is required, generate a tidy SIGFPE exception, 17841da177e4SLinus Torvalds * without updating the result register. 17851da177e4SLinus Torvalds * Note: cause exception bits do not accumulate, they are rewritten 17861da177e4SLinus Torvalds * for each op; only the flag/sticky bits accumulate. 17871da177e4SLinus Torvalds */ 17881da177e4SLinus Torvalds ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 17891da177e4SLinus Torvalds if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 17903f7cac41SRalf Baechle /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ 17911da177e4SLinus Torvalds return SIGFPE; 17921da177e4SLinus Torvalds } 17931da177e4SLinus Torvalds 17941da177e4SLinus Torvalds /* 17951da177e4SLinus Torvalds * Now we can safely write the result back to the register file. 17961da177e4SLinus Torvalds */ 17971da177e4SLinus Torvalds switch (rfmt) { 179808a07904SRalf Baechle case -1: 179908a07904SRalf Baechle 180008a07904SRalf Baechle if (cpu_has_mips_4_5_r) 180108a07904SRalf Baechle cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 18021da177e4SLinus Torvalds else 180308a07904SRalf Baechle cbit = FPU_CSR_COND; 180408a07904SRalf Baechle if (rv.w) 180508a07904SRalf Baechle ctx->fcr31 |= cbit; 180608a07904SRalf Baechle else 180708a07904SRalf Baechle ctx->fcr31 &= ~cbit; 18081da177e4SLinus Torvalds break; 180908a07904SRalf Baechle 18101da177e4SLinus Torvalds case d_fmt: 18111da177e4SLinus Torvalds DPTOREG(rv.d, MIPSInst_FD(ir)); 18121da177e4SLinus Torvalds break; 18131da177e4SLinus Torvalds case s_fmt: 18141da177e4SLinus Torvalds SPTOREG(rv.s, MIPSInst_FD(ir)); 18151da177e4SLinus Torvalds break; 18161da177e4SLinus Torvalds case w_fmt: 18171da177e4SLinus Torvalds SITOREG(rv.w, MIPSInst_FD(ir)); 18181da177e4SLinus Torvalds break; 18191da177e4SLinus Torvalds case l_fmt: 182008a07904SRalf Baechle if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 182108a07904SRalf Baechle return SIGILL; 182208a07904SRalf Baechle 18231da177e4SLinus Torvalds DITOREG(rv.l, MIPSInst_FD(ir)); 18241da177e4SLinus Torvalds break; 18251da177e4SLinus Torvalds default: 18261da177e4SLinus Torvalds return SIGILL; 18271da177e4SLinus Torvalds } 18281da177e4SLinus Torvalds 18291da177e4SLinus Torvalds return 0; 18301da177e4SLinus Torvalds } 18311da177e4SLinus Torvalds 1832e04582b7SAtsushi Nemoto int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1833515b029dSDavid Daney int has_fpu, void *__user *fault_addr) 18341da177e4SLinus Torvalds { 1835333d1f67SRalf Baechle unsigned long oldepc, prevepc; 1836102cedc3SLeonid Yegoshin struct mm_decoded_insn dec_insn; 1837102cedc3SLeonid Yegoshin u16 instr[4]; 1838102cedc3SLeonid Yegoshin u16 *instr_ptr; 18391da177e4SLinus Torvalds int sig = 0; 18401da177e4SLinus Torvalds 18411da177e4SLinus Torvalds oldepc = xcp->cp0_epc; 18421da177e4SLinus Torvalds do { 18431da177e4SLinus Torvalds prevepc = xcp->cp0_epc; 18441da177e4SLinus Torvalds 1845102cedc3SLeonid Yegoshin if (get_isa16_mode(prevepc) && cpu_has_mmips) { 1846102cedc3SLeonid Yegoshin /* 1847102cedc3SLeonid Yegoshin * Get next 2 microMIPS instructions and convert them 1848102cedc3SLeonid Yegoshin * into 32-bit instructions. 1849102cedc3SLeonid Yegoshin */ 1850102cedc3SLeonid Yegoshin if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 1851102cedc3SLeonid Yegoshin (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 1852102cedc3SLeonid Yegoshin (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 1853102cedc3SLeonid Yegoshin (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 1854b6ee75edSDavid Daney MIPS_FPU_EMU_INC_STATS(errors); 18551da177e4SLinus Torvalds return SIGBUS; 18561da177e4SLinus Torvalds } 1857102cedc3SLeonid Yegoshin instr_ptr = instr; 1858102cedc3SLeonid Yegoshin 1859102cedc3SLeonid Yegoshin /* Get first instruction. */ 1860102cedc3SLeonid Yegoshin if (mm_insn_16bit(*instr_ptr)) { 1861102cedc3SLeonid Yegoshin /* Duplicate the half-word. */ 1862102cedc3SLeonid Yegoshin dec_insn.insn = (*instr_ptr << 16) | 1863102cedc3SLeonid Yegoshin (*instr_ptr); 1864102cedc3SLeonid Yegoshin /* 16-bit instruction. */ 1865102cedc3SLeonid Yegoshin dec_insn.pc_inc = 2; 1866102cedc3SLeonid Yegoshin instr_ptr += 1; 1867102cedc3SLeonid Yegoshin } else { 1868102cedc3SLeonid Yegoshin dec_insn.insn = (*instr_ptr << 16) | 1869102cedc3SLeonid Yegoshin *(instr_ptr+1); 1870102cedc3SLeonid Yegoshin /* 32-bit instruction. */ 1871102cedc3SLeonid Yegoshin dec_insn.pc_inc = 4; 1872102cedc3SLeonid Yegoshin instr_ptr += 2; 1873515b029dSDavid Daney } 1874102cedc3SLeonid Yegoshin /* Get second instruction. */ 1875102cedc3SLeonid Yegoshin if (mm_insn_16bit(*instr_ptr)) { 1876102cedc3SLeonid Yegoshin /* Duplicate the half-word. */ 1877102cedc3SLeonid Yegoshin dec_insn.next_insn = (*instr_ptr << 16) | 1878102cedc3SLeonid Yegoshin (*instr_ptr); 1879102cedc3SLeonid Yegoshin /* 16-bit instruction. */ 1880102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 2; 1881102cedc3SLeonid Yegoshin } else { 1882102cedc3SLeonid Yegoshin dec_insn.next_insn = (*instr_ptr << 16) | 1883102cedc3SLeonid Yegoshin *(instr_ptr+1); 1884102cedc3SLeonid Yegoshin /* 32-bit instruction. */ 1885102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 4; 1886102cedc3SLeonid Yegoshin } 1887102cedc3SLeonid Yegoshin dec_insn.micro_mips_mode = 1; 1888102cedc3SLeonid Yegoshin } else { 1889102cedc3SLeonid Yegoshin if ((get_user(dec_insn.insn, 1890102cedc3SLeonid Yegoshin (mips_instruction __user *) xcp->cp0_epc)) || 1891102cedc3SLeonid Yegoshin (get_user(dec_insn.next_insn, 1892102cedc3SLeonid Yegoshin (mips_instruction __user *)(xcp->cp0_epc+4)))) { 1893102cedc3SLeonid Yegoshin MIPS_FPU_EMU_INC_STATS(errors); 1894102cedc3SLeonid Yegoshin return SIGBUS; 1895102cedc3SLeonid Yegoshin } 1896102cedc3SLeonid Yegoshin dec_insn.pc_inc = 4; 1897102cedc3SLeonid Yegoshin dec_insn.next_pc_inc = 4; 1898102cedc3SLeonid Yegoshin dec_insn.micro_mips_mode = 0; 1899102cedc3SLeonid Yegoshin } 1900102cedc3SLeonid Yegoshin 1901102cedc3SLeonid Yegoshin if ((dec_insn.insn == 0) || 1902102cedc3SLeonid Yegoshin ((dec_insn.pc_inc == 2) && 1903102cedc3SLeonid Yegoshin ((dec_insn.insn & 0xffff) == MM_NOP16))) 1904102cedc3SLeonid Yegoshin xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 19051da177e4SLinus Torvalds else { 1906cd21dfcfSRalf Baechle /* 1907cd21dfcfSRalf Baechle * The 'ieee754_csr' is an alias of 1908cd21dfcfSRalf Baechle * ctx->fcr31. No need to copy ctx->fcr31 to 1909cd21dfcfSRalf Baechle * ieee754_csr. But ieee754_csr.rm is ieee 1910cd21dfcfSRalf Baechle * library modes. (not mips rounding mode) 1911cd21dfcfSRalf Baechle */ 1912102cedc3SLeonid Yegoshin sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 19131da177e4SLinus Torvalds } 19141da177e4SLinus Torvalds 1915e04582b7SAtsushi Nemoto if (has_fpu) 19161da177e4SLinus Torvalds break; 19171da177e4SLinus Torvalds if (sig) 19181da177e4SLinus Torvalds break; 19191da177e4SLinus Torvalds 19201da177e4SLinus Torvalds cond_resched(); 19211da177e4SLinus Torvalds } while (xcp->cp0_epc > prevepc); 19221da177e4SLinus Torvalds 19231da177e4SLinus Torvalds /* SIGILL indicates a non-fpu instruction */ 19241da177e4SLinus Torvalds if (sig == SIGILL && xcp->cp0_epc != oldepc) 19253f7cac41SRalf Baechle /* but if EPC has advanced, then ignore it */ 19261da177e4SLinus Torvalds sig = 0; 19271da177e4SLinus Torvalds 19281da177e4SLinus Torvalds return sig; 19291da177e4SLinus Torvalds } 1930