1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2010, 2011, 2012, Lemote, Inc. 4 * Author: Chen Huacai, chenhc@lemote.com 5 */ 6 7 #include <irq.h> 8 #include <linux/init.h> 9 #include <linux/cpu.h> 10 #include <linux/sched.h> 11 #include <linux/sched/hotplug.h> 12 #include <linux/sched/task_stack.h> 13 #include <linux/smp.h> 14 #include <linux/cpufreq.h> 15 #include <linux/kexec.h> 16 #include <asm/processor.h> 17 #include <asm/smp.h> 18 #include <asm/time.h> 19 #include <asm/tlbflush.h> 20 #include <asm/cacheflush.h> 21 #include <loongson.h> 22 #include <loongson_regs.h> 23 #include <workarounds.h> 24 25 #include "smp.h" 26 27 DEFINE_PER_CPU(int, cpu_state); 28 29 #define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6) 30 31 static void *ipi_set0_regs[16]; 32 static void *ipi_clear0_regs[16]; 33 static void *ipi_status0_regs[16]; 34 static void *ipi_en0_regs[16]; 35 static void *ipi_mailbox_buf[16]; 36 static uint32_t core0_c0count[NR_CPUS]; 37 38 /* read a 32bit value from ipi register */ 39 #define loongson3_ipi_read32(addr) readl(addr) 40 /* read a 64bit value from ipi register */ 41 #define loongson3_ipi_read64(addr) readq(addr) 42 /* write a 32bit value to ipi register */ 43 #define loongson3_ipi_write32(action, addr) \ 44 do { \ 45 writel(action, addr); \ 46 __wbflush(); \ 47 } while (0) 48 /* write a 64bit value to ipi register */ 49 #define loongson3_ipi_write64(action, addr) \ 50 do { \ 51 writeq(action, addr); \ 52 __wbflush(); \ 53 } while (0) 54 55 static u32 (*ipi_read_clear)(int cpu); 56 static void (*ipi_write_action)(int cpu, u32 action); 57 static void (*ipi_write_enable)(int cpu); 58 static void (*ipi_clear_buf)(int cpu); 59 static void (*ipi_write_buf)(int cpu, struct task_struct *idle); 60 61 /* send mail via Mail_Send register for 3A4000+ CPU */ 62 static void csr_mail_send(uint64_t data, int cpu, int mailbox) 63 { 64 uint64_t val; 65 66 /* send high 32 bits */ 67 val = CSR_MAIL_SEND_BLOCK; 68 val |= (CSR_MAIL_SEND_BOX_HIGH(mailbox) << CSR_MAIL_SEND_BOX_SHIFT); 69 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); 70 val |= (data & CSR_MAIL_SEND_H32_MASK); 71 csr_writeq(val, LOONGSON_CSR_MAIL_SEND); 72 73 /* send low 32 bits */ 74 val = CSR_MAIL_SEND_BLOCK; 75 val |= (CSR_MAIL_SEND_BOX_LOW(mailbox) << CSR_MAIL_SEND_BOX_SHIFT); 76 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); 77 val |= (data << CSR_MAIL_SEND_BUF_SHIFT); 78 csr_writeq(val, LOONGSON_CSR_MAIL_SEND); 79 }; 80 81 static u32 csr_ipi_read_clear(int cpu) 82 { 83 u32 action; 84 85 /* Load the ipi register to figure out what we're supposed to do */ 86 action = csr_readl(LOONGSON_CSR_IPI_STATUS); 87 /* Clear the ipi register to clear the interrupt */ 88 csr_writel(action, LOONGSON_CSR_IPI_CLEAR); 89 90 return action; 91 } 92 93 static void csr_ipi_write_action(int cpu, u32 action) 94 { 95 unsigned int irq = 0; 96 97 while ((irq = ffs(action))) { 98 uint32_t val = CSR_IPI_SEND_BLOCK; 99 val |= (irq - 1); 100 val |= (cpu << CSR_IPI_SEND_CPU_SHIFT); 101 csr_writel(val, LOONGSON_CSR_IPI_SEND); 102 action &= ~BIT(irq - 1); 103 } 104 } 105 106 static void csr_ipi_write_enable(int cpu) 107 { 108 csr_writel(0xffffffff, LOONGSON_CSR_IPI_EN); 109 } 110 111 static void csr_ipi_clear_buf(int cpu) 112 { 113 csr_writeq(0, LOONGSON_CSR_MAIL_BUF0); 114 } 115 116 static void csr_ipi_write_buf(int cpu, struct task_struct *idle) 117 { 118 unsigned long startargs[4]; 119 120 /* startargs[] are initial PC, SP and GP for secondary CPU */ 121 startargs[0] = (unsigned long)&smp_bootstrap; 122 startargs[1] = (unsigned long)__KSTK_TOS(idle); 123 startargs[2] = (unsigned long)task_thread_info(idle); 124 startargs[3] = 0; 125 126 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", 127 cpu, startargs[0], startargs[1], startargs[2]); 128 129 csr_mail_send(startargs[3], cpu_logical_map(cpu), 3); 130 csr_mail_send(startargs[2], cpu_logical_map(cpu), 2); 131 csr_mail_send(startargs[1], cpu_logical_map(cpu), 1); 132 csr_mail_send(startargs[0], cpu_logical_map(cpu), 0); 133 } 134 135 static u32 legacy_ipi_read_clear(int cpu) 136 { 137 u32 action; 138 139 /* Load the ipi register to figure out what we're supposed to do */ 140 action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]); 141 /* Clear the ipi register to clear the interrupt */ 142 loongson3_ipi_write32(action, ipi_clear0_regs[cpu_logical_map(cpu)]); 143 144 return action; 145 } 146 147 static void legacy_ipi_write_action(int cpu, u32 action) 148 { 149 loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]); 150 } 151 152 static void legacy_ipi_write_enable(int cpu) 153 { 154 loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); 155 } 156 157 static void legacy_ipi_clear_buf(int cpu) 158 { 159 loongson3_ipi_write64(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); 160 } 161 162 static void legacy_ipi_write_buf(int cpu, struct task_struct *idle) 163 { 164 unsigned long startargs[4]; 165 166 /* startargs[] are initial PC, SP and GP for secondary CPU */ 167 startargs[0] = (unsigned long)&smp_bootstrap; 168 startargs[1] = (unsigned long)__KSTK_TOS(idle); 169 startargs[2] = (unsigned long)task_thread_info(idle); 170 startargs[3] = 0; 171 172 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", 173 cpu, startargs[0], startargs[1], startargs[2]); 174 175 loongson3_ipi_write64(startargs[3], 176 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18); 177 loongson3_ipi_write64(startargs[2], 178 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10); 179 loongson3_ipi_write64(startargs[1], 180 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8); 181 loongson3_ipi_write64(startargs[0], 182 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); 183 } 184 185 static void csr_ipi_probe(void) 186 { 187 if (cpu_has_csr() && csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_IPI) { 188 ipi_read_clear = csr_ipi_read_clear; 189 ipi_write_action = csr_ipi_write_action; 190 ipi_write_enable = csr_ipi_write_enable; 191 ipi_clear_buf = csr_ipi_clear_buf; 192 ipi_write_buf = csr_ipi_write_buf; 193 } else { 194 ipi_read_clear = legacy_ipi_read_clear; 195 ipi_write_action = legacy_ipi_write_action; 196 ipi_write_enable = legacy_ipi_write_enable; 197 ipi_clear_buf = legacy_ipi_clear_buf; 198 ipi_write_buf = legacy_ipi_write_buf; 199 } 200 } 201 202 static void ipi_set0_regs_init(void) 203 { 204 ipi_set0_regs[0] = (void *) 205 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0); 206 ipi_set0_regs[1] = (void *) 207 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0); 208 ipi_set0_regs[2] = (void *) 209 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0); 210 ipi_set0_regs[3] = (void *) 211 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0); 212 ipi_set0_regs[4] = (void *) 213 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0); 214 ipi_set0_regs[5] = (void *) 215 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0); 216 ipi_set0_regs[6] = (void *) 217 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0); 218 ipi_set0_regs[7] = (void *) 219 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0); 220 ipi_set0_regs[8] = (void *) 221 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0); 222 ipi_set0_regs[9] = (void *) 223 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0); 224 ipi_set0_regs[10] = (void *) 225 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0); 226 ipi_set0_regs[11] = (void *) 227 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0); 228 ipi_set0_regs[12] = (void *) 229 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0); 230 ipi_set0_regs[13] = (void *) 231 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0); 232 ipi_set0_regs[14] = (void *) 233 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0); 234 ipi_set0_regs[15] = (void *) 235 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0); 236 } 237 238 static void ipi_clear0_regs_init(void) 239 { 240 ipi_clear0_regs[0] = (void *) 241 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0); 242 ipi_clear0_regs[1] = (void *) 243 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0); 244 ipi_clear0_regs[2] = (void *) 245 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0); 246 ipi_clear0_regs[3] = (void *) 247 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0); 248 ipi_clear0_regs[4] = (void *) 249 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0); 250 ipi_clear0_regs[5] = (void *) 251 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0); 252 ipi_clear0_regs[6] = (void *) 253 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0); 254 ipi_clear0_regs[7] = (void *) 255 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0); 256 ipi_clear0_regs[8] = (void *) 257 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0); 258 ipi_clear0_regs[9] = (void *) 259 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0); 260 ipi_clear0_regs[10] = (void *) 261 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0); 262 ipi_clear0_regs[11] = (void *) 263 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0); 264 ipi_clear0_regs[12] = (void *) 265 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0); 266 ipi_clear0_regs[13] = (void *) 267 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0); 268 ipi_clear0_regs[14] = (void *) 269 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0); 270 ipi_clear0_regs[15] = (void *) 271 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0); 272 } 273 274 static void ipi_status0_regs_init(void) 275 { 276 ipi_status0_regs[0] = (void *) 277 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0); 278 ipi_status0_regs[1] = (void *) 279 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0); 280 ipi_status0_regs[2] = (void *) 281 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0); 282 ipi_status0_regs[3] = (void *) 283 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0); 284 ipi_status0_regs[4] = (void *) 285 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0); 286 ipi_status0_regs[5] = (void *) 287 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0); 288 ipi_status0_regs[6] = (void *) 289 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0); 290 ipi_status0_regs[7] = (void *) 291 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0); 292 ipi_status0_regs[8] = (void *) 293 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0); 294 ipi_status0_regs[9] = (void *) 295 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0); 296 ipi_status0_regs[10] = (void *) 297 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0); 298 ipi_status0_regs[11] = (void *) 299 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0); 300 ipi_status0_regs[12] = (void *) 301 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0); 302 ipi_status0_regs[13] = (void *) 303 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0); 304 ipi_status0_regs[14] = (void *) 305 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0); 306 ipi_status0_regs[15] = (void *) 307 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0); 308 } 309 310 static void ipi_en0_regs_init(void) 311 { 312 ipi_en0_regs[0] = (void *) 313 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0); 314 ipi_en0_regs[1] = (void *) 315 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0); 316 ipi_en0_regs[2] = (void *) 317 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0); 318 ipi_en0_regs[3] = (void *) 319 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0); 320 ipi_en0_regs[4] = (void *) 321 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0); 322 ipi_en0_regs[5] = (void *) 323 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0); 324 ipi_en0_regs[6] = (void *) 325 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0); 326 ipi_en0_regs[7] = (void *) 327 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0); 328 ipi_en0_regs[8] = (void *) 329 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0); 330 ipi_en0_regs[9] = (void *) 331 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0); 332 ipi_en0_regs[10] = (void *) 333 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0); 334 ipi_en0_regs[11] = (void *) 335 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0); 336 ipi_en0_regs[12] = (void *) 337 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0); 338 ipi_en0_regs[13] = (void *) 339 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0); 340 ipi_en0_regs[14] = (void *) 341 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0); 342 ipi_en0_regs[15] = (void *) 343 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0); 344 } 345 346 static void ipi_mailbox_buf_init(void) 347 { 348 ipi_mailbox_buf[0] = (void *) 349 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF); 350 ipi_mailbox_buf[1] = (void *) 351 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF); 352 ipi_mailbox_buf[2] = (void *) 353 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF); 354 ipi_mailbox_buf[3] = (void *) 355 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF); 356 ipi_mailbox_buf[4] = (void *) 357 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF); 358 ipi_mailbox_buf[5] = (void *) 359 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF); 360 ipi_mailbox_buf[6] = (void *) 361 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF); 362 ipi_mailbox_buf[7] = (void *) 363 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF); 364 ipi_mailbox_buf[8] = (void *) 365 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF); 366 ipi_mailbox_buf[9] = (void *) 367 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF); 368 ipi_mailbox_buf[10] = (void *) 369 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF); 370 ipi_mailbox_buf[11] = (void *) 371 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF); 372 ipi_mailbox_buf[12] = (void *) 373 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF); 374 ipi_mailbox_buf[13] = (void *) 375 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF); 376 ipi_mailbox_buf[14] = (void *) 377 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF); 378 ipi_mailbox_buf[15] = (void *) 379 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF); 380 } 381 382 /* 383 * Simple enough, just poke the appropriate ipi register 384 */ 385 static void loongson3_send_ipi_single(int cpu, unsigned int action) 386 { 387 ipi_write_action(cpu_logical_map(cpu), (u32)action); 388 } 389 390 static void 391 loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) 392 { 393 unsigned int i; 394 395 for_each_cpu(i, mask) 396 ipi_write_action(cpu_logical_map(i), (u32)action); 397 } 398 399 400 static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) 401 { 402 int i, cpu = smp_processor_id(); 403 unsigned int action, c0count; 404 405 action = ipi_read_clear(cpu); 406 407 if (action & SMP_RESCHEDULE_YOURSELF) 408 scheduler_ipi(); 409 410 if (action & SMP_CALL_FUNCTION) { 411 irq_enter(); 412 generic_smp_call_function_interrupt(); 413 irq_exit(); 414 } 415 416 if (action & SMP_ASK_C0COUNT) { 417 BUG_ON(cpu != 0); 418 c0count = read_c0_count(); 419 c0count = c0count ? c0count : 1; 420 for (i = 1; i < nr_cpu_ids; i++) 421 core0_c0count[i] = c0count; 422 __wbflush(); /* Let others see the result ASAP */ 423 } 424 425 return IRQ_HANDLED; 426 } 427 428 #define MAX_LOOPS 800 429 /* 430 * SMP init and finish on secondary CPUs 431 */ 432 static void loongson3_init_secondary(void) 433 { 434 int i; 435 uint32_t initcount; 436 unsigned int cpu = smp_processor_id(); 437 unsigned int imask = STATUSF_IP7 | STATUSF_IP6 | 438 STATUSF_IP3 | STATUSF_IP2; 439 440 /* Set interrupt mask, but don't enable */ 441 change_c0_status(ST0_IM, imask); 442 ipi_write_enable(cpu); 443 444 per_cpu(cpu_state, cpu) = CPU_ONLINE; 445 cpu_set_core(&cpu_data[cpu], 446 cpu_logical_map(cpu) % loongson_sysconf.cores_per_package); 447 cpu_data[cpu].package = 448 cpu_logical_map(cpu) / loongson_sysconf.cores_per_package; 449 450 i = 0; 451 core0_c0count[cpu] = 0; 452 loongson3_send_ipi_single(0, SMP_ASK_C0COUNT); 453 while (!core0_c0count[cpu]) { 454 i++; 455 cpu_relax(); 456 } 457 458 if (i > MAX_LOOPS) 459 i = MAX_LOOPS; 460 if (cpu_data[cpu].package) 461 initcount = core0_c0count[cpu] + i; 462 else /* Local access is faster for loops */ 463 initcount = core0_c0count[cpu] + i/2; 464 465 write_c0_count(initcount); 466 } 467 468 static void loongson3_smp_finish(void) 469 { 470 int cpu = smp_processor_id(); 471 472 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); 473 local_irq_enable(); 474 ipi_clear_buf(cpu); 475 476 pr_info("CPU#%d finished, CP0_ST=%x\n", 477 smp_processor_id(), read_c0_status()); 478 } 479 480 static void __init loongson3_smp_setup(void) 481 { 482 int i = 0, num = 0; /* i: physical id, num: logical id */ 483 484 init_cpu_possible(cpu_none_mask); 485 486 /* For unified kernel, NR_CPUS is the maximum possible value, 487 * loongson_sysconf.nr_cpus is the really present value 488 */ 489 while (i < loongson_sysconf.nr_cpus) { 490 if (loongson_sysconf.reserved_cpus_mask & (1<<i)) { 491 /* Reserved physical CPU cores */ 492 __cpu_number_map[i] = -1; 493 } else { 494 __cpu_number_map[i] = num; 495 __cpu_logical_map[num] = i; 496 set_cpu_possible(num, true); 497 /* Loongson processors are always grouped by 4 */ 498 cpu_set_cluster(&cpu_data[num], i / 4); 499 num++; 500 } 501 i++; 502 } 503 pr_info("Detected %i available CPU(s)\n", num); 504 505 while (num < loongson_sysconf.nr_cpus) { 506 __cpu_logical_map[num] = -1; 507 num++; 508 } 509 510 csr_ipi_probe(); 511 ipi_set0_regs_init(); 512 ipi_clear0_regs_init(); 513 ipi_status0_regs_init(); 514 ipi_en0_regs_init(); 515 ipi_mailbox_buf_init(); 516 ipi_write_enable(0); 517 518 cpu_set_core(&cpu_data[0], 519 cpu_logical_map(0) % loongson_sysconf.cores_per_package); 520 cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package; 521 } 522 523 static void __init loongson3_prepare_cpus(unsigned int max_cpus) 524 { 525 if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt, 526 IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL)) 527 pr_err("Failed to request IPI IRQ\n"); 528 init_cpu_present(cpu_possible_mask); 529 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 530 } 531 532 /* 533 * Setup the PC, SP, and GP of a secondary processor and start it runing! 534 */ 535 static int loongson3_boot_secondary(int cpu, struct task_struct *idle) 536 { 537 pr_info("Booting CPU#%d...\n", cpu); 538 539 ipi_write_buf(cpu, idle); 540 541 return 0; 542 } 543 544 #ifdef CONFIG_HOTPLUG_CPU 545 546 static int loongson3_cpu_disable(void) 547 { 548 unsigned long flags; 549 unsigned int cpu = smp_processor_id(); 550 551 set_cpu_online(cpu, false); 552 calculate_cpu_foreign_map(); 553 local_irq_save(flags); 554 clear_c0_status(ST0_IM); 555 local_irq_restore(flags); 556 local_flush_tlb_all(); 557 558 return 0; 559 } 560 561 562 static void loongson3_cpu_die(unsigned int cpu) 563 { 564 while (per_cpu(cpu_state, cpu) != CPU_DEAD) 565 cpu_relax(); 566 567 mb(); 568 } 569 570 /* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and 571 * flush all L1 entries at first. Then, another core (usually Core 0) can 572 * safely disable the clock of the target core. loongson3_play_dead() is 573 * called via CKSEG1 (uncached and unmmaped) 574 */ 575 static void loongson3_type1_play_dead(int *state_addr) 576 { 577 register int val; 578 register long cpuid, core, node, count; 579 register void *addr, *base, *initfunc; 580 581 __asm__ __volatile__( 582 " .set push \n" 583 " .set noreorder \n" 584 " li %[addr], 0x80000000 \n" /* KSEG0 */ 585 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ 586 " cache 0, 1(%[addr]) \n" 587 " cache 0, 2(%[addr]) \n" 588 " cache 0, 3(%[addr]) \n" 589 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */ 590 " cache 1, 1(%[addr]) \n" 591 " cache 1, 2(%[addr]) \n" 592 " cache 1, 3(%[addr]) \n" 593 " addiu %[sets], %[sets], -1 \n" 594 " bnez %[sets], 1b \n" 595 " addiu %[addr], %[addr], 0x20 \n" 596 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ 597 " sw %[val], (%[state_addr]) \n" 598 " sync \n" 599 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */ 600 " .set pop \n" 601 : [addr] "=&r" (addr), [val] "=&r" (val) 602 : [state_addr] "r" (state_addr), 603 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); 604 605 __asm__ __volatile__( 606 " .set push \n" 607 " .set noreorder \n" 608 " .set mips64 \n" 609 " mfc0 %[cpuid], $15, 1 \n" 610 " andi %[cpuid], 0x3ff \n" 611 " dli %[base], 0x900000003ff01000 \n" 612 " andi %[core], %[cpuid], 0x3 \n" 613 " sll %[core], 8 \n" /* get core id */ 614 " or %[base], %[base], %[core] \n" 615 " andi %[node], %[cpuid], 0xc \n" 616 " dsll %[node], 42 \n" /* get node id */ 617 " or %[base], %[base], %[node] \n" 618 "1: li %[count], 0x100 \n" /* wait for init loop */ 619 "2: bnez %[count], 2b \n" /* limit mailbox access */ 620 " addiu %[count], -1 \n" 621 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */ 622 " beqz %[initfunc], 1b \n" 623 " nop \n" 624 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ 625 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ 626 " ld $a1, 0x38(%[base]) \n" 627 " jr %[initfunc] \n" /* jump to initial PC */ 628 " nop \n" 629 " .set pop \n" 630 : [core] "=&r" (core), [node] "=&r" (node), 631 [base] "=&r" (base), [cpuid] "=&r" (cpuid), 632 [count] "=&r" (count), [initfunc] "=&r" (initfunc) 633 : /* No Input */ 634 : "a1"); 635 } 636 637 static void loongson3_type2_play_dead(int *state_addr) 638 { 639 register int val; 640 register long cpuid, core, node, count; 641 register void *addr, *base, *initfunc; 642 643 __asm__ __volatile__( 644 " .set push \n" 645 " .set noreorder \n" 646 " li %[addr], 0x80000000 \n" /* KSEG0 */ 647 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ 648 " cache 0, 1(%[addr]) \n" 649 " cache 0, 2(%[addr]) \n" 650 " cache 0, 3(%[addr]) \n" 651 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */ 652 " cache 1, 1(%[addr]) \n" 653 " cache 1, 2(%[addr]) \n" 654 " cache 1, 3(%[addr]) \n" 655 " addiu %[sets], %[sets], -1 \n" 656 " bnez %[sets], 1b \n" 657 " addiu %[addr], %[addr], 0x20 \n" 658 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ 659 " sw %[val], (%[state_addr]) \n" 660 " sync \n" 661 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */ 662 " .set pop \n" 663 : [addr] "=&r" (addr), [val] "=&r" (val) 664 : [state_addr] "r" (state_addr), 665 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); 666 667 __asm__ __volatile__( 668 " .set push \n" 669 " .set noreorder \n" 670 " .set mips64 \n" 671 " mfc0 %[cpuid], $15, 1 \n" 672 " andi %[cpuid], 0x3ff \n" 673 " dli %[base], 0x900000003ff01000 \n" 674 " andi %[core], %[cpuid], 0x3 \n" 675 " sll %[core], 8 \n" /* get core id */ 676 " or %[base], %[base], %[core] \n" 677 " andi %[node], %[cpuid], 0xc \n" 678 " dsll %[node], 42 \n" /* get node id */ 679 " or %[base], %[base], %[node] \n" 680 " dsrl %[node], 30 \n" /* 15:14 */ 681 " or %[base], %[base], %[node] \n" 682 "1: li %[count], 0x100 \n" /* wait for init loop */ 683 "2: bnez %[count], 2b \n" /* limit mailbox access */ 684 " addiu %[count], -1 \n" 685 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */ 686 " beqz %[initfunc], 1b \n" 687 " nop \n" 688 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ 689 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ 690 " ld $a1, 0x38(%[base]) \n" 691 " jr %[initfunc] \n" /* jump to initial PC */ 692 " nop \n" 693 " .set pop \n" 694 : [core] "=&r" (core), [node] "=&r" (node), 695 [base] "=&r" (base), [cpuid] "=&r" (cpuid), 696 [count] "=&r" (count), [initfunc] "=&r" (initfunc) 697 : /* No Input */ 698 : "a1"); 699 } 700 701 static void loongson3_type3_play_dead(int *state_addr) 702 { 703 register int val; 704 register long cpuid, core, node, count; 705 register void *addr, *base, *initfunc; 706 707 __asm__ __volatile__( 708 " .set push \n" 709 " .set noreorder \n" 710 " li %[addr], 0x80000000 \n" /* KSEG0 */ 711 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ 712 " cache 0, 1(%[addr]) \n" 713 " cache 0, 2(%[addr]) \n" 714 " cache 0, 3(%[addr]) \n" 715 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */ 716 " cache 1, 1(%[addr]) \n" 717 " cache 1, 2(%[addr]) \n" 718 " cache 1, 3(%[addr]) \n" 719 " addiu %[sets], %[sets], -1 \n" 720 " bnez %[sets], 1b \n" 721 " addiu %[addr], %[addr], 0x40 \n" 722 " li %[addr], 0x80000000 \n" /* KSEG0 */ 723 "2: cache 2, 0(%[addr]) \n" /* flush L1 VCache */ 724 " cache 2, 1(%[addr]) \n" 725 " cache 2, 2(%[addr]) \n" 726 " cache 2, 3(%[addr]) \n" 727 " cache 2, 4(%[addr]) \n" 728 " cache 2, 5(%[addr]) \n" 729 " cache 2, 6(%[addr]) \n" 730 " cache 2, 7(%[addr]) \n" 731 " cache 2, 8(%[addr]) \n" 732 " cache 2, 9(%[addr]) \n" 733 " cache 2, 10(%[addr]) \n" 734 " cache 2, 11(%[addr]) \n" 735 " cache 2, 12(%[addr]) \n" 736 " cache 2, 13(%[addr]) \n" 737 " cache 2, 14(%[addr]) \n" 738 " cache 2, 15(%[addr]) \n" 739 " addiu %[vsets], %[vsets], -1 \n" 740 " bnez %[vsets], 2b \n" 741 " addiu %[addr], %[addr], 0x40 \n" 742 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ 743 " sw %[val], (%[state_addr]) \n" 744 " sync \n" 745 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */ 746 " .set pop \n" 747 : [addr] "=&r" (addr), [val] "=&r" (val) 748 : [state_addr] "r" (state_addr), 749 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets), 750 [vsets] "r" (cpu_data[smp_processor_id()].vcache.sets)); 751 752 __asm__ __volatile__( 753 " .set push \n" 754 " .set noreorder \n" 755 " .set mips64 \n" 756 " mfc0 %[cpuid], $15, 1 \n" 757 " andi %[cpuid], 0x3ff \n" 758 " dli %[base], 0x900000003ff01000 \n" 759 " andi %[core], %[cpuid], 0x3 \n" 760 " sll %[core], 8 \n" /* get core id */ 761 " or %[base], %[base], %[core] \n" 762 " andi %[node], %[cpuid], 0xc \n" 763 " dsll %[node], 42 \n" /* get node id */ 764 " or %[base], %[base], %[node] \n" 765 "1: li %[count], 0x100 \n" /* wait for init loop */ 766 "2: bnez %[count], 2b \n" /* limit mailbox access */ 767 " addiu %[count], -1 \n" 768 " lw %[initfunc], 0x20(%[base]) \n" /* check lower 32-bit as jump indicator */ 769 " beqz %[initfunc], 1b \n" 770 " nop \n" 771 " ld %[initfunc], 0x20(%[base]) \n" /* get PC (whole 64-bit) via mailbox */ 772 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ 773 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ 774 " ld $a1, 0x38(%[base]) \n" 775 " jr %[initfunc] \n" /* jump to initial PC */ 776 " nop \n" 777 " .set pop \n" 778 : [core] "=&r" (core), [node] "=&r" (node), 779 [base] "=&r" (base), [cpuid] "=&r" (cpuid), 780 [count] "=&r" (count), [initfunc] "=&r" (initfunc) 781 : /* No Input */ 782 : "a1"); 783 } 784 785 void play_dead(void) 786 { 787 int prid_imp, prid_rev, *state_addr; 788 unsigned int cpu = smp_processor_id(); 789 void (*play_dead_at_ckseg1)(int *); 790 791 idle_task_exit(); 792 793 prid_imp = read_c0_prid() & PRID_IMP_MASK; 794 prid_rev = read_c0_prid() & PRID_REV_MASK; 795 796 if (prid_imp == PRID_IMP_LOONGSON_64G) { 797 play_dead_at_ckseg1 = 798 (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead); 799 goto out; 800 } 801 802 switch (prid_rev) { 803 case PRID_REV_LOONGSON3A_R1: 804 default: 805 play_dead_at_ckseg1 = 806 (void *)CKSEG1ADDR((unsigned long)loongson3_type1_play_dead); 807 break; 808 case PRID_REV_LOONGSON3B_R1: 809 case PRID_REV_LOONGSON3B_R2: 810 play_dead_at_ckseg1 = 811 (void *)CKSEG1ADDR((unsigned long)loongson3_type2_play_dead); 812 break; 813 case PRID_REV_LOONGSON3A_R2_0: 814 case PRID_REV_LOONGSON3A_R2_1: 815 case PRID_REV_LOONGSON3A_R3_0: 816 case PRID_REV_LOONGSON3A_R3_1: 817 play_dead_at_ckseg1 = 818 (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead); 819 break; 820 } 821 822 out: 823 state_addr = &per_cpu(cpu_state, cpu); 824 mb(); 825 play_dead_at_ckseg1(state_addr); 826 BUG(); 827 } 828 829 static int loongson3_disable_clock(unsigned int cpu) 830 { 831 uint64_t core_id = cpu_core(&cpu_data[cpu]); 832 uint64_t package_id = cpu_data[cpu].package; 833 834 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) { 835 LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id)); 836 } else { 837 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG)) 838 LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3)); 839 } 840 return 0; 841 } 842 843 static int loongson3_enable_clock(unsigned int cpu) 844 { 845 uint64_t core_id = cpu_core(&cpu_data[cpu]); 846 uint64_t package_id = cpu_data[cpu].package; 847 848 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) { 849 LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id); 850 } else { 851 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG)) 852 LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3); 853 } 854 return 0; 855 } 856 857 static int register_loongson3_notifier(void) 858 { 859 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE, 860 "mips/loongson:prepare", 861 loongson3_enable_clock, 862 loongson3_disable_clock); 863 } 864 early_initcall(register_loongson3_notifier); 865 866 #endif 867 868 const struct plat_smp_ops loongson3_smp_ops = { 869 .send_ipi_single = loongson3_send_ipi_single, 870 .send_ipi_mask = loongson3_send_ipi_mask, 871 .init_secondary = loongson3_init_secondary, 872 .smp_finish = loongson3_smp_finish, 873 .boot_secondary = loongson3_boot_secondary, 874 .smp_setup = loongson3_smp_setup, 875 .prepare_cpus = loongson3_prepare_cpus, 876 #ifdef CONFIG_HOTPLUG_CPU 877 .cpu_disable = loongson3_cpu_disable, 878 .cpu_die = loongson3_cpu_die, 879 #endif 880 #ifdef CONFIG_KEXEC 881 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 882 #endif 883 }; 884