1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2010, 2011, 2012, Lemote, Inc. 4 * Author: Chen Huacai, chenhc@lemote.com 5 */ 6 7 #include <irq.h> 8 #include <linux/init.h> 9 #include <linux/cpu.h> 10 #include <linux/sched.h> 11 #include <linux/sched/hotplug.h> 12 #include <linux/sched/task_stack.h> 13 #include <linux/smp.h> 14 #include <linux/cpufreq.h> 15 #include <linux/kexec.h> 16 #include <asm/processor.h> 17 #include <asm/smp.h> 18 #include <asm/time.h> 19 #include <asm/tlbflush.h> 20 #include <asm/cacheflush.h> 21 #include <loongson.h> 22 #include <loongson_regs.h> 23 #include <workarounds.h> 24 25 #include "smp.h" 26 27 DEFINE_PER_CPU(int, cpu_state); 28 29 #define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6) 30 31 static void __iomem *ipi_set0_regs[16]; 32 static void __iomem *ipi_clear0_regs[16]; 33 static void __iomem *ipi_status0_regs[16]; 34 static void __iomem *ipi_en0_regs[16]; 35 static void __iomem *ipi_mailbox_buf[16]; 36 static uint32_t core0_c0count[NR_CPUS]; 37 38 static u32 (*ipi_read_clear)(int cpu); 39 static void (*ipi_write_action)(int cpu, u32 action); 40 static void (*ipi_write_enable)(int cpu); 41 static void (*ipi_clear_buf)(int cpu); 42 static void (*ipi_write_buf)(int cpu, struct task_struct *idle); 43 44 /* send mail via Mail_Send register for 3A4000+ CPU */ 45 static void csr_mail_send(uint64_t data, int cpu, int mailbox) 46 { 47 uint64_t val; 48 49 /* send high 32 bits */ 50 val = CSR_MAIL_SEND_BLOCK; 51 val |= (CSR_MAIL_SEND_BOX_HIGH(mailbox) << CSR_MAIL_SEND_BOX_SHIFT); 52 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); 53 val |= (data & CSR_MAIL_SEND_H32_MASK); 54 csr_writeq(val, LOONGSON_CSR_MAIL_SEND); 55 56 /* send low 32 bits */ 57 val = CSR_MAIL_SEND_BLOCK; 58 val |= (CSR_MAIL_SEND_BOX_LOW(mailbox) << CSR_MAIL_SEND_BOX_SHIFT); 59 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); 60 val |= (data << CSR_MAIL_SEND_BUF_SHIFT); 61 csr_writeq(val, LOONGSON_CSR_MAIL_SEND); 62 }; 63 64 static u32 csr_ipi_read_clear(int cpu) 65 { 66 u32 action; 67 68 /* Load the ipi register to figure out what we're supposed to do */ 69 action = csr_readl(LOONGSON_CSR_IPI_STATUS); 70 /* Clear the ipi register to clear the interrupt */ 71 csr_writel(action, LOONGSON_CSR_IPI_CLEAR); 72 73 return action; 74 } 75 76 static void csr_ipi_write_action(int cpu, u32 action) 77 { 78 unsigned int irq = 0; 79 80 while ((irq = ffs(action))) { 81 uint32_t val = CSR_IPI_SEND_BLOCK; 82 val |= (irq - 1); 83 val |= (cpu << CSR_IPI_SEND_CPU_SHIFT); 84 csr_writel(val, LOONGSON_CSR_IPI_SEND); 85 action &= ~BIT(irq - 1); 86 } 87 } 88 89 static void csr_ipi_write_enable(int cpu) 90 { 91 csr_writel(0xffffffff, LOONGSON_CSR_IPI_EN); 92 } 93 94 static void csr_ipi_clear_buf(int cpu) 95 { 96 csr_writeq(0, LOONGSON_CSR_MAIL_BUF0); 97 } 98 99 static void csr_ipi_write_buf(int cpu, struct task_struct *idle) 100 { 101 unsigned long startargs[4]; 102 103 /* startargs[] are initial PC, SP and GP for secondary CPU */ 104 startargs[0] = (unsigned long)&smp_bootstrap; 105 startargs[1] = (unsigned long)__KSTK_TOS(idle); 106 startargs[2] = (unsigned long)task_thread_info(idle); 107 startargs[3] = 0; 108 109 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", 110 cpu, startargs[0], startargs[1], startargs[2]); 111 112 csr_mail_send(startargs[3], cpu_logical_map(cpu), 3); 113 csr_mail_send(startargs[2], cpu_logical_map(cpu), 2); 114 csr_mail_send(startargs[1], cpu_logical_map(cpu), 1); 115 csr_mail_send(startargs[0], cpu_logical_map(cpu), 0); 116 } 117 118 static u32 legacy_ipi_read_clear(int cpu) 119 { 120 u32 action; 121 122 /* Load the ipi register to figure out what we're supposed to do */ 123 action = readl_relaxed(ipi_status0_regs[cpu_logical_map(cpu)]); 124 /* Clear the ipi register to clear the interrupt */ 125 writel_relaxed(action, ipi_clear0_regs[cpu_logical_map(cpu)]); 126 nudge_writes(); 127 128 return action; 129 } 130 131 static void legacy_ipi_write_action(int cpu, u32 action) 132 { 133 writel_relaxed((u32)action, ipi_set0_regs[cpu]); 134 nudge_writes(); 135 } 136 137 static void legacy_ipi_write_enable(int cpu) 138 { 139 writel_relaxed(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); 140 } 141 142 static void legacy_ipi_clear_buf(int cpu) 143 { 144 writeq_relaxed(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); 145 } 146 147 static void legacy_ipi_write_buf(int cpu, struct task_struct *idle) 148 { 149 unsigned long startargs[4]; 150 151 /* startargs[] are initial PC, SP and GP for secondary CPU */ 152 startargs[0] = (unsigned long)&smp_bootstrap; 153 startargs[1] = (unsigned long)__KSTK_TOS(idle); 154 startargs[2] = (unsigned long)task_thread_info(idle); 155 startargs[3] = 0; 156 157 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", 158 cpu, startargs[0], startargs[1], startargs[2]); 159 160 writeq_relaxed(startargs[3], 161 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18); 162 writeq_relaxed(startargs[2], 163 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10); 164 writeq_relaxed(startargs[1], 165 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8); 166 writeq_relaxed(startargs[0], 167 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); 168 nudge_writes(); 169 } 170 171 static void csr_ipi_probe(void) 172 { 173 if (cpu_has_csr() && csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_IPI) { 174 ipi_read_clear = csr_ipi_read_clear; 175 ipi_write_action = csr_ipi_write_action; 176 ipi_write_enable = csr_ipi_write_enable; 177 ipi_clear_buf = csr_ipi_clear_buf; 178 ipi_write_buf = csr_ipi_write_buf; 179 } else { 180 ipi_read_clear = legacy_ipi_read_clear; 181 ipi_write_action = legacy_ipi_write_action; 182 ipi_write_enable = legacy_ipi_write_enable; 183 ipi_clear_buf = legacy_ipi_clear_buf; 184 ipi_write_buf = legacy_ipi_write_buf; 185 } 186 } 187 188 static void ipi_set0_regs_init(void) 189 { 190 ipi_set0_regs[0] = (void __iomem *) 191 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0); 192 ipi_set0_regs[1] = (void __iomem *) 193 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0); 194 ipi_set0_regs[2] = (void __iomem *) 195 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0); 196 ipi_set0_regs[3] = (void __iomem *) 197 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0); 198 ipi_set0_regs[4] = (void __iomem *) 199 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0); 200 ipi_set0_regs[5] = (void __iomem *) 201 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0); 202 ipi_set0_regs[6] = (void __iomem *) 203 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0); 204 ipi_set0_regs[7] = (void __iomem *) 205 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0); 206 ipi_set0_regs[8] = (void __iomem *) 207 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0); 208 ipi_set0_regs[9] = (void __iomem *) 209 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0); 210 ipi_set0_regs[10] = (void __iomem *) 211 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0); 212 ipi_set0_regs[11] = (void __iomem *) 213 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0); 214 ipi_set0_regs[12] = (void __iomem *) 215 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0); 216 ipi_set0_regs[13] = (void __iomem *) 217 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0); 218 ipi_set0_regs[14] = (void __iomem *) 219 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0); 220 ipi_set0_regs[15] = (void __iomem *) 221 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0); 222 } 223 224 static void ipi_clear0_regs_init(void) 225 { 226 ipi_clear0_regs[0] = (void __iomem *) 227 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0); 228 ipi_clear0_regs[1] = (void __iomem *) 229 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0); 230 ipi_clear0_regs[2] = (void __iomem *) 231 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0); 232 ipi_clear0_regs[3] = (void __iomem *) 233 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0); 234 ipi_clear0_regs[4] = (void __iomem *) 235 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0); 236 ipi_clear0_regs[5] = (void __iomem *) 237 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0); 238 ipi_clear0_regs[6] = (void __iomem *) 239 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0); 240 ipi_clear0_regs[7] = (void __iomem *) 241 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0); 242 ipi_clear0_regs[8] = (void __iomem *) 243 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0); 244 ipi_clear0_regs[9] = (void __iomem *) 245 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0); 246 ipi_clear0_regs[10] = (void __iomem *) 247 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0); 248 ipi_clear0_regs[11] = (void __iomem *) 249 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0); 250 ipi_clear0_regs[12] = (void __iomem *) 251 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0); 252 ipi_clear0_regs[13] = (void __iomem *) 253 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0); 254 ipi_clear0_regs[14] = (void __iomem *) 255 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0); 256 ipi_clear0_regs[15] = (void __iomem *) 257 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0); 258 } 259 260 static void ipi_status0_regs_init(void) 261 { 262 ipi_status0_regs[0] = (void __iomem *) 263 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0); 264 ipi_status0_regs[1] = (void __iomem *) 265 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0); 266 ipi_status0_regs[2] = (void __iomem *) 267 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0); 268 ipi_status0_regs[3] = (void __iomem *) 269 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0); 270 ipi_status0_regs[4] = (void __iomem *) 271 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0); 272 ipi_status0_regs[5] = (void __iomem *) 273 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0); 274 ipi_status0_regs[6] = (void __iomem *) 275 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0); 276 ipi_status0_regs[7] = (void __iomem *) 277 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0); 278 ipi_status0_regs[8] = (void __iomem *) 279 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0); 280 ipi_status0_regs[9] = (void __iomem *) 281 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0); 282 ipi_status0_regs[10] = (void __iomem *) 283 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0); 284 ipi_status0_regs[11] = (void __iomem *) 285 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0); 286 ipi_status0_regs[12] = (void __iomem *) 287 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0); 288 ipi_status0_regs[13] = (void __iomem *) 289 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0); 290 ipi_status0_regs[14] = (void __iomem *) 291 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0); 292 ipi_status0_regs[15] = (void __iomem *) 293 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0); 294 } 295 296 static void ipi_en0_regs_init(void) 297 { 298 ipi_en0_regs[0] = (void __iomem *) 299 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0); 300 ipi_en0_regs[1] = (void __iomem *) 301 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0); 302 ipi_en0_regs[2] = (void __iomem *) 303 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0); 304 ipi_en0_regs[3] = (void __iomem *) 305 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0); 306 ipi_en0_regs[4] = (void __iomem *) 307 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0); 308 ipi_en0_regs[5] = (void __iomem *) 309 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0); 310 ipi_en0_regs[6] = (void __iomem *) 311 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0); 312 ipi_en0_regs[7] = (void __iomem *) 313 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0); 314 ipi_en0_regs[8] = (void __iomem *) 315 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0); 316 ipi_en0_regs[9] = (void __iomem *) 317 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0); 318 ipi_en0_regs[10] = (void __iomem *) 319 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0); 320 ipi_en0_regs[11] = (void __iomem *) 321 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0); 322 ipi_en0_regs[12] = (void __iomem *) 323 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0); 324 ipi_en0_regs[13] = (void __iomem *) 325 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0); 326 ipi_en0_regs[14] = (void __iomem *) 327 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0); 328 ipi_en0_regs[15] = (void __iomem *) 329 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0); 330 } 331 332 static void ipi_mailbox_buf_init(void) 333 { 334 ipi_mailbox_buf[0] = (void __iomem *) 335 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF); 336 ipi_mailbox_buf[1] = (void __iomem *) 337 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF); 338 ipi_mailbox_buf[2] = (void __iomem *) 339 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF); 340 ipi_mailbox_buf[3] = (void __iomem *) 341 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF); 342 ipi_mailbox_buf[4] = (void __iomem *) 343 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF); 344 ipi_mailbox_buf[5] = (void __iomem *) 345 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF); 346 ipi_mailbox_buf[6] = (void __iomem *) 347 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF); 348 ipi_mailbox_buf[7] = (void __iomem *) 349 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF); 350 ipi_mailbox_buf[8] = (void __iomem *) 351 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF); 352 ipi_mailbox_buf[9] = (void __iomem *) 353 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF); 354 ipi_mailbox_buf[10] = (void __iomem *) 355 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF); 356 ipi_mailbox_buf[11] = (void __iomem *) 357 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF); 358 ipi_mailbox_buf[12] = (void __iomem *) 359 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF); 360 ipi_mailbox_buf[13] = (void __iomem *) 361 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF); 362 ipi_mailbox_buf[14] = (void __iomem *) 363 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF); 364 ipi_mailbox_buf[15] = (void __iomem *) 365 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF); 366 } 367 368 /* 369 * Simple enough, just poke the appropriate ipi register 370 */ 371 static void loongson3_send_ipi_single(int cpu, unsigned int action) 372 { 373 ipi_write_action(cpu_logical_map(cpu), (u32)action); 374 } 375 376 static void 377 loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) 378 { 379 unsigned int i; 380 381 for_each_cpu(i, mask) 382 ipi_write_action(cpu_logical_map(i), (u32)action); 383 } 384 385 386 static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) 387 { 388 int i, cpu = smp_processor_id(); 389 unsigned int action, c0count; 390 391 action = ipi_read_clear(cpu); 392 393 if (action & SMP_RESCHEDULE_YOURSELF) 394 scheduler_ipi(); 395 396 if (action & SMP_CALL_FUNCTION) { 397 irq_enter(); 398 generic_smp_call_function_interrupt(); 399 irq_exit(); 400 } 401 402 if (action & SMP_ASK_C0COUNT) { 403 BUG_ON(cpu != 0); 404 c0count = read_c0_count(); 405 c0count = c0count ? c0count : 1; 406 for (i = 1; i < nr_cpu_ids; i++) 407 core0_c0count[i] = c0count; 408 nudge_writes(); /* Let others see the result ASAP */ 409 } 410 411 return IRQ_HANDLED; 412 } 413 414 #define MAX_LOOPS 800 415 /* 416 * SMP init and finish on secondary CPUs 417 */ 418 static void loongson3_init_secondary(void) 419 { 420 int i; 421 uint32_t initcount; 422 unsigned int cpu = smp_processor_id(); 423 unsigned int imask = STATUSF_IP7 | STATUSF_IP6 | 424 STATUSF_IP3 | STATUSF_IP2; 425 426 /* Set interrupt mask, but don't enable */ 427 change_c0_status(ST0_IM, imask); 428 ipi_write_enable(cpu); 429 430 per_cpu(cpu_state, cpu) = CPU_ONLINE; 431 cpu_set_core(&cpu_data[cpu], 432 cpu_logical_map(cpu) % loongson_sysconf.cores_per_package); 433 cpu_data[cpu].package = 434 cpu_logical_map(cpu) / loongson_sysconf.cores_per_package; 435 436 i = 0; 437 core0_c0count[cpu] = 0; 438 loongson3_send_ipi_single(0, SMP_ASK_C0COUNT); 439 while (!core0_c0count[cpu]) { 440 i++; 441 cpu_relax(); 442 } 443 444 if (i > MAX_LOOPS) 445 i = MAX_LOOPS; 446 if (cpu_data[cpu].package) 447 initcount = core0_c0count[cpu] + i; 448 else /* Local access is faster for loops */ 449 initcount = core0_c0count[cpu] + i/2; 450 451 write_c0_count(initcount); 452 } 453 454 static void loongson3_smp_finish(void) 455 { 456 int cpu = smp_processor_id(); 457 458 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); 459 local_irq_enable(); 460 ipi_clear_buf(cpu); 461 462 pr_info("CPU#%d finished, CP0_ST=%x\n", 463 smp_processor_id(), read_c0_status()); 464 } 465 466 static void __init loongson3_smp_setup(void) 467 { 468 int i = 0, num = 0; /* i: physical id, num: logical id */ 469 int max_cpus = 0; 470 471 init_cpu_possible(cpu_none_mask); 472 473 for (i = 0; i < ARRAY_SIZE(smp_group); i++) { 474 if (!smp_group[i]) 475 break; 476 max_cpus += loongson_sysconf.cores_per_node; 477 } 478 479 if (max_cpus < loongson_sysconf.nr_cpus) { 480 pr_err("SMP Groups are less than the number of CPUs\n"); 481 loongson_sysconf.nr_cpus = max_cpus ? max_cpus : 1; 482 } 483 484 /* For unified kernel, NR_CPUS is the maximum possible value, 485 * loongson_sysconf.nr_cpus is the really present value 486 */ 487 i = 0; 488 while (i < loongson_sysconf.nr_cpus) { 489 if (loongson_sysconf.reserved_cpus_mask & (1<<i)) { 490 /* Reserved physical CPU cores */ 491 __cpu_number_map[i] = -1; 492 } else { 493 __cpu_number_map[i] = num; 494 __cpu_logical_map[num] = i; 495 set_cpu_possible(num, true); 496 /* Loongson processors are always grouped by 4 */ 497 cpu_set_cluster(&cpu_data[num], i / 4); 498 num++; 499 } 500 i++; 501 } 502 pr_info("Detected %i available CPU(s)\n", num); 503 504 while (num < loongson_sysconf.nr_cpus) { 505 __cpu_logical_map[num] = -1; 506 num++; 507 } 508 csr_ipi_probe(); 509 ipi_set0_regs_init(); 510 ipi_clear0_regs_init(); 511 ipi_status0_regs_init(); 512 ipi_en0_regs_init(); 513 ipi_mailbox_buf_init(); 514 if (smp_group[0]) 515 ipi_write_enable(0); 516 517 cpu_set_core(&cpu_data[0], 518 cpu_logical_map(0) % loongson_sysconf.cores_per_package); 519 cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package; 520 } 521 522 static void __init loongson3_prepare_cpus(unsigned int max_cpus) 523 { 524 if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt, 525 IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL)) 526 pr_err("Failed to request IPI IRQ\n"); 527 init_cpu_present(cpu_possible_mask); 528 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 529 } 530 531 /* 532 * Setup the PC, SP, and GP of a secondary processor and start it runing! 533 */ 534 static int loongson3_boot_secondary(int cpu, struct task_struct *idle) 535 { 536 pr_info("Booting CPU#%d...\n", cpu); 537 538 ipi_write_buf(cpu, idle); 539 540 return 0; 541 } 542 543 #ifdef CONFIG_HOTPLUG_CPU 544 545 static int loongson3_cpu_disable(void) 546 { 547 unsigned long flags; 548 unsigned int cpu = smp_processor_id(); 549 550 set_cpu_online(cpu, false); 551 calculate_cpu_foreign_map(); 552 local_irq_save(flags); 553 clear_c0_status(ST0_IM); 554 local_irq_restore(flags); 555 local_flush_tlb_all(); 556 557 return 0; 558 } 559 560 561 static void loongson3_cpu_die(unsigned int cpu) 562 { 563 while (per_cpu(cpu_state, cpu) != CPU_DEAD) 564 cpu_relax(); 565 566 mb(); 567 } 568 569 /* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and 570 * flush all L1 entries at first. Then, another core (usually Core 0) can 571 * safely disable the clock of the target core. loongson3_play_dead() is 572 * called via CKSEG1 (uncached and unmmaped) 573 */ 574 static void loongson3_type1_play_dead(int *state_addr) 575 { 576 register int val; 577 register long cpuid, core, node, count; 578 register void *addr, *base, *initfunc; 579 580 __asm__ __volatile__( 581 " .set push \n" 582 " .set noreorder \n" 583 " li %[addr], 0x80000000 \n" /* KSEG0 */ 584 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ 585 " cache 0, 1(%[addr]) \n" 586 " cache 0, 2(%[addr]) \n" 587 " cache 0, 3(%[addr]) \n" 588 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */ 589 " cache 1, 1(%[addr]) \n" 590 " cache 1, 2(%[addr]) \n" 591 " cache 1, 3(%[addr]) \n" 592 " addiu %[sets], %[sets], -1 \n" 593 " bnez %[sets], 1b \n" 594 " addiu %[addr], %[addr], 0x20 \n" 595 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ 596 " sw %[val], (%[state_addr]) \n" 597 " sync \n" 598 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */ 599 " .set pop \n" 600 : [addr] "=&r" (addr), [val] "=&r" (val) 601 : [state_addr] "r" (state_addr), 602 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); 603 604 __asm__ __volatile__( 605 " .set push \n" 606 " .set noreorder \n" 607 " .set mips64 \n" 608 " mfc0 %[cpuid], $15, 1 \n" 609 " andi %[cpuid], 0x3ff \n" 610 " dli %[base], 0x900000003ff01000 \n" 611 " andi %[core], %[cpuid], 0x3 \n" 612 " sll %[core], 8 \n" /* get core id */ 613 " or %[base], %[base], %[core] \n" 614 " andi %[node], %[cpuid], 0xc \n" 615 " dsll %[node], 42 \n" /* get node id */ 616 " or %[base], %[base], %[node] \n" 617 "1: li %[count], 0x100 \n" /* wait for init loop */ 618 "2: bnez %[count], 2b \n" /* limit mailbox access */ 619 " addiu %[count], -1 \n" 620 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */ 621 " beqz %[initfunc], 1b \n" 622 " nop \n" 623 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ 624 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ 625 " ld $a1, 0x38(%[base]) \n" 626 " jr %[initfunc] \n" /* jump to initial PC */ 627 " nop \n" 628 " .set pop \n" 629 : [core] "=&r" (core), [node] "=&r" (node), 630 [base] "=&r" (base), [cpuid] "=&r" (cpuid), 631 [count] "=&r" (count), [initfunc] "=&r" (initfunc) 632 : /* No Input */ 633 : "a1"); 634 } 635 636 static void loongson3_type2_play_dead(int *state_addr) 637 { 638 register int val; 639 register long cpuid, core, node, count; 640 register void *addr, *base, *initfunc; 641 642 __asm__ __volatile__( 643 " .set push \n" 644 " .set noreorder \n" 645 " li %[addr], 0x80000000 \n" /* KSEG0 */ 646 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ 647 " cache 0, 1(%[addr]) \n" 648 " cache 0, 2(%[addr]) \n" 649 " cache 0, 3(%[addr]) \n" 650 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */ 651 " cache 1, 1(%[addr]) \n" 652 " cache 1, 2(%[addr]) \n" 653 " cache 1, 3(%[addr]) \n" 654 " addiu %[sets], %[sets], -1 \n" 655 " bnez %[sets], 1b \n" 656 " addiu %[addr], %[addr], 0x20 \n" 657 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ 658 " sw %[val], (%[state_addr]) \n" 659 " sync \n" 660 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */ 661 " .set pop \n" 662 : [addr] "=&r" (addr), [val] "=&r" (val) 663 : [state_addr] "r" (state_addr), 664 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); 665 666 __asm__ __volatile__( 667 " .set push \n" 668 " .set noreorder \n" 669 " .set mips64 \n" 670 " mfc0 %[cpuid], $15, 1 \n" 671 " andi %[cpuid], 0x3ff \n" 672 " dli %[base], 0x900000003ff01000 \n" 673 " andi %[core], %[cpuid], 0x3 \n" 674 " sll %[core], 8 \n" /* get core id */ 675 " or %[base], %[base], %[core] \n" 676 " andi %[node], %[cpuid], 0xc \n" 677 " dsll %[node], 42 \n" /* get node id */ 678 " or %[base], %[base], %[node] \n" 679 " dsrl %[node], 30 \n" /* 15:14 */ 680 " or %[base], %[base], %[node] \n" 681 "1: li %[count], 0x100 \n" /* wait for init loop */ 682 "2: bnez %[count], 2b \n" /* limit mailbox access */ 683 " addiu %[count], -1 \n" 684 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */ 685 " beqz %[initfunc], 1b \n" 686 " nop \n" 687 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ 688 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ 689 " ld $a1, 0x38(%[base]) \n" 690 " jr %[initfunc] \n" /* jump to initial PC */ 691 " nop \n" 692 " .set pop \n" 693 : [core] "=&r" (core), [node] "=&r" (node), 694 [base] "=&r" (base), [cpuid] "=&r" (cpuid), 695 [count] "=&r" (count), [initfunc] "=&r" (initfunc) 696 : /* No Input */ 697 : "a1"); 698 } 699 700 static void loongson3_type3_play_dead(int *state_addr) 701 { 702 register int val; 703 register long cpuid, core, node, count; 704 register void *addr, *base, *initfunc; 705 706 __asm__ __volatile__( 707 " .set push \n" 708 " .set noreorder \n" 709 " li %[addr], 0x80000000 \n" /* KSEG0 */ 710 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ 711 " cache 0, 1(%[addr]) \n" 712 " cache 0, 2(%[addr]) \n" 713 " cache 0, 3(%[addr]) \n" 714 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */ 715 " cache 1, 1(%[addr]) \n" 716 " cache 1, 2(%[addr]) \n" 717 " cache 1, 3(%[addr]) \n" 718 " addiu %[sets], %[sets], -1 \n" 719 " bnez %[sets], 1b \n" 720 " addiu %[addr], %[addr], 0x40 \n" 721 " li %[addr], 0x80000000 \n" /* KSEG0 */ 722 "2: cache 2, 0(%[addr]) \n" /* flush L1 VCache */ 723 " cache 2, 1(%[addr]) \n" 724 " cache 2, 2(%[addr]) \n" 725 " cache 2, 3(%[addr]) \n" 726 " cache 2, 4(%[addr]) \n" 727 " cache 2, 5(%[addr]) \n" 728 " cache 2, 6(%[addr]) \n" 729 " cache 2, 7(%[addr]) \n" 730 " cache 2, 8(%[addr]) \n" 731 " cache 2, 9(%[addr]) \n" 732 " cache 2, 10(%[addr]) \n" 733 " cache 2, 11(%[addr]) \n" 734 " cache 2, 12(%[addr]) \n" 735 " cache 2, 13(%[addr]) \n" 736 " cache 2, 14(%[addr]) \n" 737 " cache 2, 15(%[addr]) \n" 738 " addiu %[vsets], %[vsets], -1 \n" 739 " bnez %[vsets], 2b \n" 740 " addiu %[addr], %[addr], 0x40 \n" 741 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ 742 " sw %[val], (%[state_addr]) \n" 743 " sync \n" 744 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */ 745 " .set pop \n" 746 : [addr] "=&r" (addr), [val] "=&r" (val) 747 : [state_addr] "r" (state_addr), 748 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets), 749 [vsets] "r" (cpu_data[smp_processor_id()].vcache.sets)); 750 751 __asm__ __volatile__( 752 " .set push \n" 753 " .set noreorder \n" 754 " .set mips64 \n" 755 " mfc0 %[cpuid], $15, 1 \n" 756 " andi %[cpuid], 0x3ff \n" 757 " dli %[base], 0x900000003ff01000 \n" 758 " andi %[core], %[cpuid], 0x3 \n" 759 " sll %[core], 8 \n" /* get core id */ 760 " or %[base], %[base], %[core] \n" 761 " andi %[node], %[cpuid], 0xc \n" 762 " dsll %[node], 42 \n" /* get node id */ 763 " or %[base], %[base], %[node] \n" 764 "1: li %[count], 0x100 \n" /* wait for init loop */ 765 "2: bnez %[count], 2b \n" /* limit mailbox access */ 766 " addiu %[count], -1 \n" 767 " lw %[initfunc], 0x20(%[base]) \n" /* check lower 32-bit as jump indicator */ 768 " beqz %[initfunc], 1b \n" 769 " nop \n" 770 " ld %[initfunc], 0x20(%[base]) \n" /* get PC (whole 64-bit) via mailbox */ 771 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ 772 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ 773 " ld $a1, 0x38(%[base]) \n" 774 " jr %[initfunc] \n" /* jump to initial PC */ 775 " nop \n" 776 " .set pop \n" 777 : [core] "=&r" (core), [node] "=&r" (node), 778 [base] "=&r" (base), [cpuid] "=&r" (cpuid), 779 [count] "=&r" (count), [initfunc] "=&r" (initfunc) 780 : /* No Input */ 781 : "a1"); 782 } 783 784 void play_dead(void) 785 { 786 int prid_imp, prid_rev, *state_addr; 787 unsigned int cpu = smp_processor_id(); 788 void (*play_dead_at_ckseg1)(int *); 789 790 idle_task_exit(); 791 cpuhp_ap_report_dead(); 792 793 prid_imp = read_c0_prid() & PRID_IMP_MASK; 794 prid_rev = read_c0_prid() & PRID_REV_MASK; 795 796 if (prid_imp == PRID_IMP_LOONGSON_64G) { 797 play_dead_at_ckseg1 = 798 (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead); 799 goto out; 800 } 801 802 switch (prid_rev) { 803 case PRID_REV_LOONGSON3A_R1: 804 default: 805 play_dead_at_ckseg1 = 806 (void *)CKSEG1ADDR((unsigned long)loongson3_type1_play_dead); 807 break; 808 case PRID_REV_LOONGSON3B_R1: 809 case PRID_REV_LOONGSON3B_R2: 810 play_dead_at_ckseg1 = 811 (void *)CKSEG1ADDR((unsigned long)loongson3_type2_play_dead); 812 break; 813 case PRID_REV_LOONGSON3A_R2_0: 814 case PRID_REV_LOONGSON3A_R2_1: 815 case PRID_REV_LOONGSON3A_R3_0: 816 case PRID_REV_LOONGSON3A_R3_1: 817 play_dead_at_ckseg1 = 818 (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead); 819 break; 820 } 821 822 out: 823 state_addr = &per_cpu(cpu_state, cpu); 824 mb(); 825 play_dead_at_ckseg1(state_addr); 826 BUG(); 827 } 828 829 static int loongson3_disable_clock(unsigned int cpu) 830 { 831 uint64_t core_id = cpu_core(&cpu_data[cpu]); 832 uint64_t package_id = cpu_data[cpu].package; 833 834 if (!loongson_chipcfg[package_id] || !loongson_freqctrl[package_id]) 835 return 0; 836 837 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) { 838 LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id)); 839 } else { 840 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG)) 841 LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3)); 842 } 843 return 0; 844 } 845 846 static int loongson3_enable_clock(unsigned int cpu) 847 { 848 uint64_t core_id = cpu_core(&cpu_data[cpu]); 849 uint64_t package_id = cpu_data[cpu].package; 850 851 if (!loongson_chipcfg[package_id] || !loongson_freqctrl[package_id]) 852 return 0; 853 854 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) { 855 LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id); 856 } else { 857 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG)) 858 LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3); 859 } 860 return 0; 861 } 862 863 static int register_loongson3_notifier(void) 864 { 865 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE, 866 "mips/loongson:prepare", 867 loongson3_enable_clock, 868 loongson3_disable_clock); 869 } 870 early_initcall(register_loongson3_notifier); 871 872 #endif 873 874 const struct plat_smp_ops loongson3_smp_ops = { 875 .send_ipi_single = loongson3_send_ipi_single, 876 .send_ipi_mask = loongson3_send_ipi_mask, 877 .init_secondary = loongson3_init_secondary, 878 .smp_finish = loongson3_smp_finish, 879 .boot_secondary = loongson3_boot_secondary, 880 .smp_setup = loongson3_smp_setup, 881 .prepare_cpus = loongson3_prepare_cpus, 882 #ifdef CONFIG_HOTPLUG_CPU 883 .cpu_disable = loongson3_cpu_disable, 884 .cpu_die = loongson3_cpu_die, 885 #endif 886 #ifdef CONFIG_KEXEC 887 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 888 #endif 889 }; 890