1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2010, 2011, 2012, Lemote, Inc. 4 * Author: Chen Huacai, chenhc@lemote.com 5 */ 6 7 #include <irq.h> 8 #include <linux/init.h> 9 #include <linux/cpu.h> 10 #include <linux/sched.h> 11 #include <linux/sched/hotplug.h> 12 #include <linux/sched/task_stack.h> 13 #include <linux/smp.h> 14 #include <linux/cpufreq.h> 15 #include <linux/kexec.h> 16 #include <asm/processor.h> 17 #include <asm/time.h> 18 #include <asm/tlbflush.h> 19 #include <asm/cacheflush.h> 20 #include <loongson.h> 21 #include <loongson_regs.h> 22 #include <workarounds.h> 23 24 #include "smp.h" 25 26 DEFINE_PER_CPU(int, cpu_state); 27 28 #define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6) 29 30 static void __iomem *ipi_set0_regs[16]; 31 static void __iomem *ipi_clear0_regs[16]; 32 static void __iomem *ipi_status0_regs[16]; 33 static void __iomem *ipi_en0_regs[16]; 34 static void __iomem *ipi_mailbox_buf[16]; 35 static uint32_t core0_c0count[NR_CPUS]; 36 37 static u32 (*ipi_read_clear)(int cpu); 38 static void (*ipi_write_action)(int cpu, u32 action); 39 static void (*ipi_write_enable)(int cpu); 40 static void (*ipi_clear_buf)(int cpu); 41 static void (*ipi_write_buf)(int cpu, struct task_struct *idle); 42 43 /* send mail via Mail_Send register for 3A4000+ CPU */ 44 static void csr_mail_send(uint64_t data, int cpu, int mailbox) 45 { 46 uint64_t val; 47 48 /* send high 32 bits */ 49 val = CSR_MAIL_SEND_BLOCK; 50 val |= (CSR_MAIL_SEND_BOX_HIGH(mailbox) << CSR_MAIL_SEND_BOX_SHIFT); 51 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); 52 val |= (data & CSR_MAIL_SEND_H32_MASK); 53 csr_writeq(val, LOONGSON_CSR_MAIL_SEND); 54 55 /* send low 32 bits */ 56 val = CSR_MAIL_SEND_BLOCK; 57 val |= (CSR_MAIL_SEND_BOX_LOW(mailbox) << CSR_MAIL_SEND_BOX_SHIFT); 58 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); 59 val |= (data << CSR_MAIL_SEND_BUF_SHIFT); 60 csr_writeq(val, LOONGSON_CSR_MAIL_SEND); 61 }; 62 63 static u32 csr_ipi_read_clear(int cpu) 64 { 65 u32 action; 66 67 /* Load the ipi register to figure out what we're supposed to do */ 68 action = csr_readl(LOONGSON_CSR_IPI_STATUS); 69 /* Clear the ipi register to clear the interrupt */ 70 csr_writel(action, LOONGSON_CSR_IPI_CLEAR); 71 72 return action; 73 } 74 75 static void csr_ipi_write_action(int cpu, u32 action) 76 { 77 unsigned int irq = 0; 78 79 while ((irq = ffs(action))) { 80 uint32_t val = CSR_IPI_SEND_BLOCK; 81 val |= (irq - 1); 82 val |= (cpu << CSR_IPI_SEND_CPU_SHIFT); 83 csr_writel(val, LOONGSON_CSR_IPI_SEND); 84 action &= ~BIT(irq - 1); 85 } 86 } 87 88 static void csr_ipi_write_enable(int cpu) 89 { 90 csr_writel(0xffffffff, LOONGSON_CSR_IPI_EN); 91 } 92 93 static void csr_ipi_clear_buf(int cpu) 94 { 95 csr_writeq(0, LOONGSON_CSR_MAIL_BUF0); 96 } 97 98 static void csr_ipi_write_buf(int cpu, struct task_struct *idle) 99 { 100 unsigned long startargs[4]; 101 102 /* startargs[] are initial PC, SP and GP for secondary CPU */ 103 startargs[0] = (unsigned long)&smp_bootstrap; 104 startargs[1] = (unsigned long)__KSTK_TOS(idle); 105 startargs[2] = (unsigned long)task_thread_info(idle); 106 startargs[3] = 0; 107 108 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", 109 cpu, startargs[0], startargs[1], startargs[2]); 110 111 csr_mail_send(startargs[3], cpu_logical_map(cpu), 3); 112 csr_mail_send(startargs[2], cpu_logical_map(cpu), 2); 113 csr_mail_send(startargs[1], cpu_logical_map(cpu), 1); 114 csr_mail_send(startargs[0], cpu_logical_map(cpu), 0); 115 } 116 117 static u32 legacy_ipi_read_clear(int cpu) 118 { 119 u32 action; 120 121 /* Load the ipi register to figure out what we're supposed to do */ 122 action = readl_relaxed(ipi_status0_regs[cpu_logical_map(cpu)]); 123 /* Clear the ipi register to clear the interrupt */ 124 writel_relaxed(action, ipi_clear0_regs[cpu_logical_map(cpu)]); 125 nudge_writes(); 126 127 return action; 128 } 129 130 static void legacy_ipi_write_action(int cpu, u32 action) 131 { 132 writel_relaxed((u32)action, ipi_set0_regs[cpu]); 133 nudge_writes(); 134 } 135 136 static void legacy_ipi_write_enable(int cpu) 137 { 138 writel_relaxed(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); 139 } 140 141 static void legacy_ipi_clear_buf(int cpu) 142 { 143 writeq_relaxed(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); 144 } 145 146 static void legacy_ipi_write_buf(int cpu, struct task_struct *idle) 147 { 148 unsigned long startargs[4]; 149 150 /* startargs[] are initial PC, SP and GP for secondary CPU */ 151 startargs[0] = (unsigned long)&smp_bootstrap; 152 startargs[1] = (unsigned long)__KSTK_TOS(idle); 153 startargs[2] = (unsigned long)task_thread_info(idle); 154 startargs[3] = 0; 155 156 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", 157 cpu, startargs[0], startargs[1], startargs[2]); 158 159 writeq_relaxed(startargs[3], 160 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18); 161 writeq_relaxed(startargs[2], 162 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10); 163 writeq_relaxed(startargs[1], 164 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8); 165 writeq_relaxed(startargs[0], 166 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); 167 nudge_writes(); 168 } 169 170 static void csr_ipi_probe(void) 171 { 172 if (cpu_has_csr() && csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_IPI) { 173 ipi_read_clear = csr_ipi_read_clear; 174 ipi_write_action = csr_ipi_write_action; 175 ipi_write_enable = csr_ipi_write_enable; 176 ipi_clear_buf = csr_ipi_clear_buf; 177 ipi_write_buf = csr_ipi_write_buf; 178 } else { 179 ipi_read_clear = legacy_ipi_read_clear; 180 ipi_write_action = legacy_ipi_write_action; 181 ipi_write_enable = legacy_ipi_write_enable; 182 ipi_clear_buf = legacy_ipi_clear_buf; 183 ipi_write_buf = legacy_ipi_write_buf; 184 } 185 } 186 187 static void ipi_set0_regs_init(void) 188 { 189 ipi_set0_regs[0] = (void *) 190 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0); 191 ipi_set0_regs[1] = (void *) 192 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0); 193 ipi_set0_regs[2] = (void *) 194 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0); 195 ipi_set0_regs[3] = (void *) 196 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0); 197 ipi_set0_regs[4] = (void *) 198 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0); 199 ipi_set0_regs[5] = (void *) 200 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0); 201 ipi_set0_regs[6] = (void *) 202 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0); 203 ipi_set0_regs[7] = (void *) 204 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0); 205 ipi_set0_regs[8] = (void *) 206 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0); 207 ipi_set0_regs[9] = (void *) 208 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0); 209 ipi_set0_regs[10] = (void *) 210 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0); 211 ipi_set0_regs[11] = (void *) 212 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0); 213 ipi_set0_regs[12] = (void *) 214 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0); 215 ipi_set0_regs[13] = (void *) 216 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0); 217 ipi_set0_regs[14] = (void *) 218 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0); 219 ipi_set0_regs[15] = (void *) 220 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0); 221 } 222 223 static void ipi_clear0_regs_init(void) 224 { 225 ipi_clear0_regs[0] = (void *) 226 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0); 227 ipi_clear0_regs[1] = (void *) 228 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0); 229 ipi_clear0_regs[2] = (void *) 230 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0); 231 ipi_clear0_regs[3] = (void *) 232 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0); 233 ipi_clear0_regs[4] = (void *) 234 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0); 235 ipi_clear0_regs[5] = (void *) 236 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0); 237 ipi_clear0_regs[6] = (void *) 238 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0); 239 ipi_clear0_regs[7] = (void *) 240 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0); 241 ipi_clear0_regs[8] = (void *) 242 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0); 243 ipi_clear0_regs[9] = (void *) 244 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0); 245 ipi_clear0_regs[10] = (void *) 246 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0); 247 ipi_clear0_regs[11] = (void *) 248 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0); 249 ipi_clear0_regs[12] = (void *) 250 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0); 251 ipi_clear0_regs[13] = (void *) 252 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0); 253 ipi_clear0_regs[14] = (void *) 254 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0); 255 ipi_clear0_regs[15] = (void *) 256 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0); 257 } 258 259 static void ipi_status0_regs_init(void) 260 { 261 ipi_status0_regs[0] = (void *) 262 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0); 263 ipi_status0_regs[1] = (void *) 264 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0); 265 ipi_status0_regs[2] = (void *) 266 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0); 267 ipi_status0_regs[3] = (void *) 268 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0); 269 ipi_status0_regs[4] = (void *) 270 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0); 271 ipi_status0_regs[5] = (void *) 272 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0); 273 ipi_status0_regs[6] = (void *) 274 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0); 275 ipi_status0_regs[7] = (void *) 276 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0); 277 ipi_status0_regs[8] = (void *) 278 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0); 279 ipi_status0_regs[9] = (void *) 280 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0); 281 ipi_status0_regs[10] = (void *) 282 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0); 283 ipi_status0_regs[11] = (void *) 284 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0); 285 ipi_status0_regs[12] = (void *) 286 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0); 287 ipi_status0_regs[13] = (void *) 288 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0); 289 ipi_status0_regs[14] = (void *) 290 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0); 291 ipi_status0_regs[15] = (void *) 292 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0); 293 } 294 295 static void ipi_en0_regs_init(void) 296 { 297 ipi_en0_regs[0] = (void *) 298 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0); 299 ipi_en0_regs[1] = (void *) 300 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0); 301 ipi_en0_regs[2] = (void *) 302 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0); 303 ipi_en0_regs[3] = (void *) 304 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0); 305 ipi_en0_regs[4] = (void *) 306 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0); 307 ipi_en0_regs[5] = (void *) 308 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0); 309 ipi_en0_regs[6] = (void *) 310 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0); 311 ipi_en0_regs[7] = (void *) 312 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0); 313 ipi_en0_regs[8] = (void *) 314 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0); 315 ipi_en0_regs[9] = (void *) 316 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0); 317 ipi_en0_regs[10] = (void *) 318 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0); 319 ipi_en0_regs[11] = (void *) 320 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0); 321 ipi_en0_regs[12] = (void *) 322 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0); 323 ipi_en0_regs[13] = (void *) 324 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0); 325 ipi_en0_regs[14] = (void *) 326 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0); 327 ipi_en0_regs[15] = (void *) 328 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0); 329 } 330 331 static void ipi_mailbox_buf_init(void) 332 { 333 ipi_mailbox_buf[0] = (void *) 334 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF); 335 ipi_mailbox_buf[1] = (void *) 336 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF); 337 ipi_mailbox_buf[2] = (void *) 338 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF); 339 ipi_mailbox_buf[3] = (void *) 340 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF); 341 ipi_mailbox_buf[4] = (void *) 342 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF); 343 ipi_mailbox_buf[5] = (void *) 344 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF); 345 ipi_mailbox_buf[6] = (void *) 346 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF); 347 ipi_mailbox_buf[7] = (void *) 348 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF); 349 ipi_mailbox_buf[8] = (void *) 350 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF); 351 ipi_mailbox_buf[9] = (void *) 352 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF); 353 ipi_mailbox_buf[10] = (void *) 354 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF); 355 ipi_mailbox_buf[11] = (void *) 356 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF); 357 ipi_mailbox_buf[12] = (void *) 358 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF); 359 ipi_mailbox_buf[13] = (void *) 360 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF); 361 ipi_mailbox_buf[14] = (void *) 362 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF); 363 ipi_mailbox_buf[15] = (void *) 364 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF); 365 } 366 367 /* 368 * Simple enough, just poke the appropriate ipi register 369 */ 370 static void loongson3_send_ipi_single(int cpu, unsigned int action) 371 { 372 ipi_write_action(cpu_logical_map(cpu), (u32)action); 373 } 374 375 static void 376 loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) 377 { 378 unsigned int i; 379 380 for_each_cpu(i, mask) 381 ipi_write_action(cpu_logical_map(i), (u32)action); 382 } 383 384 385 static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) 386 { 387 int i, cpu = smp_processor_id(); 388 unsigned int action, c0count; 389 390 action = ipi_read_clear(cpu); 391 392 if (action & SMP_RESCHEDULE_YOURSELF) 393 scheduler_ipi(); 394 395 if (action & SMP_CALL_FUNCTION) { 396 irq_enter(); 397 generic_smp_call_function_interrupt(); 398 irq_exit(); 399 } 400 401 if (action & SMP_ASK_C0COUNT) { 402 BUG_ON(cpu != 0); 403 c0count = read_c0_count(); 404 c0count = c0count ? c0count : 1; 405 for (i = 1; i < nr_cpu_ids; i++) 406 core0_c0count[i] = c0count; 407 nudge_writes(); /* Let others see the result ASAP */ 408 } 409 410 return IRQ_HANDLED; 411 } 412 413 #define MAX_LOOPS 800 414 /* 415 * SMP init and finish on secondary CPUs 416 */ 417 static void loongson3_init_secondary(void) 418 { 419 int i; 420 uint32_t initcount; 421 unsigned int cpu = smp_processor_id(); 422 unsigned int imask = STATUSF_IP7 | STATUSF_IP6 | 423 STATUSF_IP3 | STATUSF_IP2; 424 425 /* Set interrupt mask, but don't enable */ 426 change_c0_status(ST0_IM, imask); 427 ipi_write_enable(cpu); 428 429 per_cpu(cpu_state, cpu) = CPU_ONLINE; 430 cpu_set_core(&cpu_data[cpu], 431 cpu_logical_map(cpu) % loongson_sysconf.cores_per_package); 432 cpu_data[cpu].package = 433 cpu_logical_map(cpu) / loongson_sysconf.cores_per_package; 434 435 i = 0; 436 core0_c0count[cpu] = 0; 437 loongson3_send_ipi_single(0, SMP_ASK_C0COUNT); 438 while (!core0_c0count[cpu]) { 439 i++; 440 cpu_relax(); 441 } 442 443 if (i > MAX_LOOPS) 444 i = MAX_LOOPS; 445 if (cpu_data[cpu].package) 446 initcount = core0_c0count[cpu] + i; 447 else /* Local access is faster for loops */ 448 initcount = core0_c0count[cpu] + i/2; 449 450 write_c0_count(initcount); 451 } 452 453 static void loongson3_smp_finish(void) 454 { 455 int cpu = smp_processor_id(); 456 457 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); 458 local_irq_enable(); 459 ipi_clear_buf(cpu); 460 461 pr_info("CPU#%d finished, CP0_ST=%x\n", 462 smp_processor_id(), read_c0_status()); 463 } 464 465 static void __init loongson3_smp_setup(void) 466 { 467 int i = 0, num = 0; /* i: physical id, num: logical id */ 468 469 init_cpu_possible(cpu_none_mask); 470 471 /* For unified kernel, NR_CPUS is the maximum possible value, 472 * loongson_sysconf.nr_cpus is the really present value 473 */ 474 while (i < loongson_sysconf.nr_cpus) { 475 if (loongson_sysconf.reserved_cpus_mask & (1<<i)) { 476 /* Reserved physical CPU cores */ 477 __cpu_number_map[i] = -1; 478 } else { 479 __cpu_number_map[i] = num; 480 __cpu_logical_map[num] = i; 481 set_cpu_possible(num, true); 482 /* Loongson processors are always grouped by 4 */ 483 cpu_set_cluster(&cpu_data[num], i / 4); 484 num++; 485 } 486 i++; 487 } 488 pr_info("Detected %i available CPU(s)\n", num); 489 490 while (num < loongson_sysconf.nr_cpus) { 491 __cpu_logical_map[num] = -1; 492 num++; 493 } 494 495 csr_ipi_probe(); 496 ipi_set0_regs_init(); 497 ipi_clear0_regs_init(); 498 ipi_status0_regs_init(); 499 ipi_en0_regs_init(); 500 ipi_mailbox_buf_init(); 501 ipi_write_enable(0); 502 503 cpu_set_core(&cpu_data[0], 504 cpu_logical_map(0) % loongson_sysconf.cores_per_package); 505 cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package; 506 } 507 508 static void __init loongson3_prepare_cpus(unsigned int max_cpus) 509 { 510 if (request_irq(LS_IPI_IRQ, loongson3_ipi_interrupt, 511 IRQF_PERCPU | IRQF_NO_SUSPEND, "SMP_IPI", NULL)) 512 pr_err("Failed to request IPI IRQ\n"); 513 init_cpu_present(cpu_possible_mask); 514 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 515 } 516 517 /* 518 * Setup the PC, SP, and GP of a secondary processor and start it runing! 519 */ 520 static int loongson3_boot_secondary(int cpu, struct task_struct *idle) 521 { 522 pr_info("Booting CPU#%d...\n", cpu); 523 524 ipi_write_buf(cpu, idle); 525 526 return 0; 527 } 528 529 #ifdef CONFIG_HOTPLUG_CPU 530 531 static int loongson3_cpu_disable(void) 532 { 533 unsigned long flags; 534 unsigned int cpu = smp_processor_id(); 535 536 set_cpu_online(cpu, false); 537 calculate_cpu_foreign_map(); 538 local_irq_save(flags); 539 clear_c0_status(ST0_IM); 540 local_irq_restore(flags); 541 local_flush_tlb_all(); 542 543 return 0; 544 } 545 546 547 static void loongson3_cpu_die(unsigned int cpu) 548 { 549 while (per_cpu(cpu_state, cpu) != CPU_DEAD) 550 cpu_relax(); 551 552 mb(); 553 } 554 555 /* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and 556 * flush all L1 entries at first. Then, another core (usually Core 0) can 557 * safely disable the clock of the target core. loongson3_play_dead() is 558 * called via CKSEG1 (uncached and unmmaped) 559 */ 560 static void loongson3_type1_play_dead(int *state_addr) 561 { 562 register int val; 563 register long cpuid, core, node, count; 564 register void *addr, *base, *initfunc; 565 566 __asm__ __volatile__( 567 " .set push \n" 568 " .set noreorder \n" 569 " li %[addr], 0x80000000 \n" /* KSEG0 */ 570 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ 571 " cache 0, 1(%[addr]) \n" 572 " cache 0, 2(%[addr]) \n" 573 " cache 0, 3(%[addr]) \n" 574 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */ 575 " cache 1, 1(%[addr]) \n" 576 " cache 1, 2(%[addr]) \n" 577 " cache 1, 3(%[addr]) \n" 578 " addiu %[sets], %[sets], -1 \n" 579 " bnez %[sets], 1b \n" 580 " addiu %[addr], %[addr], 0x20 \n" 581 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ 582 " sw %[val], (%[state_addr]) \n" 583 " sync \n" 584 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */ 585 " .set pop \n" 586 : [addr] "=&r" (addr), [val] "=&r" (val) 587 : [state_addr] "r" (state_addr), 588 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); 589 590 __asm__ __volatile__( 591 " .set push \n" 592 " .set noreorder \n" 593 " .set mips64 \n" 594 " mfc0 %[cpuid], $15, 1 \n" 595 " andi %[cpuid], 0x3ff \n" 596 " dli %[base], 0x900000003ff01000 \n" 597 " andi %[core], %[cpuid], 0x3 \n" 598 " sll %[core], 8 \n" /* get core id */ 599 " or %[base], %[base], %[core] \n" 600 " andi %[node], %[cpuid], 0xc \n" 601 " dsll %[node], 42 \n" /* get node id */ 602 " or %[base], %[base], %[node] \n" 603 "1: li %[count], 0x100 \n" /* wait for init loop */ 604 "2: bnez %[count], 2b \n" /* limit mailbox access */ 605 " addiu %[count], -1 \n" 606 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */ 607 " beqz %[initfunc], 1b \n" 608 " nop \n" 609 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ 610 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ 611 " ld $a1, 0x38(%[base]) \n" 612 " jr %[initfunc] \n" /* jump to initial PC */ 613 " nop \n" 614 " .set pop \n" 615 : [core] "=&r" (core), [node] "=&r" (node), 616 [base] "=&r" (base), [cpuid] "=&r" (cpuid), 617 [count] "=&r" (count), [initfunc] "=&r" (initfunc) 618 : /* No Input */ 619 : "a1"); 620 } 621 622 static void loongson3_type2_play_dead(int *state_addr) 623 { 624 register int val; 625 register long cpuid, core, node, count; 626 register void *addr, *base, *initfunc; 627 628 __asm__ __volatile__( 629 " .set push \n" 630 " .set noreorder \n" 631 " li %[addr], 0x80000000 \n" /* KSEG0 */ 632 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ 633 " cache 0, 1(%[addr]) \n" 634 " cache 0, 2(%[addr]) \n" 635 " cache 0, 3(%[addr]) \n" 636 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */ 637 " cache 1, 1(%[addr]) \n" 638 " cache 1, 2(%[addr]) \n" 639 " cache 1, 3(%[addr]) \n" 640 " addiu %[sets], %[sets], -1 \n" 641 " bnez %[sets], 1b \n" 642 " addiu %[addr], %[addr], 0x20 \n" 643 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ 644 " sw %[val], (%[state_addr]) \n" 645 " sync \n" 646 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */ 647 " .set pop \n" 648 : [addr] "=&r" (addr), [val] "=&r" (val) 649 : [state_addr] "r" (state_addr), 650 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets)); 651 652 __asm__ __volatile__( 653 " .set push \n" 654 " .set noreorder \n" 655 " .set mips64 \n" 656 " mfc0 %[cpuid], $15, 1 \n" 657 " andi %[cpuid], 0x3ff \n" 658 " dli %[base], 0x900000003ff01000 \n" 659 " andi %[core], %[cpuid], 0x3 \n" 660 " sll %[core], 8 \n" /* get core id */ 661 " or %[base], %[base], %[core] \n" 662 " andi %[node], %[cpuid], 0xc \n" 663 " dsll %[node], 42 \n" /* get node id */ 664 " or %[base], %[base], %[node] \n" 665 " dsrl %[node], 30 \n" /* 15:14 */ 666 " or %[base], %[base], %[node] \n" 667 "1: li %[count], 0x100 \n" /* wait for init loop */ 668 "2: bnez %[count], 2b \n" /* limit mailbox access */ 669 " addiu %[count], -1 \n" 670 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */ 671 " beqz %[initfunc], 1b \n" 672 " nop \n" 673 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ 674 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ 675 " ld $a1, 0x38(%[base]) \n" 676 " jr %[initfunc] \n" /* jump to initial PC */ 677 " nop \n" 678 " .set pop \n" 679 : [core] "=&r" (core), [node] "=&r" (node), 680 [base] "=&r" (base), [cpuid] "=&r" (cpuid), 681 [count] "=&r" (count), [initfunc] "=&r" (initfunc) 682 : /* No Input */ 683 : "a1"); 684 } 685 686 static void loongson3_type3_play_dead(int *state_addr) 687 { 688 register int val; 689 register long cpuid, core, node, count; 690 register void *addr, *base, *initfunc; 691 692 __asm__ __volatile__( 693 " .set push \n" 694 " .set noreorder \n" 695 " li %[addr], 0x80000000 \n" /* KSEG0 */ 696 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */ 697 " cache 0, 1(%[addr]) \n" 698 " cache 0, 2(%[addr]) \n" 699 " cache 0, 3(%[addr]) \n" 700 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */ 701 " cache 1, 1(%[addr]) \n" 702 " cache 1, 2(%[addr]) \n" 703 " cache 1, 3(%[addr]) \n" 704 " addiu %[sets], %[sets], -1 \n" 705 " bnez %[sets], 1b \n" 706 " addiu %[addr], %[addr], 0x40 \n" 707 " li %[addr], 0x80000000 \n" /* KSEG0 */ 708 "2: cache 2, 0(%[addr]) \n" /* flush L1 VCache */ 709 " cache 2, 1(%[addr]) \n" 710 " cache 2, 2(%[addr]) \n" 711 " cache 2, 3(%[addr]) \n" 712 " cache 2, 4(%[addr]) \n" 713 " cache 2, 5(%[addr]) \n" 714 " cache 2, 6(%[addr]) \n" 715 " cache 2, 7(%[addr]) \n" 716 " cache 2, 8(%[addr]) \n" 717 " cache 2, 9(%[addr]) \n" 718 " cache 2, 10(%[addr]) \n" 719 " cache 2, 11(%[addr]) \n" 720 " cache 2, 12(%[addr]) \n" 721 " cache 2, 13(%[addr]) \n" 722 " cache 2, 14(%[addr]) \n" 723 " cache 2, 15(%[addr]) \n" 724 " addiu %[vsets], %[vsets], -1 \n" 725 " bnez %[vsets], 2b \n" 726 " addiu %[addr], %[addr], 0x40 \n" 727 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */ 728 " sw %[val], (%[state_addr]) \n" 729 " sync \n" 730 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */ 731 " .set pop \n" 732 : [addr] "=&r" (addr), [val] "=&r" (val) 733 : [state_addr] "r" (state_addr), 734 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets), 735 [vsets] "r" (cpu_data[smp_processor_id()].vcache.sets)); 736 737 __asm__ __volatile__( 738 " .set push \n" 739 " .set noreorder \n" 740 " .set mips64 \n" 741 " mfc0 %[cpuid], $15, 1 \n" 742 " andi %[cpuid], 0x3ff \n" 743 " dli %[base], 0x900000003ff01000 \n" 744 " andi %[core], %[cpuid], 0x3 \n" 745 " sll %[core], 8 \n" /* get core id */ 746 " or %[base], %[base], %[core] \n" 747 " andi %[node], %[cpuid], 0xc \n" 748 " dsll %[node], 42 \n" /* get node id */ 749 " or %[base], %[base], %[node] \n" 750 "1: li %[count], 0x100 \n" /* wait for init loop */ 751 "2: bnez %[count], 2b \n" /* limit mailbox access */ 752 " addiu %[count], -1 \n" 753 " lw %[initfunc], 0x20(%[base]) \n" /* check lower 32-bit as jump indicator */ 754 " beqz %[initfunc], 1b \n" 755 " nop \n" 756 " ld %[initfunc], 0x20(%[base]) \n" /* get PC (whole 64-bit) via mailbox */ 757 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */ 758 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */ 759 " ld $a1, 0x38(%[base]) \n" 760 " jr %[initfunc] \n" /* jump to initial PC */ 761 " nop \n" 762 " .set pop \n" 763 : [core] "=&r" (core), [node] "=&r" (node), 764 [base] "=&r" (base), [cpuid] "=&r" (cpuid), 765 [count] "=&r" (count), [initfunc] "=&r" (initfunc) 766 : /* No Input */ 767 : "a1"); 768 } 769 770 void play_dead(void) 771 { 772 int prid_imp, prid_rev, *state_addr; 773 unsigned int cpu = smp_processor_id(); 774 void (*play_dead_at_ckseg1)(int *); 775 776 idle_task_exit(); 777 778 prid_imp = read_c0_prid() & PRID_IMP_MASK; 779 prid_rev = read_c0_prid() & PRID_REV_MASK; 780 781 if (prid_imp == PRID_IMP_LOONGSON_64G) { 782 play_dead_at_ckseg1 = 783 (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead); 784 goto out; 785 } 786 787 switch (prid_rev) { 788 case PRID_REV_LOONGSON3A_R1: 789 default: 790 play_dead_at_ckseg1 = 791 (void *)CKSEG1ADDR((unsigned long)loongson3_type1_play_dead); 792 break; 793 case PRID_REV_LOONGSON3B_R1: 794 case PRID_REV_LOONGSON3B_R2: 795 play_dead_at_ckseg1 = 796 (void *)CKSEG1ADDR((unsigned long)loongson3_type2_play_dead); 797 break; 798 case PRID_REV_LOONGSON3A_R2_0: 799 case PRID_REV_LOONGSON3A_R2_1: 800 case PRID_REV_LOONGSON3A_R3_0: 801 case PRID_REV_LOONGSON3A_R3_1: 802 play_dead_at_ckseg1 = 803 (void *)CKSEG1ADDR((unsigned long)loongson3_type3_play_dead); 804 break; 805 } 806 807 out: 808 state_addr = &per_cpu(cpu_state, cpu); 809 mb(); 810 play_dead_at_ckseg1(state_addr); 811 } 812 813 static int loongson3_disable_clock(unsigned int cpu) 814 { 815 uint64_t core_id = cpu_core(&cpu_data[cpu]); 816 uint64_t package_id = cpu_data[cpu].package; 817 818 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) { 819 LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id)); 820 } else { 821 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG)) 822 LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3)); 823 } 824 return 0; 825 } 826 827 static int loongson3_enable_clock(unsigned int cpu) 828 { 829 uint64_t core_id = cpu_core(&cpu_data[cpu]); 830 uint64_t package_id = cpu_data[cpu].package; 831 832 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) { 833 LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id); 834 } else { 835 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG)) 836 LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3); 837 } 838 return 0; 839 } 840 841 static int register_loongson3_notifier(void) 842 { 843 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE, 844 "mips/loongson:prepare", 845 loongson3_enable_clock, 846 loongson3_disable_clock); 847 } 848 early_initcall(register_loongson3_notifier); 849 850 #endif 851 852 const struct plat_smp_ops loongson3_smp_ops = { 853 .send_ipi_single = loongson3_send_ipi_single, 854 .send_ipi_mask = loongson3_send_ipi_mask, 855 .init_secondary = loongson3_init_secondary, 856 .smp_finish = loongson3_smp_finish, 857 .boot_secondary = loongson3_boot_secondary, 858 .smp_setup = loongson3_smp_setup, 859 .prepare_cpus = loongson3_prepare_cpus, 860 #ifdef CONFIG_HOTPLUG_CPU 861 .cpu_disable = loongson3_cpu_disable, 862 .cpu_die = loongson3_cpu_die, 863 #endif 864 #ifdef CONFIG_KEXEC 865 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 866 #endif 867 }; 868