1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology 4 * Author: Fuxin Zhang, zhangfx@lemote.com 5 */ 6 #include <linux/interrupt.h> 7 8 #include <asm/irq_cpu.h> 9 #include <asm/i8259.h> 10 11 #include <loongson.h> 12 13 static void i8259_irqdispatch(void) 14 { 15 int irq; 16 17 irq = i8259_irq(); 18 if (irq >= 0) 19 do_IRQ(irq); 20 else 21 spurious_interrupt(); 22 } 23 24 asmlinkage void mach_irq_dispatch(unsigned int pending) 25 { 26 if (pending & CAUSEF_IP7) 27 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 28 else if (pending & CAUSEF_IP6) /* perf counter loverflow */ 29 do_perfcnt_IRQ(); 30 else if (pending & CAUSEF_IP5) 31 i8259_irqdispatch(); 32 else if (pending & CAUSEF_IP2) 33 bonito_irqdispatch(); 34 else 35 spurious_interrupt(); 36 } 37 38 static struct irqaction cascade_irqaction = { 39 .handler = no_action, 40 .name = "cascade", 41 .flags = IRQF_NO_THREAD, 42 }; 43 44 void __init mach_init_irq(void) 45 { 46 /* init all controller 47 * 0-15 ------> i8259 interrupt 48 * 16-23 ------> mips cpu interrupt 49 * 32-63 ------> bonito irq 50 */ 51 52 /* most bonito irq should be level triggered */ 53 LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR | 54 LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES; 55 56 /* Sets the first-level interrupt dispatcher. */ 57 mips_cpu_irq_init(); 58 init_i8259_irqs(); 59 bonito_irq_init(); 60 61 /* bonito irq at IP2 */ 62 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); 63 /* 8259 irq at IP5 */ 64 setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); 65 } 66