1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2011-2012 John Crispin <john@phrozen.org> 5 * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG 6 */ 7 8 #include <linux/ioport.h> 9 #include <linux/export.h> 10 #include <linux/clkdev.h> 11 #include <linux/spinlock.h> 12 #include <linux/of.h> 13 #include <linux/of_platform.h> 14 #include <linux/of_address.h> 15 16 #include <lantiq_soc.h> 17 18 #include "../clk.h" 19 #include "../prom.h" 20 21 /* clock control register for legacy */ 22 #define CGU_IFCCR 0x0018 23 #define CGU_IFCCR_VR9 0x0024 24 /* system clock register for legacy */ 25 #define CGU_SYS 0x0010 26 /* pci control register */ 27 #define CGU_PCICR 0x0034 28 #define CGU_PCICR_VR9 0x0038 29 /* ephy configuration register */ 30 #define CGU_EPHY 0x10 31 32 /* Legacy PMU register for ar9, ase, danube */ 33 /* power control register */ 34 #define PMU_PWDCR 0x1C 35 /* power status register */ 36 #define PMU_PWDSR 0x20 37 /* power control register */ 38 #define PMU_PWDCR1 0x24 39 /* power status register */ 40 #define PMU_PWDSR1 0x28 41 /* power control register */ 42 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR)) 43 /* power status register */ 44 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) 45 46 47 /* PMU register for ar10 and grx390 */ 48 49 /* First register set */ 50 #define PMU_CLK_SR 0x20 /* status */ 51 #define PMU_CLK_CR_A 0x24 /* Enable */ 52 #define PMU_CLK_CR_B 0x28 /* Disable */ 53 /* Second register set */ 54 #define PMU_CLK_SR1 0x30 /* status */ 55 #define PMU_CLK_CR1_A 0x34 /* Enable */ 56 #define PMU_CLK_CR1_B 0x38 /* Disable */ 57 /* Third register set */ 58 #define PMU_ANA_SR 0x40 /* status */ 59 #define PMU_ANA_CR_A 0x44 /* Enable */ 60 #define PMU_ANA_CR_B 0x48 /* Disable */ 61 62 /* Status */ 63 static u32 pmu_clk_sr[] = { 64 PMU_CLK_SR, 65 PMU_CLK_SR1, 66 PMU_ANA_SR, 67 }; 68 69 /* Enable */ 70 static u32 pmu_clk_cr_a[] = { 71 PMU_CLK_CR_A, 72 PMU_CLK_CR1_A, 73 PMU_ANA_CR_A, 74 }; 75 76 /* Disable */ 77 static u32 pmu_clk_cr_b[] = { 78 PMU_CLK_CR_B, 79 PMU_CLK_CR1_B, 80 PMU_ANA_CR_B, 81 }; 82 83 #define PWDCR_EN_XRX(x) (pmu_clk_cr_a[(x)]) 84 #define PWDCR_DIS_XRX(x) (pmu_clk_cr_b[(x)]) 85 #define PWDSR_XRX(x) (pmu_clk_sr[(x)]) 86 87 /* clock gates that we can en/disable */ 88 #define PMU_USB0_P BIT(0) 89 #define PMU_ASE_SDIO BIT(2) /* ASE special */ 90 #define PMU_PCI BIT(4) 91 #define PMU_DMA BIT(5) 92 #define PMU_USB0 BIT(6) 93 #define PMU_ASC0 BIT(7) 94 #define PMU_EPHY BIT(7) /* ase */ 95 #define PMU_USIF BIT(7) /* from vr9 until grx390 */ 96 #define PMU_SPI BIT(8) 97 #define PMU_DFE BIT(9) 98 #define PMU_EBU BIT(10) 99 #define PMU_STP BIT(11) 100 #define PMU_GPT BIT(12) 101 #define PMU_AHBS BIT(13) /* vr9 */ 102 #define PMU_FPI BIT(14) 103 #define PMU_AHBM BIT(15) 104 #define PMU_SDIO BIT(16) /* danube, ar9, vr9 */ 105 #define PMU_ASC1 BIT(17) 106 #define PMU_PPE_QSB BIT(18) 107 #define PMU_PPE_SLL01 BIT(19) 108 #define PMU_DEU BIT(20) 109 #define PMU_PPE_TC BIT(21) 110 #define PMU_PPE_EMA BIT(22) 111 #define PMU_PPE_DPLUM BIT(23) 112 #define PMU_PPE_DP BIT(23) 113 #define PMU_PPE_DPLUS BIT(24) 114 #define PMU_USB1_P BIT(26) 115 #define PMU_USB1 BIT(27) 116 #define PMU_SWITCH BIT(28) 117 #define PMU_PPE_TOP BIT(29) 118 #define PMU_GPHY BIT(30) 119 #define PMU_PCIE_CLK BIT(31) 120 121 #define PMU1_PCIE_PHY BIT(0) /* vr9-specific,moved in ar10/grx390 */ 122 #define PMU1_PCIE_CTL BIT(1) 123 #define PMU1_PCIE_PDI BIT(4) 124 #define PMU1_PCIE_MSI BIT(5) 125 #define PMU1_CKE BIT(6) 126 #define PMU1_PCIE1_CTL BIT(17) 127 #define PMU1_PCIE1_PDI BIT(20) 128 #define PMU1_PCIE1_MSI BIT(21) 129 #define PMU1_PCIE2_CTL BIT(25) 130 #define PMU1_PCIE2_PDI BIT(26) 131 #define PMU1_PCIE2_MSI BIT(27) 132 133 #define PMU_ANALOG_USB0_P BIT(0) 134 #define PMU_ANALOG_USB1_P BIT(1) 135 #define PMU_ANALOG_PCIE0_P BIT(8) 136 #define PMU_ANALOG_PCIE1_P BIT(9) 137 #define PMU_ANALOG_PCIE2_P BIT(10) 138 #define PMU_ANALOG_DSL_AFE BIT(16) 139 #define PMU_ANALOG_DCDC_2V5 BIT(17) 140 #define PMU_ANALOG_DCDC_1VX BIT(18) 141 #define PMU_ANALOG_DCDC_1V0 BIT(19) 142 143 #define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y)) 144 #define pmu_r32(x) ltq_r32(pmu_membase + (x)) 145 146 static void __iomem *pmu_membase; 147 void __iomem *ltq_cgu_membase; 148 void __iomem *ltq_ebu_membase; 149 150 static u32 ifccr = CGU_IFCCR; 151 static u32 pcicr = CGU_PCICR; 152 153 static DEFINE_SPINLOCK(g_pmu_lock); 154 155 /* legacy function kept alive to ease clkdev transition */ 156 void ltq_pmu_enable(unsigned int module) 157 { 158 int retry = 1000000; 159 160 spin_lock(&g_pmu_lock); 161 pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR); 162 do {} while (--retry && (pmu_r32(PMU_PWDSR) & module)); 163 spin_unlock(&g_pmu_lock); 164 165 if (!retry) 166 panic("activating PMU module failed!"); 167 } 168 EXPORT_SYMBOL(ltq_pmu_enable); 169 170 /* legacy function kept alive to ease clkdev transition */ 171 void ltq_pmu_disable(unsigned int module) 172 { 173 int retry = 1000000; 174 175 spin_lock(&g_pmu_lock); 176 pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR); 177 do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module))); 178 spin_unlock(&g_pmu_lock); 179 180 if (!retry) 181 pr_warn("deactivating PMU module failed!"); 182 } 183 EXPORT_SYMBOL(ltq_pmu_disable); 184 185 /* enable a hw clock */ 186 static int cgu_enable(struct clk *clk) 187 { 188 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); 189 return 0; 190 } 191 192 /* disable a hw clock */ 193 static void cgu_disable(struct clk *clk) 194 { 195 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); 196 } 197 198 /* enable a clock gate */ 199 static int pmu_enable(struct clk *clk) 200 { 201 int retry = 1000000; 202 203 if (of_machine_is_compatible("lantiq,ar10") 204 || of_machine_is_compatible("lantiq,grx390")) { 205 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module)); 206 do {} while (--retry && 207 (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits))); 208 209 } else { 210 spin_lock(&g_pmu_lock); 211 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits, 212 PWDCR(clk->module)); 213 do {} while (--retry && 214 (pmu_r32(PWDSR(clk->module)) & clk->bits)); 215 spin_unlock(&g_pmu_lock); 216 } 217 218 if (!retry) 219 panic("activating PMU module failed!"); 220 221 return 0; 222 } 223 224 /* disable a clock gate */ 225 static void pmu_disable(struct clk *clk) 226 { 227 int retry = 1000000; 228 229 if (of_machine_is_compatible("lantiq,ar10") 230 || of_machine_is_compatible("lantiq,grx390")) { 231 pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module)); 232 do {} while (--retry && 233 (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)); 234 } else { 235 spin_lock(&g_pmu_lock); 236 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits, 237 PWDCR(clk->module)); 238 do {} while (--retry && 239 (!(pmu_r32(PWDSR(clk->module)) & clk->bits))); 240 spin_unlock(&g_pmu_lock); 241 } 242 243 if (!retry) 244 pr_warn("deactivating PMU module failed!"); 245 } 246 247 /* the pci enable helper */ 248 static int pci_enable(struct clk *clk) 249 { 250 unsigned int val = ltq_cgu_r32(ifccr); 251 /* set bus clock speed */ 252 if (of_machine_is_compatible("lantiq,ar9") || 253 of_machine_is_compatible("lantiq,vr9")) { 254 val &= ~0x1f00000; 255 if (clk->rate == CLOCK_33M) 256 val |= 0xe00000; 257 else 258 val |= 0x700000; /* 62.5M */ 259 } else { 260 val &= ~0xf00000; 261 if (clk->rate == CLOCK_33M) 262 val |= 0x800000; 263 else 264 val |= 0x400000; /* 62.5M */ 265 } 266 ltq_cgu_w32(val, ifccr); 267 pmu_enable(clk); 268 return 0; 269 } 270 271 /* enable the external clock as a source */ 272 static int pci_ext_enable(struct clk *clk) 273 { 274 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr); 275 ltq_cgu_w32((1 << 30), pcicr); 276 return 0; 277 } 278 279 /* disable the external clock as a source */ 280 static void pci_ext_disable(struct clk *clk) 281 { 282 ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr); 283 ltq_cgu_w32((1 << 31) | (1 << 30), pcicr); 284 } 285 286 /* enable a clockout source */ 287 static int clkout_enable(struct clk *clk) 288 { 289 int i; 290 291 /* get the correct rate */ 292 for (i = 0; i < 4; i++) { 293 if (clk->rates[i] == clk->rate) { 294 int shift = 14 - (2 * clk->module); 295 int enable = 7 - clk->module; 296 unsigned int val = ltq_cgu_r32(ifccr); 297 298 val &= ~(3 << shift); 299 val |= i << shift; 300 val |= enable; 301 ltq_cgu_w32(val, ifccr); 302 return 0; 303 } 304 } 305 return -1; 306 } 307 308 /* manage the clock gates via PMU */ 309 static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate, 310 unsigned int module, unsigned int bits) 311 { 312 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 313 314 clk->cl.dev_id = dev; 315 clk->cl.con_id = con; 316 clk->cl.clk = clk; 317 clk->enable = pmu_enable; 318 clk->disable = pmu_disable; 319 clk->module = module; 320 clk->bits = bits; 321 if (deactivate) { 322 /* 323 * Disable it during the initialization. Module should enable 324 * when used 325 */ 326 pmu_disable(clk); 327 } 328 clkdev_add(&clk->cl); 329 } 330 331 /* manage the clock generator */ 332 static void clkdev_add_cgu(const char *dev, const char *con, 333 unsigned int bits) 334 { 335 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 336 337 clk->cl.dev_id = dev; 338 clk->cl.con_id = con; 339 clk->cl.clk = clk; 340 clk->enable = cgu_enable; 341 clk->disable = cgu_disable; 342 clk->bits = bits; 343 clkdev_add(&clk->cl); 344 } 345 346 /* pci needs its own enable function as the setup is a bit more complex */ 347 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0}; 348 349 static void clkdev_add_pci(void) 350 { 351 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 352 struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); 353 354 /* main pci clock */ 355 clk->cl.dev_id = "17000000.pci"; 356 clk->cl.con_id = NULL; 357 clk->cl.clk = clk; 358 clk->rate = CLOCK_33M; 359 clk->rates = valid_pci_rates; 360 clk->enable = pci_enable; 361 clk->disable = pmu_disable; 362 clk->module = 0; 363 clk->bits = PMU_PCI; 364 clkdev_add(&clk->cl); 365 366 /* use internal/external bus clock */ 367 clk_ext->cl.dev_id = "17000000.pci"; 368 clk_ext->cl.con_id = "external"; 369 clk_ext->cl.clk = clk_ext; 370 clk_ext->enable = pci_ext_enable; 371 clk_ext->disable = pci_ext_disable; 372 clkdev_add(&clk_ext->cl); 373 } 374 375 /* xway socs can generate clocks on gpio pins */ 376 static unsigned long valid_clkout_rates[4][5] = { 377 {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0}, 378 {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0}, 379 {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0}, 380 {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0}, 381 }; 382 383 static void clkdev_add_clkout(void) 384 { 385 int i; 386 387 for (i = 0; i < 4; i++) { 388 struct clk *clk; 389 char *name; 390 391 name = kzalloc(sizeof("clkout0"), GFP_KERNEL); 392 sprintf(name, "clkout%d", i); 393 394 clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 395 clk->cl.dev_id = "1f103000.cgu"; 396 clk->cl.con_id = name; 397 clk->cl.clk = clk; 398 clk->rate = 0; 399 clk->rates = valid_clkout_rates[i]; 400 clk->enable = clkout_enable; 401 clk->module = i; 402 clkdev_add(&clk->cl); 403 } 404 } 405 406 /* bring up all register ranges that we need for basic system control */ 407 void __init ltq_soc_init(void) 408 { 409 struct resource res_pmu, res_cgu, res_ebu; 410 struct device_node *np_pmu = 411 of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway"); 412 struct device_node *np_cgu = 413 of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway"); 414 struct device_node *np_ebu = 415 of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway"); 416 417 /* check if all the core register ranges are available */ 418 if (!np_pmu || !np_cgu || !np_ebu) 419 panic("Failed to load core nodes from devicetree"); 420 421 if (of_address_to_resource(np_pmu, 0, &res_pmu) || 422 of_address_to_resource(np_cgu, 0, &res_cgu) || 423 of_address_to_resource(np_ebu, 0, &res_ebu)) 424 panic("Failed to get core resources"); 425 426 if (!request_mem_region(res_pmu.start, resource_size(&res_pmu), 427 res_pmu.name) || 428 !request_mem_region(res_cgu.start, resource_size(&res_cgu), 429 res_cgu.name) || 430 !request_mem_region(res_ebu.start, resource_size(&res_ebu), 431 res_ebu.name)) 432 pr_err("Failed to request core resources"); 433 434 pmu_membase = ioremap(res_pmu.start, resource_size(&res_pmu)); 435 ltq_cgu_membase = ioremap(res_cgu.start, 436 resource_size(&res_cgu)); 437 ltq_ebu_membase = ioremap(res_ebu.start, 438 resource_size(&res_ebu)); 439 if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase) 440 panic("Failed to remap core resources"); 441 442 /* make sure to unprotect the memory region where flash is located */ 443 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); 444 445 /* add our generic xway clocks */ 446 clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI); 447 clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT); 448 clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP); 449 clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1); 450 clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA); 451 clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI); 452 clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU); 453 clkdev_add_clkout(); 454 455 /* add the soc dependent clocks */ 456 if (of_machine_is_compatible("lantiq,vr9")) { 457 ifccr = CGU_IFCCR_VR9; 458 pcicr = CGU_PCICR_VR9; 459 } else { 460 clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE); 461 } 462 463 if (!of_machine_is_compatible("lantiq,ase")) 464 clkdev_add_pci(); 465 466 if (of_machine_is_compatible("lantiq,grx390") || 467 of_machine_is_compatible("lantiq,ar10")) { 468 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P); 469 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P); 470 /* rc 0 */ 471 clkdev_add_pmu("1f106800.phy", "phy", 1, 2, PMU_ANALOG_PCIE0_P); 472 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI); 473 clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI); 474 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL); 475 /* rc 1 */ 476 clkdev_add_pmu("1f700400.phy", "phy", 1, 2, PMU_ANALOG_PCIE1_P); 477 clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI); 478 clkdev_add_pmu("1f700400.phy", "pdi", 1, 1, PMU1_PCIE1_PDI); 479 clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL); 480 } 481 482 if (of_machine_is_compatible("lantiq,ase")) { 483 if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) 484 clkdev_add_static(CLOCK_266M, CLOCK_133M, 485 CLOCK_133M, CLOCK_266M); 486 else 487 clkdev_add_static(CLOCK_133M, CLOCK_133M, 488 CLOCK_133M, CLOCK_133M); 489 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0); 490 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P); 491 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE); 492 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY); 493 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY); 494 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO); 495 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); 496 } else if (of_machine_is_compatible("lantiq,grx390")) { 497 clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(), 498 ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz()); 499 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0); 500 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1); 501 /* rc 2 */ 502 clkdev_add_pmu("1f106a00.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P); 503 clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI); 504 clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI); 505 clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL); 506 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP); 507 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF); 508 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); 509 } else if (of_machine_is_compatible("lantiq,ar10")) { 510 clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(), 511 ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz()); 512 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0); 513 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1); 514 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | 515 PMU_PPE_DP | PMU_PPE_TC); 516 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF); 517 clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY); 518 clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY); 519 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); 520 clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE); 521 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); 522 } else if (of_machine_is_compatible("lantiq,vr9")) { 523 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), 524 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz()); 525 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P); 526 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM); 527 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P); 528 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM); 529 clkdev_add_pmu("1f106800.phy", "phy", 1, 1, PMU1_PCIE_PHY); 530 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK); 531 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI); 532 clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI); 533 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL); 534 clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS); 535 536 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF); 537 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, 538 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | 539 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | 540 PMU_PPE_QSB | PMU_PPE_TOP); 541 clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY); 542 clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY); 543 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO); 544 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); 545 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); 546 } else if (of_machine_is_compatible("lantiq,ar9")) { 547 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), 548 ltq_ar9_fpi_hz(), CLOCK_250M); 549 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P); 550 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM); 551 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P); 552 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM); 553 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH); 554 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO); 555 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); 556 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); 557 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); 558 } else { 559 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), 560 ltq_danube_fpi_hz(), ltq_danube_pp32_hz()); 561 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM); 562 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P); 563 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO); 564 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU); 565 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); 566 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); 567 } 568 } 569