1287e3f3fSJohn Crispin /* 2287e3f3fSJohn Crispin * This program is free software; you can redistribute it and/or modify it 3287e3f3fSJohn Crispin * under the terms of the GNU General Public License version 2 as published 4287e3f3fSJohn Crispin * by the Free Software Foundation. 5287e3f3fSJohn Crispin * 6287e3f3fSJohn Crispin * Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org> 7cab7b836SHauke Mehrtens * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG 8287e3f3fSJohn Crispin */ 9287e3f3fSJohn Crispin 10287e3f3fSJohn Crispin #include <linux/ioport.h> 11287e3f3fSJohn Crispin #include <linux/export.h> 12287e3f3fSJohn Crispin #include <linux/clkdev.h> 13758d2443SHauke Mehrtens #include <linux/spinlock.h> 14287e3f3fSJohn Crispin #include <linux/of.h> 15287e3f3fSJohn Crispin #include <linux/of_platform.h> 16287e3f3fSJohn Crispin #include <linux/of_address.h> 17287e3f3fSJohn Crispin 18287e3f3fSJohn Crispin #include <lantiq_soc.h> 19287e3f3fSJohn Crispin 20287e3f3fSJohn Crispin #include "../clk.h" 21287e3f3fSJohn Crispin #include "../prom.h" 22287e3f3fSJohn Crispin 23758d2443SHauke Mehrtens /* clock control register for legacy */ 24287e3f3fSJohn Crispin #define CGU_IFCCR 0x0018 25e29b72f5SJohn Crispin #define CGU_IFCCR_VR9 0x0024 26758d2443SHauke Mehrtens /* system clock register for legacy */ 27287e3f3fSJohn Crispin #define CGU_SYS 0x0010 28287e3f3fSJohn Crispin /* pci control register */ 29287e3f3fSJohn Crispin #define CGU_PCICR 0x0034 30e29b72f5SJohn Crispin #define CGU_PCICR_VR9 0x0038 31287e3f3fSJohn Crispin /* ephy configuration register */ 32287e3f3fSJohn Crispin #define CGU_EPHY 0x10 33758d2443SHauke Mehrtens 34758d2443SHauke Mehrtens /* Legacy PMU register for ar9, ase, danube */ 35287e3f3fSJohn Crispin /* power control register */ 36287e3f3fSJohn Crispin #define PMU_PWDCR 0x1C 37287e3f3fSJohn Crispin /* power status register */ 38287e3f3fSJohn Crispin #define PMU_PWDSR 0x20 39287e3f3fSJohn Crispin /* power control register */ 40287e3f3fSJohn Crispin #define PMU_PWDCR1 0x24 41287e3f3fSJohn Crispin /* power status register */ 42287e3f3fSJohn Crispin #define PMU_PWDSR1 0x28 43287e3f3fSJohn Crispin /* power control register */ 44287e3f3fSJohn Crispin #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR)) 45287e3f3fSJohn Crispin /* power status register */ 46287e3f3fSJohn Crispin #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) 47287e3f3fSJohn Crispin 48758d2443SHauke Mehrtens 49758d2443SHauke Mehrtens /* PMU register for ar10 and grx390 */ 50758d2443SHauke Mehrtens 51758d2443SHauke Mehrtens /* First register set */ 52758d2443SHauke Mehrtens #define PMU_CLK_SR 0x20 /* status */ 53758d2443SHauke Mehrtens #define PMU_CLK_CR_A 0x24 /* Enable */ 54758d2443SHauke Mehrtens #define PMU_CLK_CR_B 0x28 /* Disable */ 55758d2443SHauke Mehrtens /* Second register set */ 56758d2443SHauke Mehrtens #define PMU_CLK_SR1 0x30 /* status */ 57758d2443SHauke Mehrtens #define PMU_CLK_CR1_A 0x34 /* Enable */ 58758d2443SHauke Mehrtens #define PMU_CLK_CR1_B 0x38 /* Disable */ 59758d2443SHauke Mehrtens /* Third register set */ 60758d2443SHauke Mehrtens #define PMU_ANA_SR 0x40 /* status */ 61758d2443SHauke Mehrtens #define PMU_ANA_CR_A 0x44 /* Enable */ 62758d2443SHauke Mehrtens #define PMU_ANA_CR_B 0x48 /* Disable */ 63758d2443SHauke Mehrtens 64758d2443SHauke Mehrtens /* Status */ 65758d2443SHauke Mehrtens static u32 pmu_clk_sr[] = { 66758d2443SHauke Mehrtens PMU_CLK_SR, 67758d2443SHauke Mehrtens PMU_CLK_SR1, 68758d2443SHauke Mehrtens PMU_ANA_SR, 69758d2443SHauke Mehrtens }; 70758d2443SHauke Mehrtens 71758d2443SHauke Mehrtens /* Enable */ 72758d2443SHauke Mehrtens static u32 pmu_clk_cr_a[] = { 73758d2443SHauke Mehrtens PMU_CLK_CR_A, 74758d2443SHauke Mehrtens PMU_CLK_CR1_A, 75758d2443SHauke Mehrtens PMU_ANA_CR_A, 76758d2443SHauke Mehrtens }; 77758d2443SHauke Mehrtens 78758d2443SHauke Mehrtens /* Disable */ 79758d2443SHauke Mehrtens static u32 pmu_clk_cr_b[] = { 80758d2443SHauke Mehrtens PMU_CLK_CR_B, 81758d2443SHauke Mehrtens PMU_CLK_CR1_B, 82758d2443SHauke Mehrtens PMU_ANA_CR_B, 83758d2443SHauke Mehrtens }; 84758d2443SHauke Mehrtens 85758d2443SHauke Mehrtens #define PWDCR_EN_XRX(x) (pmu_clk_cr_a[(x)]) 86758d2443SHauke Mehrtens #define PWDCR_DIS_XRX(x) (pmu_clk_cr_b[(x)]) 87758d2443SHauke Mehrtens #define PWDSR_XRX(x) (pmu_clk_sr[(x)]) 88758d2443SHauke Mehrtens 89287e3f3fSJohn Crispin /* clock gates that we can en/disable */ 90287e3f3fSJohn Crispin #define PMU_USB0_P BIT(0) 91287e3f3fSJohn Crispin #define PMU_PCI BIT(4) 92009d6914SJohn Crispin #define PMU_DMA BIT(5) 93287e3f3fSJohn Crispin #define PMU_USB0 BIT(6) 94287e3f3fSJohn Crispin #define PMU_ASC0 BIT(7) 95287e3f3fSJohn Crispin #define PMU_EPHY BIT(7) /* ase */ 96287e3f3fSJohn Crispin #define PMU_SPI BIT(8) 97287e3f3fSJohn Crispin #define PMU_DFE BIT(9) 98287e3f3fSJohn Crispin #define PMU_EBU BIT(10) 99287e3f3fSJohn Crispin #define PMU_STP BIT(11) 100009d6914SJohn Crispin #define PMU_GPT BIT(12) 101287e3f3fSJohn Crispin #define PMU_AHBS BIT(13) /* vr9 */ 102009d6914SJohn Crispin #define PMU_FPI BIT(14) 103287e3f3fSJohn Crispin #define PMU_AHBM BIT(15) 104287e3f3fSJohn Crispin #define PMU_ASC1 BIT(17) 105287e3f3fSJohn Crispin #define PMU_PPE_QSB BIT(18) 106287e3f3fSJohn Crispin #define PMU_PPE_SLL01 BIT(19) 107287e3f3fSJohn Crispin #define PMU_PPE_TC BIT(21) 108287e3f3fSJohn Crispin #define PMU_PPE_EMA BIT(22) 109287e3f3fSJohn Crispin #define PMU_PPE_DPLUM BIT(23) 110287e3f3fSJohn Crispin #define PMU_PPE_DPLUS BIT(24) 111287e3f3fSJohn Crispin #define PMU_USB1_P BIT(26) 112287e3f3fSJohn Crispin #define PMU_USB1 BIT(27) 113009d6914SJohn Crispin #define PMU_SWITCH BIT(28) 114287e3f3fSJohn Crispin #define PMU_PPE_TOP BIT(29) 115287e3f3fSJohn Crispin #define PMU_GPHY BIT(30) 116287e3f3fSJohn Crispin #define PMU_PCIE_CLK BIT(31) 117287e3f3fSJohn Crispin 118287e3f3fSJohn Crispin #define PMU1_PCIE_PHY BIT(0) 119287e3f3fSJohn Crispin #define PMU1_PCIE_CTL BIT(1) 120287e3f3fSJohn Crispin #define PMU1_PCIE_PDI BIT(4) 121287e3f3fSJohn Crispin #define PMU1_PCIE_MSI BIT(5) 122287e3f3fSJohn Crispin 123287e3f3fSJohn Crispin #define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y)) 124287e3f3fSJohn Crispin #define pmu_r32(x) ltq_r32(pmu_membase + (x)) 125287e3f3fSJohn Crispin 126287e3f3fSJohn Crispin static void __iomem *pmu_membase; 127287e3f3fSJohn Crispin void __iomem *ltq_cgu_membase; 128287e3f3fSJohn Crispin void __iomem *ltq_ebu_membase; 129287e3f3fSJohn Crispin 130e29b72f5SJohn Crispin static u32 ifccr = CGU_IFCCR; 131e29b72f5SJohn Crispin static u32 pcicr = CGU_PCICR; 132e29b72f5SJohn Crispin 133cab7b836SHauke Mehrtens static DEFINE_SPINLOCK(g_pmu_lock); 134cab7b836SHauke Mehrtens 135287e3f3fSJohn Crispin /* legacy function kept alive to ease clkdev transition */ 136287e3f3fSJohn Crispin void ltq_pmu_enable(unsigned int module) 137287e3f3fSJohn Crispin { 138cab7b836SHauke Mehrtens int retry = 1000000; 139287e3f3fSJohn Crispin 140cab7b836SHauke Mehrtens spin_lock(&g_pmu_lock); 141287e3f3fSJohn Crispin pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR); 142cab7b836SHauke Mehrtens do {} while (--retry && (pmu_r32(PMU_PWDSR) & module)); 143cab7b836SHauke Mehrtens spin_unlock(&g_pmu_lock); 144287e3f3fSJohn Crispin 145cab7b836SHauke Mehrtens if (!retry) 146287e3f3fSJohn Crispin panic("activating PMU module failed!"); 147287e3f3fSJohn Crispin } 148287e3f3fSJohn Crispin EXPORT_SYMBOL(ltq_pmu_enable); 149287e3f3fSJohn Crispin 150287e3f3fSJohn Crispin /* legacy function kept alive to ease clkdev transition */ 151287e3f3fSJohn Crispin void ltq_pmu_disable(unsigned int module) 152287e3f3fSJohn Crispin { 153cab7b836SHauke Mehrtens int retry = 1000000; 154cab7b836SHauke Mehrtens 155cab7b836SHauke Mehrtens spin_lock(&g_pmu_lock); 156287e3f3fSJohn Crispin pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR); 157cab7b836SHauke Mehrtens do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module))); 158cab7b836SHauke Mehrtens spin_unlock(&g_pmu_lock); 159cab7b836SHauke Mehrtens 160cab7b836SHauke Mehrtens if (!retry) 161cab7b836SHauke Mehrtens pr_warn("deactivating PMU module failed!"); 162287e3f3fSJohn Crispin } 163287e3f3fSJohn Crispin EXPORT_SYMBOL(ltq_pmu_disable); 164287e3f3fSJohn Crispin 165287e3f3fSJohn Crispin /* enable a hw clock */ 166287e3f3fSJohn Crispin static int cgu_enable(struct clk *clk) 167287e3f3fSJohn Crispin { 168e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); 169287e3f3fSJohn Crispin return 0; 170287e3f3fSJohn Crispin } 171287e3f3fSJohn Crispin 172287e3f3fSJohn Crispin /* disable a hw clock */ 173287e3f3fSJohn Crispin static void cgu_disable(struct clk *clk) 174287e3f3fSJohn Crispin { 175e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); 176287e3f3fSJohn Crispin } 177287e3f3fSJohn Crispin 178287e3f3fSJohn Crispin /* enable a clock gate */ 179287e3f3fSJohn Crispin static int pmu_enable(struct clk *clk) 180287e3f3fSJohn Crispin { 181287e3f3fSJohn Crispin int retry = 1000000; 182287e3f3fSJohn Crispin 183758d2443SHauke Mehrtens if (of_machine_is_compatible("lantiq,ar10") 184758d2443SHauke Mehrtens || of_machine_is_compatible("lantiq,grx390")) { 185758d2443SHauke Mehrtens pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module)); 186758d2443SHauke Mehrtens do {} while (--retry && 187758d2443SHauke Mehrtens (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits))); 188758d2443SHauke Mehrtens 189758d2443SHauke Mehrtens } else { 190cab7b836SHauke Mehrtens spin_lock(&g_pmu_lock); 191287e3f3fSJohn Crispin pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits, 192287e3f3fSJohn Crispin PWDCR(clk->module)); 193758d2443SHauke Mehrtens do {} while (--retry && 194758d2443SHauke Mehrtens (pmu_r32(PWDSR(clk->module)) & clk->bits)); 195cab7b836SHauke Mehrtens spin_unlock(&g_pmu_lock); 196758d2443SHauke Mehrtens } 197287e3f3fSJohn Crispin 198287e3f3fSJohn Crispin if (!retry) 199f7777dccSRalf Baechle panic("activating PMU module failed!"); 200287e3f3fSJohn Crispin 201287e3f3fSJohn Crispin return 0; 202287e3f3fSJohn Crispin } 203287e3f3fSJohn Crispin 204287e3f3fSJohn Crispin /* disable a clock gate */ 205287e3f3fSJohn Crispin static void pmu_disable(struct clk *clk) 206287e3f3fSJohn Crispin { 207cab7b836SHauke Mehrtens int retry = 1000000; 208cab7b836SHauke Mehrtens 209758d2443SHauke Mehrtens if (of_machine_is_compatible("lantiq,ar10") 210758d2443SHauke Mehrtens || of_machine_is_compatible("lantiq,grx390")) { 211758d2443SHauke Mehrtens pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module)); 212758d2443SHauke Mehrtens do {} while (--retry && 213758d2443SHauke Mehrtens (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)); 214758d2443SHauke Mehrtens } else { 215cab7b836SHauke Mehrtens spin_lock(&g_pmu_lock); 216758d2443SHauke Mehrtens pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits, 217758d2443SHauke Mehrtens PWDCR(clk->module)); 218758d2443SHauke Mehrtens do {} while (--retry && 219758d2443SHauke Mehrtens (!(pmu_r32(PWDSR(clk->module)) & clk->bits))); 220cab7b836SHauke Mehrtens spin_unlock(&g_pmu_lock); 221758d2443SHauke Mehrtens } 222cab7b836SHauke Mehrtens 223cab7b836SHauke Mehrtens if (!retry) 224cab7b836SHauke Mehrtens pr_warn("deactivating PMU module failed!"); 225287e3f3fSJohn Crispin } 226287e3f3fSJohn Crispin 227287e3f3fSJohn Crispin /* the pci enable helper */ 228287e3f3fSJohn Crispin static int pci_enable(struct clk *clk) 229287e3f3fSJohn Crispin { 230e29b72f5SJohn Crispin unsigned int val = ltq_cgu_r32(ifccr); 231287e3f3fSJohn Crispin /* set bus clock speed */ 232f40e1f9dSJohn Crispin if (of_machine_is_compatible("lantiq,ar9") || 233f40e1f9dSJohn Crispin of_machine_is_compatible("lantiq,vr9")) { 234e29b72f5SJohn Crispin val &= ~0x1f00000; 235287e3f3fSJohn Crispin if (clk->rate == CLOCK_33M) 236e29b72f5SJohn Crispin val |= 0xe00000; 237287e3f3fSJohn Crispin else 238e29b72f5SJohn Crispin val |= 0x700000; /* 62.5M */ 239287e3f3fSJohn Crispin } else { 240e29b72f5SJohn Crispin val &= ~0xf00000; 241287e3f3fSJohn Crispin if (clk->rate == CLOCK_33M) 242e29b72f5SJohn Crispin val |= 0x800000; 243287e3f3fSJohn Crispin else 244e29b72f5SJohn Crispin val |= 0x400000; /* 62.5M */ 245287e3f3fSJohn Crispin } 246e29b72f5SJohn Crispin ltq_cgu_w32(val, ifccr); 247287e3f3fSJohn Crispin pmu_enable(clk); 248287e3f3fSJohn Crispin return 0; 249287e3f3fSJohn Crispin } 250287e3f3fSJohn Crispin 251287e3f3fSJohn Crispin /* enable the external clock as a source */ 252287e3f3fSJohn Crispin static int pci_ext_enable(struct clk *clk) 253287e3f3fSJohn Crispin { 254e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr); 255e29b72f5SJohn Crispin ltq_cgu_w32((1 << 30), pcicr); 256287e3f3fSJohn Crispin return 0; 257287e3f3fSJohn Crispin } 258287e3f3fSJohn Crispin 259287e3f3fSJohn Crispin /* disable the external clock as a source */ 260287e3f3fSJohn Crispin static void pci_ext_disable(struct clk *clk) 261287e3f3fSJohn Crispin { 262e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr); 263e29b72f5SJohn Crispin ltq_cgu_w32((1 << 31) | (1 << 30), pcicr); 264287e3f3fSJohn Crispin } 265287e3f3fSJohn Crispin 266287e3f3fSJohn Crispin /* enable a clockout source */ 267287e3f3fSJohn Crispin static int clkout_enable(struct clk *clk) 268287e3f3fSJohn Crispin { 269287e3f3fSJohn Crispin int i; 270287e3f3fSJohn Crispin 271287e3f3fSJohn Crispin /* get the correct rate */ 272287e3f3fSJohn Crispin for (i = 0; i < 4; i++) { 273287e3f3fSJohn Crispin if (clk->rates[i] == clk->rate) { 274287e3f3fSJohn Crispin int shift = 14 - (2 * clk->module); 27598dbc576SJohn Crispin int enable = 7 - clk->module; 276e29b72f5SJohn Crispin unsigned int val = ltq_cgu_r32(ifccr); 277287e3f3fSJohn Crispin 278e29b72f5SJohn Crispin val &= ~(3 << shift); 279e29b72f5SJohn Crispin val |= i << shift; 28098dbc576SJohn Crispin val |= enable; 281e29b72f5SJohn Crispin ltq_cgu_w32(val, ifccr); 282287e3f3fSJohn Crispin return 0; 283287e3f3fSJohn Crispin } 284287e3f3fSJohn Crispin } 285287e3f3fSJohn Crispin return -1; 286287e3f3fSJohn Crispin } 287287e3f3fSJohn Crispin 288287e3f3fSJohn Crispin /* manage the clock gates via PMU */ 289287e3f3fSJohn Crispin static void clkdev_add_pmu(const char *dev, const char *con, 290287e3f3fSJohn Crispin unsigned int module, unsigned int bits) 291287e3f3fSJohn Crispin { 292287e3f3fSJohn Crispin struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 293287e3f3fSJohn Crispin 294287e3f3fSJohn Crispin clk->cl.dev_id = dev; 295287e3f3fSJohn Crispin clk->cl.con_id = con; 296287e3f3fSJohn Crispin clk->cl.clk = clk; 297287e3f3fSJohn Crispin clk->enable = pmu_enable; 298287e3f3fSJohn Crispin clk->disable = pmu_disable; 299287e3f3fSJohn Crispin clk->module = module; 300287e3f3fSJohn Crispin clk->bits = bits; 301287e3f3fSJohn Crispin clkdev_add(&clk->cl); 302287e3f3fSJohn Crispin } 303287e3f3fSJohn Crispin 304287e3f3fSJohn Crispin /* manage the clock generator */ 305287e3f3fSJohn Crispin static void clkdev_add_cgu(const char *dev, const char *con, 306287e3f3fSJohn Crispin unsigned int bits) 307287e3f3fSJohn Crispin { 308287e3f3fSJohn Crispin struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 309287e3f3fSJohn Crispin 310287e3f3fSJohn Crispin clk->cl.dev_id = dev; 311287e3f3fSJohn Crispin clk->cl.con_id = con; 312287e3f3fSJohn Crispin clk->cl.clk = clk; 313287e3f3fSJohn Crispin clk->enable = cgu_enable; 314287e3f3fSJohn Crispin clk->disable = cgu_disable; 315287e3f3fSJohn Crispin clk->bits = bits; 316287e3f3fSJohn Crispin clkdev_add(&clk->cl); 317287e3f3fSJohn Crispin } 318287e3f3fSJohn Crispin 319287e3f3fSJohn Crispin /* pci needs its own enable function as the setup is a bit more complex */ 320287e3f3fSJohn Crispin static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0}; 321287e3f3fSJohn Crispin 322287e3f3fSJohn Crispin static void clkdev_add_pci(void) 323287e3f3fSJohn Crispin { 324287e3f3fSJohn Crispin struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 325287e3f3fSJohn Crispin struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); 326287e3f3fSJohn Crispin 327287e3f3fSJohn Crispin /* main pci clock */ 328287e3f3fSJohn Crispin clk->cl.dev_id = "17000000.pci"; 329287e3f3fSJohn Crispin clk->cl.con_id = NULL; 330287e3f3fSJohn Crispin clk->cl.clk = clk; 331287e3f3fSJohn Crispin clk->rate = CLOCK_33M; 332287e3f3fSJohn Crispin clk->rates = valid_pci_rates; 333287e3f3fSJohn Crispin clk->enable = pci_enable; 334287e3f3fSJohn Crispin clk->disable = pmu_disable; 335287e3f3fSJohn Crispin clk->module = 0; 336287e3f3fSJohn Crispin clk->bits = PMU_PCI; 337287e3f3fSJohn Crispin clkdev_add(&clk->cl); 338287e3f3fSJohn Crispin 339287e3f3fSJohn Crispin /* use internal/external bus clock */ 340287e3f3fSJohn Crispin clk_ext->cl.dev_id = "17000000.pci"; 341287e3f3fSJohn Crispin clk_ext->cl.con_id = "external"; 342287e3f3fSJohn Crispin clk_ext->cl.clk = clk_ext; 343287e3f3fSJohn Crispin clk_ext->enable = pci_ext_enable; 344287e3f3fSJohn Crispin clk_ext->disable = pci_ext_disable; 345287e3f3fSJohn Crispin clkdev_add(&clk_ext->cl); 346287e3f3fSJohn Crispin } 347287e3f3fSJohn Crispin 348287e3f3fSJohn Crispin /* xway socs can generate clocks on gpio pins */ 349287e3f3fSJohn Crispin static unsigned long valid_clkout_rates[4][5] = { 350287e3f3fSJohn Crispin {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0}, 351287e3f3fSJohn Crispin {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0}, 352287e3f3fSJohn Crispin {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0}, 353287e3f3fSJohn Crispin {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0}, 354287e3f3fSJohn Crispin }; 355287e3f3fSJohn Crispin 356287e3f3fSJohn Crispin static void clkdev_add_clkout(void) 357287e3f3fSJohn Crispin { 358287e3f3fSJohn Crispin int i; 359287e3f3fSJohn Crispin 360287e3f3fSJohn Crispin for (i = 0; i < 4; i++) { 361287e3f3fSJohn Crispin struct clk *clk; 362287e3f3fSJohn Crispin char *name; 363287e3f3fSJohn Crispin 364287e3f3fSJohn Crispin name = kzalloc(sizeof("clkout0"), GFP_KERNEL); 365287e3f3fSJohn Crispin sprintf(name, "clkout%d", i); 366287e3f3fSJohn Crispin 367287e3f3fSJohn Crispin clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 368287e3f3fSJohn Crispin clk->cl.dev_id = "1f103000.cgu"; 369287e3f3fSJohn Crispin clk->cl.con_id = name; 370287e3f3fSJohn Crispin clk->cl.clk = clk; 371287e3f3fSJohn Crispin clk->rate = 0; 372287e3f3fSJohn Crispin clk->rates = valid_clkout_rates[i]; 373287e3f3fSJohn Crispin clk->enable = clkout_enable; 374287e3f3fSJohn Crispin clk->module = i; 375287e3f3fSJohn Crispin clkdev_add(&clk->cl); 376287e3f3fSJohn Crispin } 377287e3f3fSJohn Crispin } 378287e3f3fSJohn Crispin 379287e3f3fSJohn Crispin /* bring up all register ranges that we need for basic system control */ 380287e3f3fSJohn Crispin void __init ltq_soc_init(void) 381287e3f3fSJohn Crispin { 382287e3f3fSJohn Crispin struct resource res_pmu, res_cgu, res_ebu; 383287e3f3fSJohn Crispin struct device_node *np_pmu = 384287e3f3fSJohn Crispin of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway"); 385287e3f3fSJohn Crispin struct device_node *np_cgu = 386287e3f3fSJohn Crispin of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway"); 387287e3f3fSJohn Crispin struct device_node *np_ebu = 388287e3f3fSJohn Crispin of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway"); 389287e3f3fSJohn Crispin 390287e3f3fSJohn Crispin /* check if all the core register ranges are available */ 391287e3f3fSJohn Crispin if (!np_pmu || !np_cgu || !np_ebu) 3923d18c17eSJohn Crispin panic("Failed to load core nodes from devicetree"); 393287e3f3fSJohn Crispin 394287e3f3fSJohn Crispin if (of_address_to_resource(np_pmu, 0, &res_pmu) || 395287e3f3fSJohn Crispin of_address_to_resource(np_cgu, 0, &res_cgu) || 396287e3f3fSJohn Crispin of_address_to_resource(np_ebu, 0, &res_ebu)) 397287e3f3fSJohn Crispin panic("Failed to get core resources"); 398287e3f3fSJohn Crispin 399287e3f3fSJohn Crispin if ((request_mem_region(res_pmu.start, resource_size(&res_pmu), 400287e3f3fSJohn Crispin res_pmu.name) < 0) || 401287e3f3fSJohn Crispin (request_mem_region(res_cgu.start, resource_size(&res_cgu), 402287e3f3fSJohn Crispin res_cgu.name) < 0) || 403287e3f3fSJohn Crispin (request_mem_region(res_ebu.start, resource_size(&res_ebu), 404287e3f3fSJohn Crispin res_ebu.name) < 0)) 4051a84db56SMasanari Iida pr_err("Failed to request core resources"); 406287e3f3fSJohn Crispin 407287e3f3fSJohn Crispin pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu)); 408287e3f3fSJohn Crispin ltq_cgu_membase = ioremap_nocache(res_cgu.start, 409287e3f3fSJohn Crispin resource_size(&res_cgu)); 410287e3f3fSJohn Crispin ltq_ebu_membase = ioremap_nocache(res_ebu.start, 411287e3f3fSJohn Crispin resource_size(&res_ebu)); 412287e3f3fSJohn Crispin if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase) 413287e3f3fSJohn Crispin panic("Failed to remap core resources"); 414287e3f3fSJohn Crispin 415287e3f3fSJohn Crispin /* make sure to unprotect the memory region where flash is located */ 416287e3f3fSJohn Crispin ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); 417287e3f3fSJohn Crispin 418287e3f3fSJohn Crispin /* add our generic xway clocks */ 419287e3f3fSJohn Crispin clkdev_add_pmu("10000000.fpi", NULL, 0, PMU_FPI); 420287e3f3fSJohn Crispin clkdev_add_pmu("1e100400.serial", NULL, 0, PMU_ASC0); 421287e3f3fSJohn Crispin clkdev_add_pmu("1e100a00.gptu", NULL, 0, PMU_GPT); 422287e3f3fSJohn Crispin clkdev_add_pmu("1e100bb0.stp", NULL, 0, PMU_STP); 423287e3f3fSJohn Crispin clkdev_add_pmu("1e104100.dma", NULL, 0, PMU_DMA); 424287e3f3fSJohn Crispin clkdev_add_pmu("1e100800.spi", NULL, 0, PMU_SPI); 425287e3f3fSJohn Crispin clkdev_add_pmu("1e105300.ebu", NULL, 0, PMU_EBU); 426287e3f3fSJohn Crispin clkdev_add_clkout(); 427287e3f3fSJohn Crispin 428287e3f3fSJohn Crispin /* add the soc dependent clocks */ 429e29b72f5SJohn Crispin if (of_machine_is_compatible("lantiq,vr9")) { 430e29b72f5SJohn Crispin ifccr = CGU_IFCCR_VR9; 431e29b72f5SJohn Crispin pcicr = CGU_PCICR_VR9; 432e29b72f5SJohn Crispin } else { 433287e3f3fSJohn Crispin clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE); 434e29b72f5SJohn Crispin } 435287e3f3fSJohn Crispin 436287e3f3fSJohn Crispin if (!of_machine_is_compatible("lantiq,ase")) { 437287e3f3fSJohn Crispin clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1); 438287e3f3fSJohn Crispin clkdev_add_pci(); 439287e3f3fSJohn Crispin } 440287e3f3fSJohn Crispin 441287e3f3fSJohn Crispin if (of_machine_is_compatible("lantiq,ase")) { 442287e3f3fSJohn Crispin if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) 443740c606eSJohn Crispin clkdev_add_static(CLOCK_266M, CLOCK_133M, 444740c606eSJohn Crispin CLOCK_133M, CLOCK_266M); 445287e3f3fSJohn Crispin else 446740c606eSJohn Crispin clkdev_add_static(CLOCK_133M, CLOCK_133M, 447740c606eSJohn Crispin CLOCK_133M, CLOCK_133M); 448287e3f3fSJohn Crispin clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY), 449287e3f3fSJohn Crispin clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY); 450287e3f3fSJohn Crispin } else if (of_machine_is_compatible("lantiq,vr9")) { 451287e3f3fSJohn Crispin clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), 452740c606eSJohn Crispin ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz()); 453287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY); 454287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK); 455287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI); 456287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI); 457287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL); 458287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); 459f2bbe41cSJohn Crispin clkdev_add_pmu("1e108000.eth", NULL, 0, 460f2bbe41cSJohn Crispin PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | 461f2bbe41cSJohn Crispin PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | 462f2bbe41cSJohn Crispin PMU_PPE_QSB | PMU_PPE_TOP); 463d0c550dcSJohn Crispin clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY); 464287e3f3fSJohn Crispin } else if (of_machine_is_compatible("lantiq,ar9")) { 465287e3f3fSJohn Crispin clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), 466740c606eSJohn Crispin ltq_ar9_fpi_hz(), CLOCK_250M); 467287e3f3fSJohn Crispin clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH); 468287e3f3fSJohn Crispin } else { 469287e3f3fSJohn Crispin clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), 470740c606eSJohn Crispin ltq_danube_fpi_hz(), ltq_danube_pp32_hz()); 471287e3f3fSJohn Crispin } 472287e3f3fSJohn Crispin } 473