1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 14 * 15 * Copyright (C) 2011 John Crispin <john@phrozen.org> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/io.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/export.h> 23 #include <linux/spinlock.h> 24 #include <linux/clk.h> 25 #include <linux/err.h> 26 27 #include <lantiq_soc.h> 28 #include <xway_dma.h> 29 30 #define LTQ_DMA_ID 0x08 31 #define LTQ_DMA_CTRL 0x10 32 #define LTQ_DMA_CPOLL 0x14 33 #define LTQ_DMA_CS 0x18 34 #define LTQ_DMA_CCTRL 0x1C 35 #define LTQ_DMA_CDBA 0x20 36 #define LTQ_DMA_CDLEN 0x24 37 #define LTQ_DMA_CIS 0x28 38 #define LTQ_DMA_CIE 0x2C 39 #define LTQ_DMA_PS 0x40 40 #define LTQ_DMA_PCTRL 0x44 41 #define LTQ_DMA_IRNEN 0xf4 42 43 #define DMA_DESCPT BIT(3) /* descriptor complete irq */ 44 #define DMA_TX BIT(8) /* TX channel direction */ 45 #define DMA_CHAN_ON BIT(0) /* channel on / off bit */ 46 #define DMA_PDEN BIT(6) /* enable packet drop */ 47 #define DMA_CHAN_RST BIT(1) /* channel on / off bit */ 48 #define DMA_RESET BIT(0) /* channel on / off bit */ 49 #define DMA_IRQ_ACK 0x7e /* IRQ status register */ 50 #define DMA_POLL BIT(31) /* turn on channel polling */ 51 #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ 52 #define DMA_2W_BURST BIT(1) /* 2 word burst length */ 53 #define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ 54 #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */ 55 #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ 56 57 #define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x)) 58 #define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y)) 59 #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ 60 ltq_dma_membase + (z)) 61 62 static void __iomem *ltq_dma_membase; 63 static DEFINE_SPINLOCK(ltq_dma_lock); 64 65 void 66 ltq_dma_enable_irq(struct ltq_dma_channel *ch) 67 { 68 unsigned long flags; 69 70 spin_lock_irqsave(<q_dma_lock, flags); 71 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 72 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 73 spin_unlock_irqrestore(<q_dma_lock, flags); 74 } 75 EXPORT_SYMBOL_GPL(ltq_dma_enable_irq); 76 77 void 78 ltq_dma_disable_irq(struct ltq_dma_channel *ch) 79 { 80 unsigned long flags; 81 82 spin_lock_irqsave(<q_dma_lock, flags); 83 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 84 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); 85 spin_unlock_irqrestore(<q_dma_lock, flags); 86 } 87 EXPORT_SYMBOL_GPL(ltq_dma_disable_irq); 88 89 void 90 ltq_dma_ack_irq(struct ltq_dma_channel *ch) 91 { 92 unsigned long flags; 93 94 spin_lock_irqsave(<q_dma_lock, flags); 95 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 96 ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS); 97 spin_unlock_irqrestore(<q_dma_lock, flags); 98 } 99 EXPORT_SYMBOL_GPL(ltq_dma_ack_irq); 100 101 void 102 ltq_dma_open(struct ltq_dma_channel *ch) 103 { 104 unsigned long flag; 105 106 spin_lock_irqsave(<q_dma_lock, flag); 107 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 108 ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL); 109 spin_unlock_irqrestore(<q_dma_lock, flag); 110 } 111 EXPORT_SYMBOL_GPL(ltq_dma_open); 112 113 void 114 ltq_dma_close(struct ltq_dma_channel *ch) 115 { 116 unsigned long flag; 117 118 spin_lock_irqsave(<q_dma_lock, flag); 119 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 120 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 121 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); 122 spin_unlock_irqrestore(<q_dma_lock, flag); 123 } 124 EXPORT_SYMBOL_GPL(ltq_dma_close); 125 126 static void 127 ltq_dma_alloc(struct ltq_dma_channel *ch) 128 { 129 unsigned long flags; 130 131 ch->desc = 0; 132 ch->desc_base = dma_zalloc_coherent(ch->dev, 133 LTQ_DESC_NUM * LTQ_DESC_SIZE, 134 &ch->phys, GFP_ATOMIC); 135 136 spin_lock_irqsave(<q_dma_lock, flags); 137 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 138 ltq_dma_w32(ch->phys, LTQ_DMA_CDBA); 139 ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN); 140 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 141 wmb(); 142 ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL); 143 while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST) 144 ; 145 spin_unlock_irqrestore(<q_dma_lock, flags); 146 } 147 148 void 149 ltq_dma_alloc_tx(struct ltq_dma_channel *ch) 150 { 151 unsigned long flags; 152 153 ltq_dma_alloc(ch); 154 155 spin_lock_irqsave(<q_dma_lock, flags); 156 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); 157 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 158 ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL); 159 spin_unlock_irqrestore(<q_dma_lock, flags); 160 } 161 EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx); 162 163 void 164 ltq_dma_alloc_rx(struct ltq_dma_channel *ch) 165 { 166 unsigned long flags; 167 168 ltq_dma_alloc(ch); 169 170 spin_lock_irqsave(<q_dma_lock, flags); 171 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); 172 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 173 ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL); 174 spin_unlock_irqrestore(<q_dma_lock, flags); 175 } 176 EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx); 177 178 void 179 ltq_dma_free(struct ltq_dma_channel *ch) 180 { 181 if (!ch->desc_base) 182 return; 183 ltq_dma_close(ch); 184 dma_free_coherent(ch->dev, LTQ_DESC_NUM * LTQ_DESC_SIZE, 185 ch->desc_base, ch->phys); 186 } 187 EXPORT_SYMBOL_GPL(ltq_dma_free); 188 189 void 190 ltq_dma_init_port(int p) 191 { 192 ltq_dma_w32(p, LTQ_DMA_PS); 193 switch (p) { 194 case DMA_PORT_ETOP: 195 /* 196 * Tell the DMA engine to swap the endianness of data frames and 197 * drop packets if the channel arbitration fails. 198 */ 199 ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN, 200 LTQ_DMA_PCTRL); 201 break; 202 203 case DMA_PORT_DEU: 204 ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2), 205 LTQ_DMA_PCTRL); 206 break; 207 208 default: 209 break; 210 } 211 } 212 EXPORT_SYMBOL_GPL(ltq_dma_init_port); 213 214 static int 215 ltq_dma_init(struct platform_device *pdev) 216 { 217 struct clk *clk; 218 struct resource *res; 219 unsigned id; 220 int i; 221 222 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 223 ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res); 224 if (IS_ERR(ltq_dma_membase)) 225 panic("Failed to remap dma resource"); 226 227 /* power up and reset the dma engine */ 228 clk = clk_get(&pdev->dev, NULL); 229 if (IS_ERR(clk)) 230 panic("Failed to get dma clock"); 231 232 clk_enable(clk); 233 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); 234 235 /* disable all interrupts */ 236 ltq_dma_w32(0, LTQ_DMA_IRNEN); 237 238 /* reset/configure each channel */ 239 for (i = 0; i < DMA_MAX_CHANNEL; i++) { 240 ltq_dma_w32(i, LTQ_DMA_CS); 241 ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL); 242 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); 243 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 244 } 245 246 id = ltq_dma_r32(LTQ_DMA_ID); 247 dev_info(&pdev->dev, 248 "Init done - hw rev: %X, ports: %d, channels: %d\n", 249 id & 0x1f, (id >> 16) & 0xf, id >> 20); 250 251 return 0; 252 } 253 254 static const struct of_device_id dma_match[] = { 255 { .compatible = "lantiq,dma-xway" }, 256 {}, 257 }; 258 259 static struct platform_driver dma_driver = { 260 .probe = ltq_dma_init, 261 .driver = { 262 .name = "dma-xway", 263 .of_match_table = dma_match, 264 }, 265 }; 266 267 int __init 268 dma_init(void) 269 { 270 return platform_driver_register(&dma_driver); 271 } 272 273 postcore_initcall(dma_init); 274