1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2011 John Crispin <john@phrozen.org> 5 */ 6 7 #include <linux/init.h> 8 #include <linux/platform_device.h> 9 #include <linux/io.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/export.h> 12 #include <linux/spinlock.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/of.h> 17 18 #include <lantiq_soc.h> 19 #include <xway_dma.h> 20 21 #define LTQ_DMA_ID 0x08 22 #define LTQ_DMA_CTRL 0x10 23 #define LTQ_DMA_CPOLL 0x14 24 #define LTQ_DMA_CS 0x18 25 #define LTQ_DMA_CCTRL 0x1C 26 #define LTQ_DMA_CDBA 0x20 27 #define LTQ_DMA_CDLEN 0x24 28 #define LTQ_DMA_CIS 0x28 29 #define LTQ_DMA_CIE 0x2C 30 #define LTQ_DMA_PS 0x40 31 #define LTQ_DMA_PCTRL 0x44 32 #define LTQ_DMA_IRNEN 0xf4 33 34 #define DMA_ID_CHNR GENMASK(26, 20) /* channel number */ 35 #define DMA_DESCPT BIT(3) /* descriptor complete irq */ 36 #define DMA_TX BIT(8) /* TX channel direction */ 37 #define DMA_CHAN_ON BIT(0) /* channel on / off bit */ 38 #define DMA_PDEN BIT(6) /* enable packet drop */ 39 #define DMA_CHAN_RST BIT(1) /* channel on / off bit */ 40 #define DMA_RESET BIT(0) /* channel on / off bit */ 41 #define DMA_IRQ_ACK 0x7e /* IRQ status register */ 42 #define DMA_POLL BIT(31) /* turn on channel polling */ 43 #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ 44 #define DMA_PCTRL_2W_BURST 0x1 /* 2 word burst length */ 45 #define DMA_PCTRL_4W_BURST 0x2 /* 4 word burst length */ 46 #define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */ 47 #define DMA_TX_BURST_SHIFT 4 /* tx burst shift */ 48 #define DMA_RX_BURST_SHIFT 2 /* rx burst shift */ 49 #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */ 50 #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ 51 52 #define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x)) 53 #define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y)) 54 #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ 55 ltq_dma_membase + (z)) 56 57 static void __iomem *ltq_dma_membase; 58 static DEFINE_SPINLOCK(ltq_dma_lock); 59 60 void 61 ltq_dma_enable_irq(struct ltq_dma_channel *ch) 62 { 63 unsigned long flags; 64 65 spin_lock_irqsave(<q_dma_lock, flags); 66 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 67 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 68 spin_unlock_irqrestore(<q_dma_lock, flags); 69 } 70 EXPORT_SYMBOL_GPL(ltq_dma_enable_irq); 71 72 void 73 ltq_dma_disable_irq(struct ltq_dma_channel *ch) 74 { 75 unsigned long flags; 76 77 spin_lock_irqsave(<q_dma_lock, flags); 78 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 79 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); 80 spin_unlock_irqrestore(<q_dma_lock, flags); 81 } 82 EXPORT_SYMBOL_GPL(ltq_dma_disable_irq); 83 84 void 85 ltq_dma_ack_irq(struct ltq_dma_channel *ch) 86 { 87 unsigned long flags; 88 89 spin_lock_irqsave(<q_dma_lock, flags); 90 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 91 ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS); 92 spin_unlock_irqrestore(<q_dma_lock, flags); 93 } 94 EXPORT_SYMBOL_GPL(ltq_dma_ack_irq); 95 96 void 97 ltq_dma_open(struct ltq_dma_channel *ch) 98 { 99 unsigned long flag; 100 101 spin_lock_irqsave(<q_dma_lock, flag); 102 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 103 ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL); 104 spin_unlock_irqrestore(<q_dma_lock, flag); 105 } 106 EXPORT_SYMBOL_GPL(ltq_dma_open); 107 108 void 109 ltq_dma_close(struct ltq_dma_channel *ch) 110 { 111 unsigned long flag; 112 113 spin_lock_irqsave(<q_dma_lock, flag); 114 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 115 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 116 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); 117 spin_unlock_irqrestore(<q_dma_lock, flag); 118 } 119 EXPORT_SYMBOL_GPL(ltq_dma_close); 120 121 static void 122 ltq_dma_alloc(struct ltq_dma_channel *ch) 123 { 124 unsigned long flags; 125 126 ch->desc = 0; 127 ch->desc_base = dma_alloc_coherent(ch->dev, 128 LTQ_DESC_NUM * LTQ_DESC_SIZE, 129 &ch->phys, GFP_ATOMIC); 130 131 spin_lock_irqsave(<q_dma_lock, flags); 132 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 133 ltq_dma_w32(ch->phys, LTQ_DMA_CDBA); 134 ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN); 135 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 136 wmb(); 137 ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL); 138 while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST) 139 ; 140 spin_unlock_irqrestore(<q_dma_lock, flags); 141 } 142 143 void 144 ltq_dma_alloc_tx(struct ltq_dma_channel *ch) 145 { 146 unsigned long flags; 147 148 ltq_dma_alloc(ch); 149 150 spin_lock_irqsave(<q_dma_lock, flags); 151 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); 152 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 153 ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL); 154 spin_unlock_irqrestore(<q_dma_lock, flags); 155 } 156 EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx); 157 158 void 159 ltq_dma_alloc_rx(struct ltq_dma_channel *ch) 160 { 161 unsigned long flags; 162 163 ltq_dma_alloc(ch); 164 165 spin_lock_irqsave(<q_dma_lock, flags); 166 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); 167 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 168 ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL); 169 spin_unlock_irqrestore(<q_dma_lock, flags); 170 } 171 EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx); 172 173 void 174 ltq_dma_free(struct ltq_dma_channel *ch) 175 { 176 if (!ch->desc_base) 177 return; 178 ltq_dma_close(ch); 179 dma_free_coherent(ch->dev, LTQ_DESC_NUM * LTQ_DESC_SIZE, 180 ch->desc_base, ch->phys); 181 } 182 EXPORT_SYMBOL_GPL(ltq_dma_free); 183 184 void 185 ltq_dma_init_port(int p, int tx_burst, int rx_burst) 186 { 187 ltq_dma_w32(p, LTQ_DMA_PS); 188 switch (p) { 189 case DMA_PORT_ETOP: 190 /* 191 * Tell the DMA engine to swap the endianness of data frames and 192 * drop packets if the channel arbitration fails. 193 */ 194 ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN), 195 LTQ_DMA_PCTRL); 196 break; 197 198 default: 199 break; 200 } 201 202 switch (rx_burst) { 203 case 8: 204 ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT), 205 LTQ_DMA_PCTRL); 206 break; 207 case 4: 208 ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT), 209 LTQ_DMA_PCTRL); 210 break; 211 case 2: 212 ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT), 213 LTQ_DMA_PCTRL); 214 break; 215 default: 216 break; 217 } 218 219 switch (tx_burst) { 220 case 8: 221 ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT), 222 LTQ_DMA_PCTRL); 223 break; 224 case 4: 225 ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT), 226 LTQ_DMA_PCTRL); 227 break; 228 case 2: 229 ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT), 230 LTQ_DMA_PCTRL); 231 break; 232 default: 233 break; 234 } 235 } 236 EXPORT_SYMBOL_GPL(ltq_dma_init_port); 237 238 static int 239 ltq_dma_init(struct platform_device *pdev) 240 { 241 struct clk *clk; 242 struct resource *res; 243 unsigned int id, nchannels; 244 int i; 245 246 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 247 ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res); 248 if (IS_ERR(ltq_dma_membase)) 249 panic("Failed to remap dma resource"); 250 251 /* power up and reset the dma engine */ 252 clk = clk_get(&pdev->dev, NULL); 253 if (IS_ERR(clk)) 254 panic("Failed to get dma clock"); 255 256 clk_enable(clk); 257 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); 258 259 usleep_range(1, 10); 260 261 /* disable all interrupts */ 262 ltq_dma_w32(0, LTQ_DMA_IRNEN); 263 264 /* reset/configure each channel */ 265 id = ltq_dma_r32(LTQ_DMA_ID); 266 nchannels = ((id & DMA_ID_CHNR) >> 20); 267 for (i = 0; i < nchannels; i++) { 268 ltq_dma_w32(i, LTQ_DMA_CS); 269 ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL); 270 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); 271 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 272 } 273 274 dev_info(&pdev->dev, 275 "Init done - hw rev: %X, ports: %d, channels: %d\n", 276 id & 0x1f, (id >> 16) & 0xf, nchannels); 277 278 return 0; 279 } 280 281 static const struct of_device_id dma_match[] = { 282 { .compatible = "lantiq,dma-xway" }, 283 {}, 284 }; 285 286 static struct platform_driver dma_driver = { 287 .probe = ltq_dma_init, 288 .driver = { 289 .name = "dma-xway", 290 .of_match_table = dma_match, 291 }, 292 }; 293 294 int __init 295 dma_init(void) 296 { 297 return platform_driver_register(&dma_driver); 298 } 299 300 postcore_initcall(dma_init); 301