1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 14 * 15 * Copyright (C) 2011 John Crispin <john@phrozen.org> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/io.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/export.h> 23 #include <linux/spinlock.h> 24 #include <linux/clk.h> 25 #include <linux/err.h> 26 27 #include <lantiq_soc.h> 28 #include <xway_dma.h> 29 30 #define LTQ_DMA_ID 0x08 31 #define LTQ_DMA_CTRL 0x10 32 #define LTQ_DMA_CPOLL 0x14 33 #define LTQ_DMA_CS 0x18 34 #define LTQ_DMA_CCTRL 0x1C 35 #define LTQ_DMA_CDBA 0x20 36 #define LTQ_DMA_CDLEN 0x24 37 #define LTQ_DMA_CIS 0x28 38 #define LTQ_DMA_CIE 0x2C 39 #define LTQ_DMA_PS 0x40 40 #define LTQ_DMA_PCTRL 0x44 41 #define LTQ_DMA_IRNEN 0xf4 42 43 #define DMA_DESCPT BIT(3) /* descriptor complete irq */ 44 #define DMA_TX BIT(8) /* TX channel direction */ 45 #define DMA_CHAN_ON BIT(0) /* channel on / off bit */ 46 #define DMA_PDEN BIT(6) /* enable packet drop */ 47 #define DMA_CHAN_RST BIT(1) /* channel on / off bit */ 48 #define DMA_RESET BIT(0) /* channel on / off bit */ 49 #define DMA_IRQ_ACK 0x7e /* IRQ status register */ 50 #define DMA_POLL BIT(31) /* turn on channel polling */ 51 #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ 52 #define DMA_2W_BURST BIT(1) /* 2 word burst length */ 53 #define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ 54 #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */ 55 #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ 56 57 #define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x)) 58 #define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y)) 59 #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ 60 ltq_dma_membase + (z)) 61 62 static void __iomem *ltq_dma_membase; 63 static DEFINE_SPINLOCK(ltq_dma_lock); 64 65 void 66 ltq_dma_enable_irq(struct ltq_dma_channel *ch) 67 { 68 unsigned long flags; 69 70 spin_lock_irqsave(<q_dma_lock, flags); 71 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 72 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 73 spin_unlock_irqrestore(<q_dma_lock, flags); 74 } 75 EXPORT_SYMBOL_GPL(ltq_dma_enable_irq); 76 77 void 78 ltq_dma_disable_irq(struct ltq_dma_channel *ch) 79 { 80 unsigned long flags; 81 82 spin_lock_irqsave(<q_dma_lock, flags); 83 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 84 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); 85 spin_unlock_irqrestore(<q_dma_lock, flags); 86 } 87 EXPORT_SYMBOL_GPL(ltq_dma_disable_irq); 88 89 void 90 ltq_dma_ack_irq(struct ltq_dma_channel *ch) 91 { 92 unsigned long flags; 93 94 spin_lock_irqsave(<q_dma_lock, flags); 95 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 96 ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS); 97 spin_unlock_irqrestore(<q_dma_lock, flags); 98 } 99 EXPORT_SYMBOL_GPL(ltq_dma_ack_irq); 100 101 void 102 ltq_dma_open(struct ltq_dma_channel *ch) 103 { 104 unsigned long flag; 105 106 spin_lock_irqsave(<q_dma_lock, flag); 107 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 108 ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL); 109 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 110 spin_unlock_irqrestore(<q_dma_lock, flag); 111 } 112 EXPORT_SYMBOL_GPL(ltq_dma_open); 113 114 void 115 ltq_dma_close(struct ltq_dma_channel *ch) 116 { 117 unsigned long flag; 118 119 spin_lock_irqsave(<q_dma_lock, flag); 120 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 121 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 122 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); 123 spin_unlock_irqrestore(<q_dma_lock, flag); 124 } 125 EXPORT_SYMBOL_GPL(ltq_dma_close); 126 127 static void 128 ltq_dma_alloc(struct ltq_dma_channel *ch) 129 { 130 unsigned long flags; 131 132 ch->desc = 0; 133 ch->desc_base = dma_alloc_coherent(NULL, 134 LTQ_DESC_NUM * LTQ_DESC_SIZE, 135 &ch->phys, GFP_ATOMIC); 136 memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE); 137 138 spin_lock_irqsave(<q_dma_lock, flags); 139 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 140 ltq_dma_w32(ch->phys, LTQ_DMA_CDBA); 141 ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN); 142 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 143 wmb(); 144 ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL); 145 while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST) 146 ; 147 spin_unlock_irqrestore(<q_dma_lock, flags); 148 } 149 150 void 151 ltq_dma_alloc_tx(struct ltq_dma_channel *ch) 152 { 153 unsigned long flags; 154 155 ltq_dma_alloc(ch); 156 157 spin_lock_irqsave(<q_dma_lock, flags); 158 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); 159 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 160 ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL); 161 spin_unlock_irqrestore(<q_dma_lock, flags); 162 } 163 EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx); 164 165 void 166 ltq_dma_alloc_rx(struct ltq_dma_channel *ch) 167 { 168 unsigned long flags; 169 170 ltq_dma_alloc(ch); 171 172 spin_lock_irqsave(<q_dma_lock, flags); 173 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); 174 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 175 ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL); 176 spin_unlock_irqrestore(<q_dma_lock, flags); 177 } 178 EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx); 179 180 void 181 ltq_dma_free(struct ltq_dma_channel *ch) 182 { 183 if (!ch->desc_base) 184 return; 185 ltq_dma_close(ch); 186 dma_free_coherent(NULL, LTQ_DESC_NUM * LTQ_DESC_SIZE, 187 ch->desc_base, ch->phys); 188 } 189 EXPORT_SYMBOL_GPL(ltq_dma_free); 190 191 void 192 ltq_dma_init_port(int p) 193 { 194 ltq_dma_w32(p, LTQ_DMA_PS); 195 switch (p) { 196 case DMA_PORT_ETOP: 197 /* 198 * Tell the DMA engine to swap the endianness of data frames and 199 * drop packets if the channel arbitration fails. 200 */ 201 ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN, 202 LTQ_DMA_PCTRL); 203 break; 204 205 case DMA_PORT_DEU: 206 ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2), 207 LTQ_DMA_PCTRL); 208 break; 209 210 default: 211 break; 212 } 213 } 214 EXPORT_SYMBOL_GPL(ltq_dma_init_port); 215 216 static int 217 ltq_dma_init(struct platform_device *pdev) 218 { 219 struct clk *clk; 220 struct resource *res; 221 unsigned id; 222 int i; 223 224 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 225 ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res); 226 if (IS_ERR(ltq_dma_membase)) 227 panic("Failed to remap dma resource"); 228 229 /* power up and reset the dma engine */ 230 clk = clk_get(&pdev->dev, NULL); 231 if (IS_ERR(clk)) 232 panic("Failed to get dma clock"); 233 234 clk_enable(clk); 235 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); 236 237 /* disable all interrupts */ 238 ltq_dma_w32(0, LTQ_DMA_IRNEN); 239 240 /* reset/configure each channel */ 241 for (i = 0; i < DMA_MAX_CHANNEL; i++) { 242 ltq_dma_w32(i, LTQ_DMA_CS); 243 ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL); 244 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); 245 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 246 } 247 248 id = ltq_dma_r32(LTQ_DMA_ID); 249 dev_info(&pdev->dev, 250 "Init done - hw rev: %X, ports: %d, channels: %d\n", 251 id & 0x1f, (id >> 16) & 0xf, id >> 20); 252 253 return 0; 254 } 255 256 static const struct of_device_id dma_match[] = { 257 { .compatible = "lantiq,dma-xway" }, 258 {}, 259 }; 260 261 static struct platform_driver dma_driver = { 262 .probe = ltq_dma_init, 263 .driver = { 264 .name = "dma-xway", 265 .of_match_table = dma_match, 266 }, 267 }; 268 269 int __init 270 dma_init(void) 271 { 272 return platform_driver_register(&dma_driver); 273 } 274 275 postcore_initcall(dma_init); 276