1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 14 * 15 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/io.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/module.h> 23 #include <linux/clk.h> 24 25 #include <lantiq_soc.h> 26 #include <xway_dma.h> 27 28 #define LTQ_DMA_ID 0x08 29 #define LTQ_DMA_CTRL 0x10 30 #define LTQ_DMA_CPOLL 0x14 31 #define LTQ_DMA_CS 0x18 32 #define LTQ_DMA_CCTRL 0x1C 33 #define LTQ_DMA_CDBA 0x20 34 #define LTQ_DMA_CDLEN 0x24 35 #define LTQ_DMA_CIS 0x28 36 #define LTQ_DMA_CIE 0x2C 37 #define LTQ_DMA_PS 0x40 38 #define LTQ_DMA_PCTRL 0x44 39 #define LTQ_DMA_IRNEN 0xf4 40 41 #define DMA_DESCPT BIT(3) /* descriptor complete irq */ 42 #define DMA_TX BIT(8) /* TX channel direction */ 43 #define DMA_CHAN_ON BIT(0) /* channel on / off bit */ 44 #define DMA_PDEN BIT(6) /* enable packet drop */ 45 #define DMA_CHAN_RST BIT(1) /* channel on / off bit */ 46 #define DMA_RESET BIT(0) /* channel on / off bit */ 47 #define DMA_IRQ_ACK 0x7e /* IRQ status register */ 48 #define DMA_POLL BIT(31) /* turn on channel polling */ 49 #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ 50 #define DMA_2W_BURST BIT(1) /* 2 word burst length */ 51 #define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ 52 #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */ 53 #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ 54 55 #define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x)) 56 #define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y)) 57 #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ 58 ltq_dma_membase + (z)) 59 60 static void __iomem *ltq_dma_membase; 61 62 void 63 ltq_dma_enable_irq(struct ltq_dma_channel *ch) 64 { 65 unsigned long flags; 66 67 local_irq_save(flags); 68 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 69 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 70 local_irq_restore(flags); 71 } 72 EXPORT_SYMBOL_GPL(ltq_dma_enable_irq); 73 74 void 75 ltq_dma_disable_irq(struct ltq_dma_channel *ch) 76 { 77 unsigned long flags; 78 79 local_irq_save(flags); 80 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 81 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); 82 local_irq_restore(flags); 83 } 84 EXPORT_SYMBOL_GPL(ltq_dma_disable_irq); 85 86 void 87 ltq_dma_ack_irq(struct ltq_dma_channel *ch) 88 { 89 unsigned long flags; 90 91 local_irq_save(flags); 92 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 93 ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS); 94 local_irq_restore(flags); 95 } 96 EXPORT_SYMBOL_GPL(ltq_dma_ack_irq); 97 98 void 99 ltq_dma_open(struct ltq_dma_channel *ch) 100 { 101 unsigned long flag; 102 103 local_irq_save(flag); 104 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 105 ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL); 106 ltq_dma_enable_irq(ch); 107 local_irq_restore(flag); 108 } 109 EXPORT_SYMBOL_GPL(ltq_dma_open); 110 111 void 112 ltq_dma_close(struct ltq_dma_channel *ch) 113 { 114 unsigned long flag; 115 116 local_irq_save(flag); 117 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 118 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 119 ltq_dma_disable_irq(ch); 120 local_irq_restore(flag); 121 } 122 EXPORT_SYMBOL_GPL(ltq_dma_close); 123 124 static void 125 ltq_dma_alloc(struct ltq_dma_channel *ch) 126 { 127 unsigned long flags; 128 129 ch->desc = 0; 130 ch->desc_base = dma_alloc_coherent(NULL, 131 LTQ_DESC_NUM * LTQ_DESC_SIZE, 132 &ch->phys, GFP_ATOMIC); 133 memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE); 134 135 local_irq_save(flags); 136 ltq_dma_w32(ch->nr, LTQ_DMA_CS); 137 ltq_dma_w32(ch->phys, LTQ_DMA_CDBA); 138 ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN); 139 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 140 wmb(); 141 ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL); 142 while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST) 143 ; 144 local_irq_restore(flags); 145 } 146 147 void 148 ltq_dma_alloc_tx(struct ltq_dma_channel *ch) 149 { 150 unsigned long flags; 151 152 ltq_dma_alloc(ch); 153 154 local_irq_save(flags); 155 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); 156 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 157 ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL); 158 local_irq_restore(flags); 159 } 160 EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx); 161 162 void 163 ltq_dma_alloc_rx(struct ltq_dma_channel *ch) 164 { 165 unsigned long flags; 166 167 ltq_dma_alloc(ch); 168 169 local_irq_save(flags); 170 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); 171 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); 172 ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL); 173 local_irq_restore(flags); 174 } 175 EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx); 176 177 void 178 ltq_dma_free(struct ltq_dma_channel *ch) 179 { 180 if (!ch->desc_base) 181 return; 182 ltq_dma_close(ch); 183 dma_free_coherent(NULL, LTQ_DESC_NUM * LTQ_DESC_SIZE, 184 ch->desc_base, ch->phys); 185 } 186 EXPORT_SYMBOL_GPL(ltq_dma_free); 187 188 void 189 ltq_dma_init_port(int p) 190 { 191 ltq_dma_w32(p, LTQ_DMA_PS); 192 switch (p) { 193 case DMA_PORT_ETOP: 194 /* 195 * Tell the DMA engine to swap the endianness of data frames and 196 * drop packets if the channel arbitration fails. 197 */ 198 ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN, 199 LTQ_DMA_PCTRL); 200 break; 201 202 case DMA_PORT_DEU: 203 ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2), 204 LTQ_DMA_PCTRL); 205 break; 206 207 default: 208 break; 209 } 210 } 211 EXPORT_SYMBOL_GPL(ltq_dma_init_port); 212 213 static int __devinit 214 ltq_dma_init(struct platform_device *pdev) 215 { 216 struct clk *clk; 217 struct resource *res; 218 unsigned id; 219 int i; 220 221 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 222 if (!res) 223 panic("Failed to get dma resource"); 224 225 /* remap dma register range */ 226 ltq_dma_membase = devm_request_and_ioremap(&pdev->dev, res); 227 if (!ltq_dma_membase) 228 panic("Failed to remap dma resource"); 229 230 /* power up and reset the dma engine */ 231 clk = clk_get(&pdev->dev, NULL); 232 if (IS_ERR(clk)) 233 panic("Failed to get dma clock"); 234 235 clk_enable(clk); 236 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); 237 238 /* disable all interrupts */ 239 ltq_dma_w32(0, LTQ_DMA_IRNEN); 240 241 /* reset/configure each channel */ 242 for (i = 0; i < DMA_MAX_CHANNEL; i++) { 243 ltq_dma_w32(i, LTQ_DMA_CS); 244 ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL); 245 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); 246 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 247 } 248 249 id = ltq_dma_r32(LTQ_DMA_ID); 250 dev_info(&pdev->dev, 251 "Init done - hw rev: %X, ports: %d, channels: %d\n", 252 id & 0x1f, (id >> 16) & 0xf, id >> 20); 253 254 return 0; 255 } 256 257 static const struct of_device_id dma_match[] = { 258 { .compatible = "lantiq,dma-xway" }, 259 {}, 260 }; 261 MODULE_DEVICE_TABLE(of, dma_match); 262 263 static struct platform_driver dma_driver = { 264 .probe = ltq_dma_init, 265 .driver = { 266 .name = "dma-xway", 267 .owner = THIS_MODULE, 268 .of_match_table = dma_match, 269 }, 270 }; 271 272 int __init 273 dma_init(void) 274 { 275 return platform_driver_register(&dma_driver); 276 } 277 278 postcore_initcall(dma_init); 279