1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Copyright (C) 2010 John Crispin <john@phrozen.org> 7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com> 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/ioport.h> 12 #include <linux/sched.h> 13 #include <linux/irqdomain.h> 14 #include <linux/of_platform.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 18 #include <asm/bootinfo.h> 19 #include <asm/irq_cpu.h> 20 21 #include <lantiq_soc.h> 22 #include <irq.h> 23 24 /* register definitions - internal irqs */ 25 #define LTQ_ICU_IM0_ISR 0x0000 26 #define LTQ_ICU_IM0_IER 0x0008 27 #define LTQ_ICU_IM0_IOSR 0x0010 28 #define LTQ_ICU_IM0_IRSR 0x0018 29 #define LTQ_ICU_IM0_IMR 0x0020 30 #define LTQ_ICU_IM1_ISR 0x0028 31 #define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR) 32 33 /* register definitions - external irqs */ 34 #define LTQ_EIU_EXIN_C 0x0000 35 #define LTQ_EIU_EXIN_INIC 0x0004 36 #define LTQ_EIU_EXIN_INC 0x0008 37 #define LTQ_EIU_EXIN_INEN 0x000C 38 39 /* number of external interrupts */ 40 #define MAX_EIU 6 41 42 /* the performance counter */ 43 #define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31) 44 45 /* 46 * irqs generated by devices attached to the EBU need to be acked in 47 * a special manner 48 */ 49 #define LTQ_ICU_EBU_IRQ 22 50 51 #define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y)) 52 #define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x)) 53 54 #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) 55 #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) 56 57 /* our 2 ipi interrupts for VSMP */ 58 #define MIPS_CPU_IPI_RESCHED_IRQ 0 59 #define MIPS_CPU_IPI_CALL_IRQ 1 60 61 /* we have a cascade of 8 irqs */ 62 #define MIPS_CPU_IRQ_CASCADE 8 63 64 static int exin_avail; 65 static u32 ltq_eiu_irq[MAX_EIU]; 66 static void __iomem *ltq_icu_membase[MAX_IM]; 67 static void __iomem *ltq_eiu_membase; 68 static struct irq_domain *ltq_domain; 69 static int ltq_perfcount_irq; 70 71 int ltq_eiu_get_irq(int exin) 72 { 73 if (exin < exin_avail) 74 return ltq_eiu_irq[exin]; 75 return -1; 76 } 77 78 void ltq_disable_irq(struct irq_data *d) 79 { 80 u32 ier = LTQ_ICU_IM0_IER; 81 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; 82 int im = offset / INT_NUM_IM_OFFSET; 83 84 offset %= INT_NUM_IM_OFFSET; 85 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); 86 } 87 88 void ltq_mask_and_ack_irq(struct irq_data *d) 89 { 90 u32 ier = LTQ_ICU_IM0_IER; 91 u32 isr = LTQ_ICU_IM0_ISR; 92 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; 93 int im = offset / INT_NUM_IM_OFFSET; 94 95 offset %= INT_NUM_IM_OFFSET; 96 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); 97 ltq_icu_w32(im, BIT(offset), isr); 98 } 99 100 static void ltq_ack_irq(struct irq_data *d) 101 { 102 u32 isr = LTQ_ICU_IM0_ISR; 103 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; 104 int im = offset / INT_NUM_IM_OFFSET; 105 106 offset %= INT_NUM_IM_OFFSET; 107 ltq_icu_w32(im, BIT(offset), isr); 108 } 109 110 void ltq_enable_irq(struct irq_data *d) 111 { 112 u32 ier = LTQ_ICU_IM0_IER; 113 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; 114 int im = offset / INT_NUM_IM_OFFSET; 115 116 offset %= INT_NUM_IM_OFFSET; 117 ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier); 118 } 119 120 static int ltq_eiu_settype(struct irq_data *d, unsigned int type) 121 { 122 int i; 123 124 for (i = 0; i < exin_avail; i++) { 125 if (d->hwirq == ltq_eiu_irq[i]) { 126 int val = 0; 127 int edge = 0; 128 129 switch (type) { 130 case IRQF_TRIGGER_NONE: 131 break; 132 case IRQF_TRIGGER_RISING: 133 val = 1; 134 edge = 1; 135 break; 136 case IRQF_TRIGGER_FALLING: 137 val = 2; 138 edge = 1; 139 break; 140 case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING: 141 val = 3; 142 edge = 1; 143 break; 144 case IRQF_TRIGGER_HIGH: 145 val = 5; 146 break; 147 case IRQF_TRIGGER_LOW: 148 val = 6; 149 break; 150 default: 151 pr_err("invalid type %d for irq %ld\n", 152 type, d->hwirq); 153 return -EINVAL; 154 } 155 156 if (edge) 157 irq_set_handler(d->hwirq, handle_edge_irq); 158 159 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) | 160 (val << (i * 4)), LTQ_EIU_EXIN_C); 161 } 162 } 163 164 return 0; 165 } 166 167 static unsigned int ltq_startup_eiu_irq(struct irq_data *d) 168 { 169 int i; 170 171 ltq_enable_irq(d); 172 for (i = 0; i < exin_avail; i++) { 173 if (d->hwirq == ltq_eiu_irq[i]) { 174 /* by default we are low level triggered */ 175 ltq_eiu_settype(d, IRQF_TRIGGER_LOW); 176 /* clear all pending */ 177 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i), 178 LTQ_EIU_EXIN_INC); 179 /* enable */ 180 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i), 181 LTQ_EIU_EXIN_INEN); 182 break; 183 } 184 } 185 186 return 0; 187 } 188 189 static void ltq_shutdown_eiu_irq(struct irq_data *d) 190 { 191 int i; 192 193 ltq_disable_irq(d); 194 for (i = 0; i < exin_avail; i++) { 195 if (d->hwirq == ltq_eiu_irq[i]) { 196 /* disable */ 197 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i), 198 LTQ_EIU_EXIN_INEN); 199 break; 200 } 201 } 202 } 203 204 static struct irq_chip ltq_irq_type = { 205 .name = "icu", 206 .irq_enable = ltq_enable_irq, 207 .irq_disable = ltq_disable_irq, 208 .irq_unmask = ltq_enable_irq, 209 .irq_ack = ltq_ack_irq, 210 .irq_mask = ltq_disable_irq, 211 .irq_mask_ack = ltq_mask_and_ack_irq, 212 }; 213 214 static struct irq_chip ltq_eiu_type = { 215 .name = "eiu", 216 .irq_startup = ltq_startup_eiu_irq, 217 .irq_shutdown = ltq_shutdown_eiu_irq, 218 .irq_enable = ltq_enable_irq, 219 .irq_disable = ltq_disable_irq, 220 .irq_unmask = ltq_enable_irq, 221 .irq_ack = ltq_ack_irq, 222 .irq_mask = ltq_disable_irq, 223 .irq_mask_ack = ltq_mask_and_ack_irq, 224 .irq_set_type = ltq_eiu_settype, 225 }; 226 227 static void ltq_hw_irq_handler(struct irq_desc *desc) 228 { 229 int module = irq_desc_get_irq(desc) - 2; 230 u32 irq; 231 int hwirq; 232 233 irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR); 234 if (irq == 0) 235 return; 236 237 /* 238 * silicon bug causes only the msb set to 1 to be valid. all 239 * other bits might be bogus 240 */ 241 irq = __fls(irq); 242 hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module); 243 generic_handle_irq(irq_linear_revmap(ltq_domain, hwirq)); 244 245 /* if this is a EBU irq, we need to ack it or get a deadlock */ 246 if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) 247 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, 248 LTQ_EBU_PCC_ISTAT); 249 } 250 251 static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 252 { 253 struct irq_chip *chip = <q_irq_type; 254 int i; 255 256 if (hw < MIPS_CPU_IRQ_CASCADE) 257 return 0; 258 259 for (i = 0; i < exin_avail; i++) 260 if (hw == ltq_eiu_irq[i]) 261 chip = <q_eiu_type; 262 263 irq_set_chip_and_handler(irq, chip, handle_level_irq); 264 265 return 0; 266 } 267 268 static const struct irq_domain_ops irq_domain_ops = { 269 .xlate = irq_domain_xlate_onetwocell, 270 .map = icu_map, 271 }; 272 273 int __init icu_of_init(struct device_node *node, struct device_node *parent) 274 { 275 struct device_node *eiu_node; 276 struct resource res; 277 int i, ret; 278 279 for (i = 0; i < MAX_IM; i++) { 280 if (of_address_to_resource(node, i, &res)) 281 panic("Failed to get icu memory range"); 282 283 if (!request_mem_region(res.start, resource_size(&res), 284 res.name)) 285 pr_err("Failed to request icu memory"); 286 287 ltq_icu_membase[i] = ioremap_nocache(res.start, 288 resource_size(&res)); 289 if (!ltq_icu_membase[i]) 290 panic("Failed to remap icu memory"); 291 } 292 293 /* turn off all irqs by default */ 294 for (i = 0; i < MAX_IM; i++) { 295 /* make sure all irqs are turned off by default */ 296 ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER); 297 /* clear all possibly pending interrupts */ 298 ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR); 299 } 300 301 mips_cpu_irq_init(); 302 303 for (i = 0; i < MAX_IM; i++) 304 irq_set_chained_handler(i + 2, ltq_hw_irq_handler); 305 306 ltq_domain = irq_domain_add_linear(node, 307 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE, 308 &irq_domain_ops, 0); 309 310 /* tell oprofile which irq to use */ 311 ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ); 312 313 /* the external interrupts are optional and xway only */ 314 eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway"); 315 if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) { 316 /* find out how many external irq sources we have */ 317 exin_avail = of_property_count_u32_elems(eiu_node, 318 "lantiq,eiu-irqs"); 319 320 if (exin_avail > MAX_EIU) 321 exin_avail = MAX_EIU; 322 323 ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs", 324 ltq_eiu_irq, exin_avail); 325 if (ret) 326 panic("failed to load external irq resources"); 327 328 if (!request_mem_region(res.start, resource_size(&res), 329 res.name)) 330 pr_err("Failed to request eiu memory"); 331 332 ltq_eiu_membase = ioremap_nocache(res.start, 333 resource_size(&res)); 334 if (!ltq_eiu_membase) 335 panic("Failed to remap eiu memory"); 336 } 337 338 return 0; 339 } 340 341 int get_c0_perfcount_int(void) 342 { 343 return ltq_perfcount_irq; 344 } 345 EXPORT_SYMBOL_GPL(get_c0_perfcount_int); 346 347 unsigned int get_c0_compare_int(void) 348 { 349 return CP0_LEGACY_COMPARE_IRQ; 350 } 351 352 static struct of_device_id __initdata of_irq_ids[] = { 353 { .compatible = "lantiq,icu", .data = icu_of_init }, 354 {}, 355 }; 356 357 void __init arch_init_irq(void) 358 { 359 of_irq_init(of_irq_ids); 360 } 361