1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * KVM/MIPS: MIPS specific KVM APIs 7 * 8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 9 * Authors: Sanjay Lal <sanjayl@kymasys.com> 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/errno.h> 14 #include <linux/err.h> 15 #include <linux/kdebug.h> 16 #include <linux/module.h> 17 #include <linux/uaccess.h> 18 #include <linux/vmalloc.h> 19 #include <linux/sched/signal.h> 20 #include <linux/fs.h> 21 #include <linux/memblock.h> 22 #include <linux/pgtable.h> 23 24 #include <asm/fpu.h> 25 #include <asm/page.h> 26 #include <asm/cacheflush.h> 27 #include <asm/mmu_context.h> 28 #include <asm/pgalloc.h> 29 30 #include <linux/kvm_host.h> 31 32 #include "interrupt.h" 33 34 #define CREATE_TRACE_POINTS 35 #include "trace.h" 36 37 #ifndef VECTORSPACING 38 #define VECTORSPACING 0x100 /* for EI/VI mode */ 39 #endif 40 41 const struct _kvm_stats_desc kvm_vm_stats_desc[] = { 42 KVM_GENERIC_VM_STATS() 43 }; 44 45 const struct kvm_stats_header kvm_vm_stats_header = { 46 .name_size = KVM_STATS_NAME_SIZE, 47 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), 48 .id_offset = sizeof(struct kvm_stats_header), 49 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 50 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 51 sizeof(kvm_vm_stats_desc), 52 }; 53 54 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 55 KVM_GENERIC_VCPU_STATS(), 56 STATS_DESC_COUNTER(VCPU, wait_exits), 57 STATS_DESC_COUNTER(VCPU, cache_exits), 58 STATS_DESC_COUNTER(VCPU, signal_exits), 59 STATS_DESC_COUNTER(VCPU, int_exits), 60 STATS_DESC_COUNTER(VCPU, cop_unusable_exits), 61 STATS_DESC_COUNTER(VCPU, tlbmod_exits), 62 STATS_DESC_COUNTER(VCPU, tlbmiss_ld_exits), 63 STATS_DESC_COUNTER(VCPU, tlbmiss_st_exits), 64 STATS_DESC_COUNTER(VCPU, addrerr_st_exits), 65 STATS_DESC_COUNTER(VCPU, addrerr_ld_exits), 66 STATS_DESC_COUNTER(VCPU, syscall_exits), 67 STATS_DESC_COUNTER(VCPU, resvd_inst_exits), 68 STATS_DESC_COUNTER(VCPU, break_inst_exits), 69 STATS_DESC_COUNTER(VCPU, trap_inst_exits), 70 STATS_DESC_COUNTER(VCPU, msa_fpe_exits), 71 STATS_DESC_COUNTER(VCPU, fpe_exits), 72 STATS_DESC_COUNTER(VCPU, msa_disabled_exits), 73 STATS_DESC_COUNTER(VCPU, flush_dcache_exits), 74 STATS_DESC_COUNTER(VCPU, vz_gpsi_exits), 75 STATS_DESC_COUNTER(VCPU, vz_gsfc_exits), 76 STATS_DESC_COUNTER(VCPU, vz_hc_exits), 77 STATS_DESC_COUNTER(VCPU, vz_grr_exits), 78 STATS_DESC_COUNTER(VCPU, vz_gva_exits), 79 STATS_DESC_COUNTER(VCPU, vz_ghfc_exits), 80 STATS_DESC_COUNTER(VCPU, vz_gpa_exits), 81 STATS_DESC_COUNTER(VCPU, vz_resvd_exits), 82 #ifdef CONFIG_CPU_LOONGSON64 83 STATS_DESC_COUNTER(VCPU, vz_cpucfg_exits), 84 #endif 85 }; 86 87 const struct kvm_stats_header kvm_vcpu_stats_header = { 88 .name_size = KVM_STATS_NAME_SIZE, 89 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 90 .id_offset = sizeof(struct kvm_stats_header), 91 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 92 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 93 sizeof(kvm_vcpu_stats_desc), 94 }; 95 96 bool kvm_trace_guest_mode_change; 97 98 int kvm_guest_mode_change_trace_reg(void) 99 { 100 kvm_trace_guest_mode_change = true; 101 return 0; 102 } 103 104 void kvm_guest_mode_change_trace_unreg(void) 105 { 106 kvm_trace_guest_mode_change = false; 107 } 108 109 /* 110 * XXXKYMA: We are simulatoring a processor that has the WII bit set in 111 * Config7, so we are "runnable" if interrupts are pending 112 */ 113 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 114 { 115 return !!(vcpu->arch.pending_exceptions); 116 } 117 118 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 119 { 120 return false; 121 } 122 123 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 124 { 125 return 1; 126 } 127 128 int kvm_arch_hardware_enable(void) 129 { 130 return kvm_mips_callbacks->hardware_enable(); 131 } 132 133 void kvm_arch_hardware_disable(void) 134 { 135 kvm_mips_callbacks->hardware_disable(); 136 } 137 138 int kvm_arch_hardware_setup(void *opaque) 139 { 140 return 0; 141 } 142 143 int kvm_arch_check_processor_compat(void *opaque) 144 { 145 return 0; 146 } 147 148 extern void kvm_init_loongson_ipi(struct kvm *kvm); 149 150 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 151 { 152 switch (type) { 153 case KVM_VM_MIPS_AUTO: 154 break; 155 case KVM_VM_MIPS_VZ: 156 break; 157 default: 158 /* Unsupported KVM type */ 159 return -EINVAL; 160 } 161 162 /* Allocate page table to map GPA -> RPA */ 163 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc(); 164 if (!kvm->arch.gpa_mm.pgd) 165 return -ENOMEM; 166 167 #ifdef CONFIG_CPU_LOONGSON64 168 kvm_init_loongson_ipi(kvm); 169 #endif 170 171 return 0; 172 } 173 174 void kvm_mips_free_vcpus(struct kvm *kvm) 175 { 176 unsigned int i; 177 struct kvm_vcpu *vcpu; 178 179 kvm_for_each_vcpu(i, vcpu, kvm) { 180 kvm_vcpu_destroy(vcpu); 181 } 182 183 mutex_lock(&kvm->lock); 184 185 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 186 kvm->vcpus[i] = NULL; 187 188 atomic_set(&kvm->online_vcpus, 0); 189 190 mutex_unlock(&kvm->lock); 191 } 192 193 static void kvm_mips_free_gpa_pt(struct kvm *kvm) 194 { 195 /* It should always be safe to remove after flushing the whole range */ 196 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0)); 197 pgd_free(NULL, kvm->arch.gpa_mm.pgd); 198 } 199 200 void kvm_arch_destroy_vm(struct kvm *kvm) 201 { 202 kvm_mips_free_vcpus(kvm); 203 kvm_mips_free_gpa_pt(kvm); 204 } 205 206 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, 207 unsigned long arg) 208 { 209 return -ENOIOCTLCMD; 210 } 211 212 void kvm_arch_flush_shadow_all(struct kvm *kvm) 213 { 214 /* Flush whole GPA */ 215 kvm_mips_flush_gpa_pt(kvm, 0, ~0); 216 kvm_flush_remote_tlbs(kvm); 217 } 218 219 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 220 struct kvm_memory_slot *slot) 221 { 222 /* 223 * The slot has been made invalid (ready for moving or deletion), so we 224 * need to ensure that it can no longer be accessed by any guest VCPUs. 225 */ 226 227 spin_lock(&kvm->mmu_lock); 228 /* Flush slot from GPA */ 229 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn, 230 slot->base_gfn + slot->npages - 1); 231 kvm_arch_flush_remote_tlbs_memslot(kvm, slot); 232 spin_unlock(&kvm->mmu_lock); 233 } 234 235 int kvm_arch_prepare_memory_region(struct kvm *kvm, 236 struct kvm_memory_slot *memslot, 237 const struct kvm_userspace_memory_region *mem, 238 enum kvm_mr_change change) 239 { 240 return 0; 241 } 242 243 void kvm_arch_commit_memory_region(struct kvm *kvm, 244 const struct kvm_userspace_memory_region *mem, 245 struct kvm_memory_slot *old, 246 const struct kvm_memory_slot *new, 247 enum kvm_mr_change change) 248 { 249 int needs_flush; 250 251 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n", 252 __func__, kvm, mem->slot, mem->guest_phys_addr, 253 mem->memory_size, mem->userspace_addr); 254 255 /* 256 * If dirty page logging is enabled, write protect all pages in the slot 257 * ready for dirty logging. 258 * 259 * There is no need to do this in any of the following cases: 260 * CREATE: No dirty mappings will already exist. 261 * MOVE/DELETE: The old mappings will already have been cleaned up by 262 * kvm_arch_flush_shadow_memslot() 263 */ 264 if (change == KVM_MR_FLAGS_ONLY && 265 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 266 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) { 267 spin_lock(&kvm->mmu_lock); 268 /* Write protect GPA page table entries */ 269 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn, 270 new->base_gfn + new->npages - 1); 271 if (needs_flush) 272 kvm_arch_flush_remote_tlbs_memslot(kvm, new); 273 spin_unlock(&kvm->mmu_lock); 274 } 275 } 276 277 static inline void dump_handler(const char *symbol, void *start, void *end) 278 { 279 u32 *p; 280 281 pr_debug("LEAF(%s)\n", symbol); 282 283 pr_debug("\t.set push\n"); 284 pr_debug("\t.set noreorder\n"); 285 286 for (p = start; p < (u32 *)end; ++p) 287 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p); 288 289 pr_debug("\t.set\tpop\n"); 290 291 pr_debug("\tEND(%s)\n", symbol); 292 } 293 294 /* low level hrtimer wake routine */ 295 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) 296 { 297 struct kvm_vcpu *vcpu; 298 299 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); 300 301 kvm_mips_callbacks->queue_timer_int(vcpu); 302 303 vcpu->arch.wait = 0; 304 rcuwait_wake_up(&vcpu->wait); 305 306 return kvm_mips_count_timeout(vcpu); 307 } 308 309 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 310 { 311 return 0; 312 } 313 314 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 315 { 316 int err, size; 317 void *gebase, *p, *handler, *refill_start, *refill_end; 318 int i; 319 320 kvm_debug("kvm @ %p: create cpu %d at %p\n", 321 vcpu->kvm, vcpu->vcpu_id, vcpu); 322 323 err = kvm_mips_callbacks->vcpu_init(vcpu); 324 if (err) 325 return err; 326 327 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 328 HRTIMER_MODE_REL); 329 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 330 331 /* 332 * Allocate space for host mode exception handlers that handle 333 * guest mode exits 334 */ 335 if (cpu_has_veic || cpu_has_vint) 336 size = 0x200 + VECTORSPACING * 64; 337 else 338 size = 0x4000; 339 340 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); 341 342 if (!gebase) { 343 err = -ENOMEM; 344 goto out_uninit_vcpu; 345 } 346 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", 347 ALIGN(size, PAGE_SIZE), gebase); 348 349 /* 350 * Check new ebase actually fits in CP0_EBase. The lack of a write gate 351 * limits us to the low 512MB of physical address space. If the memory 352 * we allocate is out of range, just give up now. 353 */ 354 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) { 355 kvm_err("CP0_EBase.WG required for guest exception base %pK\n", 356 gebase); 357 err = -ENOMEM; 358 goto out_free_gebase; 359 } 360 361 /* Save new ebase */ 362 vcpu->arch.guest_ebase = gebase; 363 364 /* Build guest exception vectors dynamically in unmapped memory */ 365 handler = gebase + 0x2000; 366 367 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */ 368 refill_start = gebase; 369 if (IS_ENABLED(CONFIG_64BIT)) 370 refill_start += 0x080; 371 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler); 372 373 /* General Exception Entry point */ 374 kvm_mips_build_exception(gebase + 0x180, handler); 375 376 /* For vectored interrupts poke the exception code @ all offsets 0-7 */ 377 for (i = 0; i < 8; i++) { 378 kvm_debug("L1 Vectored handler @ %p\n", 379 gebase + 0x200 + (i * VECTORSPACING)); 380 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING, 381 handler); 382 } 383 384 /* General exit handler */ 385 p = handler; 386 p = kvm_mips_build_exit(p); 387 388 /* Guest entry routine */ 389 vcpu->arch.vcpu_run = p; 390 p = kvm_mips_build_vcpu_run(p); 391 392 /* Dump the generated code */ 393 pr_debug("#include <asm/asm.h>\n"); 394 pr_debug("#include <asm/regdef.h>\n"); 395 pr_debug("\n"); 396 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p); 397 dump_handler("kvm_tlb_refill", refill_start, refill_end); 398 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200); 399 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run); 400 401 /* Invalidate the icache for these ranges */ 402 flush_icache_range((unsigned long)gebase, 403 (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); 404 405 /* Init */ 406 vcpu->arch.last_sched_cpu = -1; 407 vcpu->arch.last_exec_cpu = -1; 408 409 /* Initial guest state */ 410 err = kvm_mips_callbacks->vcpu_setup(vcpu); 411 if (err) 412 goto out_free_gebase; 413 414 return 0; 415 416 out_free_gebase: 417 kfree(gebase); 418 out_uninit_vcpu: 419 kvm_mips_callbacks->vcpu_uninit(vcpu); 420 return err; 421 } 422 423 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 424 { 425 hrtimer_cancel(&vcpu->arch.comparecount_timer); 426 427 kvm_mips_dump_stats(vcpu); 428 429 kvm_mmu_free_memory_caches(vcpu); 430 kfree(vcpu->arch.guest_ebase); 431 432 kvm_mips_callbacks->vcpu_uninit(vcpu); 433 } 434 435 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 436 struct kvm_guest_debug *dbg) 437 { 438 return -ENOIOCTLCMD; 439 } 440 441 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 442 { 443 int r = -EINTR; 444 445 vcpu_load(vcpu); 446 447 kvm_sigset_activate(vcpu); 448 449 if (vcpu->mmio_needed) { 450 if (!vcpu->mmio_is_write) 451 kvm_mips_complete_mmio_load(vcpu); 452 vcpu->mmio_needed = 0; 453 } 454 455 if (vcpu->run->immediate_exit) 456 goto out; 457 458 lose_fpu(1); 459 460 local_irq_disable(); 461 guest_enter_irqoff(); 462 trace_kvm_enter(vcpu); 463 464 /* 465 * Make sure the read of VCPU requests in vcpu_run() callback is not 466 * reordered ahead of the write to vcpu->mode, or we could miss a TLB 467 * flush request while the requester sees the VCPU as outside of guest 468 * mode and not needing an IPI. 469 */ 470 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 471 472 r = kvm_mips_callbacks->vcpu_run(vcpu); 473 474 trace_kvm_out(vcpu); 475 guest_exit_irqoff(); 476 local_irq_enable(); 477 478 out: 479 kvm_sigset_deactivate(vcpu); 480 481 vcpu_put(vcpu); 482 return r; 483 } 484 485 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 486 struct kvm_mips_interrupt *irq) 487 { 488 int intr = (int)irq->irq; 489 struct kvm_vcpu *dvcpu = NULL; 490 491 if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] || 492 intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] || 493 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) || 494 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2])) 495 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, 496 (int)intr); 497 498 if (irq->cpu == -1) 499 dvcpu = vcpu; 500 else 501 dvcpu = vcpu->kvm->vcpus[irq->cpu]; 502 503 if (intr == 2 || intr == 3 || intr == 4 || intr == 6) { 504 kvm_mips_callbacks->queue_io_int(dvcpu, irq); 505 506 } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) { 507 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); 508 } else { 509 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, 510 irq->cpu, irq->irq); 511 return -EINVAL; 512 } 513 514 dvcpu->arch.wait = 0; 515 516 rcuwait_wake_up(&dvcpu->wait); 517 518 return 0; 519 } 520 521 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 522 struct kvm_mp_state *mp_state) 523 { 524 return -ENOIOCTLCMD; 525 } 526 527 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 528 struct kvm_mp_state *mp_state) 529 { 530 return -ENOIOCTLCMD; 531 } 532 533 static u64 kvm_mips_get_one_regs[] = { 534 KVM_REG_MIPS_R0, 535 KVM_REG_MIPS_R1, 536 KVM_REG_MIPS_R2, 537 KVM_REG_MIPS_R3, 538 KVM_REG_MIPS_R4, 539 KVM_REG_MIPS_R5, 540 KVM_REG_MIPS_R6, 541 KVM_REG_MIPS_R7, 542 KVM_REG_MIPS_R8, 543 KVM_REG_MIPS_R9, 544 KVM_REG_MIPS_R10, 545 KVM_REG_MIPS_R11, 546 KVM_REG_MIPS_R12, 547 KVM_REG_MIPS_R13, 548 KVM_REG_MIPS_R14, 549 KVM_REG_MIPS_R15, 550 KVM_REG_MIPS_R16, 551 KVM_REG_MIPS_R17, 552 KVM_REG_MIPS_R18, 553 KVM_REG_MIPS_R19, 554 KVM_REG_MIPS_R20, 555 KVM_REG_MIPS_R21, 556 KVM_REG_MIPS_R22, 557 KVM_REG_MIPS_R23, 558 KVM_REG_MIPS_R24, 559 KVM_REG_MIPS_R25, 560 KVM_REG_MIPS_R26, 561 KVM_REG_MIPS_R27, 562 KVM_REG_MIPS_R28, 563 KVM_REG_MIPS_R29, 564 KVM_REG_MIPS_R30, 565 KVM_REG_MIPS_R31, 566 567 #ifndef CONFIG_CPU_MIPSR6 568 KVM_REG_MIPS_HI, 569 KVM_REG_MIPS_LO, 570 #endif 571 KVM_REG_MIPS_PC, 572 }; 573 574 static u64 kvm_mips_get_one_regs_fpu[] = { 575 KVM_REG_MIPS_FCR_IR, 576 KVM_REG_MIPS_FCR_CSR, 577 }; 578 579 static u64 kvm_mips_get_one_regs_msa[] = { 580 KVM_REG_MIPS_MSA_IR, 581 KVM_REG_MIPS_MSA_CSR, 582 }; 583 584 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu) 585 { 586 unsigned long ret; 587 588 ret = ARRAY_SIZE(kvm_mips_get_one_regs); 589 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 590 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48; 591 /* odd doubles */ 592 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64) 593 ret += 16; 594 } 595 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) 596 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32; 597 ret += kvm_mips_callbacks->num_regs(vcpu); 598 599 return ret; 600 } 601 602 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) 603 { 604 u64 index; 605 unsigned int i; 606 607 if (copy_to_user(indices, kvm_mips_get_one_regs, 608 sizeof(kvm_mips_get_one_regs))) 609 return -EFAULT; 610 indices += ARRAY_SIZE(kvm_mips_get_one_regs); 611 612 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 613 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu, 614 sizeof(kvm_mips_get_one_regs_fpu))) 615 return -EFAULT; 616 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu); 617 618 for (i = 0; i < 32; ++i) { 619 index = KVM_REG_MIPS_FPR_32(i); 620 if (copy_to_user(indices, &index, sizeof(index))) 621 return -EFAULT; 622 ++indices; 623 624 /* skip odd doubles if no F64 */ 625 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64)) 626 continue; 627 628 index = KVM_REG_MIPS_FPR_64(i); 629 if (copy_to_user(indices, &index, sizeof(index))) 630 return -EFAULT; 631 ++indices; 632 } 633 } 634 635 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) { 636 if (copy_to_user(indices, kvm_mips_get_one_regs_msa, 637 sizeof(kvm_mips_get_one_regs_msa))) 638 return -EFAULT; 639 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa); 640 641 for (i = 0; i < 32; ++i) { 642 index = KVM_REG_MIPS_VEC_128(i); 643 if (copy_to_user(indices, &index, sizeof(index))) 644 return -EFAULT; 645 ++indices; 646 } 647 } 648 649 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices); 650 } 651 652 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 653 const struct kvm_one_reg *reg) 654 { 655 struct mips_coproc *cop0 = vcpu->arch.cop0; 656 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 657 int ret; 658 s64 v; 659 s64 vs[2]; 660 unsigned int idx; 661 662 switch (reg->id) { 663 /* General purpose registers */ 664 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: 665 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; 666 break; 667 #ifndef CONFIG_CPU_MIPSR6 668 case KVM_REG_MIPS_HI: 669 v = (long)vcpu->arch.hi; 670 break; 671 case KVM_REG_MIPS_LO: 672 v = (long)vcpu->arch.lo; 673 break; 674 #endif 675 case KVM_REG_MIPS_PC: 676 v = (long)vcpu->arch.pc; 677 break; 678 679 /* Floating point registers */ 680 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 681 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 682 return -EINVAL; 683 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 684 /* Odd singles in top of even double when FR=0 */ 685 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 686 v = get_fpr32(&fpu->fpr[idx], 0); 687 else 688 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); 689 break; 690 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 691 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 692 return -EINVAL; 693 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 694 /* Can't access odd doubles in FR=0 mode */ 695 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 696 return -EINVAL; 697 v = get_fpr64(&fpu->fpr[idx], 0); 698 break; 699 case KVM_REG_MIPS_FCR_IR: 700 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 701 return -EINVAL; 702 v = boot_cpu_data.fpu_id; 703 break; 704 case KVM_REG_MIPS_FCR_CSR: 705 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 706 return -EINVAL; 707 v = fpu->fcr31; 708 break; 709 710 /* MIPS SIMD Architecture (MSA) registers */ 711 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 712 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 713 return -EINVAL; 714 /* Can't access MSA registers in FR=0 mode */ 715 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) 716 return -EINVAL; 717 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 718 #ifdef CONFIG_CPU_LITTLE_ENDIAN 719 /* least significant byte first */ 720 vs[0] = get_fpr64(&fpu->fpr[idx], 0); 721 vs[1] = get_fpr64(&fpu->fpr[idx], 1); 722 #else 723 /* most significant byte first */ 724 vs[0] = get_fpr64(&fpu->fpr[idx], 1); 725 vs[1] = get_fpr64(&fpu->fpr[idx], 0); 726 #endif 727 break; 728 case KVM_REG_MIPS_MSA_IR: 729 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 730 return -EINVAL; 731 v = boot_cpu_data.msa_id; 732 break; 733 case KVM_REG_MIPS_MSA_CSR: 734 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 735 return -EINVAL; 736 v = fpu->msacsr; 737 break; 738 739 /* registers to be handled specially */ 740 default: 741 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); 742 if (ret) 743 return ret; 744 break; 745 } 746 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 747 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 748 749 return put_user(v, uaddr64); 750 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 751 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 752 u32 v32 = (u32)v; 753 754 return put_user(v32, uaddr32); 755 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 756 void __user *uaddr = (void __user *)(long)reg->addr; 757 758 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0; 759 } else { 760 return -EINVAL; 761 } 762 } 763 764 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 765 const struct kvm_one_reg *reg) 766 { 767 struct mips_coproc *cop0 = vcpu->arch.cop0; 768 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 769 s64 v; 770 s64 vs[2]; 771 unsigned int idx; 772 773 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 774 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 775 776 if (get_user(v, uaddr64) != 0) 777 return -EFAULT; 778 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 779 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 780 s32 v32; 781 782 if (get_user(v32, uaddr32) != 0) 783 return -EFAULT; 784 v = (s64)v32; 785 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 786 void __user *uaddr = (void __user *)(long)reg->addr; 787 788 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0; 789 } else { 790 return -EINVAL; 791 } 792 793 switch (reg->id) { 794 /* General purpose registers */ 795 case KVM_REG_MIPS_R0: 796 /* Silently ignore requests to set $0 */ 797 break; 798 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: 799 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; 800 break; 801 #ifndef CONFIG_CPU_MIPSR6 802 case KVM_REG_MIPS_HI: 803 vcpu->arch.hi = v; 804 break; 805 case KVM_REG_MIPS_LO: 806 vcpu->arch.lo = v; 807 break; 808 #endif 809 case KVM_REG_MIPS_PC: 810 vcpu->arch.pc = v; 811 break; 812 813 /* Floating point registers */ 814 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 815 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 816 return -EINVAL; 817 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 818 /* Odd singles in top of even double when FR=0 */ 819 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 820 set_fpr32(&fpu->fpr[idx], 0, v); 821 else 822 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); 823 break; 824 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 825 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 826 return -EINVAL; 827 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 828 /* Can't access odd doubles in FR=0 mode */ 829 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 830 return -EINVAL; 831 set_fpr64(&fpu->fpr[idx], 0, v); 832 break; 833 case KVM_REG_MIPS_FCR_IR: 834 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 835 return -EINVAL; 836 /* Read-only */ 837 break; 838 case KVM_REG_MIPS_FCR_CSR: 839 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 840 return -EINVAL; 841 fpu->fcr31 = v; 842 break; 843 844 /* MIPS SIMD Architecture (MSA) registers */ 845 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 846 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 847 return -EINVAL; 848 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 849 #ifdef CONFIG_CPU_LITTLE_ENDIAN 850 /* least significant byte first */ 851 set_fpr64(&fpu->fpr[idx], 0, vs[0]); 852 set_fpr64(&fpu->fpr[idx], 1, vs[1]); 853 #else 854 /* most significant byte first */ 855 set_fpr64(&fpu->fpr[idx], 1, vs[0]); 856 set_fpr64(&fpu->fpr[idx], 0, vs[1]); 857 #endif 858 break; 859 case KVM_REG_MIPS_MSA_IR: 860 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 861 return -EINVAL; 862 /* Read-only */ 863 break; 864 case KVM_REG_MIPS_MSA_CSR: 865 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 866 return -EINVAL; 867 fpu->msacsr = v; 868 break; 869 870 /* registers to be handled specially */ 871 default: 872 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); 873 } 874 return 0; 875 } 876 877 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 878 struct kvm_enable_cap *cap) 879 { 880 int r = 0; 881 882 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) 883 return -EINVAL; 884 if (cap->flags) 885 return -EINVAL; 886 if (cap->args[0]) 887 return -EINVAL; 888 889 switch (cap->cap) { 890 case KVM_CAP_MIPS_FPU: 891 vcpu->arch.fpu_enabled = true; 892 break; 893 case KVM_CAP_MIPS_MSA: 894 vcpu->arch.msa_enabled = true; 895 break; 896 default: 897 r = -EINVAL; 898 break; 899 } 900 901 return r; 902 } 903 904 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl, 905 unsigned long arg) 906 { 907 struct kvm_vcpu *vcpu = filp->private_data; 908 void __user *argp = (void __user *)arg; 909 910 if (ioctl == KVM_INTERRUPT) { 911 struct kvm_mips_interrupt irq; 912 913 if (copy_from_user(&irq, argp, sizeof(irq))) 914 return -EFAULT; 915 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, 916 irq.irq); 917 918 return kvm_vcpu_ioctl_interrupt(vcpu, &irq); 919 } 920 921 return -ENOIOCTLCMD; 922 } 923 924 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, 925 unsigned long arg) 926 { 927 struct kvm_vcpu *vcpu = filp->private_data; 928 void __user *argp = (void __user *)arg; 929 long r; 930 931 vcpu_load(vcpu); 932 933 switch (ioctl) { 934 case KVM_SET_ONE_REG: 935 case KVM_GET_ONE_REG: { 936 struct kvm_one_reg reg; 937 938 r = -EFAULT; 939 if (copy_from_user(®, argp, sizeof(reg))) 940 break; 941 if (ioctl == KVM_SET_ONE_REG) 942 r = kvm_mips_set_reg(vcpu, ®); 943 else 944 r = kvm_mips_get_reg(vcpu, ®); 945 break; 946 } 947 case KVM_GET_REG_LIST: { 948 struct kvm_reg_list __user *user_list = argp; 949 struct kvm_reg_list reg_list; 950 unsigned n; 951 952 r = -EFAULT; 953 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 954 break; 955 n = reg_list.n; 956 reg_list.n = kvm_mips_num_regs(vcpu); 957 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 958 break; 959 r = -E2BIG; 960 if (n < reg_list.n) 961 break; 962 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg); 963 break; 964 } 965 case KVM_ENABLE_CAP: { 966 struct kvm_enable_cap cap; 967 968 r = -EFAULT; 969 if (copy_from_user(&cap, argp, sizeof(cap))) 970 break; 971 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 972 break; 973 } 974 default: 975 r = -ENOIOCTLCMD; 976 } 977 978 vcpu_put(vcpu); 979 return r; 980 } 981 982 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 983 { 984 985 } 986 987 int kvm_arch_flush_remote_tlb(struct kvm *kvm) 988 { 989 kvm_mips_callbacks->prepare_flush_shadow(kvm); 990 return 1; 991 } 992 993 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, 994 const struct kvm_memory_slot *memslot) 995 { 996 kvm_flush_remote_tlbs(kvm); 997 } 998 999 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 1000 { 1001 long r; 1002 1003 switch (ioctl) { 1004 default: 1005 r = -ENOIOCTLCMD; 1006 } 1007 1008 return r; 1009 } 1010 1011 int kvm_arch_init(void *opaque) 1012 { 1013 if (kvm_mips_callbacks) { 1014 kvm_err("kvm: module already exists\n"); 1015 return -EEXIST; 1016 } 1017 1018 return kvm_mips_emulation_init(&kvm_mips_callbacks); 1019 } 1020 1021 void kvm_arch_exit(void) 1022 { 1023 kvm_mips_callbacks = NULL; 1024 } 1025 1026 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 1027 struct kvm_sregs *sregs) 1028 { 1029 return -ENOIOCTLCMD; 1030 } 1031 1032 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 1033 struct kvm_sregs *sregs) 1034 { 1035 return -ENOIOCTLCMD; 1036 } 1037 1038 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 1039 { 1040 } 1041 1042 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1043 { 1044 return -ENOIOCTLCMD; 1045 } 1046 1047 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1048 { 1049 return -ENOIOCTLCMD; 1050 } 1051 1052 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 1053 { 1054 return VM_FAULT_SIGBUS; 1055 } 1056 1057 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 1058 { 1059 int r; 1060 1061 switch (ext) { 1062 case KVM_CAP_ONE_REG: 1063 case KVM_CAP_ENABLE_CAP: 1064 case KVM_CAP_READONLY_MEM: 1065 case KVM_CAP_SYNC_MMU: 1066 case KVM_CAP_IMMEDIATE_EXIT: 1067 r = 1; 1068 break; 1069 case KVM_CAP_NR_VCPUS: 1070 r = num_online_cpus(); 1071 break; 1072 case KVM_CAP_MAX_VCPUS: 1073 r = KVM_MAX_VCPUS; 1074 break; 1075 case KVM_CAP_MAX_VCPU_ID: 1076 r = KVM_MAX_VCPU_ID; 1077 break; 1078 case KVM_CAP_MIPS_FPU: 1079 /* We don't handle systems with inconsistent cpu_has_fpu */ 1080 r = !!raw_cpu_has_fpu; 1081 break; 1082 case KVM_CAP_MIPS_MSA: 1083 /* 1084 * We don't support MSA vector partitioning yet: 1085 * 1) It would require explicit support which can't be tested 1086 * yet due to lack of support in current hardware. 1087 * 2) It extends the state that would need to be saved/restored 1088 * by e.g. QEMU for migration. 1089 * 1090 * When vector partitioning hardware becomes available, support 1091 * could be added by requiring a flag when enabling 1092 * KVM_CAP_MIPS_MSA capability to indicate that userland knows 1093 * to save/restore the appropriate extra state. 1094 */ 1095 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); 1096 break; 1097 default: 1098 r = kvm_mips_callbacks->check_extension(kvm, ext); 1099 break; 1100 } 1101 return r; 1102 } 1103 1104 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 1105 { 1106 return kvm_mips_pending_timer(vcpu) || 1107 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI; 1108 } 1109 1110 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) 1111 { 1112 int i; 1113 struct mips_coproc *cop0; 1114 1115 if (!vcpu) 1116 return -1; 1117 1118 kvm_debug("VCPU Register Dump:\n"); 1119 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); 1120 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); 1121 1122 for (i = 0; i < 32; i += 4) { 1123 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, 1124 vcpu->arch.gprs[i], 1125 vcpu->arch.gprs[i + 1], 1126 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); 1127 } 1128 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); 1129 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); 1130 1131 cop0 = vcpu->arch.cop0; 1132 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n", 1133 kvm_read_c0_guest_status(cop0), 1134 kvm_read_c0_guest_cause(cop0)); 1135 1136 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); 1137 1138 return 0; 1139 } 1140 1141 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1142 { 1143 int i; 1144 1145 vcpu_load(vcpu); 1146 1147 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1148 vcpu->arch.gprs[i] = regs->gpr[i]; 1149 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ 1150 vcpu->arch.hi = regs->hi; 1151 vcpu->arch.lo = regs->lo; 1152 vcpu->arch.pc = regs->pc; 1153 1154 vcpu_put(vcpu); 1155 return 0; 1156 } 1157 1158 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1159 { 1160 int i; 1161 1162 vcpu_load(vcpu); 1163 1164 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1165 regs->gpr[i] = vcpu->arch.gprs[i]; 1166 1167 regs->hi = vcpu->arch.hi; 1168 regs->lo = vcpu->arch.lo; 1169 regs->pc = vcpu->arch.pc; 1170 1171 vcpu_put(vcpu); 1172 return 0; 1173 } 1174 1175 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 1176 struct kvm_translation *tr) 1177 { 1178 return 0; 1179 } 1180 1181 static void kvm_mips_set_c0_status(void) 1182 { 1183 u32 status = read_c0_status(); 1184 1185 if (cpu_has_dsp) 1186 status |= (ST0_MX); 1187 1188 write_c0_status(status); 1189 ehb(); 1190 } 1191 1192 /* 1193 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) 1194 */ 1195 int kvm_mips_handle_exit(struct kvm_vcpu *vcpu) 1196 { 1197 struct kvm_run *run = vcpu->run; 1198 u32 cause = vcpu->arch.host_cp0_cause; 1199 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; 1200 u32 __user *opc = (u32 __user *) vcpu->arch.pc; 1201 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; 1202 enum emulation_result er = EMULATE_DONE; 1203 u32 inst; 1204 int ret = RESUME_GUEST; 1205 1206 vcpu->mode = OUTSIDE_GUEST_MODE; 1207 1208 /* Set a default exit reason */ 1209 run->exit_reason = KVM_EXIT_UNKNOWN; 1210 run->ready_for_interrupt_injection = 1; 1211 1212 /* 1213 * Set the appropriate status bits based on host CPU features, 1214 * before we hit the scheduler 1215 */ 1216 kvm_mips_set_c0_status(); 1217 1218 local_irq_enable(); 1219 1220 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", 1221 cause, opc, run, vcpu); 1222 trace_kvm_exit(vcpu, exccode); 1223 1224 switch (exccode) { 1225 case EXCCODE_INT: 1226 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc); 1227 1228 ++vcpu->stat.int_exits; 1229 1230 if (need_resched()) 1231 cond_resched(); 1232 1233 ret = RESUME_GUEST; 1234 break; 1235 1236 case EXCCODE_CPU: 1237 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc); 1238 1239 ++vcpu->stat.cop_unusable_exits; 1240 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); 1241 /* XXXKYMA: Might need to return to user space */ 1242 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) 1243 ret = RESUME_HOST; 1244 break; 1245 1246 case EXCCODE_MOD: 1247 ++vcpu->stat.tlbmod_exits; 1248 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); 1249 break; 1250 1251 case EXCCODE_TLBS: 1252 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n", 1253 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, 1254 badvaddr); 1255 1256 ++vcpu->stat.tlbmiss_st_exits; 1257 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); 1258 break; 1259 1260 case EXCCODE_TLBL: 1261 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", 1262 cause, opc, badvaddr); 1263 1264 ++vcpu->stat.tlbmiss_ld_exits; 1265 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); 1266 break; 1267 1268 case EXCCODE_ADES: 1269 ++vcpu->stat.addrerr_st_exits; 1270 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); 1271 break; 1272 1273 case EXCCODE_ADEL: 1274 ++vcpu->stat.addrerr_ld_exits; 1275 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); 1276 break; 1277 1278 case EXCCODE_SYS: 1279 ++vcpu->stat.syscall_exits; 1280 ret = kvm_mips_callbacks->handle_syscall(vcpu); 1281 break; 1282 1283 case EXCCODE_RI: 1284 ++vcpu->stat.resvd_inst_exits; 1285 ret = kvm_mips_callbacks->handle_res_inst(vcpu); 1286 break; 1287 1288 case EXCCODE_BP: 1289 ++vcpu->stat.break_inst_exits; 1290 ret = kvm_mips_callbacks->handle_break(vcpu); 1291 break; 1292 1293 case EXCCODE_TR: 1294 ++vcpu->stat.trap_inst_exits; 1295 ret = kvm_mips_callbacks->handle_trap(vcpu); 1296 break; 1297 1298 case EXCCODE_MSAFPE: 1299 ++vcpu->stat.msa_fpe_exits; 1300 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); 1301 break; 1302 1303 case EXCCODE_FPE: 1304 ++vcpu->stat.fpe_exits; 1305 ret = kvm_mips_callbacks->handle_fpe(vcpu); 1306 break; 1307 1308 case EXCCODE_MSADIS: 1309 ++vcpu->stat.msa_disabled_exits; 1310 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); 1311 break; 1312 1313 case EXCCODE_GE: 1314 /* defer exit accounting to handler */ 1315 ret = kvm_mips_callbacks->handle_guest_exit(vcpu); 1316 break; 1317 1318 default: 1319 if (cause & CAUSEF_BD) 1320 opc += 1; 1321 inst = 0; 1322 kvm_get_badinstr(opc, vcpu, &inst); 1323 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n", 1324 exccode, opc, inst, badvaddr, 1325 kvm_read_c0_guest_status(vcpu->arch.cop0)); 1326 kvm_arch_vcpu_dump_regs(vcpu); 1327 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1328 ret = RESUME_HOST; 1329 break; 1330 1331 } 1332 1333 local_irq_disable(); 1334 1335 if (ret == RESUME_GUEST) 1336 kvm_vz_acquire_htimer(vcpu); 1337 1338 if (er == EMULATE_DONE && !(ret & RESUME_HOST)) 1339 kvm_mips_deliver_interrupts(vcpu, cause); 1340 1341 if (!(ret & RESUME_HOST)) { 1342 /* Only check for signals if not already exiting to userspace */ 1343 if (signal_pending(current)) { 1344 run->exit_reason = KVM_EXIT_INTR; 1345 ret = (-EINTR << 2) | RESUME_HOST; 1346 ++vcpu->stat.signal_exits; 1347 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL); 1348 } 1349 } 1350 1351 if (ret == RESUME_GUEST) { 1352 trace_kvm_reenter(vcpu); 1353 1354 /* 1355 * Make sure the read of VCPU requests in vcpu_reenter() 1356 * callback is not reordered ahead of the write to vcpu->mode, 1357 * or we could miss a TLB flush request while the requester sees 1358 * the VCPU as outside of guest mode and not needing an IPI. 1359 */ 1360 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 1361 1362 kvm_mips_callbacks->vcpu_reenter(vcpu); 1363 1364 /* 1365 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context 1366 * is live), restore FCR31 / MSACSR. 1367 * 1368 * This should be before returning to the guest exception 1369 * vector, as it may well cause an [MSA] FP exception if there 1370 * are pending exception bits unmasked. (see 1371 * kvm_mips_csr_die_notifier() for how that is handled). 1372 */ 1373 if (kvm_mips_guest_has_fpu(&vcpu->arch) && 1374 read_c0_status() & ST0_CU1) 1375 __kvm_restore_fcsr(&vcpu->arch); 1376 1377 if (kvm_mips_guest_has_msa(&vcpu->arch) && 1378 read_c0_config5() & MIPS_CONF5_MSAEN) 1379 __kvm_restore_msacsr(&vcpu->arch); 1380 } 1381 return ret; 1382 } 1383 1384 /* Enable FPU for guest and restore context */ 1385 void kvm_own_fpu(struct kvm_vcpu *vcpu) 1386 { 1387 struct mips_coproc *cop0 = vcpu->arch.cop0; 1388 unsigned int sr, cfg5; 1389 1390 preempt_disable(); 1391 1392 sr = kvm_read_c0_guest_status(cop0); 1393 1394 /* 1395 * If MSA state is already live, it is undefined how it interacts with 1396 * FR=0 FPU state, and we don't want to hit reserved instruction 1397 * exceptions trying to save the MSA state later when CU=1 && FR=1, so 1398 * play it safe and save it first. 1399 */ 1400 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && 1401 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) 1402 kvm_lose_fpu(vcpu); 1403 1404 /* 1405 * Enable FPU for guest 1406 * We set FR and FRE according to guest context 1407 */ 1408 change_c0_status(ST0_CU1 | ST0_FR, sr); 1409 if (cpu_has_fre) { 1410 cfg5 = kvm_read_c0_guest_config5(cop0); 1411 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1412 } 1413 enable_fpu_hazard(); 1414 1415 /* If guest FPU state not active, restore it now */ 1416 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) { 1417 __kvm_restore_fpu(&vcpu->arch); 1418 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1419 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU); 1420 } else { 1421 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU); 1422 } 1423 1424 preempt_enable(); 1425 } 1426 1427 #ifdef CONFIG_CPU_HAS_MSA 1428 /* Enable MSA for guest and restore context */ 1429 void kvm_own_msa(struct kvm_vcpu *vcpu) 1430 { 1431 struct mips_coproc *cop0 = vcpu->arch.cop0; 1432 unsigned int sr, cfg5; 1433 1434 preempt_disable(); 1435 1436 /* 1437 * Enable FPU if enabled in guest, since we're restoring FPU context 1438 * anyway. We set FR and FRE according to guest context. 1439 */ 1440 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { 1441 sr = kvm_read_c0_guest_status(cop0); 1442 1443 /* 1444 * If FR=0 FPU state is already live, it is undefined how it 1445 * interacts with MSA state, so play it safe and save it first. 1446 */ 1447 if (!(sr & ST0_FR) && 1448 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | 1449 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU) 1450 kvm_lose_fpu(vcpu); 1451 1452 change_c0_status(ST0_CU1 | ST0_FR, sr); 1453 if (sr & ST0_CU1 && cpu_has_fre) { 1454 cfg5 = kvm_read_c0_guest_config5(cop0); 1455 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1456 } 1457 } 1458 1459 /* Enable MSA for guest */ 1460 set_c0_config5(MIPS_CONF5_MSAEN); 1461 enable_fpu_hazard(); 1462 1463 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) { 1464 case KVM_MIPS_AUX_FPU: 1465 /* 1466 * Guest FPU state already loaded, only restore upper MSA state 1467 */ 1468 __kvm_restore_msa_upper(&vcpu->arch); 1469 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1470 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA); 1471 break; 1472 case 0: 1473 /* Neither FPU or MSA already active, restore full MSA state */ 1474 __kvm_restore_msa(&vcpu->arch); 1475 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1476 if (kvm_mips_guest_has_fpu(&vcpu->arch)) 1477 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1478 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, 1479 KVM_TRACE_AUX_FPU_MSA); 1480 break; 1481 default: 1482 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA); 1483 break; 1484 } 1485 1486 preempt_enable(); 1487 } 1488 #endif 1489 1490 /* Drop FPU & MSA without saving it */ 1491 void kvm_drop_fpu(struct kvm_vcpu *vcpu) 1492 { 1493 preempt_disable(); 1494 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1495 disable_msa(); 1496 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA); 1497 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA; 1498 } 1499 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1500 clear_c0_status(ST0_CU1 | ST0_FR); 1501 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU); 1502 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1503 } 1504 preempt_enable(); 1505 } 1506 1507 /* Save and disable FPU & MSA */ 1508 void kvm_lose_fpu(struct kvm_vcpu *vcpu) 1509 { 1510 /* 1511 * With T&E, FPU & MSA get disabled in root context (hardware) when it 1512 * is disabled in guest context (software), but the register state in 1513 * the hardware may still be in use. 1514 * This is why we explicitly re-enable the hardware before saving. 1515 */ 1516 1517 preempt_disable(); 1518 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1519 __kvm_save_msa(&vcpu->arch); 1520 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA); 1521 1522 /* Disable MSA & FPU */ 1523 disable_msa(); 1524 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1525 clear_c0_status(ST0_CU1 | ST0_FR); 1526 disable_fpu_hazard(); 1527 } 1528 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA); 1529 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1530 __kvm_save_fpu(&vcpu->arch); 1531 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1532 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU); 1533 1534 /* Disable FPU */ 1535 clear_c0_status(ST0_CU1 | ST0_FR); 1536 disable_fpu_hazard(); 1537 } 1538 preempt_enable(); 1539 } 1540 1541 /* 1542 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are 1543 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP 1544 * exception if cause bits are set in the value being written. 1545 */ 1546 static int kvm_mips_csr_die_notify(struct notifier_block *self, 1547 unsigned long cmd, void *ptr) 1548 { 1549 struct die_args *args = (struct die_args *)ptr; 1550 struct pt_regs *regs = args->regs; 1551 unsigned long pc; 1552 1553 /* Only interested in FPE and MSAFPE */ 1554 if (cmd != DIE_FP && cmd != DIE_MSAFP) 1555 return NOTIFY_DONE; 1556 1557 /* Return immediately if guest context isn't active */ 1558 if (!(current->flags & PF_VCPU)) 1559 return NOTIFY_DONE; 1560 1561 /* Should never get here from user mode */ 1562 BUG_ON(user_mode(regs)); 1563 1564 pc = instruction_pointer(regs); 1565 switch (cmd) { 1566 case DIE_FP: 1567 /* match 2nd instruction in __kvm_restore_fcsr */ 1568 if (pc != (unsigned long)&__kvm_restore_fcsr + 4) 1569 return NOTIFY_DONE; 1570 break; 1571 case DIE_MSAFP: 1572 /* match 2nd/3rd instruction in __kvm_restore_msacsr */ 1573 if (!cpu_has_msa || 1574 pc < (unsigned long)&__kvm_restore_msacsr + 4 || 1575 pc > (unsigned long)&__kvm_restore_msacsr + 8) 1576 return NOTIFY_DONE; 1577 break; 1578 } 1579 1580 /* Move PC forward a little and continue executing */ 1581 instruction_pointer(regs) += 4; 1582 1583 return NOTIFY_STOP; 1584 } 1585 1586 static struct notifier_block kvm_mips_csr_die_notifier = { 1587 .notifier_call = kvm_mips_csr_die_notify, 1588 }; 1589 1590 static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = { 1591 [MIPS_EXC_INT_TIMER] = C_IRQ5, 1592 [MIPS_EXC_INT_IO_1] = C_IRQ0, 1593 [MIPS_EXC_INT_IPI_1] = C_IRQ1, 1594 [MIPS_EXC_INT_IPI_2] = C_IRQ2, 1595 }; 1596 1597 static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = { 1598 [MIPS_EXC_INT_TIMER] = C_IRQ5, 1599 [MIPS_EXC_INT_IO_1] = C_IRQ0, 1600 [MIPS_EXC_INT_IO_2] = C_IRQ1, 1601 [MIPS_EXC_INT_IPI_1] = C_IRQ4, 1602 }; 1603 1604 u32 *kvm_priority_to_irq = kvm_default_priority_to_irq; 1605 1606 u32 kvm_irq_to_priority(u32 irq) 1607 { 1608 int i; 1609 1610 for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) { 1611 if (kvm_priority_to_irq[i] == (1 << (irq + 8))) 1612 return i; 1613 } 1614 1615 return MIPS_EXC_MAX; 1616 } 1617 1618 static int __init kvm_mips_init(void) 1619 { 1620 int ret; 1621 1622 if (cpu_has_mmid) { 1623 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n"); 1624 return -EOPNOTSUPP; 1625 } 1626 1627 ret = kvm_mips_entry_setup(); 1628 if (ret) 1629 return ret; 1630 1631 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); 1632 1633 if (ret) 1634 return ret; 1635 1636 if (boot_cpu_type() == CPU_LOONGSON64) 1637 kvm_priority_to_irq = kvm_loongson3_priority_to_irq; 1638 1639 register_die_notifier(&kvm_mips_csr_die_notifier); 1640 1641 return 0; 1642 } 1643 1644 static void __exit kvm_mips_exit(void) 1645 { 1646 kvm_exit(); 1647 1648 unregister_die_notifier(&kvm_mips_csr_die_notifier); 1649 } 1650 1651 module_init(kvm_mips_init); 1652 module_exit(kvm_mips_exit); 1653 1654 EXPORT_TRACEPOINT_SYMBOL(kvm_exit); 1655