1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * KVM/MIPS: MIPS specific KVM APIs 7 * 8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 9 * Authors: Sanjay Lal <sanjayl@kymasys.com> 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/errno.h> 14 #include <linux/err.h> 15 #include <linux/kdebug.h> 16 #include <linux/module.h> 17 #include <linux/vmalloc.h> 18 #include <linux/fs.h> 19 #include <linux/bootmem.h> 20 #include <asm/fpu.h> 21 #include <asm/page.h> 22 #include <asm/cacheflush.h> 23 #include <asm/mmu_context.h> 24 #include <asm/pgtable.h> 25 26 #include <linux/kvm_host.h> 27 28 #include "interrupt.h" 29 #include "commpage.h" 30 31 #define CREATE_TRACE_POINTS 32 #include "trace.h" 33 34 #ifndef VECTORSPACING 35 #define VECTORSPACING 0x100 /* for EI/VI mode */ 36 #endif 37 38 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x) 39 struct kvm_stats_debugfs_item debugfs_entries[] = { 40 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU }, 41 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU }, 42 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU }, 43 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU }, 44 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU }, 45 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU }, 46 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU }, 47 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU }, 48 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU }, 49 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU }, 50 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU }, 51 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU }, 52 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU }, 53 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU }, 54 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU }, 55 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU }, 56 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU }, 57 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU }, 58 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU }, 59 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU }, 60 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU }, 61 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU }, 62 {NULL} 63 }; 64 65 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu) 66 { 67 int i; 68 69 for_each_possible_cpu(i) { 70 vcpu->arch.guest_kernel_asid[i] = 0; 71 vcpu->arch.guest_user_asid[i] = 0; 72 } 73 74 return 0; 75 } 76 77 /* 78 * XXXKYMA: We are simulatoring a processor that has the WII bit set in 79 * Config7, so we are "runnable" if interrupts are pending 80 */ 81 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 82 { 83 return !!(vcpu->arch.pending_exceptions); 84 } 85 86 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 87 { 88 return 1; 89 } 90 91 int kvm_arch_hardware_enable(void) 92 { 93 return 0; 94 } 95 96 int kvm_arch_hardware_setup(void) 97 { 98 return 0; 99 } 100 101 void kvm_arch_check_processor_compat(void *rtn) 102 { 103 *(int *)rtn = 0; 104 } 105 106 static void kvm_mips_init_tlbs(struct kvm *kvm) 107 { 108 unsigned long wired; 109 110 /* 111 * Add a wired entry to the TLB, it is used to map the commpage to 112 * the Guest kernel 113 */ 114 wired = read_c0_wired(); 115 write_c0_wired(wired + 1); 116 mtc0_tlbw_hazard(); 117 kvm->arch.commpage_tlb = wired; 118 119 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(), 120 kvm->arch.commpage_tlb); 121 } 122 123 static void kvm_mips_init_vm_percpu(void *arg) 124 { 125 struct kvm *kvm = (struct kvm *)arg; 126 127 kvm_mips_init_tlbs(kvm); 128 kvm_mips_callbacks->vm_init(kvm); 129 130 } 131 132 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 133 { 134 if (atomic_inc_return(&kvm_mips_instance) == 1) { 135 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n", 136 __func__); 137 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1); 138 } 139 140 return 0; 141 } 142 143 void kvm_mips_free_vcpus(struct kvm *kvm) 144 { 145 unsigned int i; 146 struct kvm_vcpu *vcpu; 147 148 /* Put the pages we reserved for the guest pmap */ 149 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) { 150 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE) 151 kvm_release_pfn_clean(kvm->arch.guest_pmap[i]); 152 } 153 kfree(kvm->arch.guest_pmap); 154 155 kvm_for_each_vcpu(i, vcpu, kvm) { 156 kvm_arch_vcpu_free(vcpu); 157 } 158 159 mutex_lock(&kvm->lock); 160 161 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 162 kvm->vcpus[i] = NULL; 163 164 atomic_set(&kvm->online_vcpus, 0); 165 166 mutex_unlock(&kvm->lock); 167 } 168 169 static void kvm_mips_uninit_tlbs(void *arg) 170 { 171 /* Restore wired count */ 172 write_c0_wired(0); 173 mtc0_tlbw_hazard(); 174 /* Clear out all the TLBs */ 175 kvm_local_flush_tlb_all(); 176 } 177 178 void kvm_arch_destroy_vm(struct kvm *kvm) 179 { 180 kvm_mips_free_vcpus(kvm); 181 182 /* If this is the last instance, restore wired count */ 183 if (atomic_dec_return(&kvm_mips_instance) == 0) { 184 kvm_debug("%s: last KVM instance, restoring TLB parameters\n", 185 __func__); 186 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1); 187 } 188 } 189 190 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, 191 unsigned long arg) 192 { 193 return -ENOIOCTLCMD; 194 } 195 196 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 197 unsigned long npages) 198 { 199 return 0; 200 } 201 202 int kvm_arch_prepare_memory_region(struct kvm *kvm, 203 struct kvm_memory_slot *memslot, 204 const struct kvm_userspace_memory_region *mem, 205 enum kvm_mr_change change) 206 { 207 return 0; 208 } 209 210 void kvm_arch_commit_memory_region(struct kvm *kvm, 211 const struct kvm_userspace_memory_region *mem, 212 const struct kvm_memory_slot *old, 213 const struct kvm_memory_slot *new, 214 enum kvm_mr_change change) 215 { 216 unsigned long npages = 0; 217 int i; 218 219 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n", 220 __func__, kvm, mem->slot, mem->guest_phys_addr, 221 mem->memory_size, mem->userspace_addr); 222 223 /* Setup Guest PMAP table */ 224 if (!kvm->arch.guest_pmap) { 225 if (mem->slot == 0) 226 npages = mem->memory_size >> PAGE_SHIFT; 227 228 if (npages) { 229 kvm->arch.guest_pmap_npages = npages; 230 kvm->arch.guest_pmap = 231 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL); 232 233 if (!kvm->arch.guest_pmap) { 234 kvm_err("Failed to allocate guest PMAP\n"); 235 return; 236 } 237 238 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n", 239 npages, kvm->arch.guest_pmap); 240 241 /* Now setup the page table */ 242 for (i = 0; i < npages; i++) 243 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE; 244 } 245 } 246 } 247 248 static inline void dump_handler(const char *symbol, void *start, void *end) 249 { 250 u32 *p; 251 252 pr_debug("LEAF(%s)\n", symbol); 253 254 pr_debug("\t.set push\n"); 255 pr_debug("\t.set noreorder\n"); 256 257 for (p = start; p < (u32 *)end; ++p) 258 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p); 259 260 pr_debug("\t.set\tpop\n"); 261 262 pr_debug("\tEND(%s)\n", symbol); 263 } 264 265 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) 266 { 267 int err, size; 268 void *gebase, *p, *handler; 269 int i; 270 271 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL); 272 273 if (!vcpu) { 274 err = -ENOMEM; 275 goto out; 276 } 277 278 err = kvm_vcpu_init(vcpu, kvm, id); 279 280 if (err) 281 goto out_free_cpu; 282 283 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu); 284 285 /* 286 * Allocate space for host mode exception handlers that handle 287 * guest mode exits 288 */ 289 if (cpu_has_veic || cpu_has_vint) 290 size = 0x200 + VECTORSPACING * 64; 291 else 292 size = 0x4000; 293 294 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); 295 296 if (!gebase) { 297 err = -ENOMEM; 298 goto out_uninit_cpu; 299 } 300 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", 301 ALIGN(size, PAGE_SIZE), gebase); 302 303 /* 304 * Check new ebase actually fits in CP0_EBase. The lack of a write gate 305 * limits us to the low 512MB of physical address space. If the memory 306 * we allocate is out of range, just give up now. 307 */ 308 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) { 309 kvm_err("CP0_EBase.WG required for guest exception base %pK\n", 310 gebase); 311 err = -ENOMEM; 312 goto out_free_gebase; 313 } 314 315 /* Save new ebase */ 316 vcpu->arch.guest_ebase = gebase; 317 318 /* Build guest exception vectors dynamically in unmapped memory */ 319 handler = gebase + 0x2000; 320 321 /* TLB Refill, EXL = 0 */ 322 kvm_mips_build_exception(gebase, handler); 323 324 /* General Exception Entry point */ 325 kvm_mips_build_exception(gebase + 0x180, handler); 326 327 /* For vectored interrupts poke the exception code @ all offsets 0-7 */ 328 for (i = 0; i < 8; i++) { 329 kvm_debug("L1 Vectored handler @ %p\n", 330 gebase + 0x200 + (i * VECTORSPACING)); 331 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING, 332 handler); 333 } 334 335 /* General exit handler */ 336 p = handler; 337 p = kvm_mips_build_exit(p); 338 339 /* Guest entry routine */ 340 vcpu->arch.vcpu_run = p; 341 p = kvm_mips_build_vcpu_run(p); 342 343 /* Dump the generated code */ 344 pr_debug("#include <asm/asm.h>\n"); 345 pr_debug("#include <asm/regdef.h>\n"); 346 pr_debug("\n"); 347 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p); 348 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200); 349 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run); 350 351 /* Invalidate the icache for these ranges */ 352 local_flush_icache_range((unsigned long)gebase, 353 (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); 354 355 /* 356 * Allocate comm page for guest kernel, a TLB will be reserved for 357 * mapping GVA @ 0xFFFF8000 to this page 358 */ 359 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL); 360 361 if (!vcpu->arch.kseg0_commpage) { 362 err = -ENOMEM; 363 goto out_free_gebase; 364 } 365 366 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage); 367 kvm_mips_commpage_init(vcpu); 368 369 /* Init */ 370 vcpu->arch.last_sched_cpu = -1; 371 372 /* Start off the timer */ 373 kvm_mips_init_count(vcpu); 374 375 return vcpu; 376 377 out_free_gebase: 378 kfree(gebase); 379 380 out_uninit_cpu: 381 kvm_vcpu_uninit(vcpu); 382 383 out_free_cpu: 384 kfree(vcpu); 385 386 out: 387 return ERR_PTR(err); 388 } 389 390 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 391 { 392 hrtimer_cancel(&vcpu->arch.comparecount_timer); 393 394 kvm_vcpu_uninit(vcpu); 395 396 kvm_mips_dump_stats(vcpu); 397 398 kfree(vcpu->arch.guest_ebase); 399 kfree(vcpu->arch.kseg0_commpage); 400 kfree(vcpu); 401 } 402 403 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 404 { 405 kvm_arch_vcpu_free(vcpu); 406 } 407 408 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 409 struct kvm_guest_debug *dbg) 410 { 411 return -ENOIOCTLCMD; 412 } 413 414 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) 415 { 416 int r = 0; 417 sigset_t sigsaved; 418 419 if (vcpu->sigset_active) 420 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 421 422 if (vcpu->mmio_needed) { 423 if (!vcpu->mmio_is_write) 424 kvm_mips_complete_mmio_load(vcpu, run); 425 vcpu->mmio_needed = 0; 426 } 427 428 lose_fpu(1); 429 430 local_irq_disable(); 431 /* Check if we have any exceptions/interrupts pending */ 432 kvm_mips_deliver_interrupts(vcpu, 433 kvm_read_c0_guest_cause(vcpu->arch.cop0)); 434 435 guest_enter_irqoff(); 436 437 /* Disable hardware page table walking while in guest */ 438 htw_stop(); 439 440 trace_kvm_enter(vcpu); 441 r = vcpu->arch.vcpu_run(run, vcpu); 442 trace_kvm_out(vcpu); 443 444 /* Re-enable HTW before enabling interrupts */ 445 htw_start(); 446 447 guest_exit_irqoff(); 448 local_irq_enable(); 449 450 if (vcpu->sigset_active) 451 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 452 453 return r; 454 } 455 456 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 457 struct kvm_mips_interrupt *irq) 458 { 459 int intr = (int)irq->irq; 460 struct kvm_vcpu *dvcpu = NULL; 461 462 if (intr == 3 || intr == -3 || intr == 4 || intr == -4) 463 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, 464 (int)intr); 465 466 if (irq->cpu == -1) 467 dvcpu = vcpu; 468 else 469 dvcpu = vcpu->kvm->vcpus[irq->cpu]; 470 471 if (intr == 2 || intr == 3 || intr == 4) { 472 kvm_mips_callbacks->queue_io_int(dvcpu, irq); 473 474 } else if (intr == -2 || intr == -3 || intr == -4) { 475 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); 476 } else { 477 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, 478 irq->cpu, irq->irq); 479 return -EINVAL; 480 } 481 482 dvcpu->arch.wait = 0; 483 484 if (swait_active(&dvcpu->wq)) 485 swake_up(&dvcpu->wq); 486 487 return 0; 488 } 489 490 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 491 struct kvm_mp_state *mp_state) 492 { 493 return -ENOIOCTLCMD; 494 } 495 496 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 497 struct kvm_mp_state *mp_state) 498 { 499 return -ENOIOCTLCMD; 500 } 501 502 static u64 kvm_mips_get_one_regs[] = { 503 KVM_REG_MIPS_R0, 504 KVM_REG_MIPS_R1, 505 KVM_REG_MIPS_R2, 506 KVM_REG_MIPS_R3, 507 KVM_REG_MIPS_R4, 508 KVM_REG_MIPS_R5, 509 KVM_REG_MIPS_R6, 510 KVM_REG_MIPS_R7, 511 KVM_REG_MIPS_R8, 512 KVM_REG_MIPS_R9, 513 KVM_REG_MIPS_R10, 514 KVM_REG_MIPS_R11, 515 KVM_REG_MIPS_R12, 516 KVM_REG_MIPS_R13, 517 KVM_REG_MIPS_R14, 518 KVM_REG_MIPS_R15, 519 KVM_REG_MIPS_R16, 520 KVM_REG_MIPS_R17, 521 KVM_REG_MIPS_R18, 522 KVM_REG_MIPS_R19, 523 KVM_REG_MIPS_R20, 524 KVM_REG_MIPS_R21, 525 KVM_REG_MIPS_R22, 526 KVM_REG_MIPS_R23, 527 KVM_REG_MIPS_R24, 528 KVM_REG_MIPS_R25, 529 KVM_REG_MIPS_R26, 530 KVM_REG_MIPS_R27, 531 KVM_REG_MIPS_R28, 532 KVM_REG_MIPS_R29, 533 KVM_REG_MIPS_R30, 534 KVM_REG_MIPS_R31, 535 536 #ifndef CONFIG_CPU_MIPSR6 537 KVM_REG_MIPS_HI, 538 KVM_REG_MIPS_LO, 539 #endif 540 KVM_REG_MIPS_PC, 541 542 KVM_REG_MIPS_CP0_INDEX, 543 KVM_REG_MIPS_CP0_CONTEXT, 544 KVM_REG_MIPS_CP0_USERLOCAL, 545 KVM_REG_MIPS_CP0_PAGEMASK, 546 KVM_REG_MIPS_CP0_WIRED, 547 KVM_REG_MIPS_CP0_HWRENA, 548 KVM_REG_MIPS_CP0_BADVADDR, 549 KVM_REG_MIPS_CP0_COUNT, 550 KVM_REG_MIPS_CP0_ENTRYHI, 551 KVM_REG_MIPS_CP0_COMPARE, 552 KVM_REG_MIPS_CP0_STATUS, 553 KVM_REG_MIPS_CP0_CAUSE, 554 KVM_REG_MIPS_CP0_EPC, 555 KVM_REG_MIPS_CP0_PRID, 556 KVM_REG_MIPS_CP0_CONFIG, 557 KVM_REG_MIPS_CP0_CONFIG1, 558 KVM_REG_MIPS_CP0_CONFIG2, 559 KVM_REG_MIPS_CP0_CONFIG3, 560 KVM_REG_MIPS_CP0_CONFIG4, 561 KVM_REG_MIPS_CP0_CONFIG5, 562 KVM_REG_MIPS_CP0_CONFIG7, 563 KVM_REG_MIPS_CP0_ERROREPC, 564 565 KVM_REG_MIPS_COUNT_CTL, 566 KVM_REG_MIPS_COUNT_RESUME, 567 KVM_REG_MIPS_COUNT_HZ, 568 }; 569 570 static u64 kvm_mips_get_one_regs_fpu[] = { 571 KVM_REG_MIPS_FCR_IR, 572 KVM_REG_MIPS_FCR_CSR, 573 }; 574 575 static u64 kvm_mips_get_one_regs_msa[] = { 576 KVM_REG_MIPS_MSA_IR, 577 KVM_REG_MIPS_MSA_CSR, 578 }; 579 580 static u64 kvm_mips_get_one_regs_kscratch[] = { 581 KVM_REG_MIPS_CP0_KSCRATCH1, 582 KVM_REG_MIPS_CP0_KSCRATCH2, 583 KVM_REG_MIPS_CP0_KSCRATCH3, 584 KVM_REG_MIPS_CP0_KSCRATCH4, 585 KVM_REG_MIPS_CP0_KSCRATCH5, 586 KVM_REG_MIPS_CP0_KSCRATCH6, 587 }; 588 589 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu) 590 { 591 unsigned long ret; 592 593 ret = ARRAY_SIZE(kvm_mips_get_one_regs); 594 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 595 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48; 596 /* odd doubles */ 597 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64) 598 ret += 16; 599 } 600 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) 601 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32; 602 ret += __arch_hweight8(vcpu->arch.kscratch_enabled); 603 ret += kvm_mips_callbacks->num_regs(vcpu); 604 605 return ret; 606 } 607 608 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) 609 { 610 u64 index; 611 unsigned int i; 612 613 if (copy_to_user(indices, kvm_mips_get_one_regs, 614 sizeof(kvm_mips_get_one_regs))) 615 return -EFAULT; 616 indices += ARRAY_SIZE(kvm_mips_get_one_regs); 617 618 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 619 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu, 620 sizeof(kvm_mips_get_one_regs_fpu))) 621 return -EFAULT; 622 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu); 623 624 for (i = 0; i < 32; ++i) { 625 index = KVM_REG_MIPS_FPR_32(i); 626 if (copy_to_user(indices, &index, sizeof(index))) 627 return -EFAULT; 628 ++indices; 629 630 /* skip odd doubles if no F64 */ 631 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64)) 632 continue; 633 634 index = KVM_REG_MIPS_FPR_64(i); 635 if (copy_to_user(indices, &index, sizeof(index))) 636 return -EFAULT; 637 ++indices; 638 } 639 } 640 641 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) { 642 if (copy_to_user(indices, kvm_mips_get_one_regs_msa, 643 sizeof(kvm_mips_get_one_regs_msa))) 644 return -EFAULT; 645 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa); 646 647 for (i = 0; i < 32; ++i) { 648 index = KVM_REG_MIPS_VEC_128(i); 649 if (copy_to_user(indices, &index, sizeof(index))) 650 return -EFAULT; 651 ++indices; 652 } 653 } 654 655 for (i = 0; i < 6; ++i) { 656 if (!(vcpu->arch.kscratch_enabled & BIT(i + 2))) 657 continue; 658 659 if (copy_to_user(indices, &kvm_mips_get_one_regs_kscratch[i], 660 sizeof(kvm_mips_get_one_regs_kscratch[i]))) 661 return -EFAULT; 662 ++indices; 663 } 664 665 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices); 666 } 667 668 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 669 const struct kvm_one_reg *reg) 670 { 671 struct mips_coproc *cop0 = vcpu->arch.cop0; 672 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 673 int ret; 674 s64 v; 675 s64 vs[2]; 676 unsigned int idx; 677 678 switch (reg->id) { 679 /* General purpose registers */ 680 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: 681 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; 682 break; 683 #ifndef CONFIG_CPU_MIPSR6 684 case KVM_REG_MIPS_HI: 685 v = (long)vcpu->arch.hi; 686 break; 687 case KVM_REG_MIPS_LO: 688 v = (long)vcpu->arch.lo; 689 break; 690 #endif 691 case KVM_REG_MIPS_PC: 692 v = (long)vcpu->arch.pc; 693 break; 694 695 /* Floating point registers */ 696 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 697 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 698 return -EINVAL; 699 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 700 /* Odd singles in top of even double when FR=0 */ 701 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 702 v = get_fpr32(&fpu->fpr[idx], 0); 703 else 704 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); 705 break; 706 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 707 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 708 return -EINVAL; 709 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 710 /* Can't access odd doubles in FR=0 mode */ 711 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 712 return -EINVAL; 713 v = get_fpr64(&fpu->fpr[idx], 0); 714 break; 715 case KVM_REG_MIPS_FCR_IR: 716 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 717 return -EINVAL; 718 v = boot_cpu_data.fpu_id; 719 break; 720 case KVM_REG_MIPS_FCR_CSR: 721 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 722 return -EINVAL; 723 v = fpu->fcr31; 724 break; 725 726 /* MIPS SIMD Architecture (MSA) registers */ 727 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 728 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 729 return -EINVAL; 730 /* Can't access MSA registers in FR=0 mode */ 731 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) 732 return -EINVAL; 733 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 734 #ifdef CONFIG_CPU_LITTLE_ENDIAN 735 /* least significant byte first */ 736 vs[0] = get_fpr64(&fpu->fpr[idx], 0); 737 vs[1] = get_fpr64(&fpu->fpr[idx], 1); 738 #else 739 /* most significant byte first */ 740 vs[0] = get_fpr64(&fpu->fpr[idx], 1); 741 vs[1] = get_fpr64(&fpu->fpr[idx], 0); 742 #endif 743 break; 744 case KVM_REG_MIPS_MSA_IR: 745 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 746 return -EINVAL; 747 v = boot_cpu_data.msa_id; 748 break; 749 case KVM_REG_MIPS_MSA_CSR: 750 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 751 return -EINVAL; 752 v = fpu->msacsr; 753 break; 754 755 /* Co-processor 0 registers */ 756 case KVM_REG_MIPS_CP0_INDEX: 757 v = (long)kvm_read_c0_guest_index(cop0); 758 break; 759 case KVM_REG_MIPS_CP0_CONTEXT: 760 v = (long)kvm_read_c0_guest_context(cop0); 761 break; 762 case KVM_REG_MIPS_CP0_USERLOCAL: 763 v = (long)kvm_read_c0_guest_userlocal(cop0); 764 break; 765 case KVM_REG_MIPS_CP0_PAGEMASK: 766 v = (long)kvm_read_c0_guest_pagemask(cop0); 767 break; 768 case KVM_REG_MIPS_CP0_WIRED: 769 v = (long)kvm_read_c0_guest_wired(cop0); 770 break; 771 case KVM_REG_MIPS_CP0_HWRENA: 772 v = (long)kvm_read_c0_guest_hwrena(cop0); 773 break; 774 case KVM_REG_MIPS_CP0_BADVADDR: 775 v = (long)kvm_read_c0_guest_badvaddr(cop0); 776 break; 777 case KVM_REG_MIPS_CP0_ENTRYHI: 778 v = (long)kvm_read_c0_guest_entryhi(cop0); 779 break; 780 case KVM_REG_MIPS_CP0_COMPARE: 781 v = (long)kvm_read_c0_guest_compare(cop0); 782 break; 783 case KVM_REG_MIPS_CP0_STATUS: 784 v = (long)kvm_read_c0_guest_status(cop0); 785 break; 786 case KVM_REG_MIPS_CP0_CAUSE: 787 v = (long)kvm_read_c0_guest_cause(cop0); 788 break; 789 case KVM_REG_MIPS_CP0_EPC: 790 v = (long)kvm_read_c0_guest_epc(cop0); 791 break; 792 case KVM_REG_MIPS_CP0_PRID: 793 v = (long)kvm_read_c0_guest_prid(cop0); 794 break; 795 case KVM_REG_MIPS_CP0_CONFIG: 796 v = (long)kvm_read_c0_guest_config(cop0); 797 break; 798 case KVM_REG_MIPS_CP0_CONFIG1: 799 v = (long)kvm_read_c0_guest_config1(cop0); 800 break; 801 case KVM_REG_MIPS_CP0_CONFIG2: 802 v = (long)kvm_read_c0_guest_config2(cop0); 803 break; 804 case KVM_REG_MIPS_CP0_CONFIG3: 805 v = (long)kvm_read_c0_guest_config3(cop0); 806 break; 807 case KVM_REG_MIPS_CP0_CONFIG4: 808 v = (long)kvm_read_c0_guest_config4(cop0); 809 break; 810 case KVM_REG_MIPS_CP0_CONFIG5: 811 v = (long)kvm_read_c0_guest_config5(cop0); 812 break; 813 case KVM_REG_MIPS_CP0_CONFIG7: 814 v = (long)kvm_read_c0_guest_config7(cop0); 815 break; 816 case KVM_REG_MIPS_CP0_ERROREPC: 817 v = (long)kvm_read_c0_guest_errorepc(cop0); 818 break; 819 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6: 820 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2; 821 if (!(vcpu->arch.kscratch_enabled & BIT(idx))) 822 return -EINVAL; 823 switch (idx) { 824 case 2: 825 v = (long)kvm_read_c0_guest_kscratch1(cop0); 826 break; 827 case 3: 828 v = (long)kvm_read_c0_guest_kscratch2(cop0); 829 break; 830 case 4: 831 v = (long)kvm_read_c0_guest_kscratch3(cop0); 832 break; 833 case 5: 834 v = (long)kvm_read_c0_guest_kscratch4(cop0); 835 break; 836 case 6: 837 v = (long)kvm_read_c0_guest_kscratch5(cop0); 838 break; 839 case 7: 840 v = (long)kvm_read_c0_guest_kscratch6(cop0); 841 break; 842 } 843 break; 844 /* registers to be handled specially */ 845 default: 846 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); 847 if (ret) 848 return ret; 849 break; 850 } 851 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 852 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 853 854 return put_user(v, uaddr64); 855 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 856 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 857 u32 v32 = (u32)v; 858 859 return put_user(v32, uaddr32); 860 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 861 void __user *uaddr = (void __user *)(long)reg->addr; 862 863 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0; 864 } else { 865 return -EINVAL; 866 } 867 } 868 869 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 870 const struct kvm_one_reg *reg) 871 { 872 struct mips_coproc *cop0 = vcpu->arch.cop0; 873 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 874 s64 v; 875 s64 vs[2]; 876 unsigned int idx; 877 878 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 879 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 880 881 if (get_user(v, uaddr64) != 0) 882 return -EFAULT; 883 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 884 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 885 s32 v32; 886 887 if (get_user(v32, uaddr32) != 0) 888 return -EFAULT; 889 v = (s64)v32; 890 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 891 void __user *uaddr = (void __user *)(long)reg->addr; 892 893 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0; 894 } else { 895 return -EINVAL; 896 } 897 898 switch (reg->id) { 899 /* General purpose registers */ 900 case KVM_REG_MIPS_R0: 901 /* Silently ignore requests to set $0 */ 902 break; 903 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: 904 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; 905 break; 906 #ifndef CONFIG_CPU_MIPSR6 907 case KVM_REG_MIPS_HI: 908 vcpu->arch.hi = v; 909 break; 910 case KVM_REG_MIPS_LO: 911 vcpu->arch.lo = v; 912 break; 913 #endif 914 case KVM_REG_MIPS_PC: 915 vcpu->arch.pc = v; 916 break; 917 918 /* Floating point registers */ 919 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 920 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 921 return -EINVAL; 922 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 923 /* Odd singles in top of even double when FR=0 */ 924 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 925 set_fpr32(&fpu->fpr[idx], 0, v); 926 else 927 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); 928 break; 929 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 930 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 931 return -EINVAL; 932 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 933 /* Can't access odd doubles in FR=0 mode */ 934 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 935 return -EINVAL; 936 set_fpr64(&fpu->fpr[idx], 0, v); 937 break; 938 case KVM_REG_MIPS_FCR_IR: 939 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 940 return -EINVAL; 941 /* Read-only */ 942 break; 943 case KVM_REG_MIPS_FCR_CSR: 944 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 945 return -EINVAL; 946 fpu->fcr31 = v; 947 break; 948 949 /* MIPS SIMD Architecture (MSA) registers */ 950 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 951 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 952 return -EINVAL; 953 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 954 #ifdef CONFIG_CPU_LITTLE_ENDIAN 955 /* least significant byte first */ 956 set_fpr64(&fpu->fpr[idx], 0, vs[0]); 957 set_fpr64(&fpu->fpr[idx], 1, vs[1]); 958 #else 959 /* most significant byte first */ 960 set_fpr64(&fpu->fpr[idx], 1, vs[0]); 961 set_fpr64(&fpu->fpr[idx], 0, vs[1]); 962 #endif 963 break; 964 case KVM_REG_MIPS_MSA_IR: 965 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 966 return -EINVAL; 967 /* Read-only */ 968 break; 969 case KVM_REG_MIPS_MSA_CSR: 970 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 971 return -EINVAL; 972 fpu->msacsr = v; 973 break; 974 975 /* Co-processor 0 registers */ 976 case KVM_REG_MIPS_CP0_INDEX: 977 kvm_write_c0_guest_index(cop0, v); 978 break; 979 case KVM_REG_MIPS_CP0_CONTEXT: 980 kvm_write_c0_guest_context(cop0, v); 981 break; 982 case KVM_REG_MIPS_CP0_USERLOCAL: 983 kvm_write_c0_guest_userlocal(cop0, v); 984 break; 985 case KVM_REG_MIPS_CP0_PAGEMASK: 986 kvm_write_c0_guest_pagemask(cop0, v); 987 break; 988 case KVM_REG_MIPS_CP0_WIRED: 989 kvm_write_c0_guest_wired(cop0, v); 990 break; 991 case KVM_REG_MIPS_CP0_HWRENA: 992 kvm_write_c0_guest_hwrena(cop0, v); 993 break; 994 case KVM_REG_MIPS_CP0_BADVADDR: 995 kvm_write_c0_guest_badvaddr(cop0, v); 996 break; 997 case KVM_REG_MIPS_CP0_ENTRYHI: 998 kvm_write_c0_guest_entryhi(cop0, v); 999 break; 1000 case KVM_REG_MIPS_CP0_STATUS: 1001 kvm_write_c0_guest_status(cop0, v); 1002 break; 1003 case KVM_REG_MIPS_CP0_EPC: 1004 kvm_write_c0_guest_epc(cop0, v); 1005 break; 1006 case KVM_REG_MIPS_CP0_PRID: 1007 kvm_write_c0_guest_prid(cop0, v); 1008 break; 1009 case KVM_REG_MIPS_CP0_ERROREPC: 1010 kvm_write_c0_guest_errorepc(cop0, v); 1011 break; 1012 case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6: 1013 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2; 1014 if (!(vcpu->arch.kscratch_enabled & BIT(idx))) 1015 return -EINVAL; 1016 switch (idx) { 1017 case 2: 1018 kvm_write_c0_guest_kscratch1(cop0, v); 1019 break; 1020 case 3: 1021 kvm_write_c0_guest_kscratch2(cop0, v); 1022 break; 1023 case 4: 1024 kvm_write_c0_guest_kscratch3(cop0, v); 1025 break; 1026 case 5: 1027 kvm_write_c0_guest_kscratch4(cop0, v); 1028 break; 1029 case 6: 1030 kvm_write_c0_guest_kscratch5(cop0, v); 1031 break; 1032 case 7: 1033 kvm_write_c0_guest_kscratch6(cop0, v); 1034 break; 1035 } 1036 break; 1037 /* registers to be handled specially */ 1038 default: 1039 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); 1040 } 1041 return 0; 1042 } 1043 1044 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 1045 struct kvm_enable_cap *cap) 1046 { 1047 int r = 0; 1048 1049 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) 1050 return -EINVAL; 1051 if (cap->flags) 1052 return -EINVAL; 1053 if (cap->args[0]) 1054 return -EINVAL; 1055 1056 switch (cap->cap) { 1057 case KVM_CAP_MIPS_FPU: 1058 vcpu->arch.fpu_enabled = true; 1059 break; 1060 case KVM_CAP_MIPS_MSA: 1061 vcpu->arch.msa_enabled = true; 1062 break; 1063 default: 1064 r = -EINVAL; 1065 break; 1066 } 1067 1068 return r; 1069 } 1070 1071 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, 1072 unsigned long arg) 1073 { 1074 struct kvm_vcpu *vcpu = filp->private_data; 1075 void __user *argp = (void __user *)arg; 1076 long r; 1077 1078 switch (ioctl) { 1079 case KVM_SET_ONE_REG: 1080 case KVM_GET_ONE_REG: { 1081 struct kvm_one_reg reg; 1082 1083 if (copy_from_user(®, argp, sizeof(reg))) 1084 return -EFAULT; 1085 if (ioctl == KVM_SET_ONE_REG) 1086 return kvm_mips_set_reg(vcpu, ®); 1087 else 1088 return kvm_mips_get_reg(vcpu, ®); 1089 } 1090 case KVM_GET_REG_LIST: { 1091 struct kvm_reg_list __user *user_list = argp; 1092 struct kvm_reg_list reg_list; 1093 unsigned n; 1094 1095 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 1096 return -EFAULT; 1097 n = reg_list.n; 1098 reg_list.n = kvm_mips_num_regs(vcpu); 1099 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 1100 return -EFAULT; 1101 if (n < reg_list.n) 1102 return -E2BIG; 1103 return kvm_mips_copy_reg_indices(vcpu, user_list->reg); 1104 } 1105 case KVM_NMI: 1106 /* Treat the NMI as a CPU reset */ 1107 r = kvm_mips_reset_vcpu(vcpu); 1108 break; 1109 case KVM_INTERRUPT: 1110 { 1111 struct kvm_mips_interrupt irq; 1112 1113 r = -EFAULT; 1114 if (copy_from_user(&irq, argp, sizeof(irq))) 1115 goto out; 1116 1117 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, 1118 irq.irq); 1119 1120 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 1121 break; 1122 } 1123 case KVM_ENABLE_CAP: { 1124 struct kvm_enable_cap cap; 1125 1126 r = -EFAULT; 1127 if (copy_from_user(&cap, argp, sizeof(cap))) 1128 goto out; 1129 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 1130 break; 1131 } 1132 default: 1133 r = -ENOIOCTLCMD; 1134 } 1135 1136 out: 1137 return r; 1138 } 1139 1140 /* Get (and clear) the dirty memory log for a memory slot. */ 1141 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 1142 { 1143 struct kvm_memslots *slots; 1144 struct kvm_memory_slot *memslot; 1145 unsigned long ga, ga_end; 1146 int is_dirty = 0; 1147 int r; 1148 unsigned long n; 1149 1150 mutex_lock(&kvm->slots_lock); 1151 1152 r = kvm_get_dirty_log(kvm, log, &is_dirty); 1153 if (r) 1154 goto out; 1155 1156 /* If nothing is dirty, don't bother messing with page tables. */ 1157 if (is_dirty) { 1158 slots = kvm_memslots(kvm); 1159 memslot = id_to_memslot(slots, log->slot); 1160 1161 ga = memslot->base_gfn << PAGE_SHIFT; 1162 ga_end = ga + (memslot->npages << PAGE_SHIFT); 1163 1164 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga, 1165 ga_end); 1166 1167 n = kvm_dirty_bitmap_bytes(memslot); 1168 memset(memslot->dirty_bitmap, 0, n); 1169 } 1170 1171 r = 0; 1172 out: 1173 mutex_unlock(&kvm->slots_lock); 1174 return r; 1175 1176 } 1177 1178 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 1179 { 1180 long r; 1181 1182 switch (ioctl) { 1183 default: 1184 r = -ENOIOCTLCMD; 1185 } 1186 1187 return r; 1188 } 1189 1190 int kvm_arch_init(void *opaque) 1191 { 1192 if (kvm_mips_callbacks) { 1193 kvm_err("kvm: module already exists\n"); 1194 return -EEXIST; 1195 } 1196 1197 return kvm_mips_emulation_init(&kvm_mips_callbacks); 1198 } 1199 1200 void kvm_arch_exit(void) 1201 { 1202 kvm_mips_callbacks = NULL; 1203 } 1204 1205 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 1206 struct kvm_sregs *sregs) 1207 { 1208 return -ENOIOCTLCMD; 1209 } 1210 1211 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 1212 struct kvm_sregs *sregs) 1213 { 1214 return -ENOIOCTLCMD; 1215 } 1216 1217 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 1218 { 1219 } 1220 1221 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1222 { 1223 return -ENOIOCTLCMD; 1224 } 1225 1226 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1227 { 1228 return -ENOIOCTLCMD; 1229 } 1230 1231 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 1232 { 1233 return VM_FAULT_SIGBUS; 1234 } 1235 1236 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 1237 { 1238 int r; 1239 1240 switch (ext) { 1241 case KVM_CAP_ONE_REG: 1242 case KVM_CAP_ENABLE_CAP: 1243 r = 1; 1244 break; 1245 case KVM_CAP_COALESCED_MMIO: 1246 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 1247 break; 1248 case KVM_CAP_MIPS_FPU: 1249 /* We don't handle systems with inconsistent cpu_has_fpu */ 1250 r = !!raw_cpu_has_fpu; 1251 break; 1252 case KVM_CAP_MIPS_MSA: 1253 /* 1254 * We don't support MSA vector partitioning yet: 1255 * 1) It would require explicit support which can't be tested 1256 * yet due to lack of support in current hardware. 1257 * 2) It extends the state that would need to be saved/restored 1258 * by e.g. QEMU for migration. 1259 * 1260 * When vector partitioning hardware becomes available, support 1261 * could be added by requiring a flag when enabling 1262 * KVM_CAP_MIPS_MSA capability to indicate that userland knows 1263 * to save/restore the appropriate extra state. 1264 */ 1265 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); 1266 break; 1267 default: 1268 r = 0; 1269 break; 1270 } 1271 return r; 1272 } 1273 1274 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 1275 { 1276 return kvm_mips_pending_timer(vcpu); 1277 } 1278 1279 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) 1280 { 1281 int i; 1282 struct mips_coproc *cop0; 1283 1284 if (!vcpu) 1285 return -1; 1286 1287 kvm_debug("VCPU Register Dump:\n"); 1288 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); 1289 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); 1290 1291 for (i = 0; i < 32; i += 4) { 1292 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, 1293 vcpu->arch.gprs[i], 1294 vcpu->arch.gprs[i + 1], 1295 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); 1296 } 1297 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); 1298 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); 1299 1300 cop0 = vcpu->arch.cop0; 1301 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n", 1302 kvm_read_c0_guest_status(cop0), 1303 kvm_read_c0_guest_cause(cop0)); 1304 1305 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); 1306 1307 return 0; 1308 } 1309 1310 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1311 { 1312 int i; 1313 1314 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1315 vcpu->arch.gprs[i] = regs->gpr[i]; 1316 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ 1317 vcpu->arch.hi = regs->hi; 1318 vcpu->arch.lo = regs->lo; 1319 vcpu->arch.pc = regs->pc; 1320 1321 return 0; 1322 } 1323 1324 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1325 { 1326 int i; 1327 1328 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1329 regs->gpr[i] = vcpu->arch.gprs[i]; 1330 1331 regs->hi = vcpu->arch.hi; 1332 regs->lo = vcpu->arch.lo; 1333 regs->pc = vcpu->arch.pc; 1334 1335 return 0; 1336 } 1337 1338 static void kvm_mips_comparecount_func(unsigned long data) 1339 { 1340 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data; 1341 1342 kvm_mips_callbacks->queue_timer_int(vcpu); 1343 1344 vcpu->arch.wait = 0; 1345 if (swait_active(&vcpu->wq)) 1346 swake_up(&vcpu->wq); 1347 } 1348 1349 /* low level hrtimer wake routine */ 1350 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) 1351 { 1352 struct kvm_vcpu *vcpu; 1353 1354 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); 1355 kvm_mips_comparecount_func((unsigned long) vcpu); 1356 return kvm_mips_count_timeout(vcpu); 1357 } 1358 1359 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 1360 { 1361 kvm_mips_callbacks->vcpu_init(vcpu); 1362 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 1363 HRTIMER_MODE_REL); 1364 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 1365 return 0; 1366 } 1367 1368 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 1369 struct kvm_translation *tr) 1370 { 1371 return 0; 1372 } 1373 1374 /* Initial guest state */ 1375 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 1376 { 1377 return kvm_mips_callbacks->vcpu_setup(vcpu); 1378 } 1379 1380 static void kvm_mips_set_c0_status(void) 1381 { 1382 u32 status = read_c0_status(); 1383 1384 if (cpu_has_dsp) 1385 status |= (ST0_MX); 1386 1387 write_c0_status(status); 1388 ehb(); 1389 } 1390 1391 /* 1392 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) 1393 */ 1394 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) 1395 { 1396 u32 cause = vcpu->arch.host_cp0_cause; 1397 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; 1398 u32 __user *opc = (u32 __user *) vcpu->arch.pc; 1399 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; 1400 enum emulation_result er = EMULATE_DONE; 1401 int ret = RESUME_GUEST; 1402 1403 /* re-enable HTW before enabling interrupts */ 1404 htw_start(); 1405 1406 /* Set a default exit reason */ 1407 run->exit_reason = KVM_EXIT_UNKNOWN; 1408 run->ready_for_interrupt_injection = 1; 1409 1410 /* 1411 * Set the appropriate status bits based on host CPU features, 1412 * before we hit the scheduler 1413 */ 1414 kvm_mips_set_c0_status(); 1415 1416 local_irq_enable(); 1417 1418 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", 1419 cause, opc, run, vcpu); 1420 trace_kvm_exit(vcpu, exccode); 1421 1422 /* 1423 * Do a privilege check, if in UM most of these exit conditions end up 1424 * causing an exception to be delivered to the Guest Kernel 1425 */ 1426 er = kvm_mips_check_privilege(cause, opc, run, vcpu); 1427 if (er == EMULATE_PRIV_FAIL) { 1428 goto skip_emul; 1429 } else if (er == EMULATE_FAIL) { 1430 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1431 ret = RESUME_HOST; 1432 goto skip_emul; 1433 } 1434 1435 switch (exccode) { 1436 case EXCCODE_INT: 1437 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc); 1438 1439 ++vcpu->stat.int_exits; 1440 1441 if (need_resched()) 1442 cond_resched(); 1443 1444 ret = RESUME_GUEST; 1445 break; 1446 1447 case EXCCODE_CPU: 1448 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc); 1449 1450 ++vcpu->stat.cop_unusable_exits; 1451 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); 1452 /* XXXKYMA: Might need to return to user space */ 1453 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) 1454 ret = RESUME_HOST; 1455 break; 1456 1457 case EXCCODE_MOD: 1458 ++vcpu->stat.tlbmod_exits; 1459 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); 1460 break; 1461 1462 case EXCCODE_TLBS: 1463 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n", 1464 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, 1465 badvaddr); 1466 1467 ++vcpu->stat.tlbmiss_st_exits; 1468 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); 1469 break; 1470 1471 case EXCCODE_TLBL: 1472 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", 1473 cause, opc, badvaddr); 1474 1475 ++vcpu->stat.tlbmiss_ld_exits; 1476 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); 1477 break; 1478 1479 case EXCCODE_ADES: 1480 ++vcpu->stat.addrerr_st_exits; 1481 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); 1482 break; 1483 1484 case EXCCODE_ADEL: 1485 ++vcpu->stat.addrerr_ld_exits; 1486 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); 1487 break; 1488 1489 case EXCCODE_SYS: 1490 ++vcpu->stat.syscall_exits; 1491 ret = kvm_mips_callbacks->handle_syscall(vcpu); 1492 break; 1493 1494 case EXCCODE_RI: 1495 ++vcpu->stat.resvd_inst_exits; 1496 ret = kvm_mips_callbacks->handle_res_inst(vcpu); 1497 break; 1498 1499 case EXCCODE_BP: 1500 ++vcpu->stat.break_inst_exits; 1501 ret = kvm_mips_callbacks->handle_break(vcpu); 1502 break; 1503 1504 case EXCCODE_TR: 1505 ++vcpu->stat.trap_inst_exits; 1506 ret = kvm_mips_callbacks->handle_trap(vcpu); 1507 break; 1508 1509 case EXCCODE_MSAFPE: 1510 ++vcpu->stat.msa_fpe_exits; 1511 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); 1512 break; 1513 1514 case EXCCODE_FPE: 1515 ++vcpu->stat.fpe_exits; 1516 ret = kvm_mips_callbacks->handle_fpe(vcpu); 1517 break; 1518 1519 case EXCCODE_MSADIS: 1520 ++vcpu->stat.msa_disabled_exits; 1521 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); 1522 break; 1523 1524 default: 1525 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n", 1526 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr, 1527 kvm_read_c0_guest_status(vcpu->arch.cop0)); 1528 kvm_arch_vcpu_dump_regs(vcpu); 1529 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1530 ret = RESUME_HOST; 1531 break; 1532 1533 } 1534 1535 skip_emul: 1536 local_irq_disable(); 1537 1538 if (er == EMULATE_DONE && !(ret & RESUME_HOST)) 1539 kvm_mips_deliver_interrupts(vcpu, cause); 1540 1541 if (!(ret & RESUME_HOST)) { 1542 /* Only check for signals if not already exiting to userspace */ 1543 if (signal_pending(current)) { 1544 run->exit_reason = KVM_EXIT_INTR; 1545 ret = (-EINTR << 2) | RESUME_HOST; 1546 ++vcpu->stat.signal_exits; 1547 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL); 1548 } 1549 } 1550 1551 if (ret == RESUME_GUEST) { 1552 trace_kvm_reenter(vcpu); 1553 1554 /* 1555 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context 1556 * is live), restore FCR31 / MSACSR. 1557 * 1558 * This should be before returning to the guest exception 1559 * vector, as it may well cause an [MSA] FP exception if there 1560 * are pending exception bits unmasked. (see 1561 * kvm_mips_csr_die_notifier() for how that is handled). 1562 */ 1563 if (kvm_mips_guest_has_fpu(&vcpu->arch) && 1564 read_c0_status() & ST0_CU1) 1565 __kvm_restore_fcsr(&vcpu->arch); 1566 1567 if (kvm_mips_guest_has_msa(&vcpu->arch) && 1568 read_c0_config5() & MIPS_CONF5_MSAEN) 1569 __kvm_restore_msacsr(&vcpu->arch); 1570 } 1571 1572 /* Disable HTW before returning to guest or host */ 1573 htw_stop(); 1574 1575 return ret; 1576 } 1577 1578 /* Enable FPU for guest and restore context */ 1579 void kvm_own_fpu(struct kvm_vcpu *vcpu) 1580 { 1581 struct mips_coproc *cop0 = vcpu->arch.cop0; 1582 unsigned int sr, cfg5; 1583 1584 preempt_disable(); 1585 1586 sr = kvm_read_c0_guest_status(cop0); 1587 1588 /* 1589 * If MSA state is already live, it is undefined how it interacts with 1590 * FR=0 FPU state, and we don't want to hit reserved instruction 1591 * exceptions trying to save the MSA state later when CU=1 && FR=1, so 1592 * play it safe and save it first. 1593 * 1594 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should 1595 * get called when guest CU1 is set, however we can't trust the guest 1596 * not to clobber the status register directly via the commpage. 1597 */ 1598 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && 1599 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) 1600 kvm_lose_fpu(vcpu); 1601 1602 /* 1603 * Enable FPU for guest 1604 * We set FR and FRE according to guest context 1605 */ 1606 change_c0_status(ST0_CU1 | ST0_FR, sr); 1607 if (cpu_has_fre) { 1608 cfg5 = kvm_read_c0_guest_config5(cop0); 1609 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1610 } 1611 enable_fpu_hazard(); 1612 1613 /* If guest FPU state not active, restore it now */ 1614 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) { 1615 __kvm_restore_fpu(&vcpu->arch); 1616 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1617 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU); 1618 } else { 1619 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU); 1620 } 1621 1622 preempt_enable(); 1623 } 1624 1625 #ifdef CONFIG_CPU_HAS_MSA 1626 /* Enable MSA for guest and restore context */ 1627 void kvm_own_msa(struct kvm_vcpu *vcpu) 1628 { 1629 struct mips_coproc *cop0 = vcpu->arch.cop0; 1630 unsigned int sr, cfg5; 1631 1632 preempt_disable(); 1633 1634 /* 1635 * Enable FPU if enabled in guest, since we're restoring FPU context 1636 * anyway. We set FR and FRE according to guest context. 1637 */ 1638 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { 1639 sr = kvm_read_c0_guest_status(cop0); 1640 1641 /* 1642 * If FR=0 FPU state is already live, it is undefined how it 1643 * interacts with MSA state, so play it safe and save it first. 1644 */ 1645 if (!(sr & ST0_FR) && 1646 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | 1647 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU) 1648 kvm_lose_fpu(vcpu); 1649 1650 change_c0_status(ST0_CU1 | ST0_FR, sr); 1651 if (sr & ST0_CU1 && cpu_has_fre) { 1652 cfg5 = kvm_read_c0_guest_config5(cop0); 1653 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1654 } 1655 } 1656 1657 /* Enable MSA for guest */ 1658 set_c0_config5(MIPS_CONF5_MSAEN); 1659 enable_fpu_hazard(); 1660 1661 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) { 1662 case KVM_MIPS_AUX_FPU: 1663 /* 1664 * Guest FPU state already loaded, only restore upper MSA state 1665 */ 1666 __kvm_restore_msa_upper(&vcpu->arch); 1667 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1668 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA); 1669 break; 1670 case 0: 1671 /* Neither FPU or MSA already active, restore full MSA state */ 1672 __kvm_restore_msa(&vcpu->arch); 1673 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1674 if (kvm_mips_guest_has_fpu(&vcpu->arch)) 1675 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1676 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, 1677 KVM_TRACE_AUX_FPU_MSA); 1678 break; 1679 default: 1680 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA); 1681 break; 1682 } 1683 1684 preempt_enable(); 1685 } 1686 #endif 1687 1688 /* Drop FPU & MSA without saving it */ 1689 void kvm_drop_fpu(struct kvm_vcpu *vcpu) 1690 { 1691 preempt_disable(); 1692 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1693 disable_msa(); 1694 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA); 1695 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA; 1696 } 1697 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1698 clear_c0_status(ST0_CU1 | ST0_FR); 1699 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU); 1700 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1701 } 1702 preempt_enable(); 1703 } 1704 1705 /* Save and disable FPU & MSA */ 1706 void kvm_lose_fpu(struct kvm_vcpu *vcpu) 1707 { 1708 /* 1709 * FPU & MSA get disabled in root context (hardware) when it is disabled 1710 * in guest context (software), but the register state in the hardware 1711 * may still be in use. This is why we explicitly re-enable the hardware 1712 * before saving. 1713 */ 1714 1715 preempt_disable(); 1716 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1717 set_c0_config5(MIPS_CONF5_MSAEN); 1718 enable_fpu_hazard(); 1719 1720 __kvm_save_msa(&vcpu->arch); 1721 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA); 1722 1723 /* Disable MSA & FPU */ 1724 disable_msa(); 1725 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1726 clear_c0_status(ST0_CU1 | ST0_FR); 1727 disable_fpu_hazard(); 1728 } 1729 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA); 1730 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1731 set_c0_status(ST0_CU1); 1732 enable_fpu_hazard(); 1733 1734 __kvm_save_fpu(&vcpu->arch); 1735 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1736 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU); 1737 1738 /* Disable FPU */ 1739 clear_c0_status(ST0_CU1 | ST0_FR); 1740 disable_fpu_hazard(); 1741 } 1742 preempt_enable(); 1743 } 1744 1745 /* 1746 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are 1747 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP 1748 * exception if cause bits are set in the value being written. 1749 */ 1750 static int kvm_mips_csr_die_notify(struct notifier_block *self, 1751 unsigned long cmd, void *ptr) 1752 { 1753 struct die_args *args = (struct die_args *)ptr; 1754 struct pt_regs *regs = args->regs; 1755 unsigned long pc; 1756 1757 /* Only interested in FPE and MSAFPE */ 1758 if (cmd != DIE_FP && cmd != DIE_MSAFP) 1759 return NOTIFY_DONE; 1760 1761 /* Return immediately if guest context isn't active */ 1762 if (!(current->flags & PF_VCPU)) 1763 return NOTIFY_DONE; 1764 1765 /* Should never get here from user mode */ 1766 BUG_ON(user_mode(regs)); 1767 1768 pc = instruction_pointer(regs); 1769 switch (cmd) { 1770 case DIE_FP: 1771 /* match 2nd instruction in __kvm_restore_fcsr */ 1772 if (pc != (unsigned long)&__kvm_restore_fcsr + 4) 1773 return NOTIFY_DONE; 1774 break; 1775 case DIE_MSAFP: 1776 /* match 2nd/3rd instruction in __kvm_restore_msacsr */ 1777 if (!cpu_has_msa || 1778 pc < (unsigned long)&__kvm_restore_msacsr + 4 || 1779 pc > (unsigned long)&__kvm_restore_msacsr + 8) 1780 return NOTIFY_DONE; 1781 break; 1782 } 1783 1784 /* Move PC forward a little and continue executing */ 1785 instruction_pointer(regs) += 4; 1786 1787 return NOTIFY_STOP; 1788 } 1789 1790 static struct notifier_block kvm_mips_csr_die_notifier = { 1791 .notifier_call = kvm_mips_csr_die_notify, 1792 }; 1793 1794 static int __init kvm_mips_init(void) 1795 { 1796 int ret; 1797 1798 ret = kvm_mips_entry_setup(); 1799 if (ret) 1800 return ret; 1801 1802 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); 1803 1804 if (ret) 1805 return ret; 1806 1807 register_die_notifier(&kvm_mips_csr_die_notifier); 1808 1809 return 0; 1810 } 1811 1812 static void __exit kvm_mips_exit(void) 1813 { 1814 kvm_exit(); 1815 1816 unregister_die_notifier(&kvm_mips_csr_die_notifier); 1817 } 1818 1819 module_init(kvm_mips_init); 1820 module_exit(kvm_mips_exit); 1821 1822 EXPORT_TRACEPOINT_SYMBOL(kvm_exit); 1823