1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * KVM/MIPS: MIPS specific KVM APIs 7 * 8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 9 * Authors: Sanjay Lal <sanjayl@kymasys.com> 10 */ 11 12 #include <linux/errno.h> 13 #include <linux/err.h> 14 #include <linux/kdebug.h> 15 #include <linux/module.h> 16 #include <linux/vmalloc.h> 17 #include <linux/fs.h> 18 #include <linux/bootmem.h> 19 #include <asm/fpu.h> 20 #include <asm/page.h> 21 #include <asm/cacheflush.h> 22 #include <asm/mmu_context.h> 23 #include <asm/pgtable.h> 24 25 #include <linux/kvm_host.h> 26 27 #include "interrupt.h" 28 #include "commpage.h" 29 30 #define CREATE_TRACE_POINTS 31 #include "trace.h" 32 33 #ifndef VECTORSPACING 34 #define VECTORSPACING 0x100 /* for EI/VI mode */ 35 #endif 36 37 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x) 38 struct kvm_stats_debugfs_item debugfs_entries[] = { 39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU }, 40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU }, 41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU }, 42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU }, 43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU }, 44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU }, 45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU }, 46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU }, 47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU }, 48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU }, 49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU }, 50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU }, 51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU }, 52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU }, 53 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU }, 54 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU }, 55 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU }, 56 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU }, 57 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU }, 58 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU }, 59 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU }, 60 {NULL} 61 }; 62 63 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu) 64 { 65 int i; 66 67 for_each_possible_cpu(i) { 68 vcpu->arch.guest_kernel_asid[i] = 0; 69 vcpu->arch.guest_user_asid[i] = 0; 70 } 71 72 return 0; 73 } 74 75 /* 76 * XXXKYMA: We are simulatoring a processor that has the WII bit set in 77 * Config7, so we are "runnable" if interrupts are pending 78 */ 79 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 80 { 81 return !!(vcpu->arch.pending_exceptions); 82 } 83 84 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 85 { 86 return 1; 87 } 88 89 int kvm_arch_hardware_enable(void) 90 { 91 return 0; 92 } 93 94 int kvm_arch_hardware_setup(void) 95 { 96 return 0; 97 } 98 99 void kvm_arch_check_processor_compat(void *rtn) 100 { 101 *(int *)rtn = 0; 102 } 103 104 static void kvm_mips_init_tlbs(struct kvm *kvm) 105 { 106 unsigned long wired; 107 108 /* 109 * Add a wired entry to the TLB, it is used to map the commpage to 110 * the Guest kernel 111 */ 112 wired = read_c0_wired(); 113 write_c0_wired(wired + 1); 114 mtc0_tlbw_hazard(); 115 kvm->arch.commpage_tlb = wired; 116 117 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(), 118 kvm->arch.commpage_tlb); 119 } 120 121 static void kvm_mips_init_vm_percpu(void *arg) 122 { 123 struct kvm *kvm = (struct kvm *)arg; 124 125 kvm_mips_init_tlbs(kvm); 126 kvm_mips_callbacks->vm_init(kvm); 127 128 } 129 130 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 131 { 132 if (atomic_inc_return(&kvm_mips_instance) == 1) { 133 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n", 134 __func__); 135 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1); 136 } 137 138 return 0; 139 } 140 141 void kvm_mips_free_vcpus(struct kvm *kvm) 142 { 143 unsigned int i; 144 struct kvm_vcpu *vcpu; 145 146 /* Put the pages we reserved for the guest pmap */ 147 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) { 148 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE) 149 kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]); 150 } 151 kfree(kvm->arch.guest_pmap); 152 153 kvm_for_each_vcpu(i, vcpu, kvm) { 154 kvm_arch_vcpu_free(vcpu); 155 } 156 157 mutex_lock(&kvm->lock); 158 159 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 160 kvm->vcpus[i] = NULL; 161 162 atomic_set(&kvm->online_vcpus, 0); 163 164 mutex_unlock(&kvm->lock); 165 } 166 167 static void kvm_mips_uninit_tlbs(void *arg) 168 { 169 /* Restore wired count */ 170 write_c0_wired(0); 171 mtc0_tlbw_hazard(); 172 /* Clear out all the TLBs */ 173 kvm_local_flush_tlb_all(); 174 } 175 176 void kvm_arch_destroy_vm(struct kvm *kvm) 177 { 178 kvm_mips_free_vcpus(kvm); 179 180 /* If this is the last instance, restore wired count */ 181 if (atomic_dec_return(&kvm_mips_instance) == 0) { 182 kvm_debug("%s: last KVM instance, restoring TLB parameters\n", 183 __func__); 184 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1); 185 } 186 } 187 188 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, 189 unsigned long arg) 190 { 191 return -ENOIOCTLCMD; 192 } 193 194 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 195 unsigned long npages) 196 { 197 return 0; 198 } 199 200 int kvm_arch_prepare_memory_region(struct kvm *kvm, 201 struct kvm_memory_slot *memslot, 202 const struct kvm_userspace_memory_region *mem, 203 enum kvm_mr_change change) 204 { 205 return 0; 206 } 207 208 void kvm_arch_commit_memory_region(struct kvm *kvm, 209 const struct kvm_userspace_memory_region *mem, 210 const struct kvm_memory_slot *old, 211 const struct kvm_memory_slot *new, 212 enum kvm_mr_change change) 213 { 214 unsigned long npages = 0; 215 int i; 216 217 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n", 218 __func__, kvm, mem->slot, mem->guest_phys_addr, 219 mem->memory_size, mem->userspace_addr); 220 221 /* Setup Guest PMAP table */ 222 if (!kvm->arch.guest_pmap) { 223 if (mem->slot == 0) 224 npages = mem->memory_size >> PAGE_SHIFT; 225 226 if (npages) { 227 kvm->arch.guest_pmap_npages = npages; 228 kvm->arch.guest_pmap = 229 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL); 230 231 if (!kvm->arch.guest_pmap) { 232 kvm_err("Failed to allocate guest PMAP"); 233 return; 234 } 235 236 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n", 237 npages, kvm->arch.guest_pmap); 238 239 /* Now setup the page table */ 240 for (i = 0; i < npages; i++) 241 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE; 242 } 243 } 244 } 245 246 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) 247 { 248 int err, size, offset; 249 void *gebase; 250 int i; 251 252 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL); 253 254 if (!vcpu) { 255 err = -ENOMEM; 256 goto out; 257 } 258 259 err = kvm_vcpu_init(vcpu, kvm, id); 260 261 if (err) 262 goto out_free_cpu; 263 264 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu); 265 266 /* 267 * Allocate space for host mode exception handlers that handle 268 * guest mode exits 269 */ 270 if (cpu_has_veic || cpu_has_vint) 271 size = 0x200 + VECTORSPACING * 64; 272 else 273 size = 0x4000; 274 275 /* Save Linux EBASE */ 276 vcpu->arch.host_ebase = (void *)read_c0_ebase(); 277 278 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); 279 280 if (!gebase) { 281 err = -ENOMEM; 282 goto out_free_cpu; 283 } 284 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", 285 ALIGN(size, PAGE_SIZE), gebase); 286 287 /* Save new ebase */ 288 vcpu->arch.guest_ebase = gebase; 289 290 /* Copy L1 Guest Exception handler to correct offset */ 291 292 /* TLB Refill, EXL = 0 */ 293 memcpy(gebase, mips32_exception, 294 mips32_exceptionEnd - mips32_exception); 295 296 /* General Exception Entry point */ 297 memcpy(gebase + 0x180, mips32_exception, 298 mips32_exceptionEnd - mips32_exception); 299 300 /* For vectored interrupts poke the exception code @ all offsets 0-7 */ 301 for (i = 0; i < 8; i++) { 302 kvm_debug("L1 Vectored handler @ %p\n", 303 gebase + 0x200 + (i * VECTORSPACING)); 304 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception, 305 mips32_exceptionEnd - mips32_exception); 306 } 307 308 /* General handler, relocate to unmapped space for sanity's sake */ 309 offset = 0x2000; 310 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n", 311 gebase + offset, 312 mips32_GuestExceptionEnd - mips32_GuestException); 313 314 memcpy(gebase + offset, mips32_GuestException, 315 mips32_GuestExceptionEnd - mips32_GuestException); 316 317 /* Invalidate the icache for these ranges */ 318 local_flush_icache_range((unsigned long)gebase, 319 (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); 320 321 /* 322 * Allocate comm page for guest kernel, a TLB will be reserved for 323 * mapping GVA @ 0xFFFF8000 to this page 324 */ 325 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL); 326 327 if (!vcpu->arch.kseg0_commpage) { 328 err = -ENOMEM; 329 goto out_free_gebase; 330 } 331 332 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage); 333 kvm_mips_commpage_init(vcpu); 334 335 /* Init */ 336 vcpu->arch.last_sched_cpu = -1; 337 338 /* Start off the timer */ 339 kvm_mips_init_count(vcpu); 340 341 return vcpu; 342 343 out_free_gebase: 344 kfree(gebase); 345 346 out_free_cpu: 347 kfree(vcpu); 348 349 out: 350 return ERR_PTR(err); 351 } 352 353 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 354 { 355 hrtimer_cancel(&vcpu->arch.comparecount_timer); 356 357 kvm_vcpu_uninit(vcpu); 358 359 kvm_mips_dump_stats(vcpu); 360 361 kfree(vcpu->arch.guest_ebase); 362 kfree(vcpu->arch.kseg0_commpage); 363 kfree(vcpu); 364 } 365 366 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 367 { 368 kvm_arch_vcpu_free(vcpu); 369 } 370 371 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 372 struct kvm_guest_debug *dbg) 373 { 374 return -ENOIOCTLCMD; 375 } 376 377 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) 378 { 379 int r = 0; 380 sigset_t sigsaved; 381 382 if (vcpu->sigset_active) 383 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 384 385 if (vcpu->mmio_needed) { 386 if (!vcpu->mmio_is_write) 387 kvm_mips_complete_mmio_load(vcpu, run); 388 vcpu->mmio_needed = 0; 389 } 390 391 lose_fpu(1); 392 393 local_irq_disable(); 394 /* Check if we have any exceptions/interrupts pending */ 395 kvm_mips_deliver_interrupts(vcpu, 396 kvm_read_c0_guest_cause(vcpu->arch.cop0)); 397 398 __kvm_guest_enter(); 399 400 /* Disable hardware page table walking while in guest */ 401 htw_stop(); 402 403 r = __kvm_mips_vcpu_run(run, vcpu); 404 405 /* Re-enable HTW before enabling interrupts */ 406 htw_start(); 407 408 __kvm_guest_exit(); 409 local_irq_enable(); 410 411 if (vcpu->sigset_active) 412 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 413 414 return r; 415 } 416 417 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 418 struct kvm_mips_interrupt *irq) 419 { 420 int intr = (int)irq->irq; 421 struct kvm_vcpu *dvcpu = NULL; 422 423 if (intr == 3 || intr == -3 || intr == 4 || intr == -4) 424 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, 425 (int)intr); 426 427 if (irq->cpu == -1) 428 dvcpu = vcpu; 429 else 430 dvcpu = vcpu->kvm->vcpus[irq->cpu]; 431 432 if (intr == 2 || intr == 3 || intr == 4) { 433 kvm_mips_callbacks->queue_io_int(dvcpu, irq); 434 435 } else if (intr == -2 || intr == -3 || intr == -4) { 436 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); 437 } else { 438 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, 439 irq->cpu, irq->irq); 440 return -EINVAL; 441 } 442 443 dvcpu->arch.wait = 0; 444 445 if (waitqueue_active(&dvcpu->wq)) 446 wake_up_interruptible(&dvcpu->wq); 447 448 return 0; 449 } 450 451 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 452 struct kvm_mp_state *mp_state) 453 { 454 return -ENOIOCTLCMD; 455 } 456 457 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 458 struct kvm_mp_state *mp_state) 459 { 460 return -ENOIOCTLCMD; 461 } 462 463 static u64 kvm_mips_get_one_regs[] = { 464 KVM_REG_MIPS_R0, 465 KVM_REG_MIPS_R1, 466 KVM_REG_MIPS_R2, 467 KVM_REG_MIPS_R3, 468 KVM_REG_MIPS_R4, 469 KVM_REG_MIPS_R5, 470 KVM_REG_MIPS_R6, 471 KVM_REG_MIPS_R7, 472 KVM_REG_MIPS_R8, 473 KVM_REG_MIPS_R9, 474 KVM_REG_MIPS_R10, 475 KVM_REG_MIPS_R11, 476 KVM_REG_MIPS_R12, 477 KVM_REG_MIPS_R13, 478 KVM_REG_MIPS_R14, 479 KVM_REG_MIPS_R15, 480 KVM_REG_MIPS_R16, 481 KVM_REG_MIPS_R17, 482 KVM_REG_MIPS_R18, 483 KVM_REG_MIPS_R19, 484 KVM_REG_MIPS_R20, 485 KVM_REG_MIPS_R21, 486 KVM_REG_MIPS_R22, 487 KVM_REG_MIPS_R23, 488 KVM_REG_MIPS_R24, 489 KVM_REG_MIPS_R25, 490 KVM_REG_MIPS_R26, 491 KVM_REG_MIPS_R27, 492 KVM_REG_MIPS_R28, 493 KVM_REG_MIPS_R29, 494 KVM_REG_MIPS_R30, 495 KVM_REG_MIPS_R31, 496 497 KVM_REG_MIPS_HI, 498 KVM_REG_MIPS_LO, 499 KVM_REG_MIPS_PC, 500 501 KVM_REG_MIPS_CP0_INDEX, 502 KVM_REG_MIPS_CP0_CONTEXT, 503 KVM_REG_MIPS_CP0_USERLOCAL, 504 KVM_REG_MIPS_CP0_PAGEMASK, 505 KVM_REG_MIPS_CP0_WIRED, 506 KVM_REG_MIPS_CP0_HWRENA, 507 KVM_REG_MIPS_CP0_BADVADDR, 508 KVM_REG_MIPS_CP0_COUNT, 509 KVM_REG_MIPS_CP0_ENTRYHI, 510 KVM_REG_MIPS_CP0_COMPARE, 511 KVM_REG_MIPS_CP0_STATUS, 512 KVM_REG_MIPS_CP0_CAUSE, 513 KVM_REG_MIPS_CP0_EPC, 514 KVM_REG_MIPS_CP0_PRID, 515 KVM_REG_MIPS_CP0_CONFIG, 516 KVM_REG_MIPS_CP0_CONFIG1, 517 KVM_REG_MIPS_CP0_CONFIG2, 518 KVM_REG_MIPS_CP0_CONFIG3, 519 KVM_REG_MIPS_CP0_CONFIG4, 520 KVM_REG_MIPS_CP0_CONFIG5, 521 KVM_REG_MIPS_CP0_CONFIG7, 522 KVM_REG_MIPS_CP0_ERROREPC, 523 524 KVM_REG_MIPS_COUNT_CTL, 525 KVM_REG_MIPS_COUNT_RESUME, 526 KVM_REG_MIPS_COUNT_HZ, 527 }; 528 529 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 530 const struct kvm_one_reg *reg) 531 { 532 struct mips_coproc *cop0 = vcpu->arch.cop0; 533 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 534 int ret; 535 s64 v; 536 s64 vs[2]; 537 unsigned int idx; 538 539 switch (reg->id) { 540 /* General purpose registers */ 541 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: 542 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; 543 break; 544 case KVM_REG_MIPS_HI: 545 v = (long)vcpu->arch.hi; 546 break; 547 case KVM_REG_MIPS_LO: 548 v = (long)vcpu->arch.lo; 549 break; 550 case KVM_REG_MIPS_PC: 551 v = (long)vcpu->arch.pc; 552 break; 553 554 /* Floating point registers */ 555 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 556 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 557 return -EINVAL; 558 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 559 /* Odd singles in top of even double when FR=0 */ 560 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 561 v = get_fpr32(&fpu->fpr[idx], 0); 562 else 563 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); 564 break; 565 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 566 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 567 return -EINVAL; 568 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 569 /* Can't access odd doubles in FR=0 mode */ 570 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 571 return -EINVAL; 572 v = get_fpr64(&fpu->fpr[idx], 0); 573 break; 574 case KVM_REG_MIPS_FCR_IR: 575 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 576 return -EINVAL; 577 v = boot_cpu_data.fpu_id; 578 break; 579 case KVM_REG_MIPS_FCR_CSR: 580 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 581 return -EINVAL; 582 v = fpu->fcr31; 583 break; 584 585 /* MIPS SIMD Architecture (MSA) registers */ 586 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 587 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 588 return -EINVAL; 589 /* Can't access MSA registers in FR=0 mode */ 590 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) 591 return -EINVAL; 592 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 593 #ifdef CONFIG_CPU_LITTLE_ENDIAN 594 /* least significant byte first */ 595 vs[0] = get_fpr64(&fpu->fpr[idx], 0); 596 vs[1] = get_fpr64(&fpu->fpr[idx], 1); 597 #else 598 /* most significant byte first */ 599 vs[0] = get_fpr64(&fpu->fpr[idx], 1); 600 vs[1] = get_fpr64(&fpu->fpr[idx], 0); 601 #endif 602 break; 603 case KVM_REG_MIPS_MSA_IR: 604 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 605 return -EINVAL; 606 v = boot_cpu_data.msa_id; 607 break; 608 case KVM_REG_MIPS_MSA_CSR: 609 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 610 return -EINVAL; 611 v = fpu->msacsr; 612 break; 613 614 /* Co-processor 0 registers */ 615 case KVM_REG_MIPS_CP0_INDEX: 616 v = (long)kvm_read_c0_guest_index(cop0); 617 break; 618 case KVM_REG_MIPS_CP0_CONTEXT: 619 v = (long)kvm_read_c0_guest_context(cop0); 620 break; 621 case KVM_REG_MIPS_CP0_USERLOCAL: 622 v = (long)kvm_read_c0_guest_userlocal(cop0); 623 break; 624 case KVM_REG_MIPS_CP0_PAGEMASK: 625 v = (long)kvm_read_c0_guest_pagemask(cop0); 626 break; 627 case KVM_REG_MIPS_CP0_WIRED: 628 v = (long)kvm_read_c0_guest_wired(cop0); 629 break; 630 case KVM_REG_MIPS_CP0_HWRENA: 631 v = (long)kvm_read_c0_guest_hwrena(cop0); 632 break; 633 case KVM_REG_MIPS_CP0_BADVADDR: 634 v = (long)kvm_read_c0_guest_badvaddr(cop0); 635 break; 636 case KVM_REG_MIPS_CP0_ENTRYHI: 637 v = (long)kvm_read_c0_guest_entryhi(cop0); 638 break; 639 case KVM_REG_MIPS_CP0_COMPARE: 640 v = (long)kvm_read_c0_guest_compare(cop0); 641 break; 642 case KVM_REG_MIPS_CP0_STATUS: 643 v = (long)kvm_read_c0_guest_status(cop0); 644 break; 645 case KVM_REG_MIPS_CP0_CAUSE: 646 v = (long)kvm_read_c0_guest_cause(cop0); 647 break; 648 case KVM_REG_MIPS_CP0_EPC: 649 v = (long)kvm_read_c0_guest_epc(cop0); 650 break; 651 case KVM_REG_MIPS_CP0_PRID: 652 v = (long)kvm_read_c0_guest_prid(cop0); 653 break; 654 case KVM_REG_MIPS_CP0_CONFIG: 655 v = (long)kvm_read_c0_guest_config(cop0); 656 break; 657 case KVM_REG_MIPS_CP0_CONFIG1: 658 v = (long)kvm_read_c0_guest_config1(cop0); 659 break; 660 case KVM_REG_MIPS_CP0_CONFIG2: 661 v = (long)kvm_read_c0_guest_config2(cop0); 662 break; 663 case KVM_REG_MIPS_CP0_CONFIG3: 664 v = (long)kvm_read_c0_guest_config3(cop0); 665 break; 666 case KVM_REG_MIPS_CP0_CONFIG4: 667 v = (long)kvm_read_c0_guest_config4(cop0); 668 break; 669 case KVM_REG_MIPS_CP0_CONFIG5: 670 v = (long)kvm_read_c0_guest_config5(cop0); 671 break; 672 case KVM_REG_MIPS_CP0_CONFIG7: 673 v = (long)kvm_read_c0_guest_config7(cop0); 674 break; 675 case KVM_REG_MIPS_CP0_ERROREPC: 676 v = (long)kvm_read_c0_guest_errorepc(cop0); 677 break; 678 /* registers to be handled specially */ 679 case KVM_REG_MIPS_CP0_COUNT: 680 case KVM_REG_MIPS_COUNT_CTL: 681 case KVM_REG_MIPS_COUNT_RESUME: 682 case KVM_REG_MIPS_COUNT_HZ: 683 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); 684 if (ret) 685 return ret; 686 break; 687 default: 688 return -EINVAL; 689 } 690 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 691 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 692 693 return put_user(v, uaddr64); 694 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 695 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 696 u32 v32 = (u32)v; 697 698 return put_user(v32, uaddr32); 699 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 700 void __user *uaddr = (void __user *)(long)reg->addr; 701 702 return copy_to_user(uaddr, vs, 16); 703 } else { 704 return -EINVAL; 705 } 706 } 707 708 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 709 const struct kvm_one_reg *reg) 710 { 711 struct mips_coproc *cop0 = vcpu->arch.cop0; 712 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 713 s64 v; 714 s64 vs[2]; 715 unsigned int idx; 716 717 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 718 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 719 720 if (get_user(v, uaddr64) != 0) 721 return -EFAULT; 722 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 723 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 724 s32 v32; 725 726 if (get_user(v32, uaddr32) != 0) 727 return -EFAULT; 728 v = (s64)v32; 729 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 730 void __user *uaddr = (void __user *)(long)reg->addr; 731 732 return copy_from_user(vs, uaddr, 16); 733 } else { 734 return -EINVAL; 735 } 736 737 switch (reg->id) { 738 /* General purpose registers */ 739 case KVM_REG_MIPS_R0: 740 /* Silently ignore requests to set $0 */ 741 break; 742 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: 743 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; 744 break; 745 case KVM_REG_MIPS_HI: 746 vcpu->arch.hi = v; 747 break; 748 case KVM_REG_MIPS_LO: 749 vcpu->arch.lo = v; 750 break; 751 case KVM_REG_MIPS_PC: 752 vcpu->arch.pc = v; 753 break; 754 755 /* Floating point registers */ 756 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 757 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 758 return -EINVAL; 759 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 760 /* Odd singles in top of even double when FR=0 */ 761 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 762 set_fpr32(&fpu->fpr[idx], 0, v); 763 else 764 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); 765 break; 766 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 767 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 768 return -EINVAL; 769 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 770 /* Can't access odd doubles in FR=0 mode */ 771 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 772 return -EINVAL; 773 set_fpr64(&fpu->fpr[idx], 0, v); 774 break; 775 case KVM_REG_MIPS_FCR_IR: 776 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 777 return -EINVAL; 778 /* Read-only */ 779 break; 780 case KVM_REG_MIPS_FCR_CSR: 781 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 782 return -EINVAL; 783 fpu->fcr31 = v; 784 break; 785 786 /* MIPS SIMD Architecture (MSA) registers */ 787 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 788 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 789 return -EINVAL; 790 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 791 #ifdef CONFIG_CPU_LITTLE_ENDIAN 792 /* least significant byte first */ 793 set_fpr64(&fpu->fpr[idx], 0, vs[0]); 794 set_fpr64(&fpu->fpr[idx], 1, vs[1]); 795 #else 796 /* most significant byte first */ 797 set_fpr64(&fpu->fpr[idx], 1, vs[0]); 798 set_fpr64(&fpu->fpr[idx], 0, vs[1]); 799 #endif 800 break; 801 case KVM_REG_MIPS_MSA_IR: 802 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 803 return -EINVAL; 804 /* Read-only */ 805 break; 806 case KVM_REG_MIPS_MSA_CSR: 807 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 808 return -EINVAL; 809 fpu->msacsr = v; 810 break; 811 812 /* Co-processor 0 registers */ 813 case KVM_REG_MIPS_CP0_INDEX: 814 kvm_write_c0_guest_index(cop0, v); 815 break; 816 case KVM_REG_MIPS_CP0_CONTEXT: 817 kvm_write_c0_guest_context(cop0, v); 818 break; 819 case KVM_REG_MIPS_CP0_USERLOCAL: 820 kvm_write_c0_guest_userlocal(cop0, v); 821 break; 822 case KVM_REG_MIPS_CP0_PAGEMASK: 823 kvm_write_c0_guest_pagemask(cop0, v); 824 break; 825 case KVM_REG_MIPS_CP0_WIRED: 826 kvm_write_c0_guest_wired(cop0, v); 827 break; 828 case KVM_REG_MIPS_CP0_HWRENA: 829 kvm_write_c0_guest_hwrena(cop0, v); 830 break; 831 case KVM_REG_MIPS_CP0_BADVADDR: 832 kvm_write_c0_guest_badvaddr(cop0, v); 833 break; 834 case KVM_REG_MIPS_CP0_ENTRYHI: 835 kvm_write_c0_guest_entryhi(cop0, v); 836 break; 837 case KVM_REG_MIPS_CP0_STATUS: 838 kvm_write_c0_guest_status(cop0, v); 839 break; 840 case KVM_REG_MIPS_CP0_EPC: 841 kvm_write_c0_guest_epc(cop0, v); 842 break; 843 case KVM_REG_MIPS_CP0_PRID: 844 kvm_write_c0_guest_prid(cop0, v); 845 break; 846 case KVM_REG_MIPS_CP0_ERROREPC: 847 kvm_write_c0_guest_errorepc(cop0, v); 848 break; 849 /* registers to be handled specially */ 850 case KVM_REG_MIPS_CP0_COUNT: 851 case KVM_REG_MIPS_CP0_COMPARE: 852 case KVM_REG_MIPS_CP0_CAUSE: 853 case KVM_REG_MIPS_CP0_CONFIG: 854 case KVM_REG_MIPS_CP0_CONFIG1: 855 case KVM_REG_MIPS_CP0_CONFIG2: 856 case KVM_REG_MIPS_CP0_CONFIG3: 857 case KVM_REG_MIPS_CP0_CONFIG4: 858 case KVM_REG_MIPS_CP0_CONFIG5: 859 case KVM_REG_MIPS_COUNT_CTL: 860 case KVM_REG_MIPS_COUNT_RESUME: 861 case KVM_REG_MIPS_COUNT_HZ: 862 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); 863 default: 864 return -EINVAL; 865 } 866 return 0; 867 } 868 869 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 870 struct kvm_enable_cap *cap) 871 { 872 int r = 0; 873 874 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) 875 return -EINVAL; 876 if (cap->flags) 877 return -EINVAL; 878 if (cap->args[0]) 879 return -EINVAL; 880 881 switch (cap->cap) { 882 case KVM_CAP_MIPS_FPU: 883 vcpu->arch.fpu_enabled = true; 884 break; 885 case KVM_CAP_MIPS_MSA: 886 vcpu->arch.msa_enabled = true; 887 break; 888 default: 889 r = -EINVAL; 890 break; 891 } 892 893 return r; 894 } 895 896 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, 897 unsigned long arg) 898 { 899 struct kvm_vcpu *vcpu = filp->private_data; 900 void __user *argp = (void __user *)arg; 901 long r; 902 903 switch (ioctl) { 904 case KVM_SET_ONE_REG: 905 case KVM_GET_ONE_REG: { 906 struct kvm_one_reg reg; 907 908 if (copy_from_user(®, argp, sizeof(reg))) 909 return -EFAULT; 910 if (ioctl == KVM_SET_ONE_REG) 911 return kvm_mips_set_reg(vcpu, ®); 912 else 913 return kvm_mips_get_reg(vcpu, ®); 914 } 915 case KVM_GET_REG_LIST: { 916 struct kvm_reg_list __user *user_list = argp; 917 u64 __user *reg_dest; 918 struct kvm_reg_list reg_list; 919 unsigned n; 920 921 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 922 return -EFAULT; 923 n = reg_list.n; 924 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs); 925 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 926 return -EFAULT; 927 if (n < reg_list.n) 928 return -E2BIG; 929 reg_dest = user_list->reg; 930 if (copy_to_user(reg_dest, kvm_mips_get_one_regs, 931 sizeof(kvm_mips_get_one_regs))) 932 return -EFAULT; 933 return 0; 934 } 935 case KVM_NMI: 936 /* Treat the NMI as a CPU reset */ 937 r = kvm_mips_reset_vcpu(vcpu); 938 break; 939 case KVM_INTERRUPT: 940 { 941 struct kvm_mips_interrupt irq; 942 943 r = -EFAULT; 944 if (copy_from_user(&irq, argp, sizeof(irq))) 945 goto out; 946 947 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, 948 irq.irq); 949 950 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 951 break; 952 } 953 case KVM_ENABLE_CAP: { 954 struct kvm_enable_cap cap; 955 956 r = -EFAULT; 957 if (copy_from_user(&cap, argp, sizeof(cap))) 958 goto out; 959 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 960 break; 961 } 962 default: 963 r = -ENOIOCTLCMD; 964 } 965 966 out: 967 return r; 968 } 969 970 /* Get (and clear) the dirty memory log for a memory slot. */ 971 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 972 { 973 struct kvm_memslots *slots; 974 struct kvm_memory_slot *memslot; 975 unsigned long ga, ga_end; 976 int is_dirty = 0; 977 int r; 978 unsigned long n; 979 980 mutex_lock(&kvm->slots_lock); 981 982 r = kvm_get_dirty_log(kvm, log, &is_dirty); 983 if (r) 984 goto out; 985 986 /* If nothing is dirty, don't bother messing with page tables. */ 987 if (is_dirty) { 988 slots = kvm_memslots(kvm); 989 memslot = id_to_memslot(slots, log->slot); 990 991 ga = memslot->base_gfn << PAGE_SHIFT; 992 ga_end = ga + (memslot->npages << PAGE_SHIFT); 993 994 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga, 995 ga_end); 996 997 n = kvm_dirty_bitmap_bytes(memslot); 998 memset(memslot->dirty_bitmap, 0, n); 999 } 1000 1001 r = 0; 1002 out: 1003 mutex_unlock(&kvm->slots_lock); 1004 return r; 1005 1006 } 1007 1008 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 1009 { 1010 long r; 1011 1012 switch (ioctl) { 1013 default: 1014 r = -ENOIOCTLCMD; 1015 } 1016 1017 return r; 1018 } 1019 1020 int kvm_arch_init(void *opaque) 1021 { 1022 if (kvm_mips_callbacks) { 1023 kvm_err("kvm: module already exists\n"); 1024 return -EEXIST; 1025 } 1026 1027 return kvm_mips_emulation_init(&kvm_mips_callbacks); 1028 } 1029 1030 void kvm_arch_exit(void) 1031 { 1032 kvm_mips_callbacks = NULL; 1033 } 1034 1035 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 1036 struct kvm_sregs *sregs) 1037 { 1038 return -ENOIOCTLCMD; 1039 } 1040 1041 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 1042 struct kvm_sregs *sregs) 1043 { 1044 return -ENOIOCTLCMD; 1045 } 1046 1047 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 1048 { 1049 } 1050 1051 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1052 { 1053 return -ENOIOCTLCMD; 1054 } 1055 1056 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1057 { 1058 return -ENOIOCTLCMD; 1059 } 1060 1061 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 1062 { 1063 return VM_FAULT_SIGBUS; 1064 } 1065 1066 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 1067 { 1068 int r; 1069 1070 switch (ext) { 1071 case KVM_CAP_ONE_REG: 1072 case KVM_CAP_ENABLE_CAP: 1073 r = 1; 1074 break; 1075 case KVM_CAP_COALESCED_MMIO: 1076 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 1077 break; 1078 case KVM_CAP_MIPS_FPU: 1079 r = !!cpu_has_fpu; 1080 break; 1081 case KVM_CAP_MIPS_MSA: 1082 /* 1083 * We don't support MSA vector partitioning yet: 1084 * 1) It would require explicit support which can't be tested 1085 * yet due to lack of support in current hardware. 1086 * 2) It extends the state that would need to be saved/restored 1087 * by e.g. QEMU for migration. 1088 * 1089 * When vector partitioning hardware becomes available, support 1090 * could be added by requiring a flag when enabling 1091 * KVM_CAP_MIPS_MSA capability to indicate that userland knows 1092 * to save/restore the appropriate extra state. 1093 */ 1094 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); 1095 break; 1096 default: 1097 r = 0; 1098 break; 1099 } 1100 return r; 1101 } 1102 1103 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 1104 { 1105 return kvm_mips_pending_timer(vcpu); 1106 } 1107 1108 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) 1109 { 1110 int i; 1111 struct mips_coproc *cop0; 1112 1113 if (!vcpu) 1114 return -1; 1115 1116 kvm_debug("VCPU Register Dump:\n"); 1117 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); 1118 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); 1119 1120 for (i = 0; i < 32; i += 4) { 1121 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, 1122 vcpu->arch.gprs[i], 1123 vcpu->arch.gprs[i + 1], 1124 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); 1125 } 1126 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); 1127 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); 1128 1129 cop0 = vcpu->arch.cop0; 1130 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n", 1131 kvm_read_c0_guest_status(cop0), 1132 kvm_read_c0_guest_cause(cop0)); 1133 1134 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); 1135 1136 return 0; 1137 } 1138 1139 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1140 { 1141 int i; 1142 1143 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1144 vcpu->arch.gprs[i] = regs->gpr[i]; 1145 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ 1146 vcpu->arch.hi = regs->hi; 1147 vcpu->arch.lo = regs->lo; 1148 vcpu->arch.pc = regs->pc; 1149 1150 return 0; 1151 } 1152 1153 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1154 { 1155 int i; 1156 1157 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1158 regs->gpr[i] = vcpu->arch.gprs[i]; 1159 1160 regs->hi = vcpu->arch.hi; 1161 regs->lo = vcpu->arch.lo; 1162 regs->pc = vcpu->arch.pc; 1163 1164 return 0; 1165 } 1166 1167 static void kvm_mips_comparecount_func(unsigned long data) 1168 { 1169 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data; 1170 1171 kvm_mips_callbacks->queue_timer_int(vcpu); 1172 1173 vcpu->arch.wait = 0; 1174 if (waitqueue_active(&vcpu->wq)) 1175 wake_up_interruptible(&vcpu->wq); 1176 } 1177 1178 /* low level hrtimer wake routine */ 1179 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) 1180 { 1181 struct kvm_vcpu *vcpu; 1182 1183 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); 1184 kvm_mips_comparecount_func((unsigned long) vcpu); 1185 return kvm_mips_count_timeout(vcpu); 1186 } 1187 1188 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 1189 { 1190 kvm_mips_callbacks->vcpu_init(vcpu); 1191 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 1192 HRTIMER_MODE_REL); 1193 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 1194 return 0; 1195 } 1196 1197 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 1198 struct kvm_translation *tr) 1199 { 1200 return 0; 1201 } 1202 1203 /* Initial guest state */ 1204 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 1205 { 1206 return kvm_mips_callbacks->vcpu_setup(vcpu); 1207 } 1208 1209 static void kvm_mips_set_c0_status(void) 1210 { 1211 uint32_t status = read_c0_status(); 1212 1213 if (cpu_has_dsp) 1214 status |= (ST0_MX); 1215 1216 write_c0_status(status); 1217 ehb(); 1218 } 1219 1220 /* 1221 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) 1222 */ 1223 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) 1224 { 1225 uint32_t cause = vcpu->arch.host_cp0_cause; 1226 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; 1227 uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc; 1228 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; 1229 enum emulation_result er = EMULATE_DONE; 1230 int ret = RESUME_GUEST; 1231 1232 /* re-enable HTW before enabling interrupts */ 1233 htw_start(); 1234 1235 /* Set a default exit reason */ 1236 run->exit_reason = KVM_EXIT_UNKNOWN; 1237 run->ready_for_interrupt_injection = 1; 1238 1239 /* 1240 * Set the appropriate status bits based on host CPU features, 1241 * before we hit the scheduler 1242 */ 1243 kvm_mips_set_c0_status(); 1244 1245 local_irq_enable(); 1246 1247 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", 1248 cause, opc, run, vcpu); 1249 1250 /* 1251 * Do a privilege check, if in UM most of these exit conditions end up 1252 * causing an exception to be delivered to the Guest Kernel 1253 */ 1254 er = kvm_mips_check_privilege(cause, opc, run, vcpu); 1255 if (er == EMULATE_PRIV_FAIL) { 1256 goto skip_emul; 1257 } else if (er == EMULATE_FAIL) { 1258 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1259 ret = RESUME_HOST; 1260 goto skip_emul; 1261 } 1262 1263 switch (exccode) { 1264 case T_INT: 1265 kvm_debug("[%d]T_INT @ %p\n", vcpu->vcpu_id, opc); 1266 1267 ++vcpu->stat.int_exits; 1268 trace_kvm_exit(vcpu, INT_EXITS); 1269 1270 if (need_resched()) 1271 cond_resched(); 1272 1273 ret = RESUME_GUEST; 1274 break; 1275 1276 case T_COP_UNUSABLE: 1277 kvm_debug("T_COP_UNUSABLE: @ PC: %p\n", opc); 1278 1279 ++vcpu->stat.cop_unusable_exits; 1280 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS); 1281 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); 1282 /* XXXKYMA: Might need to return to user space */ 1283 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) 1284 ret = RESUME_HOST; 1285 break; 1286 1287 case T_TLB_MOD: 1288 ++vcpu->stat.tlbmod_exits; 1289 trace_kvm_exit(vcpu, TLBMOD_EXITS); 1290 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); 1291 break; 1292 1293 case T_TLB_ST_MISS: 1294 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n", 1295 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, 1296 badvaddr); 1297 1298 ++vcpu->stat.tlbmiss_st_exits; 1299 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS); 1300 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); 1301 break; 1302 1303 case T_TLB_LD_MISS: 1304 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", 1305 cause, opc, badvaddr); 1306 1307 ++vcpu->stat.tlbmiss_ld_exits; 1308 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS); 1309 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); 1310 break; 1311 1312 case T_ADDR_ERR_ST: 1313 ++vcpu->stat.addrerr_st_exits; 1314 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS); 1315 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); 1316 break; 1317 1318 case T_ADDR_ERR_LD: 1319 ++vcpu->stat.addrerr_ld_exits; 1320 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS); 1321 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); 1322 break; 1323 1324 case T_SYSCALL: 1325 ++vcpu->stat.syscall_exits; 1326 trace_kvm_exit(vcpu, SYSCALL_EXITS); 1327 ret = kvm_mips_callbacks->handle_syscall(vcpu); 1328 break; 1329 1330 case T_RES_INST: 1331 ++vcpu->stat.resvd_inst_exits; 1332 trace_kvm_exit(vcpu, RESVD_INST_EXITS); 1333 ret = kvm_mips_callbacks->handle_res_inst(vcpu); 1334 break; 1335 1336 case T_BREAK: 1337 ++vcpu->stat.break_inst_exits; 1338 trace_kvm_exit(vcpu, BREAK_INST_EXITS); 1339 ret = kvm_mips_callbacks->handle_break(vcpu); 1340 break; 1341 1342 case T_TRAP: 1343 ++vcpu->stat.trap_inst_exits; 1344 trace_kvm_exit(vcpu, TRAP_INST_EXITS); 1345 ret = kvm_mips_callbacks->handle_trap(vcpu); 1346 break; 1347 1348 case T_MSAFPE: 1349 ++vcpu->stat.msa_fpe_exits; 1350 trace_kvm_exit(vcpu, MSA_FPE_EXITS); 1351 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); 1352 break; 1353 1354 case T_FPE: 1355 ++vcpu->stat.fpe_exits; 1356 trace_kvm_exit(vcpu, FPE_EXITS); 1357 ret = kvm_mips_callbacks->handle_fpe(vcpu); 1358 break; 1359 1360 case T_MSADIS: 1361 ++vcpu->stat.msa_disabled_exits; 1362 trace_kvm_exit(vcpu, MSA_DISABLED_EXITS); 1363 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); 1364 break; 1365 1366 default: 1367 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n", 1368 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr, 1369 kvm_read_c0_guest_status(vcpu->arch.cop0)); 1370 kvm_arch_vcpu_dump_regs(vcpu); 1371 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1372 ret = RESUME_HOST; 1373 break; 1374 1375 } 1376 1377 skip_emul: 1378 local_irq_disable(); 1379 1380 if (er == EMULATE_DONE && !(ret & RESUME_HOST)) 1381 kvm_mips_deliver_interrupts(vcpu, cause); 1382 1383 if (!(ret & RESUME_HOST)) { 1384 /* Only check for signals if not already exiting to userspace */ 1385 if (signal_pending(current)) { 1386 run->exit_reason = KVM_EXIT_INTR; 1387 ret = (-EINTR << 2) | RESUME_HOST; 1388 ++vcpu->stat.signal_exits; 1389 trace_kvm_exit(vcpu, SIGNAL_EXITS); 1390 } 1391 } 1392 1393 if (ret == RESUME_GUEST) { 1394 /* 1395 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context 1396 * is live), restore FCR31 / MSACSR. 1397 * 1398 * This should be before returning to the guest exception 1399 * vector, as it may well cause an [MSA] FP exception if there 1400 * are pending exception bits unmasked. (see 1401 * kvm_mips_csr_die_notifier() for how that is handled). 1402 */ 1403 if (kvm_mips_guest_has_fpu(&vcpu->arch) && 1404 read_c0_status() & ST0_CU1) 1405 __kvm_restore_fcsr(&vcpu->arch); 1406 1407 if (kvm_mips_guest_has_msa(&vcpu->arch) && 1408 read_c0_config5() & MIPS_CONF5_MSAEN) 1409 __kvm_restore_msacsr(&vcpu->arch); 1410 } 1411 1412 /* Disable HTW before returning to guest or host */ 1413 htw_stop(); 1414 1415 return ret; 1416 } 1417 1418 /* Enable FPU for guest and restore context */ 1419 void kvm_own_fpu(struct kvm_vcpu *vcpu) 1420 { 1421 struct mips_coproc *cop0 = vcpu->arch.cop0; 1422 unsigned int sr, cfg5; 1423 1424 preempt_disable(); 1425 1426 sr = kvm_read_c0_guest_status(cop0); 1427 1428 /* 1429 * If MSA state is already live, it is undefined how it interacts with 1430 * FR=0 FPU state, and we don't want to hit reserved instruction 1431 * exceptions trying to save the MSA state later when CU=1 && FR=1, so 1432 * play it safe and save it first. 1433 * 1434 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should 1435 * get called when guest CU1 is set, however we can't trust the guest 1436 * not to clobber the status register directly via the commpage. 1437 */ 1438 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && 1439 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) 1440 kvm_lose_fpu(vcpu); 1441 1442 /* 1443 * Enable FPU for guest 1444 * We set FR and FRE according to guest context 1445 */ 1446 change_c0_status(ST0_CU1 | ST0_FR, sr); 1447 if (cpu_has_fre) { 1448 cfg5 = kvm_read_c0_guest_config5(cop0); 1449 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1450 } 1451 enable_fpu_hazard(); 1452 1453 /* If guest FPU state not active, restore it now */ 1454 if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) { 1455 __kvm_restore_fpu(&vcpu->arch); 1456 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU; 1457 } 1458 1459 preempt_enable(); 1460 } 1461 1462 #ifdef CONFIG_CPU_HAS_MSA 1463 /* Enable MSA for guest and restore context */ 1464 void kvm_own_msa(struct kvm_vcpu *vcpu) 1465 { 1466 struct mips_coproc *cop0 = vcpu->arch.cop0; 1467 unsigned int sr, cfg5; 1468 1469 preempt_disable(); 1470 1471 /* 1472 * Enable FPU if enabled in guest, since we're restoring FPU context 1473 * anyway. We set FR and FRE according to guest context. 1474 */ 1475 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { 1476 sr = kvm_read_c0_guest_status(cop0); 1477 1478 /* 1479 * If FR=0 FPU state is already live, it is undefined how it 1480 * interacts with MSA state, so play it safe and save it first. 1481 */ 1482 if (!(sr & ST0_FR) && 1483 (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | 1484 KVM_MIPS_FPU_MSA)) == KVM_MIPS_FPU_FPU) 1485 kvm_lose_fpu(vcpu); 1486 1487 change_c0_status(ST0_CU1 | ST0_FR, sr); 1488 if (sr & ST0_CU1 && cpu_has_fre) { 1489 cfg5 = kvm_read_c0_guest_config5(cop0); 1490 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1491 } 1492 } 1493 1494 /* Enable MSA for guest */ 1495 set_c0_config5(MIPS_CONF5_MSAEN); 1496 enable_fpu_hazard(); 1497 1498 switch (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA)) { 1499 case KVM_MIPS_FPU_FPU: 1500 /* 1501 * Guest FPU state already loaded, only restore upper MSA state 1502 */ 1503 __kvm_restore_msa_upper(&vcpu->arch); 1504 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA; 1505 break; 1506 case 0: 1507 /* Neither FPU or MSA already active, restore full MSA state */ 1508 __kvm_restore_msa(&vcpu->arch); 1509 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA; 1510 if (kvm_mips_guest_has_fpu(&vcpu->arch)) 1511 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU; 1512 break; 1513 default: 1514 break; 1515 } 1516 1517 preempt_enable(); 1518 } 1519 #endif 1520 1521 /* Drop FPU & MSA without saving it */ 1522 void kvm_drop_fpu(struct kvm_vcpu *vcpu) 1523 { 1524 preempt_disable(); 1525 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) { 1526 disable_msa(); 1527 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_MSA; 1528 } 1529 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) { 1530 clear_c0_status(ST0_CU1 | ST0_FR); 1531 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU; 1532 } 1533 preempt_enable(); 1534 } 1535 1536 /* Save and disable FPU & MSA */ 1537 void kvm_lose_fpu(struct kvm_vcpu *vcpu) 1538 { 1539 /* 1540 * FPU & MSA get disabled in root context (hardware) when it is disabled 1541 * in guest context (software), but the register state in the hardware 1542 * may still be in use. This is why we explicitly re-enable the hardware 1543 * before saving. 1544 */ 1545 1546 preempt_disable(); 1547 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) { 1548 set_c0_config5(MIPS_CONF5_MSAEN); 1549 enable_fpu_hazard(); 1550 1551 __kvm_save_msa(&vcpu->arch); 1552 1553 /* Disable MSA & FPU */ 1554 disable_msa(); 1555 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) 1556 clear_c0_status(ST0_CU1 | ST0_FR); 1557 vcpu->arch.fpu_inuse &= ~(KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA); 1558 } else if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) { 1559 set_c0_status(ST0_CU1); 1560 enable_fpu_hazard(); 1561 1562 __kvm_save_fpu(&vcpu->arch); 1563 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU; 1564 1565 /* Disable FPU */ 1566 clear_c0_status(ST0_CU1 | ST0_FR); 1567 } 1568 preempt_enable(); 1569 } 1570 1571 /* 1572 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are 1573 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP 1574 * exception if cause bits are set in the value being written. 1575 */ 1576 static int kvm_mips_csr_die_notify(struct notifier_block *self, 1577 unsigned long cmd, void *ptr) 1578 { 1579 struct die_args *args = (struct die_args *)ptr; 1580 struct pt_regs *regs = args->regs; 1581 unsigned long pc; 1582 1583 /* Only interested in FPE and MSAFPE */ 1584 if (cmd != DIE_FP && cmd != DIE_MSAFP) 1585 return NOTIFY_DONE; 1586 1587 /* Return immediately if guest context isn't active */ 1588 if (!(current->flags & PF_VCPU)) 1589 return NOTIFY_DONE; 1590 1591 /* Should never get here from user mode */ 1592 BUG_ON(user_mode(regs)); 1593 1594 pc = instruction_pointer(regs); 1595 switch (cmd) { 1596 case DIE_FP: 1597 /* match 2nd instruction in __kvm_restore_fcsr */ 1598 if (pc != (unsigned long)&__kvm_restore_fcsr + 4) 1599 return NOTIFY_DONE; 1600 break; 1601 case DIE_MSAFP: 1602 /* match 2nd/3rd instruction in __kvm_restore_msacsr */ 1603 if (!cpu_has_msa || 1604 pc < (unsigned long)&__kvm_restore_msacsr + 4 || 1605 pc > (unsigned long)&__kvm_restore_msacsr + 8) 1606 return NOTIFY_DONE; 1607 break; 1608 } 1609 1610 /* Move PC forward a little and continue executing */ 1611 instruction_pointer(regs) += 4; 1612 1613 return NOTIFY_STOP; 1614 } 1615 1616 static struct notifier_block kvm_mips_csr_die_notifier = { 1617 .notifier_call = kvm_mips_csr_die_notify, 1618 }; 1619 1620 int __init kvm_mips_init(void) 1621 { 1622 int ret; 1623 1624 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); 1625 1626 if (ret) 1627 return ret; 1628 1629 register_die_notifier(&kvm_mips_csr_die_notifier); 1630 1631 /* 1632 * On MIPS, kernel modules are executed from "mapped space", which 1633 * requires TLBs. The TLB handling code is statically linked with 1634 * the rest of the kernel (tlb.c) to avoid the possibility of 1635 * double faulting. The issue is that the TLB code references 1636 * routines that are part of the the KVM module, which are only 1637 * available once the module is loaded. 1638 */ 1639 kvm_mips_gfn_to_pfn = gfn_to_pfn; 1640 kvm_mips_release_pfn_clean = kvm_release_pfn_clean; 1641 kvm_mips_is_error_pfn = is_error_pfn; 1642 1643 return 0; 1644 } 1645 1646 void __exit kvm_mips_exit(void) 1647 { 1648 kvm_exit(); 1649 1650 kvm_mips_gfn_to_pfn = NULL; 1651 kvm_mips_release_pfn_clean = NULL; 1652 kvm_mips_is_error_pfn = NULL; 1653 1654 unregister_die_notifier(&kvm_mips_csr_die_notifier); 1655 } 1656 1657 module_init(kvm_mips_init); 1658 module_exit(kvm_mips_exit); 1659 1660 EXPORT_TRACEPOINT_SYMBOL(kvm_exit); 1661