1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * KVM/MIPS: MIPS specific KVM APIs 7 * 8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 9 * Authors: Sanjay Lal <sanjayl@kymasys.com> 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/errno.h> 14 #include <linux/err.h> 15 #include <linux/kdebug.h> 16 #include <linux/module.h> 17 #include <linux/uaccess.h> 18 #include <linux/vmalloc.h> 19 #include <linux/sched/signal.h> 20 #include <linux/fs.h> 21 #include <linux/memblock.h> 22 #include <linux/pgtable.h> 23 24 #include <asm/fpu.h> 25 #include <asm/page.h> 26 #include <asm/cacheflush.h> 27 #include <asm/mmu_context.h> 28 #include <asm/pgalloc.h> 29 30 #include <linux/kvm_host.h> 31 32 #include "interrupt.h" 33 #include "commpage.h" 34 35 #define CREATE_TRACE_POINTS 36 #include "trace.h" 37 38 #ifndef VECTORSPACING 39 #define VECTORSPACING 0x100 /* for EI/VI mode */ 40 #endif 41 42 struct kvm_stats_debugfs_item debugfs_entries[] = { 43 VCPU_STAT("wait", wait_exits), 44 VCPU_STAT("cache", cache_exits), 45 VCPU_STAT("signal", signal_exits), 46 VCPU_STAT("interrupt", int_exits), 47 VCPU_STAT("cop_unusable", cop_unusable_exits), 48 VCPU_STAT("tlbmod", tlbmod_exits), 49 VCPU_STAT("tlbmiss_ld", tlbmiss_ld_exits), 50 VCPU_STAT("tlbmiss_st", tlbmiss_st_exits), 51 VCPU_STAT("addrerr_st", addrerr_st_exits), 52 VCPU_STAT("addrerr_ld", addrerr_ld_exits), 53 VCPU_STAT("syscall", syscall_exits), 54 VCPU_STAT("resvd_inst", resvd_inst_exits), 55 VCPU_STAT("break_inst", break_inst_exits), 56 VCPU_STAT("trap_inst", trap_inst_exits), 57 VCPU_STAT("msa_fpe", msa_fpe_exits), 58 VCPU_STAT("fpe", fpe_exits), 59 VCPU_STAT("msa_disabled", msa_disabled_exits), 60 VCPU_STAT("flush_dcache", flush_dcache_exits), 61 #ifdef CONFIG_KVM_MIPS_VZ 62 VCPU_STAT("vz_gpsi", vz_gpsi_exits), 63 VCPU_STAT("vz_gsfc", vz_gsfc_exits), 64 VCPU_STAT("vz_hc", vz_hc_exits), 65 VCPU_STAT("vz_grr", vz_grr_exits), 66 VCPU_STAT("vz_gva", vz_gva_exits), 67 VCPU_STAT("vz_ghfc", vz_ghfc_exits), 68 VCPU_STAT("vz_gpa", vz_gpa_exits), 69 VCPU_STAT("vz_resvd", vz_resvd_exits), 70 VCPU_STAT("vz_cpucfg", vz_cpucfg_exits), 71 #endif 72 VCPU_STAT("halt_successful_poll", halt_successful_poll), 73 VCPU_STAT("halt_attempted_poll", halt_attempted_poll), 74 VCPU_STAT("halt_poll_invalid", halt_poll_invalid), 75 VCPU_STAT("halt_wakeup", halt_wakeup), 76 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns), 77 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns), 78 {NULL} 79 }; 80 81 bool kvm_trace_guest_mode_change; 82 83 int kvm_guest_mode_change_trace_reg(void) 84 { 85 kvm_trace_guest_mode_change = true; 86 return 0; 87 } 88 89 void kvm_guest_mode_change_trace_unreg(void) 90 { 91 kvm_trace_guest_mode_change = false; 92 } 93 94 /* 95 * XXXKYMA: We are simulatoring a processor that has the WII bit set in 96 * Config7, so we are "runnable" if interrupts are pending 97 */ 98 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 99 { 100 return !!(vcpu->arch.pending_exceptions); 101 } 102 103 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 104 { 105 return false; 106 } 107 108 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 109 { 110 return 1; 111 } 112 113 int kvm_arch_hardware_enable(void) 114 { 115 return kvm_mips_callbacks->hardware_enable(); 116 } 117 118 void kvm_arch_hardware_disable(void) 119 { 120 kvm_mips_callbacks->hardware_disable(); 121 } 122 123 int kvm_arch_hardware_setup(void *opaque) 124 { 125 return 0; 126 } 127 128 int kvm_arch_check_processor_compat(void *opaque) 129 { 130 return 0; 131 } 132 133 extern void kvm_init_loongson_ipi(struct kvm *kvm); 134 135 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 136 { 137 switch (type) { 138 #ifdef CONFIG_KVM_MIPS_VZ 139 case KVM_VM_MIPS_VZ: 140 #else 141 case KVM_VM_MIPS_TE: 142 #endif 143 break; 144 default: 145 /* Unsupported KVM type */ 146 return -EINVAL; 147 }; 148 149 /* Allocate page table to map GPA -> RPA */ 150 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc(); 151 if (!kvm->arch.gpa_mm.pgd) 152 return -ENOMEM; 153 154 #ifdef CONFIG_CPU_LOONGSON64 155 kvm_init_loongson_ipi(kvm); 156 #endif 157 158 return 0; 159 } 160 161 void kvm_mips_free_vcpus(struct kvm *kvm) 162 { 163 unsigned int i; 164 struct kvm_vcpu *vcpu; 165 166 kvm_for_each_vcpu(i, vcpu, kvm) { 167 kvm_vcpu_destroy(vcpu); 168 } 169 170 mutex_lock(&kvm->lock); 171 172 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 173 kvm->vcpus[i] = NULL; 174 175 atomic_set(&kvm->online_vcpus, 0); 176 177 mutex_unlock(&kvm->lock); 178 } 179 180 static void kvm_mips_free_gpa_pt(struct kvm *kvm) 181 { 182 /* It should always be safe to remove after flushing the whole range */ 183 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0)); 184 pgd_free(NULL, kvm->arch.gpa_mm.pgd); 185 } 186 187 void kvm_arch_destroy_vm(struct kvm *kvm) 188 { 189 kvm_mips_free_vcpus(kvm); 190 kvm_mips_free_gpa_pt(kvm); 191 } 192 193 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, 194 unsigned long arg) 195 { 196 return -ENOIOCTLCMD; 197 } 198 199 void kvm_arch_flush_shadow_all(struct kvm *kvm) 200 { 201 /* Flush whole GPA */ 202 kvm_mips_flush_gpa_pt(kvm, 0, ~0); 203 204 /* Let implementation do the rest */ 205 kvm_mips_callbacks->flush_shadow_all(kvm); 206 } 207 208 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 209 struct kvm_memory_slot *slot) 210 { 211 /* 212 * The slot has been made invalid (ready for moving or deletion), so we 213 * need to ensure that it can no longer be accessed by any guest VCPUs. 214 */ 215 216 spin_lock(&kvm->mmu_lock); 217 /* Flush slot from GPA */ 218 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn, 219 slot->base_gfn + slot->npages - 1); 220 /* Let implementation do the rest */ 221 kvm_mips_callbacks->flush_shadow_memslot(kvm, slot); 222 spin_unlock(&kvm->mmu_lock); 223 } 224 225 int kvm_arch_prepare_memory_region(struct kvm *kvm, 226 struct kvm_memory_slot *memslot, 227 const struct kvm_userspace_memory_region *mem, 228 enum kvm_mr_change change) 229 { 230 return 0; 231 } 232 233 void kvm_arch_commit_memory_region(struct kvm *kvm, 234 const struct kvm_userspace_memory_region *mem, 235 struct kvm_memory_slot *old, 236 const struct kvm_memory_slot *new, 237 enum kvm_mr_change change) 238 { 239 int needs_flush; 240 241 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n", 242 __func__, kvm, mem->slot, mem->guest_phys_addr, 243 mem->memory_size, mem->userspace_addr); 244 245 /* 246 * If dirty page logging is enabled, write protect all pages in the slot 247 * ready for dirty logging. 248 * 249 * There is no need to do this in any of the following cases: 250 * CREATE: No dirty mappings will already exist. 251 * MOVE/DELETE: The old mappings will already have been cleaned up by 252 * kvm_arch_flush_shadow_memslot() 253 */ 254 if (change == KVM_MR_FLAGS_ONLY && 255 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 256 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) { 257 spin_lock(&kvm->mmu_lock); 258 /* Write protect GPA page table entries */ 259 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn, 260 new->base_gfn + new->npages - 1); 261 /* Let implementation do the rest */ 262 if (needs_flush) 263 kvm_mips_callbacks->flush_shadow_memslot(kvm, new); 264 spin_unlock(&kvm->mmu_lock); 265 } 266 } 267 268 static inline void dump_handler(const char *symbol, void *start, void *end) 269 { 270 u32 *p; 271 272 pr_debug("LEAF(%s)\n", symbol); 273 274 pr_debug("\t.set push\n"); 275 pr_debug("\t.set noreorder\n"); 276 277 for (p = start; p < (u32 *)end; ++p) 278 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p); 279 280 pr_debug("\t.set\tpop\n"); 281 282 pr_debug("\tEND(%s)\n", symbol); 283 } 284 285 /* low level hrtimer wake routine */ 286 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) 287 { 288 struct kvm_vcpu *vcpu; 289 290 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); 291 292 kvm_mips_callbacks->queue_timer_int(vcpu); 293 294 vcpu->arch.wait = 0; 295 rcuwait_wake_up(&vcpu->wait); 296 297 return kvm_mips_count_timeout(vcpu); 298 } 299 300 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 301 { 302 return 0; 303 } 304 305 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 306 { 307 int err, size; 308 void *gebase, *p, *handler, *refill_start, *refill_end; 309 int i; 310 311 kvm_debug("kvm @ %p: create cpu %d at %p\n", 312 vcpu->kvm, vcpu->vcpu_id, vcpu); 313 314 err = kvm_mips_callbacks->vcpu_init(vcpu); 315 if (err) 316 return err; 317 318 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 319 HRTIMER_MODE_REL); 320 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 321 322 /* 323 * Allocate space for host mode exception handlers that handle 324 * guest mode exits 325 */ 326 if (cpu_has_veic || cpu_has_vint) 327 size = 0x200 + VECTORSPACING * 64; 328 else 329 size = 0x4000; 330 331 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); 332 333 if (!gebase) { 334 err = -ENOMEM; 335 goto out_uninit_vcpu; 336 } 337 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", 338 ALIGN(size, PAGE_SIZE), gebase); 339 340 /* 341 * Check new ebase actually fits in CP0_EBase. The lack of a write gate 342 * limits us to the low 512MB of physical address space. If the memory 343 * we allocate is out of range, just give up now. 344 */ 345 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) { 346 kvm_err("CP0_EBase.WG required for guest exception base %pK\n", 347 gebase); 348 err = -ENOMEM; 349 goto out_free_gebase; 350 } 351 352 /* Save new ebase */ 353 vcpu->arch.guest_ebase = gebase; 354 355 /* Build guest exception vectors dynamically in unmapped memory */ 356 handler = gebase + 0x2000; 357 358 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */ 359 refill_start = gebase; 360 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT)) 361 refill_start += 0x080; 362 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler); 363 364 /* General Exception Entry point */ 365 kvm_mips_build_exception(gebase + 0x180, handler); 366 367 /* For vectored interrupts poke the exception code @ all offsets 0-7 */ 368 for (i = 0; i < 8; i++) { 369 kvm_debug("L1 Vectored handler @ %p\n", 370 gebase + 0x200 + (i * VECTORSPACING)); 371 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING, 372 handler); 373 } 374 375 /* General exit handler */ 376 p = handler; 377 p = kvm_mips_build_exit(p); 378 379 /* Guest entry routine */ 380 vcpu->arch.vcpu_run = p; 381 p = kvm_mips_build_vcpu_run(p); 382 383 /* Dump the generated code */ 384 pr_debug("#include <asm/asm.h>\n"); 385 pr_debug("#include <asm/regdef.h>\n"); 386 pr_debug("\n"); 387 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p); 388 dump_handler("kvm_tlb_refill", refill_start, refill_end); 389 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200); 390 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run); 391 392 /* Invalidate the icache for these ranges */ 393 flush_icache_range((unsigned long)gebase, 394 (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); 395 396 /* 397 * Allocate comm page for guest kernel, a TLB will be reserved for 398 * mapping GVA @ 0xFFFF8000 to this page 399 */ 400 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL); 401 402 if (!vcpu->arch.kseg0_commpage) { 403 err = -ENOMEM; 404 goto out_free_gebase; 405 } 406 407 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage); 408 kvm_mips_commpage_init(vcpu); 409 410 /* Init */ 411 vcpu->arch.last_sched_cpu = -1; 412 vcpu->arch.last_exec_cpu = -1; 413 414 /* Initial guest state */ 415 err = kvm_mips_callbacks->vcpu_setup(vcpu); 416 if (err) 417 goto out_free_commpage; 418 419 return 0; 420 421 out_free_commpage: 422 kfree(vcpu->arch.kseg0_commpage); 423 out_free_gebase: 424 kfree(gebase); 425 out_uninit_vcpu: 426 kvm_mips_callbacks->vcpu_uninit(vcpu); 427 return err; 428 } 429 430 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 431 { 432 hrtimer_cancel(&vcpu->arch.comparecount_timer); 433 434 kvm_mips_dump_stats(vcpu); 435 436 kvm_mmu_free_memory_caches(vcpu); 437 kfree(vcpu->arch.guest_ebase); 438 kfree(vcpu->arch.kseg0_commpage); 439 440 kvm_mips_callbacks->vcpu_uninit(vcpu); 441 } 442 443 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 444 struct kvm_guest_debug *dbg) 445 { 446 return -ENOIOCTLCMD; 447 } 448 449 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 450 { 451 struct kvm_run *run = vcpu->run; 452 int r = -EINTR; 453 454 vcpu_load(vcpu); 455 456 kvm_sigset_activate(vcpu); 457 458 if (vcpu->mmio_needed) { 459 if (!vcpu->mmio_is_write) 460 kvm_mips_complete_mmio_load(vcpu, run); 461 vcpu->mmio_needed = 0; 462 } 463 464 if (run->immediate_exit) 465 goto out; 466 467 lose_fpu(1); 468 469 local_irq_disable(); 470 guest_enter_irqoff(); 471 trace_kvm_enter(vcpu); 472 473 /* 474 * Make sure the read of VCPU requests in vcpu_run() callback is not 475 * reordered ahead of the write to vcpu->mode, or we could miss a TLB 476 * flush request while the requester sees the VCPU as outside of guest 477 * mode and not needing an IPI. 478 */ 479 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 480 481 r = kvm_mips_callbacks->vcpu_run(run, vcpu); 482 483 trace_kvm_out(vcpu); 484 guest_exit_irqoff(); 485 local_irq_enable(); 486 487 out: 488 kvm_sigset_deactivate(vcpu); 489 490 vcpu_put(vcpu); 491 return r; 492 } 493 494 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 495 struct kvm_mips_interrupt *irq) 496 { 497 int intr = (int)irq->irq; 498 struct kvm_vcpu *dvcpu = NULL; 499 500 if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] || 501 intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] || 502 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) || 503 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2])) 504 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, 505 (int)intr); 506 507 if (irq->cpu == -1) 508 dvcpu = vcpu; 509 else 510 dvcpu = vcpu->kvm->vcpus[irq->cpu]; 511 512 if (intr == 2 || intr == 3 || intr == 4 || intr == 6) { 513 kvm_mips_callbacks->queue_io_int(dvcpu, irq); 514 515 } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) { 516 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); 517 } else { 518 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, 519 irq->cpu, irq->irq); 520 return -EINVAL; 521 } 522 523 dvcpu->arch.wait = 0; 524 525 rcuwait_wake_up(&dvcpu->wait); 526 527 return 0; 528 } 529 530 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 531 struct kvm_mp_state *mp_state) 532 { 533 return -ENOIOCTLCMD; 534 } 535 536 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 537 struct kvm_mp_state *mp_state) 538 { 539 return -ENOIOCTLCMD; 540 } 541 542 static u64 kvm_mips_get_one_regs[] = { 543 KVM_REG_MIPS_R0, 544 KVM_REG_MIPS_R1, 545 KVM_REG_MIPS_R2, 546 KVM_REG_MIPS_R3, 547 KVM_REG_MIPS_R4, 548 KVM_REG_MIPS_R5, 549 KVM_REG_MIPS_R6, 550 KVM_REG_MIPS_R7, 551 KVM_REG_MIPS_R8, 552 KVM_REG_MIPS_R9, 553 KVM_REG_MIPS_R10, 554 KVM_REG_MIPS_R11, 555 KVM_REG_MIPS_R12, 556 KVM_REG_MIPS_R13, 557 KVM_REG_MIPS_R14, 558 KVM_REG_MIPS_R15, 559 KVM_REG_MIPS_R16, 560 KVM_REG_MIPS_R17, 561 KVM_REG_MIPS_R18, 562 KVM_REG_MIPS_R19, 563 KVM_REG_MIPS_R20, 564 KVM_REG_MIPS_R21, 565 KVM_REG_MIPS_R22, 566 KVM_REG_MIPS_R23, 567 KVM_REG_MIPS_R24, 568 KVM_REG_MIPS_R25, 569 KVM_REG_MIPS_R26, 570 KVM_REG_MIPS_R27, 571 KVM_REG_MIPS_R28, 572 KVM_REG_MIPS_R29, 573 KVM_REG_MIPS_R30, 574 KVM_REG_MIPS_R31, 575 576 #ifndef CONFIG_CPU_MIPSR6 577 KVM_REG_MIPS_HI, 578 KVM_REG_MIPS_LO, 579 #endif 580 KVM_REG_MIPS_PC, 581 }; 582 583 static u64 kvm_mips_get_one_regs_fpu[] = { 584 KVM_REG_MIPS_FCR_IR, 585 KVM_REG_MIPS_FCR_CSR, 586 }; 587 588 static u64 kvm_mips_get_one_regs_msa[] = { 589 KVM_REG_MIPS_MSA_IR, 590 KVM_REG_MIPS_MSA_CSR, 591 }; 592 593 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu) 594 { 595 unsigned long ret; 596 597 ret = ARRAY_SIZE(kvm_mips_get_one_regs); 598 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 599 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48; 600 /* odd doubles */ 601 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64) 602 ret += 16; 603 } 604 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) 605 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32; 606 ret += kvm_mips_callbacks->num_regs(vcpu); 607 608 return ret; 609 } 610 611 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) 612 { 613 u64 index; 614 unsigned int i; 615 616 if (copy_to_user(indices, kvm_mips_get_one_regs, 617 sizeof(kvm_mips_get_one_regs))) 618 return -EFAULT; 619 indices += ARRAY_SIZE(kvm_mips_get_one_regs); 620 621 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 622 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu, 623 sizeof(kvm_mips_get_one_regs_fpu))) 624 return -EFAULT; 625 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu); 626 627 for (i = 0; i < 32; ++i) { 628 index = KVM_REG_MIPS_FPR_32(i); 629 if (copy_to_user(indices, &index, sizeof(index))) 630 return -EFAULT; 631 ++indices; 632 633 /* skip odd doubles if no F64 */ 634 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64)) 635 continue; 636 637 index = KVM_REG_MIPS_FPR_64(i); 638 if (copy_to_user(indices, &index, sizeof(index))) 639 return -EFAULT; 640 ++indices; 641 } 642 } 643 644 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) { 645 if (copy_to_user(indices, kvm_mips_get_one_regs_msa, 646 sizeof(kvm_mips_get_one_regs_msa))) 647 return -EFAULT; 648 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa); 649 650 for (i = 0; i < 32; ++i) { 651 index = KVM_REG_MIPS_VEC_128(i); 652 if (copy_to_user(indices, &index, sizeof(index))) 653 return -EFAULT; 654 ++indices; 655 } 656 } 657 658 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices); 659 } 660 661 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 662 const struct kvm_one_reg *reg) 663 { 664 struct mips_coproc *cop0 = vcpu->arch.cop0; 665 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 666 int ret; 667 s64 v; 668 s64 vs[2]; 669 unsigned int idx; 670 671 switch (reg->id) { 672 /* General purpose registers */ 673 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: 674 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; 675 break; 676 #ifndef CONFIG_CPU_MIPSR6 677 case KVM_REG_MIPS_HI: 678 v = (long)vcpu->arch.hi; 679 break; 680 case KVM_REG_MIPS_LO: 681 v = (long)vcpu->arch.lo; 682 break; 683 #endif 684 case KVM_REG_MIPS_PC: 685 v = (long)vcpu->arch.pc; 686 break; 687 688 /* Floating point registers */ 689 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 690 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 691 return -EINVAL; 692 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 693 /* Odd singles in top of even double when FR=0 */ 694 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 695 v = get_fpr32(&fpu->fpr[idx], 0); 696 else 697 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); 698 break; 699 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 700 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 701 return -EINVAL; 702 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 703 /* Can't access odd doubles in FR=0 mode */ 704 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 705 return -EINVAL; 706 v = get_fpr64(&fpu->fpr[idx], 0); 707 break; 708 case KVM_REG_MIPS_FCR_IR: 709 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 710 return -EINVAL; 711 v = boot_cpu_data.fpu_id; 712 break; 713 case KVM_REG_MIPS_FCR_CSR: 714 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 715 return -EINVAL; 716 v = fpu->fcr31; 717 break; 718 719 /* MIPS SIMD Architecture (MSA) registers */ 720 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 721 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 722 return -EINVAL; 723 /* Can't access MSA registers in FR=0 mode */ 724 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) 725 return -EINVAL; 726 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 727 #ifdef CONFIG_CPU_LITTLE_ENDIAN 728 /* least significant byte first */ 729 vs[0] = get_fpr64(&fpu->fpr[idx], 0); 730 vs[1] = get_fpr64(&fpu->fpr[idx], 1); 731 #else 732 /* most significant byte first */ 733 vs[0] = get_fpr64(&fpu->fpr[idx], 1); 734 vs[1] = get_fpr64(&fpu->fpr[idx], 0); 735 #endif 736 break; 737 case KVM_REG_MIPS_MSA_IR: 738 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 739 return -EINVAL; 740 v = boot_cpu_data.msa_id; 741 break; 742 case KVM_REG_MIPS_MSA_CSR: 743 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 744 return -EINVAL; 745 v = fpu->msacsr; 746 break; 747 748 /* registers to be handled specially */ 749 default: 750 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); 751 if (ret) 752 return ret; 753 break; 754 } 755 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 756 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 757 758 return put_user(v, uaddr64); 759 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 760 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 761 u32 v32 = (u32)v; 762 763 return put_user(v32, uaddr32); 764 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 765 void __user *uaddr = (void __user *)(long)reg->addr; 766 767 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0; 768 } else { 769 return -EINVAL; 770 } 771 } 772 773 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 774 const struct kvm_one_reg *reg) 775 { 776 struct mips_coproc *cop0 = vcpu->arch.cop0; 777 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 778 s64 v; 779 s64 vs[2]; 780 unsigned int idx; 781 782 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 783 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 784 785 if (get_user(v, uaddr64) != 0) 786 return -EFAULT; 787 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 788 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 789 s32 v32; 790 791 if (get_user(v32, uaddr32) != 0) 792 return -EFAULT; 793 v = (s64)v32; 794 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 795 void __user *uaddr = (void __user *)(long)reg->addr; 796 797 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0; 798 } else { 799 return -EINVAL; 800 } 801 802 switch (reg->id) { 803 /* General purpose registers */ 804 case KVM_REG_MIPS_R0: 805 /* Silently ignore requests to set $0 */ 806 break; 807 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: 808 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; 809 break; 810 #ifndef CONFIG_CPU_MIPSR6 811 case KVM_REG_MIPS_HI: 812 vcpu->arch.hi = v; 813 break; 814 case KVM_REG_MIPS_LO: 815 vcpu->arch.lo = v; 816 break; 817 #endif 818 case KVM_REG_MIPS_PC: 819 vcpu->arch.pc = v; 820 break; 821 822 /* Floating point registers */ 823 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 824 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 825 return -EINVAL; 826 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 827 /* Odd singles in top of even double when FR=0 */ 828 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 829 set_fpr32(&fpu->fpr[idx], 0, v); 830 else 831 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); 832 break; 833 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 834 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 835 return -EINVAL; 836 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 837 /* Can't access odd doubles in FR=0 mode */ 838 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 839 return -EINVAL; 840 set_fpr64(&fpu->fpr[idx], 0, v); 841 break; 842 case KVM_REG_MIPS_FCR_IR: 843 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 844 return -EINVAL; 845 /* Read-only */ 846 break; 847 case KVM_REG_MIPS_FCR_CSR: 848 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 849 return -EINVAL; 850 fpu->fcr31 = v; 851 break; 852 853 /* MIPS SIMD Architecture (MSA) registers */ 854 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 855 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 856 return -EINVAL; 857 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 858 #ifdef CONFIG_CPU_LITTLE_ENDIAN 859 /* least significant byte first */ 860 set_fpr64(&fpu->fpr[idx], 0, vs[0]); 861 set_fpr64(&fpu->fpr[idx], 1, vs[1]); 862 #else 863 /* most significant byte first */ 864 set_fpr64(&fpu->fpr[idx], 1, vs[0]); 865 set_fpr64(&fpu->fpr[idx], 0, vs[1]); 866 #endif 867 break; 868 case KVM_REG_MIPS_MSA_IR: 869 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 870 return -EINVAL; 871 /* Read-only */ 872 break; 873 case KVM_REG_MIPS_MSA_CSR: 874 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 875 return -EINVAL; 876 fpu->msacsr = v; 877 break; 878 879 /* registers to be handled specially */ 880 default: 881 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); 882 } 883 return 0; 884 } 885 886 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 887 struct kvm_enable_cap *cap) 888 { 889 int r = 0; 890 891 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) 892 return -EINVAL; 893 if (cap->flags) 894 return -EINVAL; 895 if (cap->args[0]) 896 return -EINVAL; 897 898 switch (cap->cap) { 899 case KVM_CAP_MIPS_FPU: 900 vcpu->arch.fpu_enabled = true; 901 break; 902 case KVM_CAP_MIPS_MSA: 903 vcpu->arch.msa_enabled = true; 904 break; 905 default: 906 r = -EINVAL; 907 break; 908 } 909 910 return r; 911 } 912 913 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl, 914 unsigned long arg) 915 { 916 struct kvm_vcpu *vcpu = filp->private_data; 917 void __user *argp = (void __user *)arg; 918 919 if (ioctl == KVM_INTERRUPT) { 920 struct kvm_mips_interrupt irq; 921 922 if (copy_from_user(&irq, argp, sizeof(irq))) 923 return -EFAULT; 924 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, 925 irq.irq); 926 927 return kvm_vcpu_ioctl_interrupt(vcpu, &irq); 928 } 929 930 return -ENOIOCTLCMD; 931 } 932 933 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, 934 unsigned long arg) 935 { 936 struct kvm_vcpu *vcpu = filp->private_data; 937 void __user *argp = (void __user *)arg; 938 long r; 939 940 vcpu_load(vcpu); 941 942 switch (ioctl) { 943 case KVM_SET_ONE_REG: 944 case KVM_GET_ONE_REG: { 945 struct kvm_one_reg reg; 946 947 r = -EFAULT; 948 if (copy_from_user(®, argp, sizeof(reg))) 949 break; 950 if (ioctl == KVM_SET_ONE_REG) 951 r = kvm_mips_set_reg(vcpu, ®); 952 else 953 r = kvm_mips_get_reg(vcpu, ®); 954 break; 955 } 956 case KVM_GET_REG_LIST: { 957 struct kvm_reg_list __user *user_list = argp; 958 struct kvm_reg_list reg_list; 959 unsigned n; 960 961 r = -EFAULT; 962 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 963 break; 964 n = reg_list.n; 965 reg_list.n = kvm_mips_num_regs(vcpu); 966 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 967 break; 968 r = -E2BIG; 969 if (n < reg_list.n) 970 break; 971 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg); 972 break; 973 } 974 case KVM_ENABLE_CAP: { 975 struct kvm_enable_cap cap; 976 977 r = -EFAULT; 978 if (copy_from_user(&cap, argp, sizeof(cap))) 979 break; 980 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 981 break; 982 } 983 default: 984 r = -ENOIOCTLCMD; 985 } 986 987 vcpu_put(vcpu); 988 return r; 989 } 990 991 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) 992 { 993 994 } 995 996 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, 997 struct kvm_memory_slot *memslot) 998 { 999 /* Let implementation handle TLB/GVA invalidation */ 1000 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot); 1001 } 1002 1003 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 1004 { 1005 long r; 1006 1007 switch (ioctl) { 1008 default: 1009 r = -ENOIOCTLCMD; 1010 } 1011 1012 return r; 1013 } 1014 1015 int kvm_arch_init(void *opaque) 1016 { 1017 if (kvm_mips_callbacks) { 1018 kvm_err("kvm: module already exists\n"); 1019 return -EEXIST; 1020 } 1021 1022 return kvm_mips_emulation_init(&kvm_mips_callbacks); 1023 } 1024 1025 void kvm_arch_exit(void) 1026 { 1027 kvm_mips_callbacks = NULL; 1028 } 1029 1030 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 1031 struct kvm_sregs *sregs) 1032 { 1033 return -ENOIOCTLCMD; 1034 } 1035 1036 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 1037 struct kvm_sregs *sregs) 1038 { 1039 return -ENOIOCTLCMD; 1040 } 1041 1042 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 1043 { 1044 } 1045 1046 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1047 { 1048 return -ENOIOCTLCMD; 1049 } 1050 1051 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1052 { 1053 return -ENOIOCTLCMD; 1054 } 1055 1056 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 1057 { 1058 return VM_FAULT_SIGBUS; 1059 } 1060 1061 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 1062 { 1063 int r; 1064 1065 switch (ext) { 1066 case KVM_CAP_ONE_REG: 1067 case KVM_CAP_ENABLE_CAP: 1068 case KVM_CAP_READONLY_MEM: 1069 case KVM_CAP_SYNC_MMU: 1070 case KVM_CAP_IMMEDIATE_EXIT: 1071 r = 1; 1072 break; 1073 case KVM_CAP_NR_VCPUS: 1074 r = num_online_cpus(); 1075 break; 1076 case KVM_CAP_MAX_VCPUS: 1077 r = KVM_MAX_VCPUS; 1078 break; 1079 case KVM_CAP_MAX_VCPU_ID: 1080 r = KVM_MAX_VCPU_ID; 1081 break; 1082 case KVM_CAP_MIPS_FPU: 1083 /* We don't handle systems with inconsistent cpu_has_fpu */ 1084 r = !!raw_cpu_has_fpu; 1085 break; 1086 case KVM_CAP_MIPS_MSA: 1087 /* 1088 * We don't support MSA vector partitioning yet: 1089 * 1) It would require explicit support which can't be tested 1090 * yet due to lack of support in current hardware. 1091 * 2) It extends the state that would need to be saved/restored 1092 * by e.g. QEMU for migration. 1093 * 1094 * When vector partitioning hardware becomes available, support 1095 * could be added by requiring a flag when enabling 1096 * KVM_CAP_MIPS_MSA capability to indicate that userland knows 1097 * to save/restore the appropriate extra state. 1098 */ 1099 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); 1100 break; 1101 default: 1102 r = kvm_mips_callbacks->check_extension(kvm, ext); 1103 break; 1104 } 1105 return r; 1106 } 1107 1108 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 1109 { 1110 return kvm_mips_pending_timer(vcpu) || 1111 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI; 1112 } 1113 1114 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) 1115 { 1116 int i; 1117 struct mips_coproc *cop0; 1118 1119 if (!vcpu) 1120 return -1; 1121 1122 kvm_debug("VCPU Register Dump:\n"); 1123 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); 1124 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); 1125 1126 for (i = 0; i < 32; i += 4) { 1127 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, 1128 vcpu->arch.gprs[i], 1129 vcpu->arch.gprs[i + 1], 1130 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); 1131 } 1132 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); 1133 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); 1134 1135 cop0 = vcpu->arch.cop0; 1136 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n", 1137 kvm_read_c0_guest_status(cop0), 1138 kvm_read_c0_guest_cause(cop0)); 1139 1140 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); 1141 1142 return 0; 1143 } 1144 1145 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1146 { 1147 int i; 1148 1149 vcpu_load(vcpu); 1150 1151 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1152 vcpu->arch.gprs[i] = regs->gpr[i]; 1153 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ 1154 vcpu->arch.hi = regs->hi; 1155 vcpu->arch.lo = regs->lo; 1156 vcpu->arch.pc = regs->pc; 1157 1158 vcpu_put(vcpu); 1159 return 0; 1160 } 1161 1162 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1163 { 1164 int i; 1165 1166 vcpu_load(vcpu); 1167 1168 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1169 regs->gpr[i] = vcpu->arch.gprs[i]; 1170 1171 regs->hi = vcpu->arch.hi; 1172 regs->lo = vcpu->arch.lo; 1173 regs->pc = vcpu->arch.pc; 1174 1175 vcpu_put(vcpu); 1176 return 0; 1177 } 1178 1179 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 1180 struct kvm_translation *tr) 1181 { 1182 return 0; 1183 } 1184 1185 static void kvm_mips_set_c0_status(void) 1186 { 1187 u32 status = read_c0_status(); 1188 1189 if (cpu_has_dsp) 1190 status |= (ST0_MX); 1191 1192 write_c0_status(status); 1193 ehb(); 1194 } 1195 1196 /* 1197 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) 1198 */ 1199 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) 1200 { 1201 u32 cause = vcpu->arch.host_cp0_cause; 1202 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; 1203 u32 __user *opc = (u32 __user *) vcpu->arch.pc; 1204 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; 1205 enum emulation_result er = EMULATE_DONE; 1206 u32 inst; 1207 int ret = RESUME_GUEST; 1208 1209 vcpu->mode = OUTSIDE_GUEST_MODE; 1210 1211 /* re-enable HTW before enabling interrupts */ 1212 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) 1213 htw_start(); 1214 1215 /* Set a default exit reason */ 1216 run->exit_reason = KVM_EXIT_UNKNOWN; 1217 run->ready_for_interrupt_injection = 1; 1218 1219 /* 1220 * Set the appropriate status bits based on host CPU features, 1221 * before we hit the scheduler 1222 */ 1223 kvm_mips_set_c0_status(); 1224 1225 local_irq_enable(); 1226 1227 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", 1228 cause, opc, run, vcpu); 1229 trace_kvm_exit(vcpu, exccode); 1230 1231 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1232 /* 1233 * Do a privilege check, if in UM most of these exit conditions 1234 * end up causing an exception to be delivered to the Guest 1235 * Kernel 1236 */ 1237 er = kvm_mips_check_privilege(cause, opc, run, vcpu); 1238 if (er == EMULATE_PRIV_FAIL) { 1239 goto skip_emul; 1240 } else if (er == EMULATE_FAIL) { 1241 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1242 ret = RESUME_HOST; 1243 goto skip_emul; 1244 } 1245 } 1246 1247 switch (exccode) { 1248 case EXCCODE_INT: 1249 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc); 1250 1251 ++vcpu->stat.int_exits; 1252 1253 if (need_resched()) 1254 cond_resched(); 1255 1256 ret = RESUME_GUEST; 1257 break; 1258 1259 case EXCCODE_CPU: 1260 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc); 1261 1262 ++vcpu->stat.cop_unusable_exits; 1263 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); 1264 /* XXXKYMA: Might need to return to user space */ 1265 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) 1266 ret = RESUME_HOST; 1267 break; 1268 1269 case EXCCODE_MOD: 1270 ++vcpu->stat.tlbmod_exits; 1271 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); 1272 break; 1273 1274 case EXCCODE_TLBS: 1275 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n", 1276 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, 1277 badvaddr); 1278 1279 ++vcpu->stat.tlbmiss_st_exits; 1280 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); 1281 break; 1282 1283 case EXCCODE_TLBL: 1284 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", 1285 cause, opc, badvaddr); 1286 1287 ++vcpu->stat.tlbmiss_ld_exits; 1288 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); 1289 break; 1290 1291 case EXCCODE_ADES: 1292 ++vcpu->stat.addrerr_st_exits; 1293 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); 1294 break; 1295 1296 case EXCCODE_ADEL: 1297 ++vcpu->stat.addrerr_ld_exits; 1298 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); 1299 break; 1300 1301 case EXCCODE_SYS: 1302 ++vcpu->stat.syscall_exits; 1303 ret = kvm_mips_callbacks->handle_syscall(vcpu); 1304 break; 1305 1306 case EXCCODE_RI: 1307 ++vcpu->stat.resvd_inst_exits; 1308 ret = kvm_mips_callbacks->handle_res_inst(vcpu); 1309 break; 1310 1311 case EXCCODE_BP: 1312 ++vcpu->stat.break_inst_exits; 1313 ret = kvm_mips_callbacks->handle_break(vcpu); 1314 break; 1315 1316 case EXCCODE_TR: 1317 ++vcpu->stat.trap_inst_exits; 1318 ret = kvm_mips_callbacks->handle_trap(vcpu); 1319 break; 1320 1321 case EXCCODE_MSAFPE: 1322 ++vcpu->stat.msa_fpe_exits; 1323 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); 1324 break; 1325 1326 case EXCCODE_FPE: 1327 ++vcpu->stat.fpe_exits; 1328 ret = kvm_mips_callbacks->handle_fpe(vcpu); 1329 break; 1330 1331 case EXCCODE_MSADIS: 1332 ++vcpu->stat.msa_disabled_exits; 1333 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); 1334 break; 1335 1336 case EXCCODE_GE: 1337 /* defer exit accounting to handler */ 1338 ret = kvm_mips_callbacks->handle_guest_exit(vcpu); 1339 break; 1340 1341 default: 1342 if (cause & CAUSEF_BD) 1343 opc += 1; 1344 inst = 0; 1345 kvm_get_badinstr(opc, vcpu, &inst); 1346 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n", 1347 exccode, opc, inst, badvaddr, 1348 kvm_read_c0_guest_status(vcpu->arch.cop0)); 1349 kvm_arch_vcpu_dump_regs(vcpu); 1350 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1351 ret = RESUME_HOST; 1352 break; 1353 1354 } 1355 1356 skip_emul: 1357 local_irq_disable(); 1358 1359 if (ret == RESUME_GUEST) 1360 kvm_vz_acquire_htimer(vcpu); 1361 1362 if (er == EMULATE_DONE && !(ret & RESUME_HOST)) 1363 kvm_mips_deliver_interrupts(vcpu, cause); 1364 1365 if (!(ret & RESUME_HOST)) { 1366 /* Only check for signals if not already exiting to userspace */ 1367 if (signal_pending(current)) { 1368 run->exit_reason = KVM_EXIT_INTR; 1369 ret = (-EINTR << 2) | RESUME_HOST; 1370 ++vcpu->stat.signal_exits; 1371 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL); 1372 } 1373 } 1374 1375 if (ret == RESUME_GUEST) { 1376 trace_kvm_reenter(vcpu); 1377 1378 /* 1379 * Make sure the read of VCPU requests in vcpu_reenter() 1380 * callback is not reordered ahead of the write to vcpu->mode, 1381 * or we could miss a TLB flush request while the requester sees 1382 * the VCPU as outside of guest mode and not needing an IPI. 1383 */ 1384 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 1385 1386 kvm_mips_callbacks->vcpu_reenter(run, vcpu); 1387 1388 /* 1389 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context 1390 * is live), restore FCR31 / MSACSR. 1391 * 1392 * This should be before returning to the guest exception 1393 * vector, as it may well cause an [MSA] FP exception if there 1394 * are pending exception bits unmasked. (see 1395 * kvm_mips_csr_die_notifier() for how that is handled). 1396 */ 1397 if (kvm_mips_guest_has_fpu(&vcpu->arch) && 1398 read_c0_status() & ST0_CU1) 1399 __kvm_restore_fcsr(&vcpu->arch); 1400 1401 if (kvm_mips_guest_has_msa(&vcpu->arch) && 1402 read_c0_config5() & MIPS_CONF5_MSAEN) 1403 __kvm_restore_msacsr(&vcpu->arch); 1404 } 1405 1406 /* Disable HTW before returning to guest or host */ 1407 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) 1408 htw_stop(); 1409 1410 return ret; 1411 } 1412 1413 /* Enable FPU for guest and restore context */ 1414 void kvm_own_fpu(struct kvm_vcpu *vcpu) 1415 { 1416 struct mips_coproc *cop0 = vcpu->arch.cop0; 1417 unsigned int sr, cfg5; 1418 1419 preempt_disable(); 1420 1421 sr = kvm_read_c0_guest_status(cop0); 1422 1423 /* 1424 * If MSA state is already live, it is undefined how it interacts with 1425 * FR=0 FPU state, and we don't want to hit reserved instruction 1426 * exceptions trying to save the MSA state later when CU=1 && FR=1, so 1427 * play it safe and save it first. 1428 * 1429 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should 1430 * get called when guest CU1 is set, however we can't trust the guest 1431 * not to clobber the status register directly via the commpage. 1432 */ 1433 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && 1434 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) 1435 kvm_lose_fpu(vcpu); 1436 1437 /* 1438 * Enable FPU for guest 1439 * We set FR and FRE according to guest context 1440 */ 1441 change_c0_status(ST0_CU1 | ST0_FR, sr); 1442 if (cpu_has_fre) { 1443 cfg5 = kvm_read_c0_guest_config5(cop0); 1444 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1445 } 1446 enable_fpu_hazard(); 1447 1448 /* If guest FPU state not active, restore it now */ 1449 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) { 1450 __kvm_restore_fpu(&vcpu->arch); 1451 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1452 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU); 1453 } else { 1454 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU); 1455 } 1456 1457 preempt_enable(); 1458 } 1459 1460 #ifdef CONFIG_CPU_HAS_MSA 1461 /* Enable MSA for guest and restore context */ 1462 void kvm_own_msa(struct kvm_vcpu *vcpu) 1463 { 1464 struct mips_coproc *cop0 = vcpu->arch.cop0; 1465 unsigned int sr, cfg5; 1466 1467 preempt_disable(); 1468 1469 /* 1470 * Enable FPU if enabled in guest, since we're restoring FPU context 1471 * anyway. We set FR and FRE according to guest context. 1472 */ 1473 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { 1474 sr = kvm_read_c0_guest_status(cop0); 1475 1476 /* 1477 * If FR=0 FPU state is already live, it is undefined how it 1478 * interacts with MSA state, so play it safe and save it first. 1479 */ 1480 if (!(sr & ST0_FR) && 1481 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | 1482 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU) 1483 kvm_lose_fpu(vcpu); 1484 1485 change_c0_status(ST0_CU1 | ST0_FR, sr); 1486 if (sr & ST0_CU1 && cpu_has_fre) { 1487 cfg5 = kvm_read_c0_guest_config5(cop0); 1488 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1489 } 1490 } 1491 1492 /* Enable MSA for guest */ 1493 set_c0_config5(MIPS_CONF5_MSAEN); 1494 enable_fpu_hazard(); 1495 1496 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) { 1497 case KVM_MIPS_AUX_FPU: 1498 /* 1499 * Guest FPU state already loaded, only restore upper MSA state 1500 */ 1501 __kvm_restore_msa_upper(&vcpu->arch); 1502 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1503 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA); 1504 break; 1505 case 0: 1506 /* Neither FPU or MSA already active, restore full MSA state */ 1507 __kvm_restore_msa(&vcpu->arch); 1508 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1509 if (kvm_mips_guest_has_fpu(&vcpu->arch)) 1510 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1511 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, 1512 KVM_TRACE_AUX_FPU_MSA); 1513 break; 1514 default: 1515 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA); 1516 break; 1517 } 1518 1519 preempt_enable(); 1520 } 1521 #endif 1522 1523 /* Drop FPU & MSA without saving it */ 1524 void kvm_drop_fpu(struct kvm_vcpu *vcpu) 1525 { 1526 preempt_disable(); 1527 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1528 disable_msa(); 1529 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA); 1530 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA; 1531 } 1532 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1533 clear_c0_status(ST0_CU1 | ST0_FR); 1534 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU); 1535 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1536 } 1537 preempt_enable(); 1538 } 1539 1540 /* Save and disable FPU & MSA */ 1541 void kvm_lose_fpu(struct kvm_vcpu *vcpu) 1542 { 1543 /* 1544 * With T&E, FPU & MSA get disabled in root context (hardware) when it 1545 * is disabled in guest context (software), but the register state in 1546 * the hardware may still be in use. 1547 * This is why we explicitly re-enable the hardware before saving. 1548 */ 1549 1550 preempt_disable(); 1551 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1552 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1553 set_c0_config5(MIPS_CONF5_MSAEN); 1554 enable_fpu_hazard(); 1555 } 1556 1557 __kvm_save_msa(&vcpu->arch); 1558 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA); 1559 1560 /* Disable MSA & FPU */ 1561 disable_msa(); 1562 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1563 clear_c0_status(ST0_CU1 | ST0_FR); 1564 disable_fpu_hazard(); 1565 } 1566 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA); 1567 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1568 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1569 set_c0_status(ST0_CU1); 1570 enable_fpu_hazard(); 1571 } 1572 1573 __kvm_save_fpu(&vcpu->arch); 1574 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1575 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU); 1576 1577 /* Disable FPU */ 1578 clear_c0_status(ST0_CU1 | ST0_FR); 1579 disable_fpu_hazard(); 1580 } 1581 preempt_enable(); 1582 } 1583 1584 /* 1585 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are 1586 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP 1587 * exception if cause bits are set in the value being written. 1588 */ 1589 static int kvm_mips_csr_die_notify(struct notifier_block *self, 1590 unsigned long cmd, void *ptr) 1591 { 1592 struct die_args *args = (struct die_args *)ptr; 1593 struct pt_regs *regs = args->regs; 1594 unsigned long pc; 1595 1596 /* Only interested in FPE and MSAFPE */ 1597 if (cmd != DIE_FP && cmd != DIE_MSAFP) 1598 return NOTIFY_DONE; 1599 1600 /* Return immediately if guest context isn't active */ 1601 if (!(current->flags & PF_VCPU)) 1602 return NOTIFY_DONE; 1603 1604 /* Should never get here from user mode */ 1605 BUG_ON(user_mode(regs)); 1606 1607 pc = instruction_pointer(regs); 1608 switch (cmd) { 1609 case DIE_FP: 1610 /* match 2nd instruction in __kvm_restore_fcsr */ 1611 if (pc != (unsigned long)&__kvm_restore_fcsr + 4) 1612 return NOTIFY_DONE; 1613 break; 1614 case DIE_MSAFP: 1615 /* match 2nd/3rd instruction in __kvm_restore_msacsr */ 1616 if (!cpu_has_msa || 1617 pc < (unsigned long)&__kvm_restore_msacsr + 4 || 1618 pc > (unsigned long)&__kvm_restore_msacsr + 8) 1619 return NOTIFY_DONE; 1620 break; 1621 } 1622 1623 /* Move PC forward a little and continue executing */ 1624 instruction_pointer(regs) += 4; 1625 1626 return NOTIFY_STOP; 1627 } 1628 1629 static struct notifier_block kvm_mips_csr_die_notifier = { 1630 .notifier_call = kvm_mips_csr_die_notify, 1631 }; 1632 1633 static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = { 1634 [MIPS_EXC_INT_TIMER] = C_IRQ5, 1635 [MIPS_EXC_INT_IO_1] = C_IRQ0, 1636 [MIPS_EXC_INT_IPI_1] = C_IRQ1, 1637 [MIPS_EXC_INT_IPI_2] = C_IRQ2, 1638 }; 1639 1640 static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = { 1641 [MIPS_EXC_INT_TIMER] = C_IRQ5, 1642 [MIPS_EXC_INT_IO_1] = C_IRQ0, 1643 [MIPS_EXC_INT_IO_2] = C_IRQ1, 1644 [MIPS_EXC_INT_IPI_1] = C_IRQ4, 1645 }; 1646 1647 u32 *kvm_priority_to_irq = kvm_default_priority_to_irq; 1648 1649 u32 kvm_irq_to_priority(u32 irq) 1650 { 1651 int i; 1652 1653 for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) { 1654 if (kvm_priority_to_irq[i] == (1 << (irq + 8))) 1655 return i; 1656 } 1657 1658 return MIPS_EXC_MAX; 1659 } 1660 1661 static int __init kvm_mips_init(void) 1662 { 1663 int ret; 1664 1665 if (cpu_has_mmid) { 1666 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n"); 1667 return -EOPNOTSUPP; 1668 } 1669 1670 ret = kvm_mips_entry_setup(); 1671 if (ret) 1672 return ret; 1673 1674 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); 1675 1676 if (ret) 1677 return ret; 1678 1679 if (boot_cpu_type() == CPU_LOONGSON64) 1680 kvm_priority_to_irq = kvm_loongson3_priority_to_irq; 1681 1682 register_die_notifier(&kvm_mips_csr_die_notifier); 1683 1684 return 0; 1685 } 1686 1687 static void __exit kvm_mips_exit(void) 1688 { 1689 kvm_exit(); 1690 1691 unregister_die_notifier(&kvm_mips_csr_die_notifier); 1692 } 1693 1694 module_init(kvm_mips_init); 1695 module_exit(kvm_mips_exit); 1696 1697 EXPORT_TRACEPOINT_SYMBOL(kvm_exit); 1698