1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * KVM/MIPS: MIPS specific KVM APIs 7 * 8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 9 * Authors: Sanjay Lal <sanjayl@kymasys.com> 10 */ 11 12 #include <linux/errno.h> 13 #include <linux/err.h> 14 #include <linux/kdebug.h> 15 #include <linux/module.h> 16 #include <linux/vmalloc.h> 17 #include <linux/fs.h> 18 #include <linux/bootmem.h> 19 #include <asm/fpu.h> 20 #include <asm/page.h> 21 #include <asm/cacheflush.h> 22 #include <asm/mmu_context.h> 23 #include <asm/pgtable.h> 24 25 #include <linux/kvm_host.h> 26 27 #include "interrupt.h" 28 #include "commpage.h" 29 30 #define CREATE_TRACE_POINTS 31 #include "trace.h" 32 33 #ifndef VECTORSPACING 34 #define VECTORSPACING 0x100 /* for EI/VI mode */ 35 #endif 36 37 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x) 38 struct kvm_stats_debugfs_item debugfs_entries[] = { 39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU }, 40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU }, 41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU }, 42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU }, 43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU }, 44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU }, 45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU }, 46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU }, 47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU }, 48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU }, 49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU }, 50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU }, 51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU }, 52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU }, 53 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU }, 54 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU }, 55 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU }, 56 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU }, 57 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU }, 58 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU }, 59 {NULL} 60 }; 61 62 static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu) 63 { 64 int i; 65 66 for_each_possible_cpu(i) { 67 vcpu->arch.guest_kernel_asid[i] = 0; 68 vcpu->arch.guest_user_asid[i] = 0; 69 } 70 71 return 0; 72 } 73 74 /* 75 * XXXKYMA: We are simulatoring a processor that has the WII bit set in 76 * Config7, so we are "runnable" if interrupts are pending 77 */ 78 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 79 { 80 return !!(vcpu->arch.pending_exceptions); 81 } 82 83 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 84 { 85 return 1; 86 } 87 88 int kvm_arch_hardware_enable(void) 89 { 90 return 0; 91 } 92 93 int kvm_arch_hardware_setup(void) 94 { 95 return 0; 96 } 97 98 void kvm_arch_check_processor_compat(void *rtn) 99 { 100 *(int *)rtn = 0; 101 } 102 103 static void kvm_mips_init_tlbs(struct kvm *kvm) 104 { 105 unsigned long wired; 106 107 /* 108 * Add a wired entry to the TLB, it is used to map the commpage to 109 * the Guest kernel 110 */ 111 wired = read_c0_wired(); 112 write_c0_wired(wired + 1); 113 mtc0_tlbw_hazard(); 114 kvm->arch.commpage_tlb = wired; 115 116 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(), 117 kvm->arch.commpage_tlb); 118 } 119 120 static void kvm_mips_init_vm_percpu(void *arg) 121 { 122 struct kvm *kvm = (struct kvm *)arg; 123 124 kvm_mips_init_tlbs(kvm); 125 kvm_mips_callbacks->vm_init(kvm); 126 127 } 128 129 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 130 { 131 if (atomic_inc_return(&kvm_mips_instance) == 1) { 132 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n", 133 __func__); 134 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1); 135 } 136 137 return 0; 138 } 139 140 void kvm_mips_free_vcpus(struct kvm *kvm) 141 { 142 unsigned int i; 143 struct kvm_vcpu *vcpu; 144 145 /* Put the pages we reserved for the guest pmap */ 146 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) { 147 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE) 148 kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]); 149 } 150 kfree(kvm->arch.guest_pmap); 151 152 kvm_for_each_vcpu(i, vcpu, kvm) { 153 kvm_arch_vcpu_free(vcpu); 154 } 155 156 mutex_lock(&kvm->lock); 157 158 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 159 kvm->vcpus[i] = NULL; 160 161 atomic_set(&kvm->online_vcpus, 0); 162 163 mutex_unlock(&kvm->lock); 164 } 165 166 static void kvm_mips_uninit_tlbs(void *arg) 167 { 168 /* Restore wired count */ 169 write_c0_wired(0); 170 mtc0_tlbw_hazard(); 171 /* Clear out all the TLBs */ 172 kvm_local_flush_tlb_all(); 173 } 174 175 void kvm_arch_destroy_vm(struct kvm *kvm) 176 { 177 kvm_mips_free_vcpus(kvm); 178 179 /* If this is the last instance, restore wired count */ 180 if (atomic_dec_return(&kvm_mips_instance) == 0) { 181 kvm_debug("%s: last KVM instance, restoring TLB parameters\n", 182 __func__); 183 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1); 184 } 185 } 186 187 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, 188 unsigned long arg) 189 { 190 return -ENOIOCTLCMD; 191 } 192 193 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 194 unsigned long npages) 195 { 196 return 0; 197 } 198 199 int kvm_arch_prepare_memory_region(struct kvm *kvm, 200 struct kvm_memory_slot *memslot, 201 const struct kvm_userspace_memory_region *mem, 202 enum kvm_mr_change change) 203 { 204 return 0; 205 } 206 207 void kvm_arch_commit_memory_region(struct kvm *kvm, 208 const struct kvm_userspace_memory_region *mem, 209 const struct kvm_memory_slot *old, 210 const struct kvm_memory_slot *new, 211 enum kvm_mr_change change) 212 { 213 unsigned long npages = 0; 214 int i; 215 216 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n", 217 __func__, kvm, mem->slot, mem->guest_phys_addr, 218 mem->memory_size, mem->userspace_addr); 219 220 /* Setup Guest PMAP table */ 221 if (!kvm->arch.guest_pmap) { 222 if (mem->slot == 0) 223 npages = mem->memory_size >> PAGE_SHIFT; 224 225 if (npages) { 226 kvm->arch.guest_pmap_npages = npages; 227 kvm->arch.guest_pmap = 228 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL); 229 230 if (!kvm->arch.guest_pmap) { 231 kvm_err("Failed to allocate guest PMAP"); 232 return; 233 } 234 235 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n", 236 npages, kvm->arch.guest_pmap); 237 238 /* Now setup the page table */ 239 for (i = 0; i < npages; i++) 240 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE; 241 } 242 } 243 } 244 245 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) 246 { 247 int err, size, offset; 248 void *gebase; 249 int i; 250 251 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL); 252 253 if (!vcpu) { 254 err = -ENOMEM; 255 goto out; 256 } 257 258 err = kvm_vcpu_init(vcpu, kvm, id); 259 260 if (err) 261 goto out_free_cpu; 262 263 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu); 264 265 /* 266 * Allocate space for host mode exception handlers that handle 267 * guest mode exits 268 */ 269 if (cpu_has_veic || cpu_has_vint) 270 size = 0x200 + VECTORSPACING * 64; 271 else 272 size = 0x4000; 273 274 /* Save Linux EBASE */ 275 vcpu->arch.host_ebase = (void *)read_c0_ebase(); 276 277 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); 278 279 if (!gebase) { 280 err = -ENOMEM; 281 goto out_free_cpu; 282 } 283 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", 284 ALIGN(size, PAGE_SIZE), gebase); 285 286 /* Save new ebase */ 287 vcpu->arch.guest_ebase = gebase; 288 289 /* Copy L1 Guest Exception handler to correct offset */ 290 291 /* TLB Refill, EXL = 0 */ 292 memcpy(gebase, mips32_exception, 293 mips32_exceptionEnd - mips32_exception); 294 295 /* General Exception Entry point */ 296 memcpy(gebase + 0x180, mips32_exception, 297 mips32_exceptionEnd - mips32_exception); 298 299 /* For vectored interrupts poke the exception code @ all offsets 0-7 */ 300 for (i = 0; i < 8; i++) { 301 kvm_debug("L1 Vectored handler @ %p\n", 302 gebase + 0x200 + (i * VECTORSPACING)); 303 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception, 304 mips32_exceptionEnd - mips32_exception); 305 } 306 307 /* General handler, relocate to unmapped space for sanity's sake */ 308 offset = 0x2000; 309 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n", 310 gebase + offset, 311 mips32_GuestExceptionEnd - mips32_GuestException); 312 313 memcpy(gebase + offset, mips32_GuestException, 314 mips32_GuestExceptionEnd - mips32_GuestException); 315 316 /* Invalidate the icache for these ranges */ 317 local_flush_icache_range((unsigned long)gebase, 318 (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); 319 320 /* 321 * Allocate comm page for guest kernel, a TLB will be reserved for 322 * mapping GVA @ 0xFFFF8000 to this page 323 */ 324 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL); 325 326 if (!vcpu->arch.kseg0_commpage) { 327 err = -ENOMEM; 328 goto out_free_gebase; 329 } 330 331 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage); 332 kvm_mips_commpage_init(vcpu); 333 334 /* Init */ 335 vcpu->arch.last_sched_cpu = -1; 336 337 /* Start off the timer */ 338 kvm_mips_init_count(vcpu); 339 340 return vcpu; 341 342 out_free_gebase: 343 kfree(gebase); 344 345 out_free_cpu: 346 kfree(vcpu); 347 348 out: 349 return ERR_PTR(err); 350 } 351 352 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 353 { 354 hrtimer_cancel(&vcpu->arch.comparecount_timer); 355 356 kvm_vcpu_uninit(vcpu); 357 358 kvm_mips_dump_stats(vcpu); 359 360 kfree(vcpu->arch.guest_ebase); 361 kfree(vcpu->arch.kseg0_commpage); 362 kfree(vcpu); 363 } 364 365 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 366 { 367 kvm_arch_vcpu_free(vcpu); 368 } 369 370 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 371 struct kvm_guest_debug *dbg) 372 { 373 return -ENOIOCTLCMD; 374 } 375 376 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) 377 { 378 int r = 0; 379 sigset_t sigsaved; 380 381 if (vcpu->sigset_active) 382 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 383 384 if (vcpu->mmio_needed) { 385 if (!vcpu->mmio_is_write) 386 kvm_mips_complete_mmio_load(vcpu, run); 387 vcpu->mmio_needed = 0; 388 } 389 390 lose_fpu(1); 391 392 local_irq_disable(); 393 /* Check if we have any exceptions/interrupts pending */ 394 kvm_mips_deliver_interrupts(vcpu, 395 kvm_read_c0_guest_cause(vcpu->arch.cop0)); 396 397 __kvm_guest_enter(); 398 399 /* Disable hardware page table walking while in guest */ 400 htw_stop(); 401 402 r = __kvm_mips_vcpu_run(run, vcpu); 403 404 /* Re-enable HTW before enabling interrupts */ 405 htw_start(); 406 407 __kvm_guest_exit(); 408 local_irq_enable(); 409 410 if (vcpu->sigset_active) 411 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 412 413 return r; 414 } 415 416 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 417 struct kvm_mips_interrupt *irq) 418 { 419 int intr = (int)irq->irq; 420 struct kvm_vcpu *dvcpu = NULL; 421 422 if (intr == 3 || intr == -3 || intr == 4 || intr == -4) 423 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, 424 (int)intr); 425 426 if (irq->cpu == -1) 427 dvcpu = vcpu; 428 else 429 dvcpu = vcpu->kvm->vcpus[irq->cpu]; 430 431 if (intr == 2 || intr == 3 || intr == 4) { 432 kvm_mips_callbacks->queue_io_int(dvcpu, irq); 433 434 } else if (intr == -2 || intr == -3 || intr == -4) { 435 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); 436 } else { 437 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, 438 irq->cpu, irq->irq); 439 return -EINVAL; 440 } 441 442 dvcpu->arch.wait = 0; 443 444 if (waitqueue_active(&dvcpu->wq)) 445 wake_up_interruptible(&dvcpu->wq); 446 447 return 0; 448 } 449 450 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 451 struct kvm_mp_state *mp_state) 452 { 453 return -ENOIOCTLCMD; 454 } 455 456 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 457 struct kvm_mp_state *mp_state) 458 { 459 return -ENOIOCTLCMD; 460 } 461 462 static u64 kvm_mips_get_one_regs[] = { 463 KVM_REG_MIPS_R0, 464 KVM_REG_MIPS_R1, 465 KVM_REG_MIPS_R2, 466 KVM_REG_MIPS_R3, 467 KVM_REG_MIPS_R4, 468 KVM_REG_MIPS_R5, 469 KVM_REG_MIPS_R6, 470 KVM_REG_MIPS_R7, 471 KVM_REG_MIPS_R8, 472 KVM_REG_MIPS_R9, 473 KVM_REG_MIPS_R10, 474 KVM_REG_MIPS_R11, 475 KVM_REG_MIPS_R12, 476 KVM_REG_MIPS_R13, 477 KVM_REG_MIPS_R14, 478 KVM_REG_MIPS_R15, 479 KVM_REG_MIPS_R16, 480 KVM_REG_MIPS_R17, 481 KVM_REG_MIPS_R18, 482 KVM_REG_MIPS_R19, 483 KVM_REG_MIPS_R20, 484 KVM_REG_MIPS_R21, 485 KVM_REG_MIPS_R22, 486 KVM_REG_MIPS_R23, 487 KVM_REG_MIPS_R24, 488 KVM_REG_MIPS_R25, 489 KVM_REG_MIPS_R26, 490 KVM_REG_MIPS_R27, 491 KVM_REG_MIPS_R28, 492 KVM_REG_MIPS_R29, 493 KVM_REG_MIPS_R30, 494 KVM_REG_MIPS_R31, 495 496 KVM_REG_MIPS_HI, 497 KVM_REG_MIPS_LO, 498 KVM_REG_MIPS_PC, 499 500 KVM_REG_MIPS_CP0_INDEX, 501 KVM_REG_MIPS_CP0_CONTEXT, 502 KVM_REG_MIPS_CP0_USERLOCAL, 503 KVM_REG_MIPS_CP0_PAGEMASK, 504 KVM_REG_MIPS_CP0_WIRED, 505 KVM_REG_MIPS_CP0_HWRENA, 506 KVM_REG_MIPS_CP0_BADVADDR, 507 KVM_REG_MIPS_CP0_COUNT, 508 KVM_REG_MIPS_CP0_ENTRYHI, 509 KVM_REG_MIPS_CP0_COMPARE, 510 KVM_REG_MIPS_CP0_STATUS, 511 KVM_REG_MIPS_CP0_CAUSE, 512 KVM_REG_MIPS_CP0_EPC, 513 KVM_REG_MIPS_CP0_PRID, 514 KVM_REG_MIPS_CP0_CONFIG, 515 KVM_REG_MIPS_CP0_CONFIG1, 516 KVM_REG_MIPS_CP0_CONFIG2, 517 KVM_REG_MIPS_CP0_CONFIG3, 518 KVM_REG_MIPS_CP0_CONFIG4, 519 KVM_REG_MIPS_CP0_CONFIG5, 520 KVM_REG_MIPS_CP0_CONFIG7, 521 KVM_REG_MIPS_CP0_ERROREPC, 522 523 KVM_REG_MIPS_COUNT_CTL, 524 KVM_REG_MIPS_COUNT_RESUME, 525 KVM_REG_MIPS_COUNT_HZ, 526 }; 527 528 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 529 const struct kvm_one_reg *reg) 530 { 531 struct mips_coproc *cop0 = vcpu->arch.cop0; 532 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 533 int ret; 534 s64 v; 535 s64 vs[2]; 536 unsigned int idx; 537 538 switch (reg->id) { 539 /* General purpose registers */ 540 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: 541 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; 542 break; 543 case KVM_REG_MIPS_HI: 544 v = (long)vcpu->arch.hi; 545 break; 546 case KVM_REG_MIPS_LO: 547 v = (long)vcpu->arch.lo; 548 break; 549 case KVM_REG_MIPS_PC: 550 v = (long)vcpu->arch.pc; 551 break; 552 553 /* Floating point registers */ 554 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 555 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 556 return -EINVAL; 557 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 558 /* Odd singles in top of even double when FR=0 */ 559 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 560 v = get_fpr32(&fpu->fpr[idx], 0); 561 else 562 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); 563 break; 564 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 565 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 566 return -EINVAL; 567 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 568 /* Can't access odd doubles in FR=0 mode */ 569 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 570 return -EINVAL; 571 v = get_fpr64(&fpu->fpr[idx], 0); 572 break; 573 case KVM_REG_MIPS_FCR_IR: 574 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 575 return -EINVAL; 576 v = boot_cpu_data.fpu_id; 577 break; 578 case KVM_REG_MIPS_FCR_CSR: 579 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 580 return -EINVAL; 581 v = fpu->fcr31; 582 break; 583 584 /* MIPS SIMD Architecture (MSA) registers */ 585 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 586 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 587 return -EINVAL; 588 /* Can't access MSA registers in FR=0 mode */ 589 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) 590 return -EINVAL; 591 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 592 #ifdef CONFIG_CPU_LITTLE_ENDIAN 593 /* least significant byte first */ 594 vs[0] = get_fpr64(&fpu->fpr[idx], 0); 595 vs[1] = get_fpr64(&fpu->fpr[idx], 1); 596 #else 597 /* most significant byte first */ 598 vs[0] = get_fpr64(&fpu->fpr[idx], 1); 599 vs[1] = get_fpr64(&fpu->fpr[idx], 0); 600 #endif 601 break; 602 case KVM_REG_MIPS_MSA_IR: 603 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 604 return -EINVAL; 605 v = boot_cpu_data.msa_id; 606 break; 607 case KVM_REG_MIPS_MSA_CSR: 608 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 609 return -EINVAL; 610 v = fpu->msacsr; 611 break; 612 613 /* Co-processor 0 registers */ 614 case KVM_REG_MIPS_CP0_INDEX: 615 v = (long)kvm_read_c0_guest_index(cop0); 616 break; 617 case KVM_REG_MIPS_CP0_CONTEXT: 618 v = (long)kvm_read_c0_guest_context(cop0); 619 break; 620 case KVM_REG_MIPS_CP0_USERLOCAL: 621 v = (long)kvm_read_c0_guest_userlocal(cop0); 622 break; 623 case KVM_REG_MIPS_CP0_PAGEMASK: 624 v = (long)kvm_read_c0_guest_pagemask(cop0); 625 break; 626 case KVM_REG_MIPS_CP0_WIRED: 627 v = (long)kvm_read_c0_guest_wired(cop0); 628 break; 629 case KVM_REG_MIPS_CP0_HWRENA: 630 v = (long)kvm_read_c0_guest_hwrena(cop0); 631 break; 632 case KVM_REG_MIPS_CP0_BADVADDR: 633 v = (long)kvm_read_c0_guest_badvaddr(cop0); 634 break; 635 case KVM_REG_MIPS_CP0_ENTRYHI: 636 v = (long)kvm_read_c0_guest_entryhi(cop0); 637 break; 638 case KVM_REG_MIPS_CP0_COMPARE: 639 v = (long)kvm_read_c0_guest_compare(cop0); 640 break; 641 case KVM_REG_MIPS_CP0_STATUS: 642 v = (long)kvm_read_c0_guest_status(cop0); 643 break; 644 case KVM_REG_MIPS_CP0_CAUSE: 645 v = (long)kvm_read_c0_guest_cause(cop0); 646 break; 647 case KVM_REG_MIPS_CP0_EPC: 648 v = (long)kvm_read_c0_guest_epc(cop0); 649 break; 650 case KVM_REG_MIPS_CP0_PRID: 651 v = (long)kvm_read_c0_guest_prid(cop0); 652 break; 653 case KVM_REG_MIPS_CP0_CONFIG: 654 v = (long)kvm_read_c0_guest_config(cop0); 655 break; 656 case KVM_REG_MIPS_CP0_CONFIG1: 657 v = (long)kvm_read_c0_guest_config1(cop0); 658 break; 659 case KVM_REG_MIPS_CP0_CONFIG2: 660 v = (long)kvm_read_c0_guest_config2(cop0); 661 break; 662 case KVM_REG_MIPS_CP0_CONFIG3: 663 v = (long)kvm_read_c0_guest_config3(cop0); 664 break; 665 case KVM_REG_MIPS_CP0_CONFIG4: 666 v = (long)kvm_read_c0_guest_config4(cop0); 667 break; 668 case KVM_REG_MIPS_CP0_CONFIG5: 669 v = (long)kvm_read_c0_guest_config5(cop0); 670 break; 671 case KVM_REG_MIPS_CP0_CONFIG7: 672 v = (long)kvm_read_c0_guest_config7(cop0); 673 break; 674 case KVM_REG_MIPS_CP0_ERROREPC: 675 v = (long)kvm_read_c0_guest_errorepc(cop0); 676 break; 677 /* registers to be handled specially */ 678 case KVM_REG_MIPS_CP0_COUNT: 679 case KVM_REG_MIPS_COUNT_CTL: 680 case KVM_REG_MIPS_COUNT_RESUME: 681 case KVM_REG_MIPS_COUNT_HZ: 682 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); 683 if (ret) 684 return ret; 685 break; 686 default: 687 return -EINVAL; 688 } 689 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 690 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 691 692 return put_user(v, uaddr64); 693 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 694 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 695 u32 v32 = (u32)v; 696 697 return put_user(v32, uaddr32); 698 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 699 void __user *uaddr = (void __user *)(long)reg->addr; 700 701 return copy_to_user(uaddr, vs, 16); 702 } else { 703 return -EINVAL; 704 } 705 } 706 707 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 708 const struct kvm_one_reg *reg) 709 { 710 struct mips_coproc *cop0 = vcpu->arch.cop0; 711 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 712 s64 v; 713 s64 vs[2]; 714 unsigned int idx; 715 716 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 717 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 718 719 if (get_user(v, uaddr64) != 0) 720 return -EFAULT; 721 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 722 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 723 s32 v32; 724 725 if (get_user(v32, uaddr32) != 0) 726 return -EFAULT; 727 v = (s64)v32; 728 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 729 void __user *uaddr = (void __user *)(long)reg->addr; 730 731 return copy_from_user(vs, uaddr, 16); 732 } else { 733 return -EINVAL; 734 } 735 736 switch (reg->id) { 737 /* General purpose registers */ 738 case KVM_REG_MIPS_R0: 739 /* Silently ignore requests to set $0 */ 740 break; 741 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: 742 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; 743 break; 744 case KVM_REG_MIPS_HI: 745 vcpu->arch.hi = v; 746 break; 747 case KVM_REG_MIPS_LO: 748 vcpu->arch.lo = v; 749 break; 750 case KVM_REG_MIPS_PC: 751 vcpu->arch.pc = v; 752 break; 753 754 /* Floating point registers */ 755 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 756 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 757 return -EINVAL; 758 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 759 /* Odd singles in top of even double when FR=0 */ 760 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 761 set_fpr32(&fpu->fpr[idx], 0, v); 762 else 763 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); 764 break; 765 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 766 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 767 return -EINVAL; 768 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 769 /* Can't access odd doubles in FR=0 mode */ 770 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 771 return -EINVAL; 772 set_fpr64(&fpu->fpr[idx], 0, v); 773 break; 774 case KVM_REG_MIPS_FCR_IR: 775 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 776 return -EINVAL; 777 /* Read-only */ 778 break; 779 case KVM_REG_MIPS_FCR_CSR: 780 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 781 return -EINVAL; 782 fpu->fcr31 = v; 783 break; 784 785 /* MIPS SIMD Architecture (MSA) registers */ 786 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 787 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 788 return -EINVAL; 789 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 790 #ifdef CONFIG_CPU_LITTLE_ENDIAN 791 /* least significant byte first */ 792 set_fpr64(&fpu->fpr[idx], 0, vs[0]); 793 set_fpr64(&fpu->fpr[idx], 1, vs[1]); 794 #else 795 /* most significant byte first */ 796 set_fpr64(&fpu->fpr[idx], 1, vs[0]); 797 set_fpr64(&fpu->fpr[idx], 0, vs[1]); 798 #endif 799 break; 800 case KVM_REG_MIPS_MSA_IR: 801 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 802 return -EINVAL; 803 /* Read-only */ 804 break; 805 case KVM_REG_MIPS_MSA_CSR: 806 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 807 return -EINVAL; 808 fpu->msacsr = v; 809 break; 810 811 /* Co-processor 0 registers */ 812 case KVM_REG_MIPS_CP0_INDEX: 813 kvm_write_c0_guest_index(cop0, v); 814 break; 815 case KVM_REG_MIPS_CP0_CONTEXT: 816 kvm_write_c0_guest_context(cop0, v); 817 break; 818 case KVM_REG_MIPS_CP0_USERLOCAL: 819 kvm_write_c0_guest_userlocal(cop0, v); 820 break; 821 case KVM_REG_MIPS_CP0_PAGEMASK: 822 kvm_write_c0_guest_pagemask(cop0, v); 823 break; 824 case KVM_REG_MIPS_CP0_WIRED: 825 kvm_write_c0_guest_wired(cop0, v); 826 break; 827 case KVM_REG_MIPS_CP0_HWRENA: 828 kvm_write_c0_guest_hwrena(cop0, v); 829 break; 830 case KVM_REG_MIPS_CP0_BADVADDR: 831 kvm_write_c0_guest_badvaddr(cop0, v); 832 break; 833 case KVM_REG_MIPS_CP0_ENTRYHI: 834 kvm_write_c0_guest_entryhi(cop0, v); 835 break; 836 case KVM_REG_MIPS_CP0_STATUS: 837 kvm_write_c0_guest_status(cop0, v); 838 break; 839 case KVM_REG_MIPS_CP0_EPC: 840 kvm_write_c0_guest_epc(cop0, v); 841 break; 842 case KVM_REG_MIPS_CP0_PRID: 843 kvm_write_c0_guest_prid(cop0, v); 844 break; 845 case KVM_REG_MIPS_CP0_ERROREPC: 846 kvm_write_c0_guest_errorepc(cop0, v); 847 break; 848 /* registers to be handled specially */ 849 case KVM_REG_MIPS_CP0_COUNT: 850 case KVM_REG_MIPS_CP0_COMPARE: 851 case KVM_REG_MIPS_CP0_CAUSE: 852 case KVM_REG_MIPS_CP0_CONFIG: 853 case KVM_REG_MIPS_CP0_CONFIG1: 854 case KVM_REG_MIPS_CP0_CONFIG2: 855 case KVM_REG_MIPS_CP0_CONFIG3: 856 case KVM_REG_MIPS_CP0_CONFIG4: 857 case KVM_REG_MIPS_CP0_CONFIG5: 858 case KVM_REG_MIPS_COUNT_CTL: 859 case KVM_REG_MIPS_COUNT_RESUME: 860 case KVM_REG_MIPS_COUNT_HZ: 861 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); 862 default: 863 return -EINVAL; 864 } 865 return 0; 866 } 867 868 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 869 struct kvm_enable_cap *cap) 870 { 871 int r = 0; 872 873 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) 874 return -EINVAL; 875 if (cap->flags) 876 return -EINVAL; 877 if (cap->args[0]) 878 return -EINVAL; 879 880 switch (cap->cap) { 881 case KVM_CAP_MIPS_FPU: 882 vcpu->arch.fpu_enabled = true; 883 break; 884 case KVM_CAP_MIPS_MSA: 885 vcpu->arch.msa_enabled = true; 886 break; 887 default: 888 r = -EINVAL; 889 break; 890 } 891 892 return r; 893 } 894 895 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, 896 unsigned long arg) 897 { 898 struct kvm_vcpu *vcpu = filp->private_data; 899 void __user *argp = (void __user *)arg; 900 long r; 901 902 switch (ioctl) { 903 case KVM_SET_ONE_REG: 904 case KVM_GET_ONE_REG: { 905 struct kvm_one_reg reg; 906 907 if (copy_from_user(®, argp, sizeof(reg))) 908 return -EFAULT; 909 if (ioctl == KVM_SET_ONE_REG) 910 return kvm_mips_set_reg(vcpu, ®); 911 else 912 return kvm_mips_get_reg(vcpu, ®); 913 } 914 case KVM_GET_REG_LIST: { 915 struct kvm_reg_list __user *user_list = argp; 916 u64 __user *reg_dest; 917 struct kvm_reg_list reg_list; 918 unsigned n; 919 920 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 921 return -EFAULT; 922 n = reg_list.n; 923 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs); 924 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 925 return -EFAULT; 926 if (n < reg_list.n) 927 return -E2BIG; 928 reg_dest = user_list->reg; 929 if (copy_to_user(reg_dest, kvm_mips_get_one_regs, 930 sizeof(kvm_mips_get_one_regs))) 931 return -EFAULT; 932 return 0; 933 } 934 case KVM_NMI: 935 /* Treat the NMI as a CPU reset */ 936 r = kvm_mips_reset_vcpu(vcpu); 937 break; 938 case KVM_INTERRUPT: 939 { 940 struct kvm_mips_interrupt irq; 941 942 r = -EFAULT; 943 if (copy_from_user(&irq, argp, sizeof(irq))) 944 goto out; 945 946 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, 947 irq.irq); 948 949 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 950 break; 951 } 952 case KVM_ENABLE_CAP: { 953 struct kvm_enable_cap cap; 954 955 r = -EFAULT; 956 if (copy_from_user(&cap, argp, sizeof(cap))) 957 goto out; 958 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 959 break; 960 } 961 default: 962 r = -ENOIOCTLCMD; 963 } 964 965 out: 966 return r; 967 } 968 969 /* Get (and clear) the dirty memory log for a memory slot. */ 970 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 971 { 972 struct kvm_memslots *slots; 973 struct kvm_memory_slot *memslot; 974 unsigned long ga, ga_end; 975 int is_dirty = 0; 976 int r; 977 unsigned long n; 978 979 mutex_lock(&kvm->slots_lock); 980 981 r = kvm_get_dirty_log(kvm, log, &is_dirty); 982 if (r) 983 goto out; 984 985 /* If nothing is dirty, don't bother messing with page tables. */ 986 if (is_dirty) { 987 slots = kvm_memslots(kvm); 988 memslot = id_to_memslot(slots, log->slot); 989 990 ga = memslot->base_gfn << PAGE_SHIFT; 991 ga_end = ga + (memslot->npages << PAGE_SHIFT); 992 993 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga, 994 ga_end); 995 996 n = kvm_dirty_bitmap_bytes(memslot); 997 memset(memslot->dirty_bitmap, 0, n); 998 } 999 1000 r = 0; 1001 out: 1002 mutex_unlock(&kvm->slots_lock); 1003 return r; 1004 1005 } 1006 1007 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 1008 { 1009 long r; 1010 1011 switch (ioctl) { 1012 default: 1013 r = -ENOIOCTLCMD; 1014 } 1015 1016 return r; 1017 } 1018 1019 int kvm_arch_init(void *opaque) 1020 { 1021 if (kvm_mips_callbacks) { 1022 kvm_err("kvm: module already exists\n"); 1023 return -EEXIST; 1024 } 1025 1026 return kvm_mips_emulation_init(&kvm_mips_callbacks); 1027 } 1028 1029 void kvm_arch_exit(void) 1030 { 1031 kvm_mips_callbacks = NULL; 1032 } 1033 1034 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 1035 struct kvm_sregs *sregs) 1036 { 1037 return -ENOIOCTLCMD; 1038 } 1039 1040 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 1041 struct kvm_sregs *sregs) 1042 { 1043 return -ENOIOCTLCMD; 1044 } 1045 1046 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 1047 { 1048 } 1049 1050 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1051 { 1052 return -ENOIOCTLCMD; 1053 } 1054 1055 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1056 { 1057 return -ENOIOCTLCMD; 1058 } 1059 1060 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 1061 { 1062 return VM_FAULT_SIGBUS; 1063 } 1064 1065 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 1066 { 1067 int r; 1068 1069 switch (ext) { 1070 case KVM_CAP_ONE_REG: 1071 case KVM_CAP_ENABLE_CAP: 1072 r = 1; 1073 break; 1074 case KVM_CAP_COALESCED_MMIO: 1075 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 1076 break; 1077 case KVM_CAP_MIPS_FPU: 1078 r = !!cpu_has_fpu; 1079 break; 1080 case KVM_CAP_MIPS_MSA: 1081 /* 1082 * We don't support MSA vector partitioning yet: 1083 * 1) It would require explicit support which can't be tested 1084 * yet due to lack of support in current hardware. 1085 * 2) It extends the state that would need to be saved/restored 1086 * by e.g. QEMU for migration. 1087 * 1088 * When vector partitioning hardware becomes available, support 1089 * could be added by requiring a flag when enabling 1090 * KVM_CAP_MIPS_MSA capability to indicate that userland knows 1091 * to save/restore the appropriate extra state. 1092 */ 1093 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); 1094 break; 1095 default: 1096 r = 0; 1097 break; 1098 } 1099 return r; 1100 } 1101 1102 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 1103 { 1104 return kvm_mips_pending_timer(vcpu); 1105 } 1106 1107 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) 1108 { 1109 int i; 1110 struct mips_coproc *cop0; 1111 1112 if (!vcpu) 1113 return -1; 1114 1115 kvm_debug("VCPU Register Dump:\n"); 1116 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); 1117 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); 1118 1119 for (i = 0; i < 32; i += 4) { 1120 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, 1121 vcpu->arch.gprs[i], 1122 vcpu->arch.gprs[i + 1], 1123 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); 1124 } 1125 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); 1126 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); 1127 1128 cop0 = vcpu->arch.cop0; 1129 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n", 1130 kvm_read_c0_guest_status(cop0), 1131 kvm_read_c0_guest_cause(cop0)); 1132 1133 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); 1134 1135 return 0; 1136 } 1137 1138 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1139 { 1140 int i; 1141 1142 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1143 vcpu->arch.gprs[i] = regs->gpr[i]; 1144 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ 1145 vcpu->arch.hi = regs->hi; 1146 vcpu->arch.lo = regs->lo; 1147 vcpu->arch.pc = regs->pc; 1148 1149 return 0; 1150 } 1151 1152 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1153 { 1154 int i; 1155 1156 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1157 regs->gpr[i] = vcpu->arch.gprs[i]; 1158 1159 regs->hi = vcpu->arch.hi; 1160 regs->lo = vcpu->arch.lo; 1161 regs->pc = vcpu->arch.pc; 1162 1163 return 0; 1164 } 1165 1166 static void kvm_mips_comparecount_func(unsigned long data) 1167 { 1168 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data; 1169 1170 kvm_mips_callbacks->queue_timer_int(vcpu); 1171 1172 vcpu->arch.wait = 0; 1173 if (waitqueue_active(&vcpu->wq)) 1174 wake_up_interruptible(&vcpu->wq); 1175 } 1176 1177 /* low level hrtimer wake routine */ 1178 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) 1179 { 1180 struct kvm_vcpu *vcpu; 1181 1182 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); 1183 kvm_mips_comparecount_func((unsigned long) vcpu); 1184 return kvm_mips_count_timeout(vcpu); 1185 } 1186 1187 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 1188 { 1189 kvm_mips_callbacks->vcpu_init(vcpu); 1190 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 1191 HRTIMER_MODE_REL); 1192 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 1193 return 0; 1194 } 1195 1196 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 1197 struct kvm_translation *tr) 1198 { 1199 return 0; 1200 } 1201 1202 /* Initial guest state */ 1203 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 1204 { 1205 return kvm_mips_callbacks->vcpu_setup(vcpu); 1206 } 1207 1208 static void kvm_mips_set_c0_status(void) 1209 { 1210 uint32_t status = read_c0_status(); 1211 1212 if (cpu_has_dsp) 1213 status |= (ST0_MX); 1214 1215 write_c0_status(status); 1216 ehb(); 1217 } 1218 1219 /* 1220 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) 1221 */ 1222 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) 1223 { 1224 uint32_t cause = vcpu->arch.host_cp0_cause; 1225 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; 1226 uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc; 1227 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; 1228 enum emulation_result er = EMULATE_DONE; 1229 int ret = RESUME_GUEST; 1230 1231 /* re-enable HTW before enabling interrupts */ 1232 htw_start(); 1233 1234 /* Set a default exit reason */ 1235 run->exit_reason = KVM_EXIT_UNKNOWN; 1236 run->ready_for_interrupt_injection = 1; 1237 1238 /* 1239 * Set the appropriate status bits based on host CPU features, 1240 * before we hit the scheduler 1241 */ 1242 kvm_mips_set_c0_status(); 1243 1244 local_irq_enable(); 1245 1246 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", 1247 cause, opc, run, vcpu); 1248 1249 /* 1250 * Do a privilege check, if in UM most of these exit conditions end up 1251 * causing an exception to be delivered to the Guest Kernel 1252 */ 1253 er = kvm_mips_check_privilege(cause, opc, run, vcpu); 1254 if (er == EMULATE_PRIV_FAIL) { 1255 goto skip_emul; 1256 } else if (er == EMULATE_FAIL) { 1257 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1258 ret = RESUME_HOST; 1259 goto skip_emul; 1260 } 1261 1262 switch (exccode) { 1263 case T_INT: 1264 kvm_debug("[%d]T_INT @ %p\n", vcpu->vcpu_id, opc); 1265 1266 ++vcpu->stat.int_exits; 1267 trace_kvm_exit(vcpu, INT_EXITS); 1268 1269 if (need_resched()) 1270 cond_resched(); 1271 1272 ret = RESUME_GUEST; 1273 break; 1274 1275 case T_COP_UNUSABLE: 1276 kvm_debug("T_COP_UNUSABLE: @ PC: %p\n", opc); 1277 1278 ++vcpu->stat.cop_unusable_exits; 1279 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS); 1280 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); 1281 /* XXXKYMA: Might need to return to user space */ 1282 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) 1283 ret = RESUME_HOST; 1284 break; 1285 1286 case T_TLB_MOD: 1287 ++vcpu->stat.tlbmod_exits; 1288 trace_kvm_exit(vcpu, TLBMOD_EXITS); 1289 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); 1290 break; 1291 1292 case T_TLB_ST_MISS: 1293 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n", 1294 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, 1295 badvaddr); 1296 1297 ++vcpu->stat.tlbmiss_st_exits; 1298 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS); 1299 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); 1300 break; 1301 1302 case T_TLB_LD_MISS: 1303 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", 1304 cause, opc, badvaddr); 1305 1306 ++vcpu->stat.tlbmiss_ld_exits; 1307 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS); 1308 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); 1309 break; 1310 1311 case T_ADDR_ERR_ST: 1312 ++vcpu->stat.addrerr_st_exits; 1313 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS); 1314 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); 1315 break; 1316 1317 case T_ADDR_ERR_LD: 1318 ++vcpu->stat.addrerr_ld_exits; 1319 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS); 1320 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); 1321 break; 1322 1323 case T_SYSCALL: 1324 ++vcpu->stat.syscall_exits; 1325 trace_kvm_exit(vcpu, SYSCALL_EXITS); 1326 ret = kvm_mips_callbacks->handle_syscall(vcpu); 1327 break; 1328 1329 case T_RES_INST: 1330 ++vcpu->stat.resvd_inst_exits; 1331 trace_kvm_exit(vcpu, RESVD_INST_EXITS); 1332 ret = kvm_mips_callbacks->handle_res_inst(vcpu); 1333 break; 1334 1335 case T_BREAK: 1336 ++vcpu->stat.break_inst_exits; 1337 trace_kvm_exit(vcpu, BREAK_INST_EXITS); 1338 ret = kvm_mips_callbacks->handle_break(vcpu); 1339 break; 1340 1341 case T_TRAP: 1342 ++vcpu->stat.trap_inst_exits; 1343 trace_kvm_exit(vcpu, TRAP_INST_EXITS); 1344 ret = kvm_mips_callbacks->handle_trap(vcpu); 1345 break; 1346 1347 case T_MSAFPE: 1348 ++vcpu->stat.msa_fpe_exits; 1349 trace_kvm_exit(vcpu, MSA_FPE_EXITS); 1350 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); 1351 break; 1352 1353 case T_FPE: 1354 ++vcpu->stat.fpe_exits; 1355 trace_kvm_exit(vcpu, FPE_EXITS); 1356 ret = kvm_mips_callbacks->handle_fpe(vcpu); 1357 break; 1358 1359 case T_MSADIS: 1360 ++vcpu->stat.msa_disabled_exits; 1361 trace_kvm_exit(vcpu, MSA_DISABLED_EXITS); 1362 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); 1363 break; 1364 1365 default: 1366 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n", 1367 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr, 1368 kvm_read_c0_guest_status(vcpu->arch.cop0)); 1369 kvm_arch_vcpu_dump_regs(vcpu); 1370 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1371 ret = RESUME_HOST; 1372 break; 1373 1374 } 1375 1376 skip_emul: 1377 local_irq_disable(); 1378 1379 if (er == EMULATE_DONE && !(ret & RESUME_HOST)) 1380 kvm_mips_deliver_interrupts(vcpu, cause); 1381 1382 if (!(ret & RESUME_HOST)) { 1383 /* Only check for signals if not already exiting to userspace */ 1384 if (signal_pending(current)) { 1385 run->exit_reason = KVM_EXIT_INTR; 1386 ret = (-EINTR << 2) | RESUME_HOST; 1387 ++vcpu->stat.signal_exits; 1388 trace_kvm_exit(vcpu, SIGNAL_EXITS); 1389 } 1390 } 1391 1392 if (ret == RESUME_GUEST) { 1393 /* 1394 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context 1395 * is live), restore FCR31 / MSACSR. 1396 * 1397 * This should be before returning to the guest exception 1398 * vector, as it may well cause an [MSA] FP exception if there 1399 * are pending exception bits unmasked. (see 1400 * kvm_mips_csr_die_notifier() for how that is handled). 1401 */ 1402 if (kvm_mips_guest_has_fpu(&vcpu->arch) && 1403 read_c0_status() & ST0_CU1) 1404 __kvm_restore_fcsr(&vcpu->arch); 1405 1406 if (kvm_mips_guest_has_msa(&vcpu->arch) && 1407 read_c0_config5() & MIPS_CONF5_MSAEN) 1408 __kvm_restore_msacsr(&vcpu->arch); 1409 } 1410 1411 /* Disable HTW before returning to guest or host */ 1412 htw_stop(); 1413 1414 return ret; 1415 } 1416 1417 /* Enable FPU for guest and restore context */ 1418 void kvm_own_fpu(struct kvm_vcpu *vcpu) 1419 { 1420 struct mips_coproc *cop0 = vcpu->arch.cop0; 1421 unsigned int sr, cfg5; 1422 1423 preempt_disable(); 1424 1425 sr = kvm_read_c0_guest_status(cop0); 1426 1427 /* 1428 * If MSA state is already live, it is undefined how it interacts with 1429 * FR=0 FPU state, and we don't want to hit reserved instruction 1430 * exceptions trying to save the MSA state later when CU=1 && FR=1, so 1431 * play it safe and save it first. 1432 * 1433 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should 1434 * get called when guest CU1 is set, however we can't trust the guest 1435 * not to clobber the status register directly via the commpage. 1436 */ 1437 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && 1438 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) 1439 kvm_lose_fpu(vcpu); 1440 1441 /* 1442 * Enable FPU for guest 1443 * We set FR and FRE according to guest context 1444 */ 1445 change_c0_status(ST0_CU1 | ST0_FR, sr); 1446 if (cpu_has_fre) { 1447 cfg5 = kvm_read_c0_guest_config5(cop0); 1448 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1449 } 1450 enable_fpu_hazard(); 1451 1452 /* If guest FPU state not active, restore it now */ 1453 if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) { 1454 __kvm_restore_fpu(&vcpu->arch); 1455 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU; 1456 } 1457 1458 preempt_enable(); 1459 } 1460 1461 #ifdef CONFIG_CPU_HAS_MSA 1462 /* Enable MSA for guest and restore context */ 1463 void kvm_own_msa(struct kvm_vcpu *vcpu) 1464 { 1465 struct mips_coproc *cop0 = vcpu->arch.cop0; 1466 unsigned int sr, cfg5; 1467 1468 preempt_disable(); 1469 1470 /* 1471 * Enable FPU if enabled in guest, since we're restoring FPU context 1472 * anyway. We set FR and FRE according to guest context. 1473 */ 1474 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { 1475 sr = kvm_read_c0_guest_status(cop0); 1476 1477 /* 1478 * If FR=0 FPU state is already live, it is undefined how it 1479 * interacts with MSA state, so play it safe and save it first. 1480 */ 1481 if (!(sr & ST0_FR) && 1482 (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | 1483 KVM_MIPS_FPU_MSA)) == KVM_MIPS_FPU_FPU) 1484 kvm_lose_fpu(vcpu); 1485 1486 change_c0_status(ST0_CU1 | ST0_FR, sr); 1487 if (sr & ST0_CU1 && cpu_has_fre) { 1488 cfg5 = kvm_read_c0_guest_config5(cop0); 1489 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1490 } 1491 } 1492 1493 /* Enable MSA for guest */ 1494 set_c0_config5(MIPS_CONF5_MSAEN); 1495 enable_fpu_hazard(); 1496 1497 switch (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA)) { 1498 case KVM_MIPS_FPU_FPU: 1499 /* 1500 * Guest FPU state already loaded, only restore upper MSA state 1501 */ 1502 __kvm_restore_msa_upper(&vcpu->arch); 1503 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA; 1504 break; 1505 case 0: 1506 /* Neither FPU or MSA already active, restore full MSA state */ 1507 __kvm_restore_msa(&vcpu->arch); 1508 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA; 1509 if (kvm_mips_guest_has_fpu(&vcpu->arch)) 1510 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU; 1511 break; 1512 default: 1513 break; 1514 } 1515 1516 preempt_enable(); 1517 } 1518 #endif 1519 1520 /* Drop FPU & MSA without saving it */ 1521 void kvm_drop_fpu(struct kvm_vcpu *vcpu) 1522 { 1523 preempt_disable(); 1524 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) { 1525 disable_msa(); 1526 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_MSA; 1527 } 1528 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) { 1529 clear_c0_status(ST0_CU1 | ST0_FR); 1530 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU; 1531 } 1532 preempt_enable(); 1533 } 1534 1535 /* Save and disable FPU & MSA */ 1536 void kvm_lose_fpu(struct kvm_vcpu *vcpu) 1537 { 1538 /* 1539 * FPU & MSA get disabled in root context (hardware) when it is disabled 1540 * in guest context (software), but the register state in the hardware 1541 * may still be in use. This is why we explicitly re-enable the hardware 1542 * before saving. 1543 */ 1544 1545 preempt_disable(); 1546 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) { 1547 set_c0_config5(MIPS_CONF5_MSAEN); 1548 enable_fpu_hazard(); 1549 1550 __kvm_save_msa(&vcpu->arch); 1551 1552 /* Disable MSA & FPU */ 1553 disable_msa(); 1554 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) 1555 clear_c0_status(ST0_CU1 | ST0_FR); 1556 vcpu->arch.fpu_inuse &= ~(KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA); 1557 } else if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) { 1558 set_c0_status(ST0_CU1); 1559 enable_fpu_hazard(); 1560 1561 __kvm_save_fpu(&vcpu->arch); 1562 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU; 1563 1564 /* Disable FPU */ 1565 clear_c0_status(ST0_CU1 | ST0_FR); 1566 } 1567 preempt_enable(); 1568 } 1569 1570 /* 1571 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are 1572 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP 1573 * exception if cause bits are set in the value being written. 1574 */ 1575 static int kvm_mips_csr_die_notify(struct notifier_block *self, 1576 unsigned long cmd, void *ptr) 1577 { 1578 struct die_args *args = (struct die_args *)ptr; 1579 struct pt_regs *regs = args->regs; 1580 unsigned long pc; 1581 1582 /* Only interested in FPE and MSAFPE */ 1583 if (cmd != DIE_FP && cmd != DIE_MSAFP) 1584 return NOTIFY_DONE; 1585 1586 /* Return immediately if guest context isn't active */ 1587 if (!(current->flags & PF_VCPU)) 1588 return NOTIFY_DONE; 1589 1590 /* Should never get here from user mode */ 1591 BUG_ON(user_mode(regs)); 1592 1593 pc = instruction_pointer(regs); 1594 switch (cmd) { 1595 case DIE_FP: 1596 /* match 2nd instruction in __kvm_restore_fcsr */ 1597 if (pc != (unsigned long)&__kvm_restore_fcsr + 4) 1598 return NOTIFY_DONE; 1599 break; 1600 case DIE_MSAFP: 1601 /* match 2nd/3rd instruction in __kvm_restore_msacsr */ 1602 if (!cpu_has_msa || 1603 pc < (unsigned long)&__kvm_restore_msacsr + 4 || 1604 pc > (unsigned long)&__kvm_restore_msacsr + 8) 1605 return NOTIFY_DONE; 1606 break; 1607 } 1608 1609 /* Move PC forward a little and continue executing */ 1610 instruction_pointer(regs) += 4; 1611 1612 return NOTIFY_STOP; 1613 } 1614 1615 static struct notifier_block kvm_mips_csr_die_notifier = { 1616 .notifier_call = kvm_mips_csr_die_notify, 1617 }; 1618 1619 int __init kvm_mips_init(void) 1620 { 1621 int ret; 1622 1623 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); 1624 1625 if (ret) 1626 return ret; 1627 1628 register_die_notifier(&kvm_mips_csr_die_notifier); 1629 1630 /* 1631 * On MIPS, kernel modules are executed from "mapped space", which 1632 * requires TLBs. The TLB handling code is statically linked with 1633 * the rest of the kernel (tlb.c) to avoid the possibility of 1634 * double faulting. The issue is that the TLB code references 1635 * routines that are part of the the KVM module, which are only 1636 * available once the module is loaded. 1637 */ 1638 kvm_mips_gfn_to_pfn = gfn_to_pfn; 1639 kvm_mips_release_pfn_clean = kvm_release_pfn_clean; 1640 kvm_mips_is_error_pfn = is_error_pfn; 1641 1642 return 0; 1643 } 1644 1645 void __exit kvm_mips_exit(void) 1646 { 1647 kvm_exit(); 1648 1649 kvm_mips_gfn_to_pfn = NULL; 1650 kvm_mips_release_pfn_clean = NULL; 1651 kvm_mips_is_error_pfn = NULL; 1652 1653 unregister_die_notifier(&kvm_mips_csr_die_notifier); 1654 } 1655 1656 module_init(kvm_mips_init); 1657 module_exit(kvm_mips_exit); 1658 1659 EXPORT_TRACEPOINT_SYMBOL(kvm_exit); 1660