1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * KVM/MIPS: MIPS specific KVM APIs 7 * 8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 9 * Authors: Sanjay Lal <sanjayl@kymasys.com> 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/errno.h> 14 #include <linux/err.h> 15 #include <linux/kdebug.h> 16 #include <linux/module.h> 17 #include <linux/uaccess.h> 18 #include <linux/vmalloc.h> 19 #include <linux/sched/signal.h> 20 #include <linux/fs.h> 21 #include <linux/memblock.h> 22 23 #include <asm/fpu.h> 24 #include <asm/page.h> 25 #include <asm/cacheflush.h> 26 #include <asm/mmu_context.h> 27 #include <asm/pgalloc.h> 28 #include <asm/pgtable.h> 29 30 #include <linux/kvm_host.h> 31 32 #include "interrupt.h" 33 #include "commpage.h" 34 35 #define CREATE_TRACE_POINTS 36 #include "trace.h" 37 38 #ifndef VECTORSPACING 39 #define VECTORSPACING 0x100 /* for EI/VI mode */ 40 #endif 41 42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x) 43 struct kvm_stats_debugfs_item debugfs_entries[] = { 44 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU }, 45 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU }, 46 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU }, 47 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU }, 48 { "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU }, 49 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU }, 50 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU }, 51 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU }, 52 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU }, 53 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU }, 54 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU }, 55 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU }, 56 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU }, 57 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU }, 58 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU }, 59 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU }, 60 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU }, 61 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU }, 62 #ifdef CONFIG_KVM_MIPS_VZ 63 { "vz_gpsi", VCPU_STAT(vz_gpsi_exits), KVM_STAT_VCPU }, 64 { "vz_gsfc", VCPU_STAT(vz_gsfc_exits), KVM_STAT_VCPU }, 65 { "vz_hc", VCPU_STAT(vz_hc_exits), KVM_STAT_VCPU }, 66 { "vz_grr", VCPU_STAT(vz_grr_exits), KVM_STAT_VCPU }, 67 { "vz_gva", VCPU_STAT(vz_gva_exits), KVM_STAT_VCPU }, 68 { "vz_ghfc", VCPU_STAT(vz_ghfc_exits), KVM_STAT_VCPU }, 69 { "vz_gpa", VCPU_STAT(vz_gpa_exits), KVM_STAT_VCPU }, 70 { "vz_resvd", VCPU_STAT(vz_resvd_exits), KVM_STAT_VCPU }, 71 #endif 72 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU }, 73 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU }, 74 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU }, 75 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU }, 76 {NULL} 77 }; 78 79 bool kvm_trace_guest_mode_change; 80 81 int kvm_guest_mode_change_trace_reg(void) 82 { 83 kvm_trace_guest_mode_change = 1; 84 return 0; 85 } 86 87 void kvm_guest_mode_change_trace_unreg(void) 88 { 89 kvm_trace_guest_mode_change = 0; 90 } 91 92 /* 93 * XXXKYMA: We are simulatoring a processor that has the WII bit set in 94 * Config7, so we are "runnable" if interrupts are pending 95 */ 96 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 97 { 98 return !!(vcpu->arch.pending_exceptions); 99 } 100 101 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 102 { 103 return false; 104 } 105 106 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 107 { 108 return 1; 109 } 110 111 int kvm_arch_hardware_enable(void) 112 { 113 return kvm_mips_callbacks->hardware_enable(); 114 } 115 116 void kvm_arch_hardware_disable(void) 117 { 118 kvm_mips_callbacks->hardware_disable(); 119 } 120 121 int kvm_arch_hardware_setup(void) 122 { 123 return 0; 124 } 125 126 int kvm_arch_check_processor_compat(void) 127 { 128 return 0; 129 } 130 131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 132 { 133 switch (type) { 134 #ifdef CONFIG_KVM_MIPS_VZ 135 case KVM_VM_MIPS_VZ: 136 #else 137 case KVM_VM_MIPS_TE: 138 #endif 139 break; 140 default: 141 /* Unsupported KVM type */ 142 return -EINVAL; 143 }; 144 145 /* Allocate page table to map GPA -> RPA */ 146 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc(); 147 if (!kvm->arch.gpa_mm.pgd) 148 return -ENOMEM; 149 150 return 0; 151 } 152 153 void kvm_mips_free_vcpus(struct kvm *kvm) 154 { 155 unsigned int i; 156 struct kvm_vcpu *vcpu; 157 158 kvm_for_each_vcpu(i, vcpu, kvm) { 159 kvm_vcpu_destroy(vcpu); 160 } 161 162 mutex_lock(&kvm->lock); 163 164 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 165 kvm->vcpus[i] = NULL; 166 167 atomic_set(&kvm->online_vcpus, 0); 168 169 mutex_unlock(&kvm->lock); 170 } 171 172 static void kvm_mips_free_gpa_pt(struct kvm *kvm) 173 { 174 /* It should always be safe to remove after flushing the whole range */ 175 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0)); 176 pgd_free(NULL, kvm->arch.gpa_mm.pgd); 177 } 178 179 void kvm_arch_destroy_vm(struct kvm *kvm) 180 { 181 kvm_mips_free_vcpus(kvm); 182 kvm_mips_free_gpa_pt(kvm); 183 } 184 185 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, 186 unsigned long arg) 187 { 188 return -ENOIOCTLCMD; 189 } 190 191 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 192 unsigned long npages) 193 { 194 return 0; 195 } 196 197 void kvm_arch_flush_shadow_all(struct kvm *kvm) 198 { 199 /* Flush whole GPA */ 200 kvm_mips_flush_gpa_pt(kvm, 0, ~0); 201 202 /* Let implementation do the rest */ 203 kvm_mips_callbacks->flush_shadow_all(kvm); 204 } 205 206 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 207 struct kvm_memory_slot *slot) 208 { 209 /* 210 * The slot has been made invalid (ready for moving or deletion), so we 211 * need to ensure that it can no longer be accessed by any guest VCPUs. 212 */ 213 214 spin_lock(&kvm->mmu_lock); 215 /* Flush slot from GPA */ 216 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn, 217 slot->base_gfn + slot->npages - 1); 218 /* Let implementation do the rest */ 219 kvm_mips_callbacks->flush_shadow_memslot(kvm, slot); 220 spin_unlock(&kvm->mmu_lock); 221 } 222 223 int kvm_arch_prepare_memory_region(struct kvm *kvm, 224 struct kvm_memory_slot *memslot, 225 const struct kvm_userspace_memory_region *mem, 226 enum kvm_mr_change change) 227 { 228 return 0; 229 } 230 231 void kvm_arch_commit_memory_region(struct kvm *kvm, 232 const struct kvm_userspace_memory_region *mem, 233 const struct kvm_memory_slot *old, 234 const struct kvm_memory_slot *new, 235 enum kvm_mr_change change) 236 { 237 int needs_flush; 238 239 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n", 240 __func__, kvm, mem->slot, mem->guest_phys_addr, 241 mem->memory_size, mem->userspace_addr); 242 243 /* 244 * If dirty page logging is enabled, write protect all pages in the slot 245 * ready for dirty logging. 246 * 247 * There is no need to do this in any of the following cases: 248 * CREATE: No dirty mappings will already exist. 249 * MOVE/DELETE: The old mappings will already have been cleaned up by 250 * kvm_arch_flush_shadow_memslot() 251 */ 252 if (change == KVM_MR_FLAGS_ONLY && 253 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 254 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) { 255 spin_lock(&kvm->mmu_lock); 256 /* Write protect GPA page table entries */ 257 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn, 258 new->base_gfn + new->npages - 1); 259 /* Let implementation do the rest */ 260 if (needs_flush) 261 kvm_mips_callbacks->flush_shadow_memslot(kvm, new); 262 spin_unlock(&kvm->mmu_lock); 263 } 264 } 265 266 static inline void dump_handler(const char *symbol, void *start, void *end) 267 { 268 u32 *p; 269 270 pr_debug("LEAF(%s)\n", symbol); 271 272 pr_debug("\t.set push\n"); 273 pr_debug("\t.set noreorder\n"); 274 275 for (p = start; p < (u32 *)end; ++p) 276 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p); 277 278 pr_debug("\t.set\tpop\n"); 279 280 pr_debug("\tEND(%s)\n", symbol); 281 } 282 283 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 284 { 285 return 0; 286 } 287 288 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 289 { 290 int err, size; 291 void *gebase, *p, *handler, *refill_start, *refill_end; 292 int i; 293 294 kvm_debug("kvm @ %p: create cpu %d at %p\n", 295 vcpu->kvm, vcpu->vcpu_id, vcpu); 296 297 err = kvm_mips_callbacks->vcpu_init(vcpu); 298 if (err) 299 return err; 300 301 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 302 HRTIMER_MODE_REL); 303 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 304 305 /* 306 * Allocate space for host mode exception handlers that handle 307 * guest mode exits 308 */ 309 if (cpu_has_veic || cpu_has_vint) 310 size = 0x200 + VECTORSPACING * 64; 311 else 312 size = 0x4000; 313 314 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); 315 316 if (!gebase) { 317 err = -ENOMEM; 318 goto out_uninit_vcpu; 319 } 320 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", 321 ALIGN(size, PAGE_SIZE), gebase); 322 323 /* 324 * Check new ebase actually fits in CP0_EBase. The lack of a write gate 325 * limits us to the low 512MB of physical address space. If the memory 326 * we allocate is out of range, just give up now. 327 */ 328 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) { 329 kvm_err("CP0_EBase.WG required for guest exception base %pK\n", 330 gebase); 331 err = -ENOMEM; 332 goto out_free_gebase; 333 } 334 335 /* Save new ebase */ 336 vcpu->arch.guest_ebase = gebase; 337 338 /* Build guest exception vectors dynamically in unmapped memory */ 339 handler = gebase + 0x2000; 340 341 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */ 342 refill_start = gebase; 343 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT)) 344 refill_start += 0x080; 345 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler); 346 347 /* General Exception Entry point */ 348 kvm_mips_build_exception(gebase + 0x180, handler); 349 350 /* For vectored interrupts poke the exception code @ all offsets 0-7 */ 351 for (i = 0; i < 8; i++) { 352 kvm_debug("L1 Vectored handler @ %p\n", 353 gebase + 0x200 + (i * VECTORSPACING)); 354 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING, 355 handler); 356 } 357 358 /* General exit handler */ 359 p = handler; 360 p = kvm_mips_build_exit(p); 361 362 /* Guest entry routine */ 363 vcpu->arch.vcpu_run = p; 364 p = kvm_mips_build_vcpu_run(p); 365 366 /* Dump the generated code */ 367 pr_debug("#include <asm/asm.h>\n"); 368 pr_debug("#include <asm/regdef.h>\n"); 369 pr_debug("\n"); 370 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p); 371 dump_handler("kvm_tlb_refill", refill_start, refill_end); 372 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200); 373 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run); 374 375 /* Invalidate the icache for these ranges */ 376 flush_icache_range((unsigned long)gebase, 377 (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); 378 379 /* 380 * Allocate comm page for guest kernel, a TLB will be reserved for 381 * mapping GVA @ 0xFFFF8000 to this page 382 */ 383 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL); 384 385 if (!vcpu->arch.kseg0_commpage) { 386 err = -ENOMEM; 387 goto out_free_gebase; 388 } 389 390 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage); 391 kvm_mips_commpage_init(vcpu); 392 393 /* Init */ 394 vcpu->arch.last_sched_cpu = -1; 395 vcpu->arch.last_exec_cpu = -1; 396 397 /* Initial guest state */ 398 err = kvm_mips_callbacks->vcpu_setup(vcpu); 399 if (err) 400 goto out_free_commpage; 401 402 return 0; 403 404 out_free_commpage: 405 kfree(vcpu->arch.kseg0_commpage); 406 out_free_gebase: 407 kfree(gebase); 408 out_uninit_vcpu: 409 kvm_mips_callbacks->vcpu_uninit(vcpu); 410 return err; 411 } 412 413 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 414 { 415 hrtimer_cancel(&vcpu->arch.comparecount_timer); 416 417 kvm_mips_dump_stats(vcpu); 418 419 kvm_mmu_free_memory_caches(vcpu); 420 kfree(vcpu->arch.guest_ebase); 421 kfree(vcpu->arch.kseg0_commpage); 422 423 kvm_mips_callbacks->vcpu_uninit(vcpu); 424 } 425 426 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 427 struct kvm_guest_debug *dbg) 428 { 429 return -ENOIOCTLCMD; 430 } 431 432 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) 433 { 434 int r = -EINTR; 435 436 vcpu_load(vcpu); 437 438 kvm_sigset_activate(vcpu); 439 440 if (vcpu->mmio_needed) { 441 if (!vcpu->mmio_is_write) 442 kvm_mips_complete_mmio_load(vcpu, run); 443 vcpu->mmio_needed = 0; 444 } 445 446 if (run->immediate_exit) 447 goto out; 448 449 lose_fpu(1); 450 451 local_irq_disable(); 452 guest_enter_irqoff(); 453 trace_kvm_enter(vcpu); 454 455 /* 456 * Make sure the read of VCPU requests in vcpu_run() callback is not 457 * reordered ahead of the write to vcpu->mode, or we could miss a TLB 458 * flush request while the requester sees the VCPU as outside of guest 459 * mode and not needing an IPI. 460 */ 461 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 462 463 r = kvm_mips_callbacks->vcpu_run(run, vcpu); 464 465 trace_kvm_out(vcpu); 466 guest_exit_irqoff(); 467 local_irq_enable(); 468 469 out: 470 kvm_sigset_deactivate(vcpu); 471 472 vcpu_put(vcpu); 473 return r; 474 } 475 476 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 477 struct kvm_mips_interrupt *irq) 478 { 479 int intr = (int)irq->irq; 480 struct kvm_vcpu *dvcpu = NULL; 481 482 if (intr == 3 || intr == -3 || intr == 4 || intr == -4) 483 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, 484 (int)intr); 485 486 if (irq->cpu == -1) 487 dvcpu = vcpu; 488 else 489 dvcpu = vcpu->kvm->vcpus[irq->cpu]; 490 491 if (intr == 2 || intr == 3 || intr == 4) { 492 kvm_mips_callbacks->queue_io_int(dvcpu, irq); 493 494 } else if (intr == -2 || intr == -3 || intr == -4) { 495 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); 496 } else { 497 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, 498 irq->cpu, irq->irq); 499 return -EINVAL; 500 } 501 502 dvcpu->arch.wait = 0; 503 504 if (swq_has_sleeper(&dvcpu->wq)) 505 swake_up_one(&dvcpu->wq); 506 507 return 0; 508 } 509 510 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 511 struct kvm_mp_state *mp_state) 512 { 513 return -ENOIOCTLCMD; 514 } 515 516 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 517 struct kvm_mp_state *mp_state) 518 { 519 return -ENOIOCTLCMD; 520 } 521 522 static u64 kvm_mips_get_one_regs[] = { 523 KVM_REG_MIPS_R0, 524 KVM_REG_MIPS_R1, 525 KVM_REG_MIPS_R2, 526 KVM_REG_MIPS_R3, 527 KVM_REG_MIPS_R4, 528 KVM_REG_MIPS_R5, 529 KVM_REG_MIPS_R6, 530 KVM_REG_MIPS_R7, 531 KVM_REG_MIPS_R8, 532 KVM_REG_MIPS_R9, 533 KVM_REG_MIPS_R10, 534 KVM_REG_MIPS_R11, 535 KVM_REG_MIPS_R12, 536 KVM_REG_MIPS_R13, 537 KVM_REG_MIPS_R14, 538 KVM_REG_MIPS_R15, 539 KVM_REG_MIPS_R16, 540 KVM_REG_MIPS_R17, 541 KVM_REG_MIPS_R18, 542 KVM_REG_MIPS_R19, 543 KVM_REG_MIPS_R20, 544 KVM_REG_MIPS_R21, 545 KVM_REG_MIPS_R22, 546 KVM_REG_MIPS_R23, 547 KVM_REG_MIPS_R24, 548 KVM_REG_MIPS_R25, 549 KVM_REG_MIPS_R26, 550 KVM_REG_MIPS_R27, 551 KVM_REG_MIPS_R28, 552 KVM_REG_MIPS_R29, 553 KVM_REG_MIPS_R30, 554 KVM_REG_MIPS_R31, 555 556 #ifndef CONFIG_CPU_MIPSR6 557 KVM_REG_MIPS_HI, 558 KVM_REG_MIPS_LO, 559 #endif 560 KVM_REG_MIPS_PC, 561 }; 562 563 static u64 kvm_mips_get_one_regs_fpu[] = { 564 KVM_REG_MIPS_FCR_IR, 565 KVM_REG_MIPS_FCR_CSR, 566 }; 567 568 static u64 kvm_mips_get_one_regs_msa[] = { 569 KVM_REG_MIPS_MSA_IR, 570 KVM_REG_MIPS_MSA_CSR, 571 }; 572 573 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu) 574 { 575 unsigned long ret; 576 577 ret = ARRAY_SIZE(kvm_mips_get_one_regs); 578 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 579 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48; 580 /* odd doubles */ 581 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64) 582 ret += 16; 583 } 584 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) 585 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32; 586 ret += kvm_mips_callbacks->num_regs(vcpu); 587 588 return ret; 589 } 590 591 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) 592 { 593 u64 index; 594 unsigned int i; 595 596 if (copy_to_user(indices, kvm_mips_get_one_regs, 597 sizeof(kvm_mips_get_one_regs))) 598 return -EFAULT; 599 indices += ARRAY_SIZE(kvm_mips_get_one_regs); 600 601 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 602 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu, 603 sizeof(kvm_mips_get_one_regs_fpu))) 604 return -EFAULT; 605 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu); 606 607 for (i = 0; i < 32; ++i) { 608 index = KVM_REG_MIPS_FPR_32(i); 609 if (copy_to_user(indices, &index, sizeof(index))) 610 return -EFAULT; 611 ++indices; 612 613 /* skip odd doubles if no F64 */ 614 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64)) 615 continue; 616 617 index = KVM_REG_MIPS_FPR_64(i); 618 if (copy_to_user(indices, &index, sizeof(index))) 619 return -EFAULT; 620 ++indices; 621 } 622 } 623 624 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) { 625 if (copy_to_user(indices, kvm_mips_get_one_regs_msa, 626 sizeof(kvm_mips_get_one_regs_msa))) 627 return -EFAULT; 628 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa); 629 630 for (i = 0; i < 32; ++i) { 631 index = KVM_REG_MIPS_VEC_128(i); 632 if (copy_to_user(indices, &index, sizeof(index))) 633 return -EFAULT; 634 ++indices; 635 } 636 } 637 638 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices); 639 } 640 641 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 642 const struct kvm_one_reg *reg) 643 { 644 struct mips_coproc *cop0 = vcpu->arch.cop0; 645 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 646 int ret; 647 s64 v; 648 s64 vs[2]; 649 unsigned int idx; 650 651 switch (reg->id) { 652 /* General purpose registers */ 653 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: 654 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; 655 break; 656 #ifndef CONFIG_CPU_MIPSR6 657 case KVM_REG_MIPS_HI: 658 v = (long)vcpu->arch.hi; 659 break; 660 case KVM_REG_MIPS_LO: 661 v = (long)vcpu->arch.lo; 662 break; 663 #endif 664 case KVM_REG_MIPS_PC: 665 v = (long)vcpu->arch.pc; 666 break; 667 668 /* Floating point registers */ 669 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 670 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 671 return -EINVAL; 672 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 673 /* Odd singles in top of even double when FR=0 */ 674 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 675 v = get_fpr32(&fpu->fpr[idx], 0); 676 else 677 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); 678 break; 679 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 680 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 681 return -EINVAL; 682 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 683 /* Can't access odd doubles in FR=0 mode */ 684 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 685 return -EINVAL; 686 v = get_fpr64(&fpu->fpr[idx], 0); 687 break; 688 case KVM_REG_MIPS_FCR_IR: 689 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 690 return -EINVAL; 691 v = boot_cpu_data.fpu_id; 692 break; 693 case KVM_REG_MIPS_FCR_CSR: 694 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 695 return -EINVAL; 696 v = fpu->fcr31; 697 break; 698 699 /* MIPS SIMD Architecture (MSA) registers */ 700 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 701 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 702 return -EINVAL; 703 /* Can't access MSA registers in FR=0 mode */ 704 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) 705 return -EINVAL; 706 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 707 #ifdef CONFIG_CPU_LITTLE_ENDIAN 708 /* least significant byte first */ 709 vs[0] = get_fpr64(&fpu->fpr[idx], 0); 710 vs[1] = get_fpr64(&fpu->fpr[idx], 1); 711 #else 712 /* most significant byte first */ 713 vs[0] = get_fpr64(&fpu->fpr[idx], 1); 714 vs[1] = get_fpr64(&fpu->fpr[idx], 0); 715 #endif 716 break; 717 case KVM_REG_MIPS_MSA_IR: 718 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 719 return -EINVAL; 720 v = boot_cpu_data.msa_id; 721 break; 722 case KVM_REG_MIPS_MSA_CSR: 723 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 724 return -EINVAL; 725 v = fpu->msacsr; 726 break; 727 728 /* registers to be handled specially */ 729 default: 730 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); 731 if (ret) 732 return ret; 733 break; 734 } 735 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 736 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 737 738 return put_user(v, uaddr64); 739 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 740 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 741 u32 v32 = (u32)v; 742 743 return put_user(v32, uaddr32); 744 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 745 void __user *uaddr = (void __user *)(long)reg->addr; 746 747 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0; 748 } else { 749 return -EINVAL; 750 } 751 } 752 753 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 754 const struct kvm_one_reg *reg) 755 { 756 struct mips_coproc *cop0 = vcpu->arch.cop0; 757 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 758 s64 v; 759 s64 vs[2]; 760 unsigned int idx; 761 762 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 763 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 764 765 if (get_user(v, uaddr64) != 0) 766 return -EFAULT; 767 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 768 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 769 s32 v32; 770 771 if (get_user(v32, uaddr32) != 0) 772 return -EFAULT; 773 v = (s64)v32; 774 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 775 void __user *uaddr = (void __user *)(long)reg->addr; 776 777 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0; 778 } else { 779 return -EINVAL; 780 } 781 782 switch (reg->id) { 783 /* General purpose registers */ 784 case KVM_REG_MIPS_R0: 785 /* Silently ignore requests to set $0 */ 786 break; 787 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: 788 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; 789 break; 790 #ifndef CONFIG_CPU_MIPSR6 791 case KVM_REG_MIPS_HI: 792 vcpu->arch.hi = v; 793 break; 794 case KVM_REG_MIPS_LO: 795 vcpu->arch.lo = v; 796 break; 797 #endif 798 case KVM_REG_MIPS_PC: 799 vcpu->arch.pc = v; 800 break; 801 802 /* Floating point registers */ 803 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 804 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 805 return -EINVAL; 806 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 807 /* Odd singles in top of even double when FR=0 */ 808 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 809 set_fpr32(&fpu->fpr[idx], 0, v); 810 else 811 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); 812 break; 813 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 814 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 815 return -EINVAL; 816 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 817 /* Can't access odd doubles in FR=0 mode */ 818 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 819 return -EINVAL; 820 set_fpr64(&fpu->fpr[idx], 0, v); 821 break; 822 case KVM_REG_MIPS_FCR_IR: 823 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 824 return -EINVAL; 825 /* Read-only */ 826 break; 827 case KVM_REG_MIPS_FCR_CSR: 828 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 829 return -EINVAL; 830 fpu->fcr31 = v; 831 break; 832 833 /* MIPS SIMD Architecture (MSA) registers */ 834 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 835 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 836 return -EINVAL; 837 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 838 #ifdef CONFIG_CPU_LITTLE_ENDIAN 839 /* least significant byte first */ 840 set_fpr64(&fpu->fpr[idx], 0, vs[0]); 841 set_fpr64(&fpu->fpr[idx], 1, vs[1]); 842 #else 843 /* most significant byte first */ 844 set_fpr64(&fpu->fpr[idx], 1, vs[0]); 845 set_fpr64(&fpu->fpr[idx], 0, vs[1]); 846 #endif 847 break; 848 case KVM_REG_MIPS_MSA_IR: 849 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 850 return -EINVAL; 851 /* Read-only */ 852 break; 853 case KVM_REG_MIPS_MSA_CSR: 854 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 855 return -EINVAL; 856 fpu->msacsr = v; 857 break; 858 859 /* registers to be handled specially */ 860 default: 861 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); 862 } 863 return 0; 864 } 865 866 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 867 struct kvm_enable_cap *cap) 868 { 869 int r = 0; 870 871 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) 872 return -EINVAL; 873 if (cap->flags) 874 return -EINVAL; 875 if (cap->args[0]) 876 return -EINVAL; 877 878 switch (cap->cap) { 879 case KVM_CAP_MIPS_FPU: 880 vcpu->arch.fpu_enabled = true; 881 break; 882 case KVM_CAP_MIPS_MSA: 883 vcpu->arch.msa_enabled = true; 884 break; 885 default: 886 r = -EINVAL; 887 break; 888 } 889 890 return r; 891 } 892 893 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl, 894 unsigned long arg) 895 { 896 struct kvm_vcpu *vcpu = filp->private_data; 897 void __user *argp = (void __user *)arg; 898 899 if (ioctl == KVM_INTERRUPT) { 900 struct kvm_mips_interrupt irq; 901 902 if (copy_from_user(&irq, argp, sizeof(irq))) 903 return -EFAULT; 904 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, 905 irq.irq); 906 907 return kvm_vcpu_ioctl_interrupt(vcpu, &irq); 908 } 909 910 return -ENOIOCTLCMD; 911 } 912 913 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, 914 unsigned long arg) 915 { 916 struct kvm_vcpu *vcpu = filp->private_data; 917 void __user *argp = (void __user *)arg; 918 long r; 919 920 vcpu_load(vcpu); 921 922 switch (ioctl) { 923 case KVM_SET_ONE_REG: 924 case KVM_GET_ONE_REG: { 925 struct kvm_one_reg reg; 926 927 r = -EFAULT; 928 if (copy_from_user(®, argp, sizeof(reg))) 929 break; 930 if (ioctl == KVM_SET_ONE_REG) 931 r = kvm_mips_set_reg(vcpu, ®); 932 else 933 r = kvm_mips_get_reg(vcpu, ®); 934 break; 935 } 936 case KVM_GET_REG_LIST: { 937 struct kvm_reg_list __user *user_list = argp; 938 struct kvm_reg_list reg_list; 939 unsigned n; 940 941 r = -EFAULT; 942 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 943 break; 944 n = reg_list.n; 945 reg_list.n = kvm_mips_num_regs(vcpu); 946 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 947 break; 948 r = -E2BIG; 949 if (n < reg_list.n) 950 break; 951 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg); 952 break; 953 } 954 case KVM_ENABLE_CAP: { 955 struct kvm_enable_cap cap; 956 957 r = -EFAULT; 958 if (copy_from_user(&cap, argp, sizeof(cap))) 959 break; 960 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 961 break; 962 } 963 default: 964 r = -ENOIOCTLCMD; 965 } 966 967 vcpu_put(vcpu); 968 return r; 969 } 970 971 /** 972 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 973 * @kvm: kvm instance 974 * @log: slot id and address to which we copy the log 975 * 976 * Steps 1-4 below provide general overview of dirty page logging. See 977 * kvm_get_dirty_log_protect() function description for additional details. 978 * 979 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 980 * always flush the TLB (step 4) even if previous step failed and the dirty 981 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 982 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 983 * writes will be marked dirty for next log read. 984 * 985 * 1. Take a snapshot of the bit and clear it if needed. 986 * 2. Write protect the corresponding page. 987 * 3. Copy the snapshot to the userspace. 988 * 4. Flush TLB's if needed. 989 */ 990 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 991 { 992 struct kvm_memslots *slots; 993 struct kvm_memory_slot *memslot; 994 bool flush = false; 995 int r; 996 997 mutex_lock(&kvm->slots_lock); 998 999 r = kvm_get_dirty_log_protect(kvm, log, &flush); 1000 1001 if (flush) { 1002 slots = kvm_memslots(kvm); 1003 memslot = id_to_memslot(slots, log->slot); 1004 1005 /* Let implementation handle TLB/GVA invalidation */ 1006 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot); 1007 } 1008 1009 mutex_unlock(&kvm->slots_lock); 1010 return r; 1011 } 1012 1013 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log) 1014 { 1015 struct kvm_memslots *slots; 1016 struct kvm_memory_slot *memslot; 1017 bool flush = false; 1018 int r; 1019 1020 mutex_lock(&kvm->slots_lock); 1021 1022 r = kvm_clear_dirty_log_protect(kvm, log, &flush); 1023 1024 if (flush) { 1025 slots = kvm_memslots(kvm); 1026 memslot = id_to_memslot(slots, log->slot); 1027 1028 /* Let implementation handle TLB/GVA invalidation */ 1029 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot); 1030 } 1031 1032 mutex_unlock(&kvm->slots_lock); 1033 return r; 1034 } 1035 1036 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 1037 { 1038 long r; 1039 1040 switch (ioctl) { 1041 default: 1042 r = -ENOIOCTLCMD; 1043 } 1044 1045 return r; 1046 } 1047 1048 int kvm_arch_init(void *opaque) 1049 { 1050 if (kvm_mips_callbacks) { 1051 kvm_err("kvm: module already exists\n"); 1052 return -EEXIST; 1053 } 1054 1055 return kvm_mips_emulation_init(&kvm_mips_callbacks); 1056 } 1057 1058 void kvm_arch_exit(void) 1059 { 1060 kvm_mips_callbacks = NULL; 1061 } 1062 1063 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 1064 struct kvm_sregs *sregs) 1065 { 1066 return -ENOIOCTLCMD; 1067 } 1068 1069 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 1070 struct kvm_sregs *sregs) 1071 { 1072 return -ENOIOCTLCMD; 1073 } 1074 1075 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 1076 { 1077 } 1078 1079 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1080 { 1081 return -ENOIOCTLCMD; 1082 } 1083 1084 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1085 { 1086 return -ENOIOCTLCMD; 1087 } 1088 1089 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 1090 { 1091 return VM_FAULT_SIGBUS; 1092 } 1093 1094 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 1095 { 1096 int r; 1097 1098 switch (ext) { 1099 case KVM_CAP_ONE_REG: 1100 case KVM_CAP_ENABLE_CAP: 1101 case KVM_CAP_READONLY_MEM: 1102 case KVM_CAP_SYNC_MMU: 1103 case KVM_CAP_IMMEDIATE_EXIT: 1104 r = 1; 1105 break; 1106 case KVM_CAP_NR_VCPUS: 1107 r = num_online_cpus(); 1108 break; 1109 case KVM_CAP_MAX_VCPUS: 1110 r = KVM_MAX_VCPUS; 1111 break; 1112 case KVM_CAP_MAX_VCPU_ID: 1113 r = KVM_MAX_VCPU_ID; 1114 break; 1115 case KVM_CAP_MIPS_FPU: 1116 /* We don't handle systems with inconsistent cpu_has_fpu */ 1117 r = !!raw_cpu_has_fpu; 1118 break; 1119 case KVM_CAP_MIPS_MSA: 1120 /* 1121 * We don't support MSA vector partitioning yet: 1122 * 1) It would require explicit support which can't be tested 1123 * yet due to lack of support in current hardware. 1124 * 2) It extends the state that would need to be saved/restored 1125 * by e.g. QEMU for migration. 1126 * 1127 * When vector partitioning hardware becomes available, support 1128 * could be added by requiring a flag when enabling 1129 * KVM_CAP_MIPS_MSA capability to indicate that userland knows 1130 * to save/restore the appropriate extra state. 1131 */ 1132 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); 1133 break; 1134 default: 1135 r = kvm_mips_callbacks->check_extension(kvm, ext); 1136 break; 1137 } 1138 return r; 1139 } 1140 1141 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 1142 { 1143 return kvm_mips_pending_timer(vcpu) || 1144 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI; 1145 } 1146 1147 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) 1148 { 1149 int i; 1150 struct mips_coproc *cop0; 1151 1152 if (!vcpu) 1153 return -1; 1154 1155 kvm_debug("VCPU Register Dump:\n"); 1156 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); 1157 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); 1158 1159 for (i = 0; i < 32; i += 4) { 1160 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, 1161 vcpu->arch.gprs[i], 1162 vcpu->arch.gprs[i + 1], 1163 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); 1164 } 1165 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); 1166 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); 1167 1168 cop0 = vcpu->arch.cop0; 1169 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n", 1170 kvm_read_c0_guest_status(cop0), 1171 kvm_read_c0_guest_cause(cop0)); 1172 1173 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); 1174 1175 return 0; 1176 } 1177 1178 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1179 { 1180 int i; 1181 1182 vcpu_load(vcpu); 1183 1184 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1185 vcpu->arch.gprs[i] = regs->gpr[i]; 1186 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ 1187 vcpu->arch.hi = regs->hi; 1188 vcpu->arch.lo = regs->lo; 1189 vcpu->arch.pc = regs->pc; 1190 1191 vcpu_put(vcpu); 1192 return 0; 1193 } 1194 1195 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1196 { 1197 int i; 1198 1199 vcpu_load(vcpu); 1200 1201 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1202 regs->gpr[i] = vcpu->arch.gprs[i]; 1203 1204 regs->hi = vcpu->arch.hi; 1205 regs->lo = vcpu->arch.lo; 1206 regs->pc = vcpu->arch.pc; 1207 1208 vcpu_put(vcpu); 1209 return 0; 1210 } 1211 1212 static void kvm_mips_comparecount_func(unsigned long data) 1213 { 1214 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data; 1215 1216 kvm_mips_callbacks->queue_timer_int(vcpu); 1217 1218 vcpu->arch.wait = 0; 1219 if (swq_has_sleeper(&vcpu->wq)) 1220 swake_up_one(&vcpu->wq); 1221 } 1222 1223 /* low level hrtimer wake routine */ 1224 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) 1225 { 1226 struct kvm_vcpu *vcpu; 1227 1228 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); 1229 kvm_mips_comparecount_func((unsigned long) vcpu); 1230 return kvm_mips_count_timeout(vcpu); 1231 } 1232 1233 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 1234 struct kvm_translation *tr) 1235 { 1236 return 0; 1237 } 1238 1239 static void kvm_mips_set_c0_status(void) 1240 { 1241 u32 status = read_c0_status(); 1242 1243 if (cpu_has_dsp) 1244 status |= (ST0_MX); 1245 1246 write_c0_status(status); 1247 ehb(); 1248 } 1249 1250 /* 1251 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) 1252 */ 1253 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) 1254 { 1255 u32 cause = vcpu->arch.host_cp0_cause; 1256 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; 1257 u32 __user *opc = (u32 __user *) vcpu->arch.pc; 1258 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; 1259 enum emulation_result er = EMULATE_DONE; 1260 u32 inst; 1261 int ret = RESUME_GUEST; 1262 1263 vcpu->mode = OUTSIDE_GUEST_MODE; 1264 1265 /* re-enable HTW before enabling interrupts */ 1266 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) 1267 htw_start(); 1268 1269 /* Set a default exit reason */ 1270 run->exit_reason = KVM_EXIT_UNKNOWN; 1271 run->ready_for_interrupt_injection = 1; 1272 1273 /* 1274 * Set the appropriate status bits based on host CPU features, 1275 * before we hit the scheduler 1276 */ 1277 kvm_mips_set_c0_status(); 1278 1279 local_irq_enable(); 1280 1281 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", 1282 cause, opc, run, vcpu); 1283 trace_kvm_exit(vcpu, exccode); 1284 1285 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1286 /* 1287 * Do a privilege check, if in UM most of these exit conditions 1288 * end up causing an exception to be delivered to the Guest 1289 * Kernel 1290 */ 1291 er = kvm_mips_check_privilege(cause, opc, run, vcpu); 1292 if (er == EMULATE_PRIV_FAIL) { 1293 goto skip_emul; 1294 } else if (er == EMULATE_FAIL) { 1295 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1296 ret = RESUME_HOST; 1297 goto skip_emul; 1298 } 1299 } 1300 1301 switch (exccode) { 1302 case EXCCODE_INT: 1303 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc); 1304 1305 ++vcpu->stat.int_exits; 1306 1307 if (need_resched()) 1308 cond_resched(); 1309 1310 ret = RESUME_GUEST; 1311 break; 1312 1313 case EXCCODE_CPU: 1314 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc); 1315 1316 ++vcpu->stat.cop_unusable_exits; 1317 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); 1318 /* XXXKYMA: Might need to return to user space */ 1319 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) 1320 ret = RESUME_HOST; 1321 break; 1322 1323 case EXCCODE_MOD: 1324 ++vcpu->stat.tlbmod_exits; 1325 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); 1326 break; 1327 1328 case EXCCODE_TLBS: 1329 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n", 1330 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, 1331 badvaddr); 1332 1333 ++vcpu->stat.tlbmiss_st_exits; 1334 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); 1335 break; 1336 1337 case EXCCODE_TLBL: 1338 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", 1339 cause, opc, badvaddr); 1340 1341 ++vcpu->stat.tlbmiss_ld_exits; 1342 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); 1343 break; 1344 1345 case EXCCODE_ADES: 1346 ++vcpu->stat.addrerr_st_exits; 1347 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); 1348 break; 1349 1350 case EXCCODE_ADEL: 1351 ++vcpu->stat.addrerr_ld_exits; 1352 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); 1353 break; 1354 1355 case EXCCODE_SYS: 1356 ++vcpu->stat.syscall_exits; 1357 ret = kvm_mips_callbacks->handle_syscall(vcpu); 1358 break; 1359 1360 case EXCCODE_RI: 1361 ++vcpu->stat.resvd_inst_exits; 1362 ret = kvm_mips_callbacks->handle_res_inst(vcpu); 1363 break; 1364 1365 case EXCCODE_BP: 1366 ++vcpu->stat.break_inst_exits; 1367 ret = kvm_mips_callbacks->handle_break(vcpu); 1368 break; 1369 1370 case EXCCODE_TR: 1371 ++vcpu->stat.trap_inst_exits; 1372 ret = kvm_mips_callbacks->handle_trap(vcpu); 1373 break; 1374 1375 case EXCCODE_MSAFPE: 1376 ++vcpu->stat.msa_fpe_exits; 1377 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); 1378 break; 1379 1380 case EXCCODE_FPE: 1381 ++vcpu->stat.fpe_exits; 1382 ret = kvm_mips_callbacks->handle_fpe(vcpu); 1383 break; 1384 1385 case EXCCODE_MSADIS: 1386 ++vcpu->stat.msa_disabled_exits; 1387 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); 1388 break; 1389 1390 case EXCCODE_GE: 1391 /* defer exit accounting to handler */ 1392 ret = kvm_mips_callbacks->handle_guest_exit(vcpu); 1393 break; 1394 1395 default: 1396 if (cause & CAUSEF_BD) 1397 opc += 1; 1398 inst = 0; 1399 kvm_get_badinstr(opc, vcpu, &inst); 1400 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n", 1401 exccode, opc, inst, badvaddr, 1402 kvm_read_c0_guest_status(vcpu->arch.cop0)); 1403 kvm_arch_vcpu_dump_regs(vcpu); 1404 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1405 ret = RESUME_HOST; 1406 break; 1407 1408 } 1409 1410 skip_emul: 1411 local_irq_disable(); 1412 1413 if (ret == RESUME_GUEST) 1414 kvm_vz_acquire_htimer(vcpu); 1415 1416 if (er == EMULATE_DONE && !(ret & RESUME_HOST)) 1417 kvm_mips_deliver_interrupts(vcpu, cause); 1418 1419 if (!(ret & RESUME_HOST)) { 1420 /* Only check for signals if not already exiting to userspace */ 1421 if (signal_pending(current)) { 1422 run->exit_reason = KVM_EXIT_INTR; 1423 ret = (-EINTR << 2) | RESUME_HOST; 1424 ++vcpu->stat.signal_exits; 1425 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL); 1426 } 1427 } 1428 1429 if (ret == RESUME_GUEST) { 1430 trace_kvm_reenter(vcpu); 1431 1432 /* 1433 * Make sure the read of VCPU requests in vcpu_reenter() 1434 * callback is not reordered ahead of the write to vcpu->mode, 1435 * or we could miss a TLB flush request while the requester sees 1436 * the VCPU as outside of guest mode and not needing an IPI. 1437 */ 1438 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 1439 1440 kvm_mips_callbacks->vcpu_reenter(run, vcpu); 1441 1442 /* 1443 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context 1444 * is live), restore FCR31 / MSACSR. 1445 * 1446 * This should be before returning to the guest exception 1447 * vector, as it may well cause an [MSA] FP exception if there 1448 * are pending exception bits unmasked. (see 1449 * kvm_mips_csr_die_notifier() for how that is handled). 1450 */ 1451 if (kvm_mips_guest_has_fpu(&vcpu->arch) && 1452 read_c0_status() & ST0_CU1) 1453 __kvm_restore_fcsr(&vcpu->arch); 1454 1455 if (kvm_mips_guest_has_msa(&vcpu->arch) && 1456 read_c0_config5() & MIPS_CONF5_MSAEN) 1457 __kvm_restore_msacsr(&vcpu->arch); 1458 } 1459 1460 /* Disable HTW before returning to guest or host */ 1461 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) 1462 htw_stop(); 1463 1464 return ret; 1465 } 1466 1467 /* Enable FPU for guest and restore context */ 1468 void kvm_own_fpu(struct kvm_vcpu *vcpu) 1469 { 1470 struct mips_coproc *cop0 = vcpu->arch.cop0; 1471 unsigned int sr, cfg5; 1472 1473 preempt_disable(); 1474 1475 sr = kvm_read_c0_guest_status(cop0); 1476 1477 /* 1478 * If MSA state is already live, it is undefined how it interacts with 1479 * FR=0 FPU state, and we don't want to hit reserved instruction 1480 * exceptions trying to save the MSA state later when CU=1 && FR=1, so 1481 * play it safe and save it first. 1482 * 1483 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should 1484 * get called when guest CU1 is set, however we can't trust the guest 1485 * not to clobber the status register directly via the commpage. 1486 */ 1487 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && 1488 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) 1489 kvm_lose_fpu(vcpu); 1490 1491 /* 1492 * Enable FPU for guest 1493 * We set FR and FRE according to guest context 1494 */ 1495 change_c0_status(ST0_CU1 | ST0_FR, sr); 1496 if (cpu_has_fre) { 1497 cfg5 = kvm_read_c0_guest_config5(cop0); 1498 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1499 } 1500 enable_fpu_hazard(); 1501 1502 /* If guest FPU state not active, restore it now */ 1503 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) { 1504 __kvm_restore_fpu(&vcpu->arch); 1505 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1506 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU); 1507 } else { 1508 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU); 1509 } 1510 1511 preempt_enable(); 1512 } 1513 1514 #ifdef CONFIG_CPU_HAS_MSA 1515 /* Enable MSA for guest and restore context */ 1516 void kvm_own_msa(struct kvm_vcpu *vcpu) 1517 { 1518 struct mips_coproc *cop0 = vcpu->arch.cop0; 1519 unsigned int sr, cfg5; 1520 1521 preempt_disable(); 1522 1523 /* 1524 * Enable FPU if enabled in guest, since we're restoring FPU context 1525 * anyway. We set FR and FRE according to guest context. 1526 */ 1527 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { 1528 sr = kvm_read_c0_guest_status(cop0); 1529 1530 /* 1531 * If FR=0 FPU state is already live, it is undefined how it 1532 * interacts with MSA state, so play it safe and save it first. 1533 */ 1534 if (!(sr & ST0_FR) && 1535 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | 1536 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU) 1537 kvm_lose_fpu(vcpu); 1538 1539 change_c0_status(ST0_CU1 | ST0_FR, sr); 1540 if (sr & ST0_CU1 && cpu_has_fre) { 1541 cfg5 = kvm_read_c0_guest_config5(cop0); 1542 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1543 } 1544 } 1545 1546 /* Enable MSA for guest */ 1547 set_c0_config5(MIPS_CONF5_MSAEN); 1548 enable_fpu_hazard(); 1549 1550 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) { 1551 case KVM_MIPS_AUX_FPU: 1552 /* 1553 * Guest FPU state already loaded, only restore upper MSA state 1554 */ 1555 __kvm_restore_msa_upper(&vcpu->arch); 1556 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1557 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA); 1558 break; 1559 case 0: 1560 /* Neither FPU or MSA already active, restore full MSA state */ 1561 __kvm_restore_msa(&vcpu->arch); 1562 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1563 if (kvm_mips_guest_has_fpu(&vcpu->arch)) 1564 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1565 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, 1566 KVM_TRACE_AUX_FPU_MSA); 1567 break; 1568 default: 1569 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA); 1570 break; 1571 } 1572 1573 preempt_enable(); 1574 } 1575 #endif 1576 1577 /* Drop FPU & MSA without saving it */ 1578 void kvm_drop_fpu(struct kvm_vcpu *vcpu) 1579 { 1580 preempt_disable(); 1581 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1582 disable_msa(); 1583 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA); 1584 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA; 1585 } 1586 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1587 clear_c0_status(ST0_CU1 | ST0_FR); 1588 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU); 1589 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1590 } 1591 preempt_enable(); 1592 } 1593 1594 /* Save and disable FPU & MSA */ 1595 void kvm_lose_fpu(struct kvm_vcpu *vcpu) 1596 { 1597 /* 1598 * With T&E, FPU & MSA get disabled in root context (hardware) when it 1599 * is disabled in guest context (software), but the register state in 1600 * the hardware may still be in use. 1601 * This is why we explicitly re-enable the hardware before saving. 1602 */ 1603 1604 preempt_disable(); 1605 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1606 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1607 set_c0_config5(MIPS_CONF5_MSAEN); 1608 enable_fpu_hazard(); 1609 } 1610 1611 __kvm_save_msa(&vcpu->arch); 1612 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA); 1613 1614 /* Disable MSA & FPU */ 1615 disable_msa(); 1616 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1617 clear_c0_status(ST0_CU1 | ST0_FR); 1618 disable_fpu_hazard(); 1619 } 1620 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA); 1621 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1622 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1623 set_c0_status(ST0_CU1); 1624 enable_fpu_hazard(); 1625 } 1626 1627 __kvm_save_fpu(&vcpu->arch); 1628 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1629 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU); 1630 1631 /* Disable FPU */ 1632 clear_c0_status(ST0_CU1 | ST0_FR); 1633 disable_fpu_hazard(); 1634 } 1635 preempt_enable(); 1636 } 1637 1638 /* 1639 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are 1640 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP 1641 * exception if cause bits are set in the value being written. 1642 */ 1643 static int kvm_mips_csr_die_notify(struct notifier_block *self, 1644 unsigned long cmd, void *ptr) 1645 { 1646 struct die_args *args = (struct die_args *)ptr; 1647 struct pt_regs *regs = args->regs; 1648 unsigned long pc; 1649 1650 /* Only interested in FPE and MSAFPE */ 1651 if (cmd != DIE_FP && cmd != DIE_MSAFP) 1652 return NOTIFY_DONE; 1653 1654 /* Return immediately if guest context isn't active */ 1655 if (!(current->flags & PF_VCPU)) 1656 return NOTIFY_DONE; 1657 1658 /* Should never get here from user mode */ 1659 BUG_ON(user_mode(regs)); 1660 1661 pc = instruction_pointer(regs); 1662 switch (cmd) { 1663 case DIE_FP: 1664 /* match 2nd instruction in __kvm_restore_fcsr */ 1665 if (pc != (unsigned long)&__kvm_restore_fcsr + 4) 1666 return NOTIFY_DONE; 1667 break; 1668 case DIE_MSAFP: 1669 /* match 2nd/3rd instruction in __kvm_restore_msacsr */ 1670 if (!cpu_has_msa || 1671 pc < (unsigned long)&__kvm_restore_msacsr + 4 || 1672 pc > (unsigned long)&__kvm_restore_msacsr + 8) 1673 return NOTIFY_DONE; 1674 break; 1675 } 1676 1677 /* Move PC forward a little and continue executing */ 1678 instruction_pointer(regs) += 4; 1679 1680 return NOTIFY_STOP; 1681 } 1682 1683 static struct notifier_block kvm_mips_csr_die_notifier = { 1684 .notifier_call = kvm_mips_csr_die_notify, 1685 }; 1686 1687 static int __init kvm_mips_init(void) 1688 { 1689 int ret; 1690 1691 if (cpu_has_mmid) { 1692 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n"); 1693 return -EOPNOTSUPP; 1694 } 1695 1696 ret = kvm_mips_entry_setup(); 1697 if (ret) 1698 return ret; 1699 1700 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); 1701 1702 if (ret) 1703 return ret; 1704 1705 register_die_notifier(&kvm_mips_csr_die_notifier); 1706 1707 return 0; 1708 } 1709 1710 static void __exit kvm_mips_exit(void) 1711 { 1712 kvm_exit(); 1713 1714 unregister_die_notifier(&kvm_mips_csr_die_notifier); 1715 } 1716 1717 module_init(kvm_mips_init); 1718 module_exit(kvm_mips_exit); 1719 1720 EXPORT_TRACEPOINT_SYMBOL(kvm_exit); 1721