1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * KVM/MIPS: MIPS specific KVM APIs 7 * 8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 9 * Authors: Sanjay Lal <sanjayl@kymasys.com> 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/errno.h> 14 #include <linux/err.h> 15 #include <linux/kdebug.h> 16 #include <linux/module.h> 17 #include <linux/uaccess.h> 18 #include <linux/vmalloc.h> 19 #include <linux/fs.h> 20 #include <linux/bootmem.h> 21 #include <asm/fpu.h> 22 #include <asm/page.h> 23 #include <asm/cacheflush.h> 24 #include <asm/mmu_context.h> 25 #include <asm/pgalloc.h> 26 #include <asm/pgtable.h> 27 28 #include <linux/kvm_host.h> 29 30 #include "interrupt.h" 31 #include "commpage.h" 32 33 #define CREATE_TRACE_POINTS 34 #include "trace.h" 35 36 #ifndef VECTORSPACING 37 #define VECTORSPACING 0x100 /* for EI/VI mode */ 38 #endif 39 40 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x) 41 struct kvm_stats_debugfs_item debugfs_entries[] = { 42 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU }, 43 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU }, 44 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU }, 45 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU }, 46 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU }, 47 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU }, 48 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU }, 49 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU }, 50 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU }, 51 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU }, 52 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU }, 53 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU }, 54 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU }, 55 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU }, 56 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU }, 57 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU }, 58 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU }, 59 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU }, 60 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU }, 61 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU }, 62 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU }, 63 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU }, 64 {NULL} 65 }; 66 67 /* 68 * XXXKYMA: We are simulatoring a processor that has the WII bit set in 69 * Config7, so we are "runnable" if interrupts are pending 70 */ 71 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 72 { 73 return !!(vcpu->arch.pending_exceptions); 74 } 75 76 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 77 { 78 return 1; 79 } 80 81 int kvm_arch_hardware_enable(void) 82 { 83 return 0; 84 } 85 86 int kvm_arch_hardware_setup(void) 87 { 88 return 0; 89 } 90 91 void kvm_arch_check_processor_compat(void *rtn) 92 { 93 *(int *)rtn = 0; 94 } 95 96 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 97 { 98 /* Allocate page table to map GPA -> RPA */ 99 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc(); 100 if (!kvm->arch.gpa_mm.pgd) 101 return -ENOMEM; 102 103 return 0; 104 } 105 106 bool kvm_arch_has_vcpu_debugfs(void) 107 { 108 return false; 109 } 110 111 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu) 112 { 113 return 0; 114 } 115 116 void kvm_mips_free_vcpus(struct kvm *kvm) 117 { 118 unsigned int i; 119 struct kvm_vcpu *vcpu; 120 121 kvm_for_each_vcpu(i, vcpu, kvm) { 122 kvm_arch_vcpu_free(vcpu); 123 } 124 125 mutex_lock(&kvm->lock); 126 127 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 128 kvm->vcpus[i] = NULL; 129 130 atomic_set(&kvm->online_vcpus, 0); 131 132 mutex_unlock(&kvm->lock); 133 } 134 135 static void kvm_mips_free_gpa_pt(struct kvm *kvm) 136 { 137 /* It should always be safe to remove after flushing the whole range */ 138 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0)); 139 pgd_free(NULL, kvm->arch.gpa_mm.pgd); 140 } 141 142 void kvm_arch_destroy_vm(struct kvm *kvm) 143 { 144 kvm_mips_free_vcpus(kvm); 145 kvm_mips_free_gpa_pt(kvm); 146 } 147 148 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, 149 unsigned long arg) 150 { 151 return -ENOIOCTLCMD; 152 } 153 154 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 155 unsigned long npages) 156 { 157 return 0; 158 } 159 160 void kvm_arch_flush_shadow_all(struct kvm *kvm) 161 { 162 /* Flush whole GPA */ 163 kvm_mips_flush_gpa_pt(kvm, 0, ~0); 164 165 /* Let implementation do the rest */ 166 kvm_mips_callbacks->flush_shadow_all(kvm); 167 } 168 169 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 170 struct kvm_memory_slot *slot) 171 { 172 /* 173 * The slot has been made invalid (ready for moving or deletion), so we 174 * need to ensure that it can no longer be accessed by any guest VCPUs. 175 */ 176 177 spin_lock(&kvm->mmu_lock); 178 /* Flush slot from GPA */ 179 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn, 180 slot->base_gfn + slot->npages - 1); 181 /* Let implementation do the rest */ 182 kvm_mips_callbacks->flush_shadow_memslot(kvm, slot); 183 spin_unlock(&kvm->mmu_lock); 184 } 185 186 int kvm_arch_prepare_memory_region(struct kvm *kvm, 187 struct kvm_memory_slot *memslot, 188 const struct kvm_userspace_memory_region *mem, 189 enum kvm_mr_change change) 190 { 191 return 0; 192 } 193 194 void kvm_arch_commit_memory_region(struct kvm *kvm, 195 const struct kvm_userspace_memory_region *mem, 196 const struct kvm_memory_slot *old, 197 const struct kvm_memory_slot *new, 198 enum kvm_mr_change change) 199 { 200 int needs_flush; 201 202 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n", 203 __func__, kvm, mem->slot, mem->guest_phys_addr, 204 mem->memory_size, mem->userspace_addr); 205 206 /* 207 * If dirty page logging is enabled, write protect all pages in the slot 208 * ready for dirty logging. 209 * 210 * There is no need to do this in any of the following cases: 211 * CREATE: No dirty mappings will already exist. 212 * MOVE/DELETE: The old mappings will already have been cleaned up by 213 * kvm_arch_flush_shadow_memslot() 214 */ 215 if (change == KVM_MR_FLAGS_ONLY && 216 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 217 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) { 218 spin_lock(&kvm->mmu_lock); 219 /* Write protect GPA page table entries */ 220 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn, 221 new->base_gfn + new->npages - 1); 222 /* Let implementation do the rest */ 223 if (needs_flush) 224 kvm_mips_callbacks->flush_shadow_memslot(kvm, new); 225 spin_unlock(&kvm->mmu_lock); 226 } 227 } 228 229 static inline void dump_handler(const char *symbol, void *start, void *end) 230 { 231 u32 *p; 232 233 pr_debug("LEAF(%s)\n", symbol); 234 235 pr_debug("\t.set push\n"); 236 pr_debug("\t.set noreorder\n"); 237 238 for (p = start; p < (u32 *)end; ++p) 239 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p); 240 241 pr_debug("\t.set\tpop\n"); 242 243 pr_debug("\tEND(%s)\n", symbol); 244 } 245 246 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) 247 { 248 int err, size; 249 void *gebase, *p, *handler, *refill_start, *refill_end; 250 int i; 251 252 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL); 253 254 if (!vcpu) { 255 err = -ENOMEM; 256 goto out; 257 } 258 259 err = kvm_vcpu_init(vcpu, kvm, id); 260 261 if (err) 262 goto out_free_cpu; 263 264 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu); 265 266 /* 267 * Allocate space for host mode exception handlers that handle 268 * guest mode exits 269 */ 270 if (cpu_has_veic || cpu_has_vint) 271 size = 0x200 + VECTORSPACING * 64; 272 else 273 size = 0x4000; 274 275 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); 276 277 if (!gebase) { 278 err = -ENOMEM; 279 goto out_uninit_cpu; 280 } 281 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", 282 ALIGN(size, PAGE_SIZE), gebase); 283 284 /* 285 * Check new ebase actually fits in CP0_EBase. The lack of a write gate 286 * limits us to the low 512MB of physical address space. If the memory 287 * we allocate is out of range, just give up now. 288 */ 289 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) { 290 kvm_err("CP0_EBase.WG required for guest exception base %pK\n", 291 gebase); 292 err = -ENOMEM; 293 goto out_free_gebase; 294 } 295 296 /* Save new ebase */ 297 vcpu->arch.guest_ebase = gebase; 298 299 /* Build guest exception vectors dynamically in unmapped memory */ 300 handler = gebase + 0x2000; 301 302 /* TLB refill */ 303 refill_start = gebase; 304 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler); 305 306 /* General Exception Entry point */ 307 kvm_mips_build_exception(gebase + 0x180, handler); 308 309 /* For vectored interrupts poke the exception code @ all offsets 0-7 */ 310 for (i = 0; i < 8; i++) { 311 kvm_debug("L1 Vectored handler @ %p\n", 312 gebase + 0x200 + (i * VECTORSPACING)); 313 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING, 314 handler); 315 } 316 317 /* General exit handler */ 318 p = handler; 319 p = kvm_mips_build_exit(p); 320 321 /* Guest entry routine */ 322 vcpu->arch.vcpu_run = p; 323 p = kvm_mips_build_vcpu_run(p); 324 325 /* Dump the generated code */ 326 pr_debug("#include <asm/asm.h>\n"); 327 pr_debug("#include <asm/regdef.h>\n"); 328 pr_debug("\n"); 329 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p); 330 dump_handler("kvm_tlb_refill", refill_start, refill_end); 331 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200); 332 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run); 333 334 /* Invalidate the icache for these ranges */ 335 flush_icache_range((unsigned long)gebase, 336 (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); 337 338 /* 339 * Allocate comm page for guest kernel, a TLB will be reserved for 340 * mapping GVA @ 0xFFFF8000 to this page 341 */ 342 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL); 343 344 if (!vcpu->arch.kseg0_commpage) { 345 err = -ENOMEM; 346 goto out_free_gebase; 347 } 348 349 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage); 350 kvm_mips_commpage_init(vcpu); 351 352 /* Init */ 353 vcpu->arch.last_sched_cpu = -1; 354 355 /* Start off the timer */ 356 kvm_mips_init_count(vcpu); 357 358 return vcpu; 359 360 out_free_gebase: 361 kfree(gebase); 362 363 out_uninit_cpu: 364 kvm_vcpu_uninit(vcpu); 365 366 out_free_cpu: 367 kfree(vcpu); 368 369 out: 370 return ERR_PTR(err); 371 } 372 373 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 374 { 375 hrtimer_cancel(&vcpu->arch.comparecount_timer); 376 377 kvm_vcpu_uninit(vcpu); 378 379 kvm_mips_dump_stats(vcpu); 380 381 kvm_mmu_free_memory_caches(vcpu); 382 kfree(vcpu->arch.guest_ebase); 383 kfree(vcpu->arch.kseg0_commpage); 384 kfree(vcpu); 385 } 386 387 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 388 { 389 kvm_arch_vcpu_free(vcpu); 390 } 391 392 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 393 struct kvm_guest_debug *dbg) 394 { 395 return -ENOIOCTLCMD; 396 } 397 398 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) 399 { 400 int r = -EINTR; 401 sigset_t sigsaved; 402 403 if (vcpu->sigset_active) 404 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 405 406 if (vcpu->mmio_needed) { 407 if (!vcpu->mmio_is_write) 408 kvm_mips_complete_mmio_load(vcpu, run); 409 vcpu->mmio_needed = 0; 410 } 411 412 if (run->immediate_exit) 413 goto out; 414 415 lose_fpu(1); 416 417 local_irq_disable(); 418 guest_enter_irqoff(); 419 trace_kvm_enter(vcpu); 420 421 /* 422 * Make sure the read of VCPU requests in vcpu_run() callback is not 423 * reordered ahead of the write to vcpu->mode, or we could miss a TLB 424 * flush request while the requester sees the VCPU as outside of guest 425 * mode and not needing an IPI. 426 */ 427 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 428 429 r = kvm_mips_callbacks->vcpu_run(run, vcpu); 430 431 trace_kvm_out(vcpu); 432 guest_exit_irqoff(); 433 local_irq_enable(); 434 435 out: 436 if (vcpu->sigset_active) 437 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 438 439 return r; 440 } 441 442 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 443 struct kvm_mips_interrupt *irq) 444 { 445 int intr = (int)irq->irq; 446 struct kvm_vcpu *dvcpu = NULL; 447 448 if (intr == 3 || intr == -3 || intr == 4 || intr == -4) 449 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, 450 (int)intr); 451 452 if (irq->cpu == -1) 453 dvcpu = vcpu; 454 else 455 dvcpu = vcpu->kvm->vcpus[irq->cpu]; 456 457 if (intr == 2 || intr == 3 || intr == 4) { 458 kvm_mips_callbacks->queue_io_int(dvcpu, irq); 459 460 } else if (intr == -2 || intr == -3 || intr == -4) { 461 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); 462 } else { 463 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, 464 irq->cpu, irq->irq); 465 return -EINVAL; 466 } 467 468 dvcpu->arch.wait = 0; 469 470 if (swait_active(&dvcpu->wq)) 471 swake_up(&dvcpu->wq); 472 473 return 0; 474 } 475 476 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 477 struct kvm_mp_state *mp_state) 478 { 479 return -ENOIOCTLCMD; 480 } 481 482 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 483 struct kvm_mp_state *mp_state) 484 { 485 return -ENOIOCTLCMD; 486 } 487 488 static u64 kvm_mips_get_one_regs[] = { 489 KVM_REG_MIPS_R0, 490 KVM_REG_MIPS_R1, 491 KVM_REG_MIPS_R2, 492 KVM_REG_MIPS_R3, 493 KVM_REG_MIPS_R4, 494 KVM_REG_MIPS_R5, 495 KVM_REG_MIPS_R6, 496 KVM_REG_MIPS_R7, 497 KVM_REG_MIPS_R8, 498 KVM_REG_MIPS_R9, 499 KVM_REG_MIPS_R10, 500 KVM_REG_MIPS_R11, 501 KVM_REG_MIPS_R12, 502 KVM_REG_MIPS_R13, 503 KVM_REG_MIPS_R14, 504 KVM_REG_MIPS_R15, 505 KVM_REG_MIPS_R16, 506 KVM_REG_MIPS_R17, 507 KVM_REG_MIPS_R18, 508 KVM_REG_MIPS_R19, 509 KVM_REG_MIPS_R20, 510 KVM_REG_MIPS_R21, 511 KVM_REG_MIPS_R22, 512 KVM_REG_MIPS_R23, 513 KVM_REG_MIPS_R24, 514 KVM_REG_MIPS_R25, 515 KVM_REG_MIPS_R26, 516 KVM_REG_MIPS_R27, 517 KVM_REG_MIPS_R28, 518 KVM_REG_MIPS_R29, 519 KVM_REG_MIPS_R30, 520 KVM_REG_MIPS_R31, 521 522 #ifndef CONFIG_CPU_MIPSR6 523 KVM_REG_MIPS_HI, 524 KVM_REG_MIPS_LO, 525 #endif 526 KVM_REG_MIPS_PC, 527 }; 528 529 static u64 kvm_mips_get_one_regs_fpu[] = { 530 KVM_REG_MIPS_FCR_IR, 531 KVM_REG_MIPS_FCR_CSR, 532 }; 533 534 static u64 kvm_mips_get_one_regs_msa[] = { 535 KVM_REG_MIPS_MSA_IR, 536 KVM_REG_MIPS_MSA_CSR, 537 }; 538 539 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu) 540 { 541 unsigned long ret; 542 543 ret = ARRAY_SIZE(kvm_mips_get_one_regs); 544 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 545 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48; 546 /* odd doubles */ 547 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64) 548 ret += 16; 549 } 550 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) 551 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32; 552 ret += kvm_mips_callbacks->num_regs(vcpu); 553 554 return ret; 555 } 556 557 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) 558 { 559 u64 index; 560 unsigned int i; 561 562 if (copy_to_user(indices, kvm_mips_get_one_regs, 563 sizeof(kvm_mips_get_one_regs))) 564 return -EFAULT; 565 indices += ARRAY_SIZE(kvm_mips_get_one_regs); 566 567 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 568 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu, 569 sizeof(kvm_mips_get_one_regs_fpu))) 570 return -EFAULT; 571 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu); 572 573 for (i = 0; i < 32; ++i) { 574 index = KVM_REG_MIPS_FPR_32(i); 575 if (copy_to_user(indices, &index, sizeof(index))) 576 return -EFAULT; 577 ++indices; 578 579 /* skip odd doubles if no F64 */ 580 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64)) 581 continue; 582 583 index = KVM_REG_MIPS_FPR_64(i); 584 if (copy_to_user(indices, &index, sizeof(index))) 585 return -EFAULT; 586 ++indices; 587 } 588 } 589 590 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) { 591 if (copy_to_user(indices, kvm_mips_get_one_regs_msa, 592 sizeof(kvm_mips_get_one_regs_msa))) 593 return -EFAULT; 594 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa); 595 596 for (i = 0; i < 32; ++i) { 597 index = KVM_REG_MIPS_VEC_128(i); 598 if (copy_to_user(indices, &index, sizeof(index))) 599 return -EFAULT; 600 ++indices; 601 } 602 } 603 604 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices); 605 } 606 607 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 608 const struct kvm_one_reg *reg) 609 { 610 struct mips_coproc *cop0 = vcpu->arch.cop0; 611 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 612 int ret; 613 s64 v; 614 s64 vs[2]; 615 unsigned int idx; 616 617 switch (reg->id) { 618 /* General purpose registers */ 619 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: 620 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; 621 break; 622 #ifndef CONFIG_CPU_MIPSR6 623 case KVM_REG_MIPS_HI: 624 v = (long)vcpu->arch.hi; 625 break; 626 case KVM_REG_MIPS_LO: 627 v = (long)vcpu->arch.lo; 628 break; 629 #endif 630 case KVM_REG_MIPS_PC: 631 v = (long)vcpu->arch.pc; 632 break; 633 634 /* Floating point registers */ 635 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 636 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 637 return -EINVAL; 638 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 639 /* Odd singles in top of even double when FR=0 */ 640 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 641 v = get_fpr32(&fpu->fpr[idx], 0); 642 else 643 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); 644 break; 645 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 646 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 647 return -EINVAL; 648 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 649 /* Can't access odd doubles in FR=0 mode */ 650 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 651 return -EINVAL; 652 v = get_fpr64(&fpu->fpr[idx], 0); 653 break; 654 case KVM_REG_MIPS_FCR_IR: 655 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 656 return -EINVAL; 657 v = boot_cpu_data.fpu_id; 658 break; 659 case KVM_REG_MIPS_FCR_CSR: 660 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 661 return -EINVAL; 662 v = fpu->fcr31; 663 break; 664 665 /* MIPS SIMD Architecture (MSA) registers */ 666 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 667 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 668 return -EINVAL; 669 /* Can't access MSA registers in FR=0 mode */ 670 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) 671 return -EINVAL; 672 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 673 #ifdef CONFIG_CPU_LITTLE_ENDIAN 674 /* least significant byte first */ 675 vs[0] = get_fpr64(&fpu->fpr[idx], 0); 676 vs[1] = get_fpr64(&fpu->fpr[idx], 1); 677 #else 678 /* most significant byte first */ 679 vs[0] = get_fpr64(&fpu->fpr[idx], 1); 680 vs[1] = get_fpr64(&fpu->fpr[idx], 0); 681 #endif 682 break; 683 case KVM_REG_MIPS_MSA_IR: 684 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 685 return -EINVAL; 686 v = boot_cpu_data.msa_id; 687 break; 688 case KVM_REG_MIPS_MSA_CSR: 689 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 690 return -EINVAL; 691 v = fpu->msacsr; 692 break; 693 694 /* registers to be handled specially */ 695 default: 696 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); 697 if (ret) 698 return ret; 699 break; 700 } 701 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 702 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 703 704 return put_user(v, uaddr64); 705 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 706 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 707 u32 v32 = (u32)v; 708 709 return put_user(v32, uaddr32); 710 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 711 void __user *uaddr = (void __user *)(long)reg->addr; 712 713 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0; 714 } else { 715 return -EINVAL; 716 } 717 } 718 719 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 720 const struct kvm_one_reg *reg) 721 { 722 struct mips_coproc *cop0 = vcpu->arch.cop0; 723 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 724 s64 v; 725 s64 vs[2]; 726 unsigned int idx; 727 728 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 729 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 730 731 if (get_user(v, uaddr64) != 0) 732 return -EFAULT; 733 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 734 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 735 s32 v32; 736 737 if (get_user(v32, uaddr32) != 0) 738 return -EFAULT; 739 v = (s64)v32; 740 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 741 void __user *uaddr = (void __user *)(long)reg->addr; 742 743 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0; 744 } else { 745 return -EINVAL; 746 } 747 748 switch (reg->id) { 749 /* General purpose registers */ 750 case KVM_REG_MIPS_R0: 751 /* Silently ignore requests to set $0 */ 752 break; 753 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: 754 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; 755 break; 756 #ifndef CONFIG_CPU_MIPSR6 757 case KVM_REG_MIPS_HI: 758 vcpu->arch.hi = v; 759 break; 760 case KVM_REG_MIPS_LO: 761 vcpu->arch.lo = v; 762 break; 763 #endif 764 case KVM_REG_MIPS_PC: 765 vcpu->arch.pc = v; 766 break; 767 768 /* Floating point registers */ 769 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 770 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 771 return -EINVAL; 772 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 773 /* Odd singles in top of even double when FR=0 */ 774 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 775 set_fpr32(&fpu->fpr[idx], 0, v); 776 else 777 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); 778 break; 779 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 780 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 781 return -EINVAL; 782 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 783 /* Can't access odd doubles in FR=0 mode */ 784 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 785 return -EINVAL; 786 set_fpr64(&fpu->fpr[idx], 0, v); 787 break; 788 case KVM_REG_MIPS_FCR_IR: 789 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 790 return -EINVAL; 791 /* Read-only */ 792 break; 793 case KVM_REG_MIPS_FCR_CSR: 794 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 795 return -EINVAL; 796 fpu->fcr31 = v; 797 break; 798 799 /* MIPS SIMD Architecture (MSA) registers */ 800 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 801 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 802 return -EINVAL; 803 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 804 #ifdef CONFIG_CPU_LITTLE_ENDIAN 805 /* least significant byte first */ 806 set_fpr64(&fpu->fpr[idx], 0, vs[0]); 807 set_fpr64(&fpu->fpr[idx], 1, vs[1]); 808 #else 809 /* most significant byte first */ 810 set_fpr64(&fpu->fpr[idx], 1, vs[0]); 811 set_fpr64(&fpu->fpr[idx], 0, vs[1]); 812 #endif 813 break; 814 case KVM_REG_MIPS_MSA_IR: 815 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 816 return -EINVAL; 817 /* Read-only */ 818 break; 819 case KVM_REG_MIPS_MSA_CSR: 820 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 821 return -EINVAL; 822 fpu->msacsr = v; 823 break; 824 825 /* registers to be handled specially */ 826 default: 827 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); 828 } 829 return 0; 830 } 831 832 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 833 struct kvm_enable_cap *cap) 834 { 835 int r = 0; 836 837 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) 838 return -EINVAL; 839 if (cap->flags) 840 return -EINVAL; 841 if (cap->args[0]) 842 return -EINVAL; 843 844 switch (cap->cap) { 845 case KVM_CAP_MIPS_FPU: 846 vcpu->arch.fpu_enabled = true; 847 break; 848 case KVM_CAP_MIPS_MSA: 849 vcpu->arch.msa_enabled = true; 850 break; 851 default: 852 r = -EINVAL; 853 break; 854 } 855 856 return r; 857 } 858 859 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, 860 unsigned long arg) 861 { 862 struct kvm_vcpu *vcpu = filp->private_data; 863 void __user *argp = (void __user *)arg; 864 long r; 865 866 switch (ioctl) { 867 case KVM_SET_ONE_REG: 868 case KVM_GET_ONE_REG: { 869 struct kvm_one_reg reg; 870 871 if (copy_from_user(®, argp, sizeof(reg))) 872 return -EFAULT; 873 if (ioctl == KVM_SET_ONE_REG) 874 return kvm_mips_set_reg(vcpu, ®); 875 else 876 return kvm_mips_get_reg(vcpu, ®); 877 } 878 case KVM_GET_REG_LIST: { 879 struct kvm_reg_list __user *user_list = argp; 880 struct kvm_reg_list reg_list; 881 unsigned n; 882 883 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 884 return -EFAULT; 885 n = reg_list.n; 886 reg_list.n = kvm_mips_num_regs(vcpu); 887 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 888 return -EFAULT; 889 if (n < reg_list.n) 890 return -E2BIG; 891 return kvm_mips_copy_reg_indices(vcpu, user_list->reg); 892 } 893 case KVM_INTERRUPT: 894 { 895 struct kvm_mips_interrupt irq; 896 897 if (copy_from_user(&irq, argp, sizeof(irq))) 898 return -EFAULT; 899 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, 900 irq.irq); 901 902 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 903 break; 904 } 905 case KVM_ENABLE_CAP: { 906 struct kvm_enable_cap cap; 907 908 if (copy_from_user(&cap, argp, sizeof(cap))) 909 return -EFAULT; 910 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 911 break; 912 } 913 default: 914 r = -ENOIOCTLCMD; 915 } 916 return r; 917 } 918 919 /** 920 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 921 * @kvm: kvm instance 922 * @log: slot id and address to which we copy the log 923 * 924 * Steps 1-4 below provide general overview of dirty page logging. See 925 * kvm_get_dirty_log_protect() function description for additional details. 926 * 927 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 928 * always flush the TLB (step 4) even if previous step failed and the dirty 929 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 930 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 931 * writes will be marked dirty for next log read. 932 * 933 * 1. Take a snapshot of the bit and clear it if needed. 934 * 2. Write protect the corresponding page. 935 * 3. Copy the snapshot to the userspace. 936 * 4. Flush TLB's if needed. 937 */ 938 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 939 { 940 struct kvm_memslots *slots; 941 struct kvm_memory_slot *memslot; 942 bool is_dirty = false; 943 int r; 944 945 mutex_lock(&kvm->slots_lock); 946 947 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 948 949 if (is_dirty) { 950 slots = kvm_memslots(kvm); 951 memslot = id_to_memslot(slots, log->slot); 952 953 /* Let implementation handle TLB/GVA invalidation */ 954 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot); 955 } 956 957 mutex_unlock(&kvm->slots_lock); 958 return r; 959 } 960 961 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 962 { 963 long r; 964 965 switch (ioctl) { 966 default: 967 r = -ENOIOCTLCMD; 968 } 969 970 return r; 971 } 972 973 int kvm_arch_init(void *opaque) 974 { 975 if (kvm_mips_callbacks) { 976 kvm_err("kvm: module already exists\n"); 977 return -EEXIST; 978 } 979 980 return kvm_mips_emulation_init(&kvm_mips_callbacks); 981 } 982 983 void kvm_arch_exit(void) 984 { 985 kvm_mips_callbacks = NULL; 986 } 987 988 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 989 struct kvm_sregs *sregs) 990 { 991 return -ENOIOCTLCMD; 992 } 993 994 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 995 struct kvm_sregs *sregs) 996 { 997 return -ENOIOCTLCMD; 998 } 999 1000 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 1001 { 1002 } 1003 1004 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1005 { 1006 return -ENOIOCTLCMD; 1007 } 1008 1009 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1010 { 1011 return -ENOIOCTLCMD; 1012 } 1013 1014 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 1015 { 1016 return VM_FAULT_SIGBUS; 1017 } 1018 1019 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 1020 { 1021 int r; 1022 1023 switch (ext) { 1024 case KVM_CAP_ONE_REG: 1025 case KVM_CAP_ENABLE_CAP: 1026 case KVM_CAP_READONLY_MEM: 1027 case KVM_CAP_SYNC_MMU: 1028 case KVM_CAP_IMMEDIATE_EXIT: 1029 r = 1; 1030 break; 1031 case KVM_CAP_COALESCED_MMIO: 1032 r = KVM_COALESCED_MMIO_PAGE_OFFSET; 1033 break; 1034 case KVM_CAP_NR_VCPUS: 1035 r = num_online_cpus(); 1036 break; 1037 case KVM_CAP_MAX_VCPUS: 1038 r = KVM_MAX_VCPUS; 1039 break; 1040 case KVM_CAP_MIPS_FPU: 1041 /* We don't handle systems with inconsistent cpu_has_fpu */ 1042 r = !!raw_cpu_has_fpu; 1043 break; 1044 case KVM_CAP_MIPS_MSA: 1045 /* 1046 * We don't support MSA vector partitioning yet: 1047 * 1) It would require explicit support which can't be tested 1048 * yet due to lack of support in current hardware. 1049 * 2) It extends the state that would need to be saved/restored 1050 * by e.g. QEMU for migration. 1051 * 1052 * When vector partitioning hardware becomes available, support 1053 * could be added by requiring a flag when enabling 1054 * KVM_CAP_MIPS_MSA capability to indicate that userland knows 1055 * to save/restore the appropriate extra state. 1056 */ 1057 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); 1058 break; 1059 default: 1060 r = 0; 1061 break; 1062 } 1063 return r; 1064 } 1065 1066 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 1067 { 1068 return kvm_mips_pending_timer(vcpu); 1069 } 1070 1071 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) 1072 { 1073 int i; 1074 struct mips_coproc *cop0; 1075 1076 if (!vcpu) 1077 return -1; 1078 1079 kvm_debug("VCPU Register Dump:\n"); 1080 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); 1081 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); 1082 1083 for (i = 0; i < 32; i += 4) { 1084 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, 1085 vcpu->arch.gprs[i], 1086 vcpu->arch.gprs[i + 1], 1087 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); 1088 } 1089 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); 1090 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); 1091 1092 cop0 = vcpu->arch.cop0; 1093 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n", 1094 kvm_read_c0_guest_status(cop0), 1095 kvm_read_c0_guest_cause(cop0)); 1096 1097 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); 1098 1099 return 0; 1100 } 1101 1102 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1103 { 1104 int i; 1105 1106 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1107 vcpu->arch.gprs[i] = regs->gpr[i]; 1108 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ 1109 vcpu->arch.hi = regs->hi; 1110 vcpu->arch.lo = regs->lo; 1111 vcpu->arch.pc = regs->pc; 1112 1113 return 0; 1114 } 1115 1116 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1117 { 1118 int i; 1119 1120 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1121 regs->gpr[i] = vcpu->arch.gprs[i]; 1122 1123 regs->hi = vcpu->arch.hi; 1124 regs->lo = vcpu->arch.lo; 1125 regs->pc = vcpu->arch.pc; 1126 1127 return 0; 1128 } 1129 1130 static void kvm_mips_comparecount_func(unsigned long data) 1131 { 1132 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data; 1133 1134 kvm_mips_callbacks->queue_timer_int(vcpu); 1135 1136 vcpu->arch.wait = 0; 1137 if (swait_active(&vcpu->wq)) 1138 swake_up(&vcpu->wq); 1139 } 1140 1141 /* low level hrtimer wake routine */ 1142 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) 1143 { 1144 struct kvm_vcpu *vcpu; 1145 1146 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); 1147 kvm_mips_comparecount_func((unsigned long) vcpu); 1148 return kvm_mips_count_timeout(vcpu); 1149 } 1150 1151 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 1152 { 1153 int err; 1154 1155 err = kvm_mips_callbacks->vcpu_init(vcpu); 1156 if (err) 1157 return err; 1158 1159 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 1160 HRTIMER_MODE_REL); 1161 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 1162 return 0; 1163 } 1164 1165 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 1166 { 1167 kvm_mips_callbacks->vcpu_uninit(vcpu); 1168 } 1169 1170 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 1171 struct kvm_translation *tr) 1172 { 1173 return 0; 1174 } 1175 1176 /* Initial guest state */ 1177 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 1178 { 1179 return kvm_mips_callbacks->vcpu_setup(vcpu); 1180 } 1181 1182 static void kvm_mips_set_c0_status(void) 1183 { 1184 u32 status = read_c0_status(); 1185 1186 if (cpu_has_dsp) 1187 status |= (ST0_MX); 1188 1189 write_c0_status(status); 1190 ehb(); 1191 } 1192 1193 /* 1194 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) 1195 */ 1196 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) 1197 { 1198 u32 cause = vcpu->arch.host_cp0_cause; 1199 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; 1200 u32 __user *opc = (u32 __user *) vcpu->arch.pc; 1201 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; 1202 enum emulation_result er = EMULATE_DONE; 1203 u32 inst; 1204 int ret = RESUME_GUEST; 1205 1206 vcpu->mode = OUTSIDE_GUEST_MODE; 1207 1208 /* re-enable HTW before enabling interrupts */ 1209 htw_start(); 1210 1211 /* Set a default exit reason */ 1212 run->exit_reason = KVM_EXIT_UNKNOWN; 1213 run->ready_for_interrupt_injection = 1; 1214 1215 /* 1216 * Set the appropriate status bits based on host CPU features, 1217 * before we hit the scheduler 1218 */ 1219 kvm_mips_set_c0_status(); 1220 1221 local_irq_enable(); 1222 1223 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", 1224 cause, opc, run, vcpu); 1225 trace_kvm_exit(vcpu, exccode); 1226 1227 /* 1228 * Do a privilege check, if in UM most of these exit conditions end up 1229 * causing an exception to be delivered to the Guest Kernel 1230 */ 1231 er = kvm_mips_check_privilege(cause, opc, run, vcpu); 1232 if (er == EMULATE_PRIV_FAIL) { 1233 goto skip_emul; 1234 } else if (er == EMULATE_FAIL) { 1235 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1236 ret = RESUME_HOST; 1237 goto skip_emul; 1238 } 1239 1240 switch (exccode) { 1241 case EXCCODE_INT: 1242 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc); 1243 1244 ++vcpu->stat.int_exits; 1245 1246 if (need_resched()) 1247 cond_resched(); 1248 1249 ret = RESUME_GUEST; 1250 break; 1251 1252 case EXCCODE_CPU: 1253 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc); 1254 1255 ++vcpu->stat.cop_unusable_exits; 1256 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); 1257 /* XXXKYMA: Might need to return to user space */ 1258 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) 1259 ret = RESUME_HOST; 1260 break; 1261 1262 case EXCCODE_MOD: 1263 ++vcpu->stat.tlbmod_exits; 1264 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); 1265 break; 1266 1267 case EXCCODE_TLBS: 1268 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n", 1269 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, 1270 badvaddr); 1271 1272 ++vcpu->stat.tlbmiss_st_exits; 1273 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); 1274 break; 1275 1276 case EXCCODE_TLBL: 1277 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", 1278 cause, opc, badvaddr); 1279 1280 ++vcpu->stat.tlbmiss_ld_exits; 1281 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); 1282 break; 1283 1284 case EXCCODE_ADES: 1285 ++vcpu->stat.addrerr_st_exits; 1286 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); 1287 break; 1288 1289 case EXCCODE_ADEL: 1290 ++vcpu->stat.addrerr_ld_exits; 1291 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); 1292 break; 1293 1294 case EXCCODE_SYS: 1295 ++vcpu->stat.syscall_exits; 1296 ret = kvm_mips_callbacks->handle_syscall(vcpu); 1297 break; 1298 1299 case EXCCODE_RI: 1300 ++vcpu->stat.resvd_inst_exits; 1301 ret = kvm_mips_callbacks->handle_res_inst(vcpu); 1302 break; 1303 1304 case EXCCODE_BP: 1305 ++vcpu->stat.break_inst_exits; 1306 ret = kvm_mips_callbacks->handle_break(vcpu); 1307 break; 1308 1309 case EXCCODE_TR: 1310 ++vcpu->stat.trap_inst_exits; 1311 ret = kvm_mips_callbacks->handle_trap(vcpu); 1312 break; 1313 1314 case EXCCODE_MSAFPE: 1315 ++vcpu->stat.msa_fpe_exits; 1316 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); 1317 break; 1318 1319 case EXCCODE_FPE: 1320 ++vcpu->stat.fpe_exits; 1321 ret = kvm_mips_callbacks->handle_fpe(vcpu); 1322 break; 1323 1324 case EXCCODE_MSADIS: 1325 ++vcpu->stat.msa_disabled_exits; 1326 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); 1327 break; 1328 1329 default: 1330 if (cause & CAUSEF_BD) 1331 opc += 1; 1332 inst = 0; 1333 kvm_get_badinstr(opc, vcpu, &inst); 1334 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n", 1335 exccode, opc, inst, badvaddr, 1336 kvm_read_c0_guest_status(vcpu->arch.cop0)); 1337 kvm_arch_vcpu_dump_regs(vcpu); 1338 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1339 ret = RESUME_HOST; 1340 break; 1341 1342 } 1343 1344 skip_emul: 1345 local_irq_disable(); 1346 1347 if (er == EMULATE_DONE && !(ret & RESUME_HOST)) 1348 kvm_mips_deliver_interrupts(vcpu, cause); 1349 1350 if (!(ret & RESUME_HOST)) { 1351 /* Only check for signals if not already exiting to userspace */ 1352 if (signal_pending(current)) { 1353 run->exit_reason = KVM_EXIT_INTR; 1354 ret = (-EINTR << 2) | RESUME_HOST; 1355 ++vcpu->stat.signal_exits; 1356 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL); 1357 } 1358 } 1359 1360 if (ret == RESUME_GUEST) { 1361 trace_kvm_reenter(vcpu); 1362 1363 /* 1364 * Make sure the read of VCPU requests in vcpu_reenter() 1365 * callback is not reordered ahead of the write to vcpu->mode, 1366 * or we could miss a TLB flush request while the requester sees 1367 * the VCPU as outside of guest mode and not needing an IPI. 1368 */ 1369 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 1370 1371 kvm_mips_callbacks->vcpu_reenter(run, vcpu); 1372 1373 /* 1374 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context 1375 * is live), restore FCR31 / MSACSR. 1376 * 1377 * This should be before returning to the guest exception 1378 * vector, as it may well cause an [MSA] FP exception if there 1379 * are pending exception bits unmasked. (see 1380 * kvm_mips_csr_die_notifier() for how that is handled). 1381 */ 1382 if (kvm_mips_guest_has_fpu(&vcpu->arch) && 1383 read_c0_status() & ST0_CU1) 1384 __kvm_restore_fcsr(&vcpu->arch); 1385 1386 if (kvm_mips_guest_has_msa(&vcpu->arch) && 1387 read_c0_config5() & MIPS_CONF5_MSAEN) 1388 __kvm_restore_msacsr(&vcpu->arch); 1389 } 1390 1391 /* Disable HTW before returning to guest or host */ 1392 htw_stop(); 1393 1394 return ret; 1395 } 1396 1397 /* Enable FPU for guest and restore context */ 1398 void kvm_own_fpu(struct kvm_vcpu *vcpu) 1399 { 1400 struct mips_coproc *cop0 = vcpu->arch.cop0; 1401 unsigned int sr, cfg5; 1402 1403 preempt_disable(); 1404 1405 sr = kvm_read_c0_guest_status(cop0); 1406 1407 /* 1408 * If MSA state is already live, it is undefined how it interacts with 1409 * FR=0 FPU state, and we don't want to hit reserved instruction 1410 * exceptions trying to save the MSA state later when CU=1 && FR=1, so 1411 * play it safe and save it first. 1412 * 1413 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should 1414 * get called when guest CU1 is set, however we can't trust the guest 1415 * not to clobber the status register directly via the commpage. 1416 */ 1417 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && 1418 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) 1419 kvm_lose_fpu(vcpu); 1420 1421 /* 1422 * Enable FPU for guest 1423 * We set FR and FRE according to guest context 1424 */ 1425 change_c0_status(ST0_CU1 | ST0_FR, sr); 1426 if (cpu_has_fre) { 1427 cfg5 = kvm_read_c0_guest_config5(cop0); 1428 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1429 } 1430 enable_fpu_hazard(); 1431 1432 /* If guest FPU state not active, restore it now */ 1433 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) { 1434 __kvm_restore_fpu(&vcpu->arch); 1435 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1436 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU); 1437 } else { 1438 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU); 1439 } 1440 1441 preempt_enable(); 1442 } 1443 1444 #ifdef CONFIG_CPU_HAS_MSA 1445 /* Enable MSA for guest and restore context */ 1446 void kvm_own_msa(struct kvm_vcpu *vcpu) 1447 { 1448 struct mips_coproc *cop0 = vcpu->arch.cop0; 1449 unsigned int sr, cfg5; 1450 1451 preempt_disable(); 1452 1453 /* 1454 * Enable FPU if enabled in guest, since we're restoring FPU context 1455 * anyway. We set FR and FRE according to guest context. 1456 */ 1457 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { 1458 sr = kvm_read_c0_guest_status(cop0); 1459 1460 /* 1461 * If FR=0 FPU state is already live, it is undefined how it 1462 * interacts with MSA state, so play it safe and save it first. 1463 */ 1464 if (!(sr & ST0_FR) && 1465 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | 1466 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU) 1467 kvm_lose_fpu(vcpu); 1468 1469 change_c0_status(ST0_CU1 | ST0_FR, sr); 1470 if (sr & ST0_CU1 && cpu_has_fre) { 1471 cfg5 = kvm_read_c0_guest_config5(cop0); 1472 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1473 } 1474 } 1475 1476 /* Enable MSA for guest */ 1477 set_c0_config5(MIPS_CONF5_MSAEN); 1478 enable_fpu_hazard(); 1479 1480 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) { 1481 case KVM_MIPS_AUX_FPU: 1482 /* 1483 * Guest FPU state already loaded, only restore upper MSA state 1484 */ 1485 __kvm_restore_msa_upper(&vcpu->arch); 1486 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1487 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA); 1488 break; 1489 case 0: 1490 /* Neither FPU or MSA already active, restore full MSA state */ 1491 __kvm_restore_msa(&vcpu->arch); 1492 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1493 if (kvm_mips_guest_has_fpu(&vcpu->arch)) 1494 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1495 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, 1496 KVM_TRACE_AUX_FPU_MSA); 1497 break; 1498 default: 1499 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA); 1500 break; 1501 } 1502 1503 preempt_enable(); 1504 } 1505 #endif 1506 1507 /* Drop FPU & MSA without saving it */ 1508 void kvm_drop_fpu(struct kvm_vcpu *vcpu) 1509 { 1510 preempt_disable(); 1511 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1512 disable_msa(); 1513 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA); 1514 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA; 1515 } 1516 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1517 clear_c0_status(ST0_CU1 | ST0_FR); 1518 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU); 1519 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1520 } 1521 preempt_enable(); 1522 } 1523 1524 /* Save and disable FPU & MSA */ 1525 void kvm_lose_fpu(struct kvm_vcpu *vcpu) 1526 { 1527 /* 1528 * FPU & MSA get disabled in root context (hardware) when it is disabled 1529 * in guest context (software), but the register state in the hardware 1530 * may still be in use. This is why we explicitly re-enable the hardware 1531 * before saving. 1532 */ 1533 1534 preempt_disable(); 1535 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1536 set_c0_config5(MIPS_CONF5_MSAEN); 1537 enable_fpu_hazard(); 1538 1539 __kvm_save_msa(&vcpu->arch); 1540 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA); 1541 1542 /* Disable MSA & FPU */ 1543 disable_msa(); 1544 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1545 clear_c0_status(ST0_CU1 | ST0_FR); 1546 disable_fpu_hazard(); 1547 } 1548 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA); 1549 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1550 set_c0_status(ST0_CU1); 1551 enable_fpu_hazard(); 1552 1553 __kvm_save_fpu(&vcpu->arch); 1554 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1555 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU); 1556 1557 /* Disable FPU */ 1558 clear_c0_status(ST0_CU1 | ST0_FR); 1559 disable_fpu_hazard(); 1560 } 1561 preempt_enable(); 1562 } 1563 1564 /* 1565 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are 1566 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP 1567 * exception if cause bits are set in the value being written. 1568 */ 1569 static int kvm_mips_csr_die_notify(struct notifier_block *self, 1570 unsigned long cmd, void *ptr) 1571 { 1572 struct die_args *args = (struct die_args *)ptr; 1573 struct pt_regs *regs = args->regs; 1574 unsigned long pc; 1575 1576 /* Only interested in FPE and MSAFPE */ 1577 if (cmd != DIE_FP && cmd != DIE_MSAFP) 1578 return NOTIFY_DONE; 1579 1580 /* Return immediately if guest context isn't active */ 1581 if (!(current->flags & PF_VCPU)) 1582 return NOTIFY_DONE; 1583 1584 /* Should never get here from user mode */ 1585 BUG_ON(user_mode(regs)); 1586 1587 pc = instruction_pointer(regs); 1588 switch (cmd) { 1589 case DIE_FP: 1590 /* match 2nd instruction in __kvm_restore_fcsr */ 1591 if (pc != (unsigned long)&__kvm_restore_fcsr + 4) 1592 return NOTIFY_DONE; 1593 break; 1594 case DIE_MSAFP: 1595 /* match 2nd/3rd instruction in __kvm_restore_msacsr */ 1596 if (!cpu_has_msa || 1597 pc < (unsigned long)&__kvm_restore_msacsr + 4 || 1598 pc > (unsigned long)&__kvm_restore_msacsr + 8) 1599 return NOTIFY_DONE; 1600 break; 1601 } 1602 1603 /* Move PC forward a little and continue executing */ 1604 instruction_pointer(regs) += 4; 1605 1606 return NOTIFY_STOP; 1607 } 1608 1609 static struct notifier_block kvm_mips_csr_die_notifier = { 1610 .notifier_call = kvm_mips_csr_die_notify, 1611 }; 1612 1613 static int __init kvm_mips_init(void) 1614 { 1615 int ret; 1616 1617 ret = kvm_mips_entry_setup(); 1618 if (ret) 1619 return ret; 1620 1621 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); 1622 1623 if (ret) 1624 return ret; 1625 1626 register_die_notifier(&kvm_mips_csr_die_notifier); 1627 1628 return 0; 1629 } 1630 1631 static void __exit kvm_mips_exit(void) 1632 { 1633 kvm_exit(); 1634 1635 unregister_die_notifier(&kvm_mips_csr_die_notifier); 1636 } 1637 1638 module_init(kvm_mips_init); 1639 module_exit(kvm_mips_exit); 1640 1641 EXPORT_TRACEPOINT_SYMBOL(kvm_exit); 1642