1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. 13 * Copyright (C) 2014, Imagination Technologies Ltd. 14 */ 15 #include <linux/bitops.h> 16 #include <linux/bug.h> 17 #include <linux/compiler.h> 18 #include <linux/context_tracking.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/kexec.h> 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/extable.h> 25 #include <linux/mm.h> 26 #include <linux/sched/mm.h> 27 #include <linux/sched/debug.h> 28 #include <linux/smp.h> 29 #include <linux/spinlock.h> 30 #include <linux/kallsyms.h> 31 #include <linux/memblock.h> 32 #include <linux/interrupt.h> 33 #include <linux/ptrace.h> 34 #include <linux/kgdb.h> 35 #include <linux/kdebug.h> 36 #include <linux/kprobes.h> 37 #include <linux/notifier.h> 38 #include <linux/kdb.h> 39 #include <linux/irq.h> 40 #include <linux/perf_event.h> 41 42 #include <asm/addrspace.h> 43 #include <asm/bootinfo.h> 44 #include <asm/branch.h> 45 #include <asm/break.h> 46 #include <asm/cop2.h> 47 #include <asm/cpu.h> 48 #include <asm/cpu-type.h> 49 #include <asm/dsp.h> 50 #include <asm/fpu.h> 51 #include <asm/fpu_emulator.h> 52 #include <asm/idle.h> 53 #include <asm/isa-rev.h> 54 #include <asm/mips-cps.h> 55 #include <asm/mips-r2-to-r6-emul.h> 56 #include <asm/mipsregs.h> 57 #include <asm/mipsmtregs.h> 58 #include <asm/module.h> 59 #include <asm/msa.h> 60 #include <asm/ptrace.h> 61 #include <asm/sections.h> 62 #include <asm/siginfo.h> 63 #include <asm/tlbdebug.h> 64 #include <asm/traps.h> 65 #include <linux/uaccess.h> 66 #include <asm/watch.h> 67 #include <asm/mmu_context.h> 68 #include <asm/types.h> 69 #include <asm/stacktrace.h> 70 #include <asm/tlbex.h> 71 #include <asm/uasm.h> 72 73 #include <asm/mach-loongson64/cpucfg-emul.h> 74 75 #include "access-helper.h" 76 77 extern void check_wait(void); 78 extern asmlinkage void rollback_handle_int(void); 79 extern asmlinkage void handle_int(void); 80 extern asmlinkage void handle_adel(void); 81 extern asmlinkage void handle_ades(void); 82 extern asmlinkage void handle_ibe(void); 83 extern asmlinkage void handle_dbe(void); 84 extern asmlinkage void handle_sys(void); 85 extern asmlinkage void handle_bp(void); 86 extern asmlinkage void handle_ri(void); 87 extern asmlinkage void handle_ri_rdhwr_tlbp(void); 88 extern asmlinkage void handle_ri_rdhwr(void); 89 extern asmlinkage void handle_cpu(void); 90 extern asmlinkage void handle_ov(void); 91 extern asmlinkage void handle_tr(void); 92 extern asmlinkage void handle_msa_fpe(void); 93 extern asmlinkage void handle_fpe(void); 94 extern asmlinkage void handle_ftlb(void); 95 extern asmlinkage void handle_gsexc(void); 96 extern asmlinkage void handle_msa(void); 97 extern asmlinkage void handle_mdmx(void); 98 extern asmlinkage void handle_watch(void); 99 extern asmlinkage void handle_mt(void); 100 extern asmlinkage void handle_dsp(void); 101 extern asmlinkage void handle_mcheck(void); 102 extern asmlinkage void handle_reserved(void); 103 extern void tlb_do_page_fault_0(void); 104 105 void (*board_be_init)(void); 106 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 107 void (*board_nmi_handler_setup)(void); 108 void (*board_ejtag_handler_setup)(void); 109 void (*board_bind_eic_interrupt)(int irq, int regset); 110 void (*board_ebase_setup)(void); 111 void(*board_cache_error_setup)(void); 112 113 static void show_raw_backtrace(unsigned long reg29, const char *loglvl, 114 bool user) 115 { 116 unsigned long *sp = (unsigned long *)(reg29 & ~3); 117 unsigned long addr; 118 119 printk("%sCall Trace:", loglvl); 120 #ifdef CONFIG_KALLSYMS 121 printk("%s\n", loglvl); 122 #endif 123 while (!kstack_end(sp)) { 124 if (__get_addr(&addr, sp++, user)) { 125 printk("%s (Bad stack address)", loglvl); 126 break; 127 } 128 if (__kernel_text_address(addr)) 129 print_ip_sym(loglvl, addr); 130 } 131 printk("%s\n", loglvl); 132 } 133 134 #ifdef CONFIG_KALLSYMS 135 int raw_show_trace; 136 static int __init set_raw_show_trace(char *str) 137 { 138 raw_show_trace = 1; 139 return 1; 140 } 141 __setup("raw_show_trace", set_raw_show_trace); 142 #endif 143 144 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs, 145 const char *loglvl, bool user) 146 { 147 unsigned long sp = regs->regs[29]; 148 unsigned long ra = regs->regs[31]; 149 unsigned long pc = regs->cp0_epc; 150 151 if (!task) 152 task = current; 153 154 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) { 155 show_raw_backtrace(sp, loglvl, user); 156 return; 157 } 158 printk("%sCall Trace:\n", loglvl); 159 do { 160 print_ip_sym(loglvl, pc); 161 pc = unwind_stack(task, &sp, pc, &ra); 162 } while (pc); 163 pr_cont("\n"); 164 } 165 166 /* 167 * This routine abuses get_user()/put_user() to reference pointers 168 * with at least a bit of error checking ... 169 */ 170 static void show_stacktrace(struct task_struct *task, 171 const struct pt_regs *regs, const char *loglvl, bool user) 172 { 173 const int field = 2 * sizeof(unsigned long); 174 unsigned long stackdata; 175 int i; 176 unsigned long *sp = (unsigned long *)regs->regs[29]; 177 178 printk("%sStack :", loglvl); 179 i = 0; 180 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 181 if (i && ((i % (64 / field)) == 0)) { 182 pr_cont("\n"); 183 printk("%s ", loglvl); 184 } 185 if (i > 39) { 186 pr_cont(" ..."); 187 break; 188 } 189 190 if (__get_addr(&stackdata, sp++, user)) { 191 pr_cont(" (Bad stack address)"); 192 break; 193 } 194 195 pr_cont(" %0*lx", field, stackdata); 196 i++; 197 } 198 pr_cont("\n"); 199 show_backtrace(task, regs, loglvl, user); 200 } 201 202 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl) 203 { 204 struct pt_regs regs; 205 206 regs.cp0_status = KSU_KERNEL; 207 if (sp) { 208 regs.regs[29] = (unsigned long)sp; 209 regs.regs[31] = 0; 210 regs.cp0_epc = 0; 211 } else { 212 if (task && task != current) { 213 regs.regs[29] = task->thread.reg29; 214 regs.regs[31] = 0; 215 regs.cp0_epc = task->thread.reg31; 216 } else { 217 prepare_frametrace(®s); 218 } 219 } 220 show_stacktrace(task, ®s, loglvl, false); 221 } 222 223 static void show_code(void *pc, bool user) 224 { 225 long i; 226 unsigned short *pc16 = NULL; 227 228 printk("Code:"); 229 230 if ((unsigned long)pc & 1) 231 pc16 = (u16 *)((unsigned long)pc & ~1); 232 233 for(i = -3 ; i < 6 ; i++) { 234 if (pc16) { 235 u16 insn16; 236 237 if (__get_inst16(&insn16, pc16 + i, user)) 238 goto bad_address; 239 240 pr_cont("%c%04x%c", (i?' ':'<'), insn16, (i?' ':'>')); 241 } else { 242 u32 insn32; 243 244 if (__get_inst32(&insn32, (u32 *)pc + i, user)) 245 goto bad_address; 246 247 pr_cont("%c%08x%c", (i?' ':'<'), insn32, (i?' ':'>')); 248 } 249 } 250 pr_cont("\n"); 251 return; 252 253 bad_address: 254 pr_cont(" (Bad address in epc)\n\n"); 255 } 256 257 static void __show_regs(const struct pt_regs *regs) 258 { 259 const int field = 2 * sizeof(unsigned long); 260 unsigned int cause = regs->cp0_cause; 261 unsigned int exccode; 262 int i; 263 264 show_regs_print_info(KERN_DEFAULT); 265 266 /* 267 * Saved main processor registers 268 */ 269 for (i = 0; i < 32; ) { 270 if ((i % 4) == 0) 271 printk("$%2d :", i); 272 if (i == 0) 273 pr_cont(" %0*lx", field, 0UL); 274 else if (i == 26 || i == 27) 275 pr_cont(" %*s", field, ""); 276 else 277 pr_cont(" %0*lx", field, regs->regs[i]); 278 279 i++; 280 if ((i % 4) == 0) 281 pr_cont("\n"); 282 } 283 284 #ifdef CONFIG_CPU_HAS_SMARTMIPS 285 printk("Acx : %0*lx\n", field, regs->acx); 286 #endif 287 if (MIPS_ISA_REV < 6) { 288 printk("Hi : %0*lx\n", field, regs->hi); 289 printk("Lo : %0*lx\n", field, regs->lo); 290 } 291 292 /* 293 * Saved cp0 registers 294 */ 295 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 296 (void *) regs->cp0_epc); 297 printk("ra : %0*lx %pS\n", field, regs->regs[31], 298 (void *) regs->regs[31]); 299 300 printk("Status: %08x ", (uint32_t) regs->cp0_status); 301 302 if (cpu_has_3kex) { 303 if (regs->cp0_status & ST0_KUO) 304 pr_cont("KUo "); 305 if (regs->cp0_status & ST0_IEO) 306 pr_cont("IEo "); 307 if (regs->cp0_status & ST0_KUP) 308 pr_cont("KUp "); 309 if (regs->cp0_status & ST0_IEP) 310 pr_cont("IEp "); 311 if (regs->cp0_status & ST0_KUC) 312 pr_cont("KUc "); 313 if (regs->cp0_status & ST0_IEC) 314 pr_cont("IEc "); 315 } else if (cpu_has_4kex) { 316 if (regs->cp0_status & ST0_KX) 317 pr_cont("KX "); 318 if (regs->cp0_status & ST0_SX) 319 pr_cont("SX "); 320 if (regs->cp0_status & ST0_UX) 321 pr_cont("UX "); 322 switch (regs->cp0_status & ST0_KSU) { 323 case KSU_USER: 324 pr_cont("USER "); 325 break; 326 case KSU_SUPERVISOR: 327 pr_cont("SUPERVISOR "); 328 break; 329 case KSU_KERNEL: 330 pr_cont("KERNEL "); 331 break; 332 default: 333 pr_cont("BAD_MODE "); 334 break; 335 } 336 if (regs->cp0_status & ST0_ERL) 337 pr_cont("ERL "); 338 if (regs->cp0_status & ST0_EXL) 339 pr_cont("EXL "); 340 if (regs->cp0_status & ST0_IE) 341 pr_cont("IE "); 342 } 343 pr_cont("\n"); 344 345 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 346 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode); 347 348 if (1 <= exccode && exccode <= 5) 349 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 350 351 printk("PrId : %08x (%s)\n", read_c0_prid(), 352 cpu_name_string()); 353 } 354 355 /* 356 * FIXME: really the generic show_regs should take a const pointer argument. 357 */ 358 void show_regs(struct pt_regs *regs) 359 { 360 __show_regs(regs); 361 dump_stack(); 362 } 363 364 void show_registers(struct pt_regs *regs) 365 { 366 const int field = 2 * sizeof(unsigned long); 367 368 __show_regs(regs); 369 print_modules(); 370 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 371 current->comm, current->pid, current_thread_info(), current, 372 field, current_thread_info()->tp_value); 373 if (cpu_has_userlocal) { 374 unsigned long tls; 375 376 tls = read_c0_userlocal(); 377 if (tls != current_thread_info()->tp_value) 378 printk("*HwTLS: %0*lx\n", field, tls); 379 } 380 381 show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs)); 382 show_code((void *)regs->cp0_epc, user_mode(regs)); 383 printk("\n"); 384 } 385 386 static DEFINE_RAW_SPINLOCK(die_lock); 387 388 void __noreturn die(const char *str, struct pt_regs *regs) 389 { 390 static int die_counter; 391 int sig = SIGSEGV; 392 393 oops_enter(); 394 395 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, 396 SIGSEGV) == NOTIFY_STOP) 397 sig = 0; 398 399 console_verbose(); 400 raw_spin_lock_irq(&die_lock); 401 bust_spinlocks(1); 402 403 printk("%s[#%d]:\n", str, ++die_counter); 404 show_registers(regs); 405 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 406 raw_spin_unlock_irq(&die_lock); 407 408 oops_exit(); 409 410 if (in_interrupt()) 411 panic("Fatal exception in interrupt"); 412 413 if (panic_on_oops) 414 panic("Fatal exception"); 415 416 if (regs && kexec_should_crash(current)) 417 crash_kexec(regs); 418 419 do_exit(sig); 420 } 421 422 extern struct exception_table_entry __start___dbe_table[]; 423 extern struct exception_table_entry __stop___dbe_table[]; 424 425 __asm__( 426 " .section __dbe_table, \"a\"\n" 427 " .previous \n"); 428 429 /* Given an address, look for it in the exception tables. */ 430 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 431 { 432 const struct exception_table_entry *e; 433 434 e = search_extable(__start___dbe_table, 435 __stop___dbe_table - __start___dbe_table, addr); 436 if (!e) 437 e = search_module_dbetables(addr); 438 return e; 439 } 440 441 asmlinkage void do_be(struct pt_regs *regs) 442 { 443 const int field = 2 * sizeof(unsigned long); 444 const struct exception_table_entry *fixup = NULL; 445 int data = regs->cp0_cause & 4; 446 int action = MIPS_BE_FATAL; 447 enum ctx_state prev_state; 448 449 prev_state = exception_enter(); 450 /* XXX For now. Fixme, this searches the wrong table ... */ 451 if (data && !user_mode(regs)) 452 fixup = search_dbe_tables(exception_epc(regs)); 453 454 if (fixup) 455 action = MIPS_BE_FIXUP; 456 457 if (board_be_handler) 458 action = board_be_handler(regs, fixup != NULL); 459 else 460 mips_cm_error_report(); 461 462 switch (action) { 463 case MIPS_BE_DISCARD: 464 goto out; 465 case MIPS_BE_FIXUP: 466 if (fixup) { 467 regs->cp0_epc = fixup->nextinsn; 468 goto out; 469 } 470 break; 471 default: 472 break; 473 } 474 475 /* 476 * Assume it would be too dangerous to continue ... 477 */ 478 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 479 data ? "Data" : "Instruction", 480 field, regs->cp0_epc, field, regs->regs[31]); 481 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr, 482 SIGBUS) == NOTIFY_STOP) 483 goto out; 484 485 die_if_kernel("Oops", regs); 486 force_sig(SIGBUS); 487 488 out: 489 exception_exit(prev_state); 490 } 491 492 /* 493 * ll/sc, rdhwr, sync emulation 494 */ 495 496 #define OPCODE 0xfc000000 497 #define BASE 0x03e00000 498 #define RT 0x001f0000 499 #define OFFSET 0x0000ffff 500 #define LL 0xc0000000 501 #define SC 0xe0000000 502 #define SPEC0 0x00000000 503 #define SPEC3 0x7c000000 504 #define RD 0x0000f800 505 #define FUNC 0x0000003f 506 #define SYNC 0x0000000f 507 #define RDHWR 0x0000003b 508 509 /* microMIPS definitions */ 510 #define MM_POOL32A_FUNC 0xfc00ffff 511 #define MM_RDHWR 0x00006b3c 512 #define MM_RS 0x001f0000 513 #define MM_RT 0x03e00000 514 515 /* 516 * The ll_bit is cleared by r*_switch.S 517 */ 518 519 unsigned int ll_bit; 520 struct task_struct *ll_task; 521 522 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 523 { 524 unsigned long value, __user *vaddr; 525 long offset; 526 527 /* 528 * analyse the ll instruction that just caused a ri exception 529 * and put the referenced address to addr. 530 */ 531 532 /* sign extend offset */ 533 offset = opcode & OFFSET; 534 offset <<= 16; 535 offset >>= 16; 536 537 vaddr = (unsigned long __user *) 538 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 539 540 if ((unsigned long)vaddr & 3) 541 return SIGBUS; 542 if (get_user(value, vaddr)) 543 return SIGSEGV; 544 545 preempt_disable(); 546 547 if (ll_task == NULL || ll_task == current) { 548 ll_bit = 1; 549 } else { 550 ll_bit = 0; 551 } 552 ll_task = current; 553 554 preempt_enable(); 555 556 regs->regs[(opcode & RT) >> 16] = value; 557 558 return 0; 559 } 560 561 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 562 { 563 unsigned long __user *vaddr; 564 unsigned long reg; 565 long offset; 566 567 /* 568 * analyse the sc instruction that just caused a ri exception 569 * and put the referenced address to addr. 570 */ 571 572 /* sign extend offset */ 573 offset = opcode & OFFSET; 574 offset <<= 16; 575 offset >>= 16; 576 577 vaddr = (unsigned long __user *) 578 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 579 reg = (opcode & RT) >> 16; 580 581 if ((unsigned long)vaddr & 3) 582 return SIGBUS; 583 584 preempt_disable(); 585 586 if (ll_bit == 0 || ll_task != current) { 587 regs->regs[reg] = 0; 588 preempt_enable(); 589 return 0; 590 } 591 592 preempt_enable(); 593 594 if (put_user(regs->regs[reg], vaddr)) 595 return SIGSEGV; 596 597 regs->regs[reg] = 1; 598 599 return 0; 600 } 601 602 /* 603 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 604 * opcodes are supposed to result in coprocessor unusable exceptions if 605 * executed on ll/sc-less processors. That's the theory. In practice a 606 * few processors such as NEC's VR4100 throw reserved instruction exceptions 607 * instead, so we're doing the emulation thing in both exception handlers. 608 */ 609 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 610 { 611 if ((opcode & OPCODE) == LL) { 612 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 613 1, regs, 0); 614 return simulate_ll(regs, opcode); 615 } 616 if ((opcode & OPCODE) == SC) { 617 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 618 1, regs, 0); 619 return simulate_sc(regs, opcode); 620 } 621 622 return -1; /* Must be something else ... */ 623 } 624 625 /* 626 * Simulate trapping 'rdhwr' instructions to provide user accessible 627 * registers not implemented in hardware. 628 */ 629 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) 630 { 631 struct thread_info *ti = task_thread_info(current); 632 633 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 634 1, regs, 0); 635 switch (rd) { 636 case MIPS_HWR_CPUNUM: /* CPU number */ 637 regs->regs[rt] = smp_processor_id(); 638 return 0; 639 case MIPS_HWR_SYNCISTEP: /* SYNCI length */ 640 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 641 current_cpu_data.icache.linesz); 642 return 0; 643 case MIPS_HWR_CC: /* Read count register */ 644 regs->regs[rt] = read_c0_count(); 645 return 0; 646 case MIPS_HWR_CCRES: /* Count register resolution */ 647 switch (current_cpu_type()) { 648 case CPU_20KC: 649 case CPU_25KF: 650 regs->regs[rt] = 1; 651 break; 652 default: 653 regs->regs[rt] = 2; 654 } 655 return 0; 656 case MIPS_HWR_ULR: /* Read UserLocal register */ 657 regs->regs[rt] = ti->tp_value; 658 return 0; 659 default: 660 return -1; 661 } 662 } 663 664 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) 665 { 666 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 667 int rd = (opcode & RD) >> 11; 668 int rt = (opcode & RT) >> 16; 669 670 simulate_rdhwr(regs, rd, rt); 671 return 0; 672 } 673 674 /* Not ours. */ 675 return -1; 676 } 677 678 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode) 679 { 680 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { 681 int rd = (opcode & MM_RS) >> 16; 682 int rt = (opcode & MM_RT) >> 21; 683 simulate_rdhwr(regs, rd, rt); 684 return 0; 685 } 686 687 /* Not ours. */ 688 return -1; 689 } 690 691 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 692 { 693 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 694 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 695 1, regs, 0); 696 return 0; 697 } 698 699 return -1; /* Must be something else ... */ 700 } 701 702 /* 703 * Loongson-3 CSR instructions emulation 704 */ 705 706 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION 707 708 #define LWC2 0xc8000000 709 #define RS BASE 710 #define CSR_OPCODE2 0x00000118 711 #define CSR_OPCODE2_MASK 0x000007ff 712 #define CSR_FUNC_MASK RT 713 #define CSR_FUNC_CPUCFG 0x8 714 715 static int simulate_loongson3_cpucfg(struct pt_regs *regs, 716 unsigned int opcode) 717 { 718 int op = opcode & OPCODE; 719 int op2 = opcode & CSR_OPCODE2_MASK; 720 int csr_func = (opcode & CSR_FUNC_MASK) >> 16; 721 722 if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) { 723 int rd = (opcode & RD) >> 11; 724 int rs = (opcode & RS) >> 21; 725 __u64 sel = regs->regs[rs]; 726 727 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); 728 729 /* Do not emulate on unsupported core models. */ 730 preempt_disable(); 731 if (!loongson3_cpucfg_emulation_enabled(¤t_cpu_data)) { 732 preempt_enable(); 733 return -1; 734 } 735 regs->regs[rd] = loongson3_cpucfg_read_synthesized( 736 ¤t_cpu_data, sel); 737 preempt_enable(); 738 return 0; 739 } 740 741 /* Not ours. */ 742 return -1; 743 } 744 #endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */ 745 746 asmlinkage void do_ov(struct pt_regs *regs) 747 { 748 enum ctx_state prev_state; 749 750 prev_state = exception_enter(); 751 die_if_kernel("Integer overflow", regs); 752 753 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc); 754 exception_exit(prev_state); 755 } 756 757 #ifdef CONFIG_MIPS_FP_SUPPORT 758 759 /* 760 * Send SIGFPE according to FCSR Cause bits, which must have already 761 * been masked against Enable bits. This is impotant as Inexact can 762 * happen together with Overflow or Underflow, and `ptrace' can set 763 * any bits. 764 */ 765 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr, 766 struct task_struct *tsk) 767 { 768 int si_code = FPE_FLTUNK; 769 770 if (fcr31 & FPU_CSR_INV_X) 771 si_code = FPE_FLTINV; 772 else if (fcr31 & FPU_CSR_DIV_X) 773 si_code = FPE_FLTDIV; 774 else if (fcr31 & FPU_CSR_OVF_X) 775 si_code = FPE_FLTOVF; 776 else if (fcr31 & FPU_CSR_UDF_X) 777 si_code = FPE_FLTUND; 778 else if (fcr31 & FPU_CSR_INE_X) 779 si_code = FPE_FLTRES; 780 781 force_sig_fault_to_task(SIGFPE, si_code, fault_addr, tsk); 782 } 783 784 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31) 785 { 786 int si_code; 787 struct vm_area_struct *vma; 788 789 switch (sig) { 790 case 0: 791 return 0; 792 793 case SIGFPE: 794 force_fcr31_sig(fcr31, fault_addr, current); 795 return 1; 796 797 case SIGBUS: 798 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr); 799 return 1; 800 801 case SIGSEGV: 802 mmap_read_lock(current->mm); 803 vma = find_vma(current->mm, (unsigned long)fault_addr); 804 if (vma && (vma->vm_start <= (unsigned long)fault_addr)) 805 si_code = SEGV_ACCERR; 806 else 807 si_code = SEGV_MAPERR; 808 mmap_read_unlock(current->mm); 809 force_sig_fault(SIGSEGV, si_code, fault_addr); 810 return 1; 811 812 default: 813 force_sig(sig); 814 return 1; 815 } 816 } 817 818 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 819 unsigned long old_epc, unsigned long old_ra) 820 { 821 union mips_instruction inst = { .word = opcode }; 822 void __user *fault_addr; 823 unsigned long fcr31; 824 int sig; 825 826 /* If it's obviously not an FP instruction, skip it */ 827 switch (inst.i_format.opcode) { 828 case cop1_op: 829 case cop1x_op: 830 case lwc1_op: 831 case ldc1_op: 832 case swc1_op: 833 case sdc1_op: 834 break; 835 836 default: 837 return -1; 838 } 839 840 /* 841 * do_ri skipped over the instruction via compute_return_epc, undo 842 * that for the FPU emulator. 843 */ 844 regs->cp0_epc = old_epc; 845 regs->regs[31] = old_ra; 846 847 /* Run the emulator */ 848 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 849 &fault_addr); 850 851 /* 852 * We can't allow the emulated instruction to leave any 853 * enabled Cause bits set in $fcr31. 854 */ 855 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 856 current->thread.fpu.fcr31 &= ~fcr31; 857 858 /* Restore the hardware register state */ 859 own_fpu(1); 860 861 /* Send a signal if required. */ 862 process_fpemu_return(sig, fault_addr, fcr31); 863 864 return 0; 865 } 866 867 /* 868 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 869 */ 870 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 871 { 872 enum ctx_state prev_state; 873 void __user *fault_addr; 874 int sig; 875 876 prev_state = exception_enter(); 877 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, 878 SIGFPE) == NOTIFY_STOP) 879 goto out; 880 881 /* Clear FCSR.Cause before enabling interrupts */ 882 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31)); 883 local_irq_enable(); 884 885 die_if_kernel("FP exception in kernel code", regs); 886 887 if (fcr31 & FPU_CSR_UNI_X) { 888 /* 889 * Unimplemented operation exception. If we've got the full 890 * software emulator on-board, let's use it... 891 * 892 * Force FPU to dump state into task/thread context. We're 893 * moving a lot of data here for what is probably a single 894 * instruction, but the alternative is to pre-decode the FP 895 * register operands before invoking the emulator, which seems 896 * a bit extreme for what should be an infrequent event. 897 */ 898 899 /* Run the emulator */ 900 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 901 &fault_addr); 902 903 /* 904 * We can't allow the emulated instruction to leave any 905 * enabled Cause bits set in $fcr31. 906 */ 907 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 908 current->thread.fpu.fcr31 &= ~fcr31; 909 910 /* Restore the hardware register state */ 911 own_fpu(1); /* Using the FPU again. */ 912 } else { 913 sig = SIGFPE; 914 fault_addr = (void __user *) regs->cp0_epc; 915 } 916 917 /* Send a signal if required. */ 918 process_fpemu_return(sig, fault_addr, fcr31); 919 920 out: 921 exception_exit(prev_state); 922 } 923 924 /* 925 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 926 * emulated more than some threshold number of instructions, force migration to 927 * a "CPU" that has FP support. 928 */ 929 static void mt_ase_fp_affinity(void) 930 { 931 #ifdef CONFIG_MIPS_MT_FPAFF 932 if (mt_fpemul_threshold > 0 && 933 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 934 /* 935 * If there's no FPU present, or if the application has already 936 * restricted the allowed set to exclude any CPUs with FPUs, 937 * we'll skip the procedure. 938 */ 939 if (cpumask_intersects(¤t->cpus_mask, &mt_fpu_cpumask)) { 940 cpumask_t tmask; 941 942 current->thread.user_cpus_allowed 943 = current->cpus_mask; 944 cpumask_and(&tmask, ¤t->cpus_mask, 945 &mt_fpu_cpumask); 946 set_cpus_allowed_ptr(current, &tmask); 947 set_thread_flag(TIF_FPUBOUND); 948 } 949 } 950 #endif /* CONFIG_MIPS_MT_FPAFF */ 951 } 952 953 #else /* !CONFIG_MIPS_FP_SUPPORT */ 954 955 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 956 unsigned long old_epc, unsigned long old_ra) 957 { 958 return -1; 959 } 960 961 #endif /* !CONFIG_MIPS_FP_SUPPORT */ 962 963 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code, 964 const char *str) 965 { 966 char b[40]; 967 968 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 969 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr, 970 SIGTRAP) == NOTIFY_STOP) 971 return; 972 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 973 974 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr, 975 SIGTRAP) == NOTIFY_STOP) 976 return; 977 978 /* 979 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 980 * insns, even for trap and break codes that indicate arithmetic 981 * failures. Weird ... 982 * But should we continue the brokenness??? --macro 983 */ 984 switch (code) { 985 case BRK_OVERFLOW: 986 case BRK_DIVZERO: 987 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 988 die_if_kernel(b, regs); 989 force_sig_fault(SIGFPE, 990 code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF, 991 (void __user *) regs->cp0_epc); 992 break; 993 case BRK_BUG: 994 die_if_kernel("Kernel bug detected", regs); 995 force_sig(SIGTRAP); 996 break; 997 case BRK_MEMU: 998 /* 999 * This breakpoint code is used by the FPU emulator to retake 1000 * control of the CPU after executing the instruction from the 1001 * delay slot of an emulated branch. 1002 * 1003 * Terminate if exception was recognized as a delay slot return 1004 * otherwise handle as normal. 1005 */ 1006 if (do_dsemulret(regs)) 1007 return; 1008 1009 die_if_kernel("Math emu break/trap", regs); 1010 force_sig(SIGTRAP); 1011 break; 1012 default: 1013 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 1014 die_if_kernel(b, regs); 1015 if (si_code) { 1016 force_sig_fault(SIGTRAP, si_code, NULL); 1017 } else { 1018 force_sig(SIGTRAP); 1019 } 1020 } 1021 } 1022 1023 asmlinkage void do_bp(struct pt_regs *regs) 1024 { 1025 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 1026 unsigned int opcode, bcode; 1027 enum ctx_state prev_state; 1028 bool user = user_mode(regs); 1029 1030 prev_state = exception_enter(); 1031 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1032 if (get_isa16_mode(regs->cp0_epc)) { 1033 u16 instr[2]; 1034 1035 if (__get_inst16(&instr[0], (u16 *)epc, user)) 1036 goto out_sigsegv; 1037 1038 if (!cpu_has_mmips) { 1039 /* MIPS16e mode */ 1040 bcode = (instr[0] >> 5) & 0x3f; 1041 } else if (mm_insn_16bit(instr[0])) { 1042 /* 16-bit microMIPS BREAK */ 1043 bcode = instr[0] & 0xf; 1044 } else { 1045 /* 32-bit microMIPS BREAK */ 1046 if (__get_inst16(&instr[1], (u16 *)(epc + 2), user)) 1047 goto out_sigsegv; 1048 opcode = (instr[0] << 16) | instr[1]; 1049 bcode = (opcode >> 6) & ((1 << 20) - 1); 1050 } 1051 } else { 1052 if (__get_inst32(&opcode, (u32 *)epc, user)) 1053 goto out_sigsegv; 1054 bcode = (opcode >> 6) & ((1 << 20) - 1); 1055 } 1056 1057 /* 1058 * There is the ancient bug in the MIPS assemblers that the break 1059 * code starts left to bit 16 instead to bit 6 in the opcode. 1060 * Gas is bug-compatible, but not always, grrr... 1061 * We handle both cases with a simple heuristics. --macro 1062 */ 1063 if (bcode >= (1 << 10)) 1064 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10); 1065 1066 /* 1067 * notify the kprobe handlers, if instruction is likely to 1068 * pertain to them. 1069 */ 1070 switch (bcode) { 1071 case BRK_UPROBE: 1072 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode, 1073 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1074 goto out; 1075 else 1076 break; 1077 case BRK_UPROBE_XOL: 1078 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode, 1079 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1080 goto out; 1081 else 1082 break; 1083 case BRK_KPROBE_BP: 1084 if (notify_die(DIE_BREAK, "debug", regs, bcode, 1085 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1086 goto out; 1087 else 1088 break; 1089 case BRK_KPROBE_SSTEPBP: 1090 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 1091 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1092 goto out; 1093 else 1094 break; 1095 default: 1096 break; 1097 } 1098 1099 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break"); 1100 1101 out: 1102 exception_exit(prev_state); 1103 return; 1104 1105 out_sigsegv: 1106 force_sig(SIGSEGV); 1107 goto out; 1108 } 1109 1110 asmlinkage void do_tr(struct pt_regs *regs) 1111 { 1112 u32 opcode, tcode = 0; 1113 enum ctx_state prev_state; 1114 u16 instr[2]; 1115 bool user = user_mode(regs); 1116 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 1117 1118 prev_state = exception_enter(); 1119 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1120 if (get_isa16_mode(regs->cp0_epc)) { 1121 if (__get_inst16(&instr[0], (u16 *)(epc + 0), user) || 1122 __get_inst16(&instr[1], (u16 *)(epc + 2), user)) 1123 goto out_sigsegv; 1124 opcode = (instr[0] << 16) | instr[1]; 1125 /* Immediate versions don't provide a code. */ 1126 if (!(opcode & OPCODE)) 1127 tcode = (opcode >> 12) & ((1 << 4) - 1); 1128 } else { 1129 if (__get_inst32(&opcode, (u32 *)epc, user)) 1130 goto out_sigsegv; 1131 /* Immediate versions don't provide a code. */ 1132 if (!(opcode & OPCODE)) 1133 tcode = (opcode >> 6) & ((1 << 10) - 1); 1134 } 1135 1136 do_trap_or_bp(regs, tcode, 0, "Trap"); 1137 1138 out: 1139 exception_exit(prev_state); 1140 return; 1141 1142 out_sigsegv: 1143 force_sig(SIGSEGV); 1144 goto out; 1145 } 1146 1147 asmlinkage void do_ri(struct pt_regs *regs) 1148 { 1149 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 1150 unsigned long old_epc = regs->cp0_epc; 1151 unsigned long old31 = regs->regs[31]; 1152 enum ctx_state prev_state; 1153 unsigned int opcode = 0; 1154 int status = -1; 1155 1156 /* 1157 * Avoid any kernel code. Just emulate the R2 instruction 1158 * as quickly as possible. 1159 */ 1160 if (mipsr2_emulation && cpu_has_mips_r6 && 1161 likely(user_mode(regs)) && 1162 likely(get_user(opcode, epc) >= 0)) { 1163 unsigned long fcr31 = 0; 1164 1165 status = mipsr2_decoder(regs, opcode, &fcr31); 1166 switch (status) { 1167 case 0: 1168 case SIGEMT: 1169 return; 1170 case SIGILL: 1171 goto no_r2_instr; 1172 default: 1173 process_fpemu_return(status, 1174 ¤t->thread.cp0_baduaddr, 1175 fcr31); 1176 return; 1177 } 1178 } 1179 1180 no_r2_instr: 1181 1182 prev_state = exception_enter(); 1183 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1184 1185 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, 1186 SIGILL) == NOTIFY_STOP) 1187 goto out; 1188 1189 die_if_kernel("Reserved instruction in kernel code", regs); 1190 1191 if (unlikely(compute_return_epc(regs) < 0)) 1192 goto out; 1193 1194 if (!get_isa16_mode(regs->cp0_epc)) { 1195 if (unlikely(get_user(opcode, epc) < 0)) 1196 status = SIGSEGV; 1197 1198 if (!cpu_has_llsc && status < 0) 1199 status = simulate_llsc(regs, opcode); 1200 1201 if (status < 0) 1202 status = simulate_rdhwr_normal(regs, opcode); 1203 1204 if (status < 0) 1205 status = simulate_sync(regs, opcode); 1206 1207 if (status < 0) 1208 status = simulate_fp(regs, opcode, old_epc, old31); 1209 1210 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION 1211 if (status < 0) 1212 status = simulate_loongson3_cpucfg(regs, opcode); 1213 #endif 1214 } else if (cpu_has_mmips) { 1215 unsigned short mmop[2] = { 0 }; 1216 1217 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0)) 1218 status = SIGSEGV; 1219 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0)) 1220 status = SIGSEGV; 1221 opcode = mmop[0]; 1222 opcode = (opcode << 16) | mmop[1]; 1223 1224 if (status < 0) 1225 status = simulate_rdhwr_mm(regs, opcode); 1226 } 1227 1228 if (status < 0) 1229 status = SIGILL; 1230 1231 if (unlikely(status > 0)) { 1232 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1233 regs->regs[31] = old31; 1234 force_sig(status); 1235 } 1236 1237 out: 1238 exception_exit(prev_state); 1239 } 1240 1241 /* 1242 * No lock; only written during early bootup by CPU 0. 1243 */ 1244 static RAW_NOTIFIER_HEAD(cu2_chain); 1245 1246 int __ref register_cu2_notifier(struct notifier_block *nb) 1247 { 1248 return raw_notifier_chain_register(&cu2_chain, nb); 1249 } 1250 1251 int cu2_notifier_call_chain(unsigned long val, void *v) 1252 { 1253 return raw_notifier_call_chain(&cu2_chain, val, v); 1254 } 1255 1256 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 1257 void *data) 1258 { 1259 struct pt_regs *regs = data; 1260 1261 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " 1262 "instruction", regs); 1263 force_sig(SIGILL); 1264 1265 return NOTIFY_OK; 1266 } 1267 1268 #ifdef CONFIG_MIPS_FP_SUPPORT 1269 1270 static int enable_restore_fp_context(int msa) 1271 { 1272 int err, was_fpu_owner, prior_msa; 1273 bool first_fp; 1274 1275 /* Initialize context if it hasn't been used already */ 1276 first_fp = init_fp_ctx(current); 1277 1278 if (first_fp) { 1279 preempt_disable(); 1280 err = own_fpu_inatomic(1); 1281 if (msa && !err) { 1282 enable_msa(); 1283 /* 1284 * with MSA enabled, userspace can see MSACSR 1285 * and MSA regs, but the values in them are from 1286 * other task before current task, restore them 1287 * from saved fp/msa context 1288 */ 1289 write_msa_csr(current->thread.fpu.msacsr); 1290 /* 1291 * own_fpu_inatomic(1) just restore low 64bit, 1292 * fix the high 64bit 1293 */ 1294 init_msa_upper(); 1295 set_thread_flag(TIF_USEDMSA); 1296 set_thread_flag(TIF_MSA_CTX_LIVE); 1297 } 1298 preempt_enable(); 1299 return err; 1300 } 1301 1302 /* 1303 * This task has formerly used the FP context. 1304 * 1305 * If this thread has no live MSA vector context then we can simply 1306 * restore the scalar FP context. If it has live MSA vector context 1307 * (that is, it has or may have used MSA since last performing a 1308 * function call) then we'll need to restore the vector context. This 1309 * applies even if we're currently only executing a scalar FP 1310 * instruction. This is because if we were to later execute an MSA 1311 * instruction then we'd either have to: 1312 * 1313 * - Restore the vector context & clobber any registers modified by 1314 * scalar FP instructions between now & then. 1315 * 1316 * or 1317 * 1318 * - Not restore the vector context & lose the most significant bits 1319 * of all vector registers. 1320 * 1321 * Neither of those options is acceptable. We cannot restore the least 1322 * significant bits of the registers now & only restore the most 1323 * significant bits later because the most significant bits of any 1324 * vector registers whose aliased FP register is modified now will have 1325 * been zeroed. We'd have no way to know that when restoring the vector 1326 * context & thus may load an outdated value for the most significant 1327 * bits of a vector register. 1328 */ 1329 if (!msa && !thread_msa_context_live()) 1330 return own_fpu(1); 1331 1332 /* 1333 * This task is using or has previously used MSA. Thus we require 1334 * that Status.FR == 1. 1335 */ 1336 preempt_disable(); 1337 was_fpu_owner = is_fpu_owner(); 1338 err = own_fpu_inatomic(0); 1339 if (err) 1340 goto out; 1341 1342 enable_msa(); 1343 write_msa_csr(current->thread.fpu.msacsr); 1344 set_thread_flag(TIF_USEDMSA); 1345 1346 /* 1347 * If this is the first time that the task is using MSA and it has 1348 * previously used scalar FP in this time slice then we already nave 1349 * FP context which we shouldn't clobber. We do however need to clear 1350 * the upper 64b of each vector register so that this task has no 1351 * opportunity to see data left behind by another. 1352 */ 1353 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); 1354 if (!prior_msa && was_fpu_owner) { 1355 init_msa_upper(); 1356 1357 goto out; 1358 } 1359 1360 if (!prior_msa) { 1361 /* 1362 * Restore the least significant 64b of each vector register 1363 * from the existing scalar FP context. 1364 */ 1365 _restore_fp(current); 1366 1367 /* 1368 * The task has not formerly used MSA, so clear the upper 64b 1369 * of each vector register such that it cannot see data left 1370 * behind by another task. 1371 */ 1372 init_msa_upper(); 1373 } else { 1374 /* We need to restore the vector context. */ 1375 restore_msa(current); 1376 1377 /* Restore the scalar FP control & status register */ 1378 if (!was_fpu_owner) 1379 write_32bit_cp1_register(CP1_STATUS, 1380 current->thread.fpu.fcr31); 1381 } 1382 1383 out: 1384 preempt_enable(); 1385 1386 return 0; 1387 } 1388 1389 #else /* !CONFIG_MIPS_FP_SUPPORT */ 1390 1391 static int enable_restore_fp_context(int msa) 1392 { 1393 return SIGILL; 1394 } 1395 1396 #endif /* CONFIG_MIPS_FP_SUPPORT */ 1397 1398 asmlinkage void do_cpu(struct pt_regs *regs) 1399 { 1400 enum ctx_state prev_state; 1401 unsigned int __user *epc; 1402 unsigned long old_epc, old31; 1403 unsigned int opcode; 1404 unsigned int cpid; 1405 int status; 1406 1407 prev_state = exception_enter(); 1408 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1409 1410 if (cpid != 2) 1411 die_if_kernel("do_cpu invoked from kernel context!", regs); 1412 1413 switch (cpid) { 1414 case 0: 1415 epc = (unsigned int __user *)exception_epc(regs); 1416 old_epc = regs->cp0_epc; 1417 old31 = regs->regs[31]; 1418 opcode = 0; 1419 status = -1; 1420 1421 if (unlikely(compute_return_epc(regs) < 0)) 1422 break; 1423 1424 if (!get_isa16_mode(regs->cp0_epc)) { 1425 if (unlikely(get_user(opcode, epc) < 0)) 1426 status = SIGSEGV; 1427 1428 if (!cpu_has_llsc && status < 0) 1429 status = simulate_llsc(regs, opcode); 1430 } 1431 1432 if (status < 0) 1433 status = SIGILL; 1434 1435 if (unlikely(status > 0)) { 1436 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1437 regs->regs[31] = old31; 1438 force_sig(status); 1439 } 1440 1441 break; 1442 1443 #ifdef CONFIG_MIPS_FP_SUPPORT 1444 case 3: 1445 /* 1446 * The COP3 opcode space and consequently the CP0.Status.CU3 1447 * bit and the CP0.Cause.CE=3 encoding have been removed as 1448 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs 1449 * up the space has been reused for COP1X instructions, that 1450 * are enabled by the CP0.Status.CU1 bit and consequently 1451 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable 1452 * exceptions. Some FPU-less processors that implement one 1453 * of these ISAs however use this code erroneously for COP1X 1454 * instructions. Therefore we redirect this trap to the FP 1455 * emulator too. 1456 */ 1457 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) { 1458 force_sig(SIGILL); 1459 break; 1460 } 1461 fallthrough; 1462 case 1: { 1463 void __user *fault_addr; 1464 unsigned long fcr31; 1465 int err, sig; 1466 1467 err = enable_restore_fp_context(0); 1468 1469 if (raw_cpu_has_fpu && !err) 1470 break; 1471 1472 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, 1473 &fault_addr); 1474 1475 /* 1476 * We can't allow the emulated instruction to leave 1477 * any enabled Cause bits set in $fcr31. 1478 */ 1479 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 1480 current->thread.fpu.fcr31 &= ~fcr31; 1481 1482 /* Send a signal if required. */ 1483 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err) 1484 mt_ase_fp_affinity(); 1485 1486 break; 1487 } 1488 #else /* CONFIG_MIPS_FP_SUPPORT */ 1489 case 1: 1490 case 3: 1491 force_sig(SIGILL); 1492 break; 1493 #endif /* CONFIG_MIPS_FP_SUPPORT */ 1494 1495 case 2: 1496 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1497 break; 1498 } 1499 1500 exception_exit(prev_state); 1501 } 1502 1503 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr) 1504 { 1505 enum ctx_state prev_state; 1506 1507 prev_state = exception_enter(); 1508 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1509 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0, 1510 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP) 1511 goto out; 1512 1513 /* Clear MSACSR.Cause before enabling interrupts */ 1514 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF); 1515 local_irq_enable(); 1516 1517 die_if_kernel("do_msa_fpe invoked from kernel context!", regs); 1518 force_sig(SIGFPE); 1519 out: 1520 exception_exit(prev_state); 1521 } 1522 1523 asmlinkage void do_msa(struct pt_regs *regs) 1524 { 1525 enum ctx_state prev_state; 1526 int err; 1527 1528 prev_state = exception_enter(); 1529 1530 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { 1531 force_sig(SIGILL); 1532 goto out; 1533 } 1534 1535 die_if_kernel("do_msa invoked from kernel context!", regs); 1536 1537 err = enable_restore_fp_context(1); 1538 if (err) 1539 force_sig(SIGILL); 1540 out: 1541 exception_exit(prev_state); 1542 } 1543 1544 asmlinkage void do_mdmx(struct pt_regs *regs) 1545 { 1546 enum ctx_state prev_state; 1547 1548 prev_state = exception_enter(); 1549 force_sig(SIGILL); 1550 exception_exit(prev_state); 1551 } 1552 1553 /* 1554 * Called with interrupts disabled. 1555 */ 1556 asmlinkage void do_watch(struct pt_regs *regs) 1557 { 1558 enum ctx_state prev_state; 1559 1560 prev_state = exception_enter(); 1561 /* 1562 * Clear WP (bit 22) bit of cause register so we don't loop 1563 * forever. 1564 */ 1565 clear_c0_cause(CAUSEF_WP); 1566 1567 /* 1568 * If the current thread has the watch registers loaded, save 1569 * their values and send SIGTRAP. Otherwise another thread 1570 * left the registers set, clear them and continue. 1571 */ 1572 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1573 mips_read_watch_registers(); 1574 local_irq_enable(); 1575 force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL); 1576 } else { 1577 mips_clear_watch_registers(); 1578 local_irq_enable(); 1579 } 1580 exception_exit(prev_state); 1581 } 1582 1583 asmlinkage void do_mcheck(struct pt_regs *regs) 1584 { 1585 int multi_match = regs->cp0_status & ST0_TS; 1586 enum ctx_state prev_state; 1587 1588 prev_state = exception_enter(); 1589 show_regs(regs); 1590 1591 if (multi_match) { 1592 dump_tlb_regs(); 1593 pr_info("\n"); 1594 dump_tlb_all(); 1595 } 1596 1597 show_code((void *)regs->cp0_epc, user_mode(regs)); 1598 1599 /* 1600 * Some chips may have other causes of machine check (e.g. SB1 1601 * graduation timer) 1602 */ 1603 panic("Caught Machine Check exception - %scaused by multiple " 1604 "matching entries in the TLB.", 1605 (multi_match) ? "" : "not "); 1606 } 1607 1608 asmlinkage void do_mt(struct pt_regs *regs) 1609 { 1610 int subcode; 1611 1612 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1613 >> VPECONTROL_EXCPT_SHIFT; 1614 switch (subcode) { 1615 case 0: 1616 printk(KERN_DEBUG "Thread Underflow\n"); 1617 break; 1618 case 1: 1619 printk(KERN_DEBUG "Thread Overflow\n"); 1620 break; 1621 case 2: 1622 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1623 break; 1624 case 3: 1625 printk(KERN_DEBUG "Gating Storage Exception\n"); 1626 break; 1627 case 4: 1628 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1629 break; 1630 case 5: 1631 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1632 break; 1633 default: 1634 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1635 subcode); 1636 break; 1637 } 1638 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1639 1640 force_sig(SIGILL); 1641 } 1642 1643 1644 asmlinkage void do_dsp(struct pt_regs *regs) 1645 { 1646 if (cpu_has_dsp) 1647 panic("Unexpected DSP exception"); 1648 1649 force_sig(SIGILL); 1650 } 1651 1652 asmlinkage void do_reserved(struct pt_regs *regs) 1653 { 1654 /* 1655 * Game over - no way to handle this if it ever occurs. Most probably 1656 * caused by a new unknown cpu type or after another deadly 1657 * hard/software error. 1658 */ 1659 show_regs(regs); 1660 panic("Caught reserved exception %ld - should not happen.", 1661 (regs->cp0_cause & 0x7f) >> 2); 1662 } 1663 1664 static int __initdata l1parity = 1; 1665 static int __init nol1parity(char *s) 1666 { 1667 l1parity = 0; 1668 return 1; 1669 } 1670 __setup("nol1par", nol1parity); 1671 static int __initdata l2parity = 1; 1672 static int __init nol2parity(char *s) 1673 { 1674 l2parity = 0; 1675 return 1; 1676 } 1677 __setup("nol2par", nol2parity); 1678 1679 /* 1680 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1681 * it different ways. 1682 */ 1683 static inline __init void parity_protection_init(void) 1684 { 1685 #define ERRCTL_PE 0x80000000 1686 #define ERRCTL_L2P 0x00800000 1687 1688 if (mips_cm_revision() >= CM_REV_CM3) { 1689 ulong gcr_ectl, cp0_ectl; 1690 1691 /* 1692 * With CM3 systems we need to ensure that the L1 & L2 1693 * parity enables are set to the same value, since this 1694 * is presumed by the hardware engineers. 1695 * 1696 * If the user disabled either of L1 or L2 ECC checking, 1697 * disable both. 1698 */ 1699 l1parity &= l2parity; 1700 l2parity &= l1parity; 1701 1702 /* Probe L1 ECC support */ 1703 cp0_ectl = read_c0_ecc(); 1704 write_c0_ecc(cp0_ectl | ERRCTL_PE); 1705 back_to_back_c0_hazard(); 1706 cp0_ectl = read_c0_ecc(); 1707 1708 /* Probe L2 ECC support */ 1709 gcr_ectl = read_gcr_err_control(); 1710 1711 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) || 1712 !(cp0_ectl & ERRCTL_PE)) { 1713 /* 1714 * One of L1 or L2 ECC checking isn't supported, 1715 * so we cannot enable either. 1716 */ 1717 l1parity = l2parity = 0; 1718 } 1719 1720 /* Configure L1 ECC checking */ 1721 if (l1parity) 1722 cp0_ectl |= ERRCTL_PE; 1723 else 1724 cp0_ectl &= ~ERRCTL_PE; 1725 write_c0_ecc(cp0_ectl); 1726 back_to_back_c0_hazard(); 1727 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity); 1728 1729 /* Configure L2 ECC checking */ 1730 if (l2parity) 1731 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN; 1732 else 1733 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN; 1734 write_gcr_err_control(gcr_ectl); 1735 gcr_ectl = read_gcr_err_control(); 1736 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN; 1737 WARN_ON(!!gcr_ectl != l2parity); 1738 1739 pr_info("Cache parity protection %sabled\n", 1740 l1parity ? "en" : "dis"); 1741 return; 1742 } 1743 1744 switch (current_cpu_type()) { 1745 case CPU_24K: 1746 case CPU_34K: 1747 case CPU_74K: 1748 case CPU_1004K: 1749 case CPU_1074K: 1750 case CPU_INTERAPTIV: 1751 case CPU_PROAPTIV: 1752 case CPU_P5600: 1753 case CPU_QEMU_GENERIC: 1754 case CPU_P6600: 1755 { 1756 unsigned long errctl; 1757 unsigned int l1parity_present, l2parity_present; 1758 1759 errctl = read_c0_ecc(); 1760 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1761 1762 /* probe L1 parity support */ 1763 write_c0_ecc(errctl | ERRCTL_PE); 1764 back_to_back_c0_hazard(); 1765 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1766 1767 /* probe L2 parity support */ 1768 write_c0_ecc(errctl|ERRCTL_L2P); 1769 back_to_back_c0_hazard(); 1770 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1771 1772 if (l1parity_present && l2parity_present) { 1773 if (l1parity) 1774 errctl |= ERRCTL_PE; 1775 if (l1parity ^ l2parity) 1776 errctl |= ERRCTL_L2P; 1777 } else if (l1parity_present) { 1778 if (l1parity) 1779 errctl |= ERRCTL_PE; 1780 } else if (l2parity_present) { 1781 if (l2parity) 1782 errctl |= ERRCTL_L2P; 1783 } else { 1784 /* No parity available */ 1785 } 1786 1787 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1788 1789 write_c0_ecc(errctl); 1790 back_to_back_c0_hazard(); 1791 errctl = read_c0_ecc(); 1792 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1793 1794 if (l1parity_present) 1795 printk(KERN_INFO "Cache parity protection %sabled\n", 1796 (errctl & ERRCTL_PE) ? "en" : "dis"); 1797 1798 if (l2parity_present) { 1799 if (l1parity_present && l1parity) 1800 errctl ^= ERRCTL_L2P; 1801 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1802 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1803 } 1804 } 1805 break; 1806 1807 case CPU_5KC: 1808 case CPU_5KE: 1809 case CPU_LOONGSON32: 1810 write_c0_ecc(0x80000000); 1811 back_to_back_c0_hazard(); 1812 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1813 printk(KERN_INFO "Cache parity protection %sabled\n", 1814 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1815 break; 1816 case CPU_20KC: 1817 case CPU_25KF: 1818 /* Clear the DE bit (bit 16) in the c0_status register. */ 1819 printk(KERN_INFO "Enable cache parity protection for " 1820 "MIPS 20KC/25KF CPUs.\n"); 1821 clear_c0_status(ST0_DE); 1822 break; 1823 default: 1824 break; 1825 } 1826 } 1827 1828 asmlinkage void cache_parity_error(void) 1829 { 1830 const int field = 2 * sizeof(unsigned long); 1831 unsigned int reg_val; 1832 1833 /* For the moment, report the problem and hang. */ 1834 printk("Cache error exception:\n"); 1835 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1836 reg_val = read_c0_cacheerr(); 1837 printk("c0_cacheerr == %08x\n", reg_val); 1838 1839 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1840 reg_val & (1<<30) ? "secondary" : "primary", 1841 reg_val & (1<<31) ? "data" : "insn"); 1842 if ((cpu_has_mips_r2_r6) && 1843 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1844 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1845 reg_val & (1<<29) ? "ED " : "", 1846 reg_val & (1<<28) ? "ET " : "", 1847 reg_val & (1<<27) ? "ES " : "", 1848 reg_val & (1<<26) ? "EE " : "", 1849 reg_val & (1<<25) ? "EB " : "", 1850 reg_val & (1<<24) ? "EI " : "", 1851 reg_val & (1<<23) ? "E1 " : "", 1852 reg_val & (1<<22) ? "E0 " : ""); 1853 } else { 1854 pr_err("Error bits: %s%s%s%s%s%s%s\n", 1855 reg_val & (1<<29) ? "ED " : "", 1856 reg_val & (1<<28) ? "ET " : "", 1857 reg_val & (1<<26) ? "EE " : "", 1858 reg_val & (1<<25) ? "EB " : "", 1859 reg_val & (1<<24) ? "EI " : "", 1860 reg_val & (1<<23) ? "E1 " : "", 1861 reg_val & (1<<22) ? "E0 " : ""); 1862 } 1863 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1864 1865 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1866 if (reg_val & (1<<22)) 1867 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1868 1869 if (reg_val & (1<<23)) 1870 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1871 #endif 1872 1873 panic("Can't handle the cache error!"); 1874 } 1875 1876 asmlinkage void do_ftlb(void) 1877 { 1878 const int field = 2 * sizeof(unsigned long); 1879 unsigned int reg_val; 1880 1881 /* For the moment, report the problem and hang. */ 1882 if ((cpu_has_mips_r2_r6) && 1883 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) || 1884 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) { 1885 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1886 read_c0_ecc()); 1887 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1888 reg_val = read_c0_cacheerr(); 1889 pr_err("c0_cacheerr == %08x\n", reg_val); 1890 1891 if ((reg_val & 0xc0000000) == 0xc0000000) { 1892 pr_err("Decoded c0_cacheerr: FTLB parity error\n"); 1893 } else { 1894 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1895 reg_val & (1<<30) ? "secondary" : "primary", 1896 reg_val & (1<<31) ? "data" : "insn"); 1897 } 1898 } else { 1899 pr_err("FTLB error exception\n"); 1900 } 1901 /* Just print the cacheerr bits for now */ 1902 cache_parity_error(); 1903 } 1904 1905 asmlinkage void do_gsexc(struct pt_regs *regs, u32 diag1) 1906 { 1907 u32 exccode = (diag1 & LOONGSON_DIAG1_EXCCODE) >> 1908 LOONGSON_DIAG1_EXCCODE_SHIFT; 1909 enum ctx_state prev_state; 1910 1911 prev_state = exception_enter(); 1912 1913 switch (exccode) { 1914 case 0x08: 1915 /* Undocumented exception, will trigger on certain 1916 * also-undocumented instructions accessible from userspace. 1917 * Processor state is not otherwise corrupted, but currently 1918 * we don't know how to proceed. Maybe there is some 1919 * undocumented control flag to enable the instructions? 1920 */ 1921 force_sig(SIGILL); 1922 break; 1923 1924 default: 1925 /* None of the other exceptions, documented or not, have 1926 * further details given; none are encountered in the wild 1927 * either. Panic in case some of them turn out to be fatal. 1928 */ 1929 show_regs(regs); 1930 panic("Unhandled Loongson exception - GSCause = %08x", diag1); 1931 } 1932 1933 exception_exit(prev_state); 1934 } 1935 1936 /* 1937 * SDBBP EJTAG debug exception handler. 1938 * We skip the instruction and return to the next instruction. 1939 */ 1940 void ejtag_exception_handler(struct pt_regs *regs) 1941 { 1942 const int field = 2 * sizeof(unsigned long); 1943 unsigned long depc, old_epc, old_ra; 1944 unsigned int debug; 1945 1946 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1947 depc = read_c0_depc(); 1948 debug = read_c0_debug(); 1949 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1950 if (debug & 0x80000000) { 1951 /* 1952 * In branch delay slot. 1953 * We cheat a little bit here and use EPC to calculate the 1954 * debug return address (DEPC). EPC is restored after the 1955 * calculation. 1956 */ 1957 old_epc = regs->cp0_epc; 1958 old_ra = regs->regs[31]; 1959 regs->cp0_epc = depc; 1960 compute_return_epc(regs); 1961 depc = regs->cp0_epc; 1962 regs->cp0_epc = old_epc; 1963 regs->regs[31] = old_ra; 1964 } else 1965 depc += 4; 1966 write_c0_depc(depc); 1967 1968 #if 0 1969 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1970 write_c0_debug(debug | 0x100); 1971 #endif 1972 } 1973 1974 /* 1975 * NMI exception handler. 1976 * No lock; only written during early bootup by CPU 0. 1977 */ 1978 static RAW_NOTIFIER_HEAD(nmi_chain); 1979 1980 int register_nmi_notifier(struct notifier_block *nb) 1981 { 1982 return raw_notifier_chain_register(&nmi_chain, nb); 1983 } 1984 1985 void __noreturn nmi_exception_handler(struct pt_regs *regs) 1986 { 1987 char str[100]; 1988 1989 nmi_enter(); 1990 raw_notifier_call_chain(&nmi_chain, 0, regs); 1991 bust_spinlocks(1); 1992 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", 1993 smp_processor_id(), regs->cp0_epc); 1994 regs->cp0_epc = read_c0_errorepc(); 1995 die(str, regs); 1996 nmi_exit(); 1997 } 1998 1999 unsigned long ebase; 2000 EXPORT_SYMBOL_GPL(ebase); 2001 unsigned long exception_handlers[32]; 2002 unsigned long vi_handlers[64]; 2003 2004 void reserve_exception_space(phys_addr_t addr, unsigned long size) 2005 { 2006 memblock_reserve(addr, size); 2007 } 2008 2009 void __init *set_except_vector(int n, void *addr) 2010 { 2011 unsigned long handler = (unsigned long) addr; 2012 unsigned long old_handler; 2013 2014 #ifdef CONFIG_CPU_MICROMIPS 2015 /* 2016 * Only the TLB handlers are cache aligned with an even 2017 * address. All other handlers are on an odd address and 2018 * require no modification. Otherwise, MIPS32 mode will 2019 * be entered when handling any TLB exceptions. That 2020 * would be bad...since we must stay in microMIPS mode. 2021 */ 2022 if (!(handler & 0x1)) 2023 handler |= 1; 2024 #endif 2025 old_handler = xchg(&exception_handlers[n], handler); 2026 2027 if (n == 0 && cpu_has_divec) { 2028 #ifdef CONFIG_CPU_MICROMIPS 2029 unsigned long jump_mask = ~((1 << 27) - 1); 2030 #else 2031 unsigned long jump_mask = ~((1 << 28) - 1); 2032 #endif 2033 u32 *buf = (u32 *)(ebase + 0x200); 2034 unsigned int k0 = 26; 2035 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 2036 uasm_i_j(&buf, handler & ~jump_mask); 2037 uasm_i_nop(&buf); 2038 } else { 2039 UASM_i_LA(&buf, k0, handler); 2040 uasm_i_jr(&buf, k0); 2041 uasm_i_nop(&buf); 2042 } 2043 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 2044 } 2045 return (void *)old_handler; 2046 } 2047 2048 static void do_default_vi(void) 2049 { 2050 show_regs(get_irq_regs()); 2051 panic("Caught unexpected vectored interrupt."); 2052 } 2053 2054 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 2055 { 2056 unsigned long handler; 2057 unsigned long old_handler = vi_handlers[n]; 2058 int srssets = current_cpu_data.srsets; 2059 u16 *h; 2060 unsigned char *b; 2061 2062 BUG_ON(!cpu_has_veic && !cpu_has_vint); 2063 2064 if (addr == NULL) { 2065 handler = (unsigned long) do_default_vi; 2066 srs = 0; 2067 } else 2068 handler = (unsigned long) addr; 2069 vi_handlers[n] = handler; 2070 2071 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 2072 2073 if (srs >= srssets) 2074 panic("Shadow register set %d not supported", srs); 2075 2076 if (cpu_has_veic) { 2077 if (board_bind_eic_interrupt) 2078 board_bind_eic_interrupt(n, srs); 2079 } else if (cpu_has_vint) { 2080 /* SRSMap is only defined if shadow sets are implemented */ 2081 if (srssets > 1) 2082 change_c0_srsmap(0xf << n*4, srs << n*4); 2083 } 2084 2085 if (srs == 0) { 2086 /* 2087 * If no shadow set is selected then use the default handler 2088 * that does normal register saving and standard interrupt exit 2089 */ 2090 extern char except_vec_vi, except_vec_vi_lui; 2091 extern char except_vec_vi_ori, except_vec_vi_end; 2092 extern char rollback_except_vec_vi; 2093 char *vec_start = using_rollback_handler() ? 2094 &rollback_except_vec_vi : &except_vec_vi; 2095 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) 2096 const int lui_offset = &except_vec_vi_lui - vec_start + 2; 2097 const int ori_offset = &except_vec_vi_ori - vec_start + 2; 2098 #else 2099 const int lui_offset = &except_vec_vi_lui - vec_start; 2100 const int ori_offset = &except_vec_vi_ori - vec_start; 2101 #endif 2102 const int handler_len = &except_vec_vi_end - vec_start; 2103 2104 if (handler_len > VECTORSPACING) { 2105 /* 2106 * Sigh... panicing won't help as the console 2107 * is probably not configured :( 2108 */ 2109 panic("VECTORSPACING too small"); 2110 } 2111 2112 set_handler(((unsigned long)b - ebase), vec_start, 2113 #ifdef CONFIG_CPU_MICROMIPS 2114 (handler_len - 1)); 2115 #else 2116 handler_len); 2117 #endif 2118 h = (u16 *)(b + lui_offset); 2119 *h = (handler >> 16) & 0xffff; 2120 h = (u16 *)(b + ori_offset); 2121 *h = (handler & 0xffff); 2122 local_flush_icache_range((unsigned long)b, 2123 (unsigned long)(b+handler_len)); 2124 } 2125 else { 2126 /* 2127 * In other cases jump directly to the interrupt handler. It 2128 * is the handler's responsibility to save registers if required 2129 * (eg hi/lo) and return from the exception using "eret". 2130 */ 2131 u32 insn; 2132 2133 h = (u16 *)b; 2134 /* j handler */ 2135 #ifdef CONFIG_CPU_MICROMIPS 2136 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); 2137 #else 2138 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); 2139 #endif 2140 h[0] = (insn >> 16) & 0xffff; 2141 h[1] = insn & 0xffff; 2142 h[2] = 0; 2143 h[3] = 0; 2144 local_flush_icache_range((unsigned long)b, 2145 (unsigned long)(b+8)); 2146 } 2147 2148 return (void *)old_handler; 2149 } 2150 2151 void *set_vi_handler(int n, vi_handler_t addr) 2152 { 2153 return set_vi_srs_handler(n, addr, 0); 2154 } 2155 2156 extern void tlb_init(void); 2157 2158 /* 2159 * Timer interrupt 2160 */ 2161 int cp0_compare_irq; 2162 EXPORT_SYMBOL_GPL(cp0_compare_irq); 2163 int cp0_compare_irq_shift; 2164 2165 /* 2166 * Performance counter IRQ or -1 if shared with timer 2167 */ 2168 int cp0_perfcount_irq; 2169 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 2170 2171 /* 2172 * Fast debug channel IRQ or -1 if not present 2173 */ 2174 int cp0_fdc_irq; 2175 EXPORT_SYMBOL_GPL(cp0_fdc_irq); 2176 2177 static int noulri; 2178 2179 static int __init ulri_disable(char *s) 2180 { 2181 pr_info("Disabling ulri\n"); 2182 noulri = 1; 2183 2184 return 1; 2185 } 2186 __setup("noulri", ulri_disable); 2187 2188 /* configure STATUS register */ 2189 static void configure_status(void) 2190 { 2191 /* 2192 * Disable coprocessors and select 32-bit or 64-bit addressing 2193 * and the 16/32 or 32/32 FPR register model. Reset the BEV 2194 * flag that some firmware may have left set and the TS bit (for 2195 * IP27). Set XX for ISA IV code to work. 2196 */ 2197 unsigned int status_set = ST0_KERNEL_CUMASK; 2198 #ifdef CONFIG_64BIT 2199 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 2200 #endif 2201 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) 2202 status_set |= ST0_XX; 2203 if (cpu_has_dsp) 2204 status_set |= ST0_MX; 2205 2206 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 2207 status_set); 2208 back_to_back_c0_hazard(); 2209 } 2210 2211 unsigned int hwrena; 2212 EXPORT_SYMBOL_GPL(hwrena); 2213 2214 /* configure HWRENA register */ 2215 static void configure_hwrena(void) 2216 { 2217 hwrena = cpu_hwrena_impl_bits; 2218 2219 if (cpu_has_mips_r2_r6) 2220 hwrena |= MIPS_HWRENA_CPUNUM | 2221 MIPS_HWRENA_SYNCISTEP | 2222 MIPS_HWRENA_CC | 2223 MIPS_HWRENA_CCRES; 2224 2225 if (!noulri && cpu_has_userlocal) 2226 hwrena |= MIPS_HWRENA_ULR; 2227 2228 if (hwrena) 2229 write_c0_hwrena(hwrena); 2230 } 2231 2232 static void configure_exception_vector(void) 2233 { 2234 if (cpu_has_mips_r2_r6) { 2235 unsigned long sr = set_c0_status(ST0_BEV); 2236 /* If available, use WG to set top bits of EBASE */ 2237 if (cpu_has_ebase_wg) { 2238 #ifdef CONFIG_64BIT 2239 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 2240 #else 2241 write_c0_ebase(ebase | MIPS_EBASE_WG); 2242 #endif 2243 } 2244 write_c0_ebase(ebase); 2245 write_c0_status(sr); 2246 } 2247 if (cpu_has_veic || cpu_has_vint) { 2248 /* Setting vector spacing enables EI/VI mode */ 2249 change_c0_intctl(0x3e0, VECTORSPACING); 2250 } 2251 if (cpu_has_divec) { 2252 if (cpu_has_mipsmt) { 2253 unsigned int vpflags = dvpe(); 2254 set_c0_cause(CAUSEF_IV); 2255 evpe(vpflags); 2256 } else 2257 set_c0_cause(CAUSEF_IV); 2258 } 2259 } 2260 2261 void per_cpu_trap_init(bool is_boot_cpu) 2262 { 2263 unsigned int cpu = smp_processor_id(); 2264 2265 configure_status(); 2266 configure_hwrena(); 2267 2268 configure_exception_vector(); 2269 2270 /* 2271 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 2272 * 2273 * o read IntCtl.IPTI to determine the timer interrupt 2274 * o read IntCtl.IPPCI to determine the performance counter interrupt 2275 * o read IntCtl.IPFDC to determine the fast debug channel interrupt 2276 */ 2277 if (cpu_has_mips_r2_r6) { 2278 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 2279 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 2280 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 2281 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7; 2282 if (!cp0_fdc_irq) 2283 cp0_fdc_irq = -1; 2284 2285 } else { 2286 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 2287 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 2288 cp0_perfcount_irq = -1; 2289 cp0_fdc_irq = -1; 2290 } 2291 2292 if (cpu_has_mmid) 2293 cpu_data[cpu].asid_cache = 0; 2294 else if (!cpu_data[cpu].asid_cache) 2295 cpu_data[cpu].asid_cache = asid_first_version(cpu); 2296 2297 mmgrab(&init_mm); 2298 current->active_mm = &init_mm; 2299 BUG_ON(current->mm); 2300 enter_lazy_tlb(&init_mm, current); 2301 2302 /* Boot CPU's cache setup in setup_arch(). */ 2303 if (!is_boot_cpu) 2304 cpu_cache_init(); 2305 tlb_init(); 2306 TLBMISS_HANDLER_SETUP(); 2307 } 2308 2309 /* Install CPU exception handler */ 2310 void set_handler(unsigned long offset, void *addr, unsigned long size) 2311 { 2312 #ifdef CONFIG_CPU_MICROMIPS 2313 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); 2314 #else 2315 memcpy((void *)(ebase + offset), addr, size); 2316 #endif 2317 local_flush_icache_range(ebase + offset, ebase + offset + size); 2318 } 2319 2320 static const char panic_null_cerr[] = 2321 "Trying to set NULL cache error exception handler\n"; 2322 2323 /* 2324 * Install uncached CPU exception handler. 2325 * This is suitable only for the cache error exception which is the only 2326 * exception handler that is being run uncached. 2327 */ 2328 void set_uncached_handler(unsigned long offset, void *addr, 2329 unsigned long size) 2330 { 2331 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 2332 2333 if (!addr) 2334 panic(panic_null_cerr); 2335 2336 memcpy((void *)(uncached_ebase + offset), addr, size); 2337 } 2338 2339 static int __initdata rdhwr_noopt; 2340 static int __init set_rdhwr_noopt(char *str) 2341 { 2342 rdhwr_noopt = 1; 2343 return 1; 2344 } 2345 2346 __setup("rdhwr_noopt", set_rdhwr_noopt); 2347 2348 void __init trap_init(void) 2349 { 2350 extern char except_vec3_generic; 2351 extern char except_vec4; 2352 extern char except_vec3_r4000; 2353 unsigned long i, vec_size; 2354 phys_addr_t ebase_pa; 2355 2356 check_wait(); 2357 2358 if (!cpu_has_mips_r2_r6) { 2359 ebase = CAC_BASE; 2360 vec_size = 0x400; 2361 } else { 2362 if (cpu_has_veic || cpu_has_vint) 2363 vec_size = 0x200 + VECTORSPACING*64; 2364 else 2365 vec_size = PAGE_SIZE; 2366 2367 ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); 2368 if (!ebase_pa) 2369 panic("%s: Failed to allocate %lu bytes align=0x%x\n", 2370 __func__, vec_size, 1 << fls(vec_size)); 2371 2372 /* 2373 * Try to ensure ebase resides in KSeg0 if possible. 2374 * 2375 * It shouldn't generally be in XKPhys on MIPS64 to avoid 2376 * hitting a poorly defined exception base for Cache Errors. 2377 * The allocation is likely to be in the low 512MB of physical, 2378 * in which case we should be able to convert to KSeg0. 2379 * 2380 * EVA is special though as it allows segments to be rearranged 2381 * and to become uncached during cache error handling. 2382 */ 2383 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) 2384 ebase = CKSEG0ADDR(ebase_pa); 2385 else 2386 ebase = (unsigned long)phys_to_virt(ebase_pa); 2387 } 2388 2389 if (cpu_has_mmips) { 2390 unsigned int config3 = read_c0_config3(); 2391 2392 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) 2393 write_c0_config3(config3 | MIPS_CONF3_ISA_OE); 2394 else 2395 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); 2396 } 2397 2398 if (board_ebase_setup) 2399 board_ebase_setup(); 2400 per_cpu_trap_init(true); 2401 memblock_set_bottom_up(false); 2402 2403 /* 2404 * Copy the generic exception handlers to their final destination. 2405 * This will be overridden later as suitable for a particular 2406 * configuration. 2407 */ 2408 set_handler(0x180, &except_vec3_generic, 0x80); 2409 2410 /* 2411 * Setup default vectors 2412 */ 2413 for (i = 0; i <= 31; i++) 2414 set_except_vector(i, handle_reserved); 2415 2416 /* 2417 * Copy the EJTAG debug exception vector handler code to it's final 2418 * destination. 2419 */ 2420 if (cpu_has_ejtag && board_ejtag_handler_setup) 2421 board_ejtag_handler_setup(); 2422 2423 /* 2424 * Only some CPUs have the watch exceptions. 2425 */ 2426 if (cpu_has_watch) 2427 set_except_vector(EXCCODE_WATCH, handle_watch); 2428 2429 /* 2430 * Initialise interrupt handlers 2431 */ 2432 if (cpu_has_veic || cpu_has_vint) { 2433 int nvec = cpu_has_veic ? 64 : 8; 2434 for (i = 0; i < nvec; i++) 2435 set_vi_handler(i, NULL); 2436 } 2437 else if (cpu_has_divec) 2438 set_handler(0x200, &except_vec4, 0x8); 2439 2440 /* 2441 * Some CPUs can enable/disable for cache parity detection, but does 2442 * it different ways. 2443 */ 2444 parity_protection_init(); 2445 2446 /* 2447 * The Data Bus Errors / Instruction Bus Errors are signaled 2448 * by external hardware. Therefore these two exceptions 2449 * may have board specific handlers. 2450 */ 2451 if (board_be_init) 2452 board_be_init(); 2453 2454 set_except_vector(EXCCODE_INT, using_rollback_handler() ? 2455 rollback_handle_int : handle_int); 2456 set_except_vector(EXCCODE_MOD, handle_tlbm); 2457 set_except_vector(EXCCODE_TLBL, handle_tlbl); 2458 set_except_vector(EXCCODE_TLBS, handle_tlbs); 2459 2460 set_except_vector(EXCCODE_ADEL, handle_adel); 2461 set_except_vector(EXCCODE_ADES, handle_ades); 2462 2463 set_except_vector(EXCCODE_IBE, handle_ibe); 2464 set_except_vector(EXCCODE_DBE, handle_dbe); 2465 2466 set_except_vector(EXCCODE_SYS, handle_sys); 2467 set_except_vector(EXCCODE_BP, handle_bp); 2468 2469 if (rdhwr_noopt) 2470 set_except_vector(EXCCODE_RI, handle_ri); 2471 else { 2472 if (cpu_has_vtag_icache) 2473 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 2474 else if (current_cpu_type() == CPU_LOONGSON64) 2475 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 2476 else 2477 set_except_vector(EXCCODE_RI, handle_ri_rdhwr); 2478 } 2479 2480 set_except_vector(EXCCODE_CPU, handle_cpu); 2481 set_except_vector(EXCCODE_OV, handle_ov); 2482 set_except_vector(EXCCODE_TR, handle_tr); 2483 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe); 2484 2485 if (board_nmi_handler_setup) 2486 board_nmi_handler_setup(); 2487 2488 if (cpu_has_fpu && !cpu_has_nofpuex) 2489 set_except_vector(EXCCODE_FPE, handle_fpe); 2490 2491 if (cpu_has_ftlbparex) 2492 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); 2493 2494 if (cpu_has_gsexcex) 2495 set_except_vector(LOONGSON_EXCCODE_GSEXC, handle_gsexc); 2496 2497 if (cpu_has_rixiex) { 2498 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0); 2499 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0); 2500 } 2501 2502 set_except_vector(EXCCODE_MSADIS, handle_msa); 2503 set_except_vector(EXCCODE_MDMX, handle_mdmx); 2504 2505 if (cpu_has_mcheck) 2506 set_except_vector(EXCCODE_MCHECK, handle_mcheck); 2507 2508 if (cpu_has_mipsmt) 2509 set_except_vector(EXCCODE_THREAD, handle_mt); 2510 2511 set_except_vector(EXCCODE_DSPDIS, handle_dsp); 2512 2513 if (board_cache_error_setup) 2514 board_cache_error_setup(); 2515 2516 if (cpu_has_vce) 2517 /* Special exception: R4[04]00 uses also the divec space. */ 2518 set_handler(0x180, &except_vec3_r4000, 0x100); 2519 else if (cpu_has_4kex) 2520 set_handler(0x180, &except_vec3_generic, 0x80); 2521 else 2522 set_handler(0x080, &except_vec3_generic, 0x80); 2523 2524 local_flush_icache_range(ebase, ebase + vec_size); 2525 2526 sort_extable(__start___dbe_table, __stop___dbe_table); 2527 2528 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 2529 } 2530 2531 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, 2532 void *v) 2533 { 2534 switch (cmd) { 2535 case CPU_PM_ENTER_FAILED: 2536 case CPU_PM_EXIT: 2537 configure_status(); 2538 configure_hwrena(); 2539 configure_exception_vector(); 2540 2541 /* Restore register with CPU number for TLB handlers */ 2542 TLBMISS_HANDLER_RESTORE(); 2543 2544 break; 2545 } 2546 2547 return NOTIFY_OK; 2548 } 2549 2550 static struct notifier_block trap_pm_notifier_block = { 2551 .notifier_call = trap_pm_notifier, 2552 }; 2553 2554 static int __init trap_pm_init(void) 2555 { 2556 return cpu_pm_register_notifier(&trap_pm_notifier_block); 2557 } 2558 arch_initcall(trap_pm_init); 2559