1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 13 */ 14 #include <linux/bug.h> 15 #include <linux/compiler.h> 16 #include <linux/kexec.h> 17 #include <linux/init.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/mm.h> 21 #include <linux/sched.h> 22 #include <linux/smp.h> 23 #include <linux/spinlock.h> 24 #include <linux/kallsyms.h> 25 #include <linux/bootmem.h> 26 #include <linux/interrupt.h> 27 #include <linux/ptrace.h> 28 #include <linux/kgdb.h> 29 #include <linux/kdebug.h> 30 #include <linux/kprobes.h> 31 #include <linux/notifier.h> 32 #include <linux/kdb.h> 33 #include <linux/irq.h> 34 #include <linux/perf_event.h> 35 36 #include <asm/bootinfo.h> 37 #include <asm/branch.h> 38 #include <asm/break.h> 39 #include <asm/cop2.h> 40 #include <asm/cpu.h> 41 #include <asm/dsp.h> 42 #include <asm/fpu.h> 43 #include <asm/fpu_emulator.h> 44 #include <asm/mipsregs.h> 45 #include <asm/mipsmtregs.h> 46 #include <asm/module.h> 47 #include <asm/pgtable.h> 48 #include <asm/ptrace.h> 49 #include <asm/sections.h> 50 #include <asm/tlbdebug.h> 51 #include <asm/traps.h> 52 #include <asm/uaccess.h> 53 #include <asm/watch.h> 54 #include <asm/mmu_context.h> 55 #include <asm/types.h> 56 #include <asm/stacktrace.h> 57 #include <asm/uasm.h> 58 59 extern void check_wait(void); 60 extern asmlinkage void r4k_wait(void); 61 extern asmlinkage void rollback_handle_int(void); 62 extern asmlinkage void handle_int(void); 63 extern asmlinkage void handle_tlbm(void); 64 extern asmlinkage void handle_tlbl(void); 65 extern asmlinkage void handle_tlbs(void); 66 extern asmlinkage void handle_adel(void); 67 extern asmlinkage void handle_ades(void); 68 extern asmlinkage void handle_ibe(void); 69 extern asmlinkage void handle_dbe(void); 70 extern asmlinkage void handle_sys(void); 71 extern asmlinkage void handle_bp(void); 72 extern asmlinkage void handle_ri(void); 73 extern asmlinkage void handle_ri_rdhwr_vivt(void); 74 extern asmlinkage void handle_ri_rdhwr(void); 75 extern asmlinkage void handle_cpu(void); 76 extern asmlinkage void handle_ov(void); 77 extern asmlinkage void handle_tr(void); 78 extern asmlinkage void handle_fpe(void); 79 extern asmlinkage void handle_mdmx(void); 80 extern asmlinkage void handle_watch(void); 81 extern asmlinkage void handle_mt(void); 82 extern asmlinkage void handle_dsp(void); 83 extern asmlinkage void handle_mcheck(void); 84 extern asmlinkage void handle_reserved(void); 85 86 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 87 struct mips_fpu_struct *ctx, int has_fpu, 88 void *__user *fault_addr); 89 90 void (*board_be_init)(void); 91 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 92 void (*board_nmi_handler_setup)(void); 93 void (*board_ejtag_handler_setup)(void); 94 void (*board_bind_eic_interrupt)(int irq, int regset); 95 void (*board_ebase_setup)(void); 96 void __cpuinitdata(*board_cache_error_setup)(void); 97 98 static void show_raw_backtrace(unsigned long reg29) 99 { 100 unsigned long *sp = (unsigned long *)(reg29 & ~3); 101 unsigned long addr; 102 103 printk("Call Trace:"); 104 #ifdef CONFIG_KALLSYMS 105 printk("\n"); 106 #endif 107 while (!kstack_end(sp)) { 108 unsigned long __user *p = 109 (unsigned long __user *)(unsigned long)sp++; 110 if (__get_user(addr, p)) { 111 printk(" (Bad stack address)"); 112 break; 113 } 114 if (__kernel_text_address(addr)) 115 print_ip_sym(addr); 116 } 117 printk("\n"); 118 } 119 120 #ifdef CONFIG_KALLSYMS 121 int raw_show_trace; 122 static int __init set_raw_show_trace(char *str) 123 { 124 raw_show_trace = 1; 125 return 1; 126 } 127 __setup("raw_show_trace", set_raw_show_trace); 128 #endif 129 130 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 131 { 132 unsigned long sp = regs->regs[29]; 133 unsigned long ra = regs->regs[31]; 134 unsigned long pc = regs->cp0_epc; 135 136 if (!task) 137 task = current; 138 139 if (raw_show_trace || !__kernel_text_address(pc)) { 140 show_raw_backtrace(sp); 141 return; 142 } 143 printk("Call Trace:\n"); 144 do { 145 print_ip_sym(pc); 146 pc = unwind_stack(task, &sp, pc, &ra); 147 } while (pc); 148 printk("\n"); 149 } 150 151 /* 152 * This routine abuses get_user()/put_user() to reference pointers 153 * with at least a bit of error checking ... 154 */ 155 static void show_stacktrace(struct task_struct *task, 156 const struct pt_regs *regs) 157 { 158 const int field = 2 * sizeof(unsigned long); 159 long stackdata; 160 int i; 161 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 162 163 printk("Stack :"); 164 i = 0; 165 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 166 if (i && ((i % (64 / field)) == 0)) 167 printk("\n "); 168 if (i > 39) { 169 printk(" ..."); 170 break; 171 } 172 173 if (__get_user(stackdata, sp++)) { 174 printk(" (Bad stack address)"); 175 break; 176 } 177 178 printk(" %0*lx", field, stackdata); 179 i++; 180 } 181 printk("\n"); 182 show_backtrace(task, regs); 183 } 184 185 void show_stack(struct task_struct *task, unsigned long *sp) 186 { 187 struct pt_regs regs; 188 if (sp) { 189 regs.regs[29] = (unsigned long)sp; 190 regs.regs[31] = 0; 191 regs.cp0_epc = 0; 192 } else { 193 if (task && task != current) { 194 regs.regs[29] = task->thread.reg29; 195 regs.regs[31] = 0; 196 regs.cp0_epc = task->thread.reg31; 197 #ifdef CONFIG_KGDB_KDB 198 } else if (atomic_read(&kgdb_active) != -1 && 199 kdb_current_regs) { 200 memcpy(®s, kdb_current_regs, sizeof(regs)); 201 #endif /* CONFIG_KGDB_KDB */ 202 } else { 203 prepare_frametrace(®s); 204 } 205 } 206 show_stacktrace(task, ®s); 207 } 208 209 /* 210 * The architecture-independent dump_stack generator 211 */ 212 void dump_stack(void) 213 { 214 struct pt_regs regs; 215 216 prepare_frametrace(®s); 217 show_backtrace(current, ®s); 218 } 219 220 EXPORT_SYMBOL(dump_stack); 221 222 static void show_code(unsigned int __user *pc) 223 { 224 long i; 225 unsigned short __user *pc16 = NULL; 226 227 printk("\nCode:"); 228 229 if ((unsigned long)pc & 1) 230 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 231 for(i = -3 ; i < 6 ; i++) { 232 unsigned int insn; 233 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 234 printk(" (Bad address in epc)\n"); 235 break; 236 } 237 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 238 } 239 } 240 241 static void __show_regs(const struct pt_regs *regs) 242 { 243 const int field = 2 * sizeof(unsigned long); 244 unsigned int cause = regs->cp0_cause; 245 int i; 246 247 printk("Cpu %d\n", smp_processor_id()); 248 249 /* 250 * Saved main processor registers 251 */ 252 for (i = 0; i < 32; ) { 253 if ((i % 4) == 0) 254 printk("$%2d :", i); 255 if (i == 0) 256 printk(" %0*lx", field, 0UL); 257 else if (i == 26 || i == 27) 258 printk(" %*s", field, ""); 259 else 260 printk(" %0*lx", field, regs->regs[i]); 261 262 i++; 263 if ((i % 4) == 0) 264 printk("\n"); 265 } 266 267 #ifdef CONFIG_CPU_HAS_SMARTMIPS 268 printk("Acx : %0*lx\n", field, regs->acx); 269 #endif 270 printk("Hi : %0*lx\n", field, regs->hi); 271 printk("Lo : %0*lx\n", field, regs->lo); 272 273 /* 274 * Saved cp0 registers 275 */ 276 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 277 (void *) regs->cp0_epc); 278 printk(" %s\n", print_tainted()); 279 printk("ra : %0*lx %pS\n", field, regs->regs[31], 280 (void *) regs->regs[31]); 281 282 printk("Status: %08x ", (uint32_t) regs->cp0_status); 283 284 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 285 if (regs->cp0_status & ST0_KUO) 286 printk("KUo "); 287 if (regs->cp0_status & ST0_IEO) 288 printk("IEo "); 289 if (regs->cp0_status & ST0_KUP) 290 printk("KUp "); 291 if (regs->cp0_status & ST0_IEP) 292 printk("IEp "); 293 if (regs->cp0_status & ST0_KUC) 294 printk("KUc "); 295 if (regs->cp0_status & ST0_IEC) 296 printk("IEc "); 297 } else { 298 if (regs->cp0_status & ST0_KX) 299 printk("KX "); 300 if (regs->cp0_status & ST0_SX) 301 printk("SX "); 302 if (regs->cp0_status & ST0_UX) 303 printk("UX "); 304 switch (regs->cp0_status & ST0_KSU) { 305 case KSU_USER: 306 printk("USER "); 307 break; 308 case KSU_SUPERVISOR: 309 printk("SUPERVISOR "); 310 break; 311 case KSU_KERNEL: 312 printk("KERNEL "); 313 break; 314 default: 315 printk("BAD_MODE "); 316 break; 317 } 318 if (regs->cp0_status & ST0_ERL) 319 printk("ERL "); 320 if (regs->cp0_status & ST0_EXL) 321 printk("EXL "); 322 if (regs->cp0_status & ST0_IE) 323 printk("IE "); 324 } 325 printk("\n"); 326 327 printk("Cause : %08x\n", cause); 328 329 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 330 if (1 <= cause && cause <= 5) 331 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 332 333 printk("PrId : %08x (%s)\n", read_c0_prid(), 334 cpu_name_string()); 335 } 336 337 /* 338 * FIXME: really the generic show_regs should take a const pointer argument. 339 */ 340 void show_regs(struct pt_regs *regs) 341 { 342 __show_regs((struct pt_regs *)regs); 343 } 344 345 void show_registers(struct pt_regs *regs) 346 { 347 const int field = 2 * sizeof(unsigned long); 348 349 __show_regs(regs); 350 print_modules(); 351 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 352 current->comm, current->pid, current_thread_info(), current, 353 field, current_thread_info()->tp_value); 354 if (cpu_has_userlocal) { 355 unsigned long tls; 356 357 tls = read_c0_userlocal(); 358 if (tls != current_thread_info()->tp_value) 359 printk("*HwTLS: %0*lx\n", field, tls); 360 } 361 362 show_stacktrace(current, regs); 363 show_code((unsigned int __user *) regs->cp0_epc); 364 printk("\n"); 365 } 366 367 static int regs_to_trapnr(struct pt_regs *regs) 368 { 369 return (regs->cp0_cause >> 2) & 0x1f; 370 } 371 372 static DEFINE_RAW_SPINLOCK(die_lock); 373 374 void __noreturn die(const char *str, struct pt_regs *regs) 375 { 376 static int die_counter; 377 int sig = SIGSEGV; 378 #ifdef CONFIG_MIPS_MT_SMTC 379 unsigned long dvpret; 380 #endif /* CONFIG_MIPS_MT_SMTC */ 381 382 oops_enter(); 383 384 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) 385 sig = 0; 386 387 console_verbose(); 388 raw_spin_lock_irq(&die_lock); 389 #ifdef CONFIG_MIPS_MT_SMTC 390 dvpret = dvpe(); 391 #endif /* CONFIG_MIPS_MT_SMTC */ 392 bust_spinlocks(1); 393 #ifdef CONFIG_MIPS_MT_SMTC 394 mips_mt_regdump(dvpret); 395 #endif /* CONFIG_MIPS_MT_SMTC */ 396 397 printk("%s[#%d]:\n", str, ++die_counter); 398 show_registers(regs); 399 add_taint(TAINT_DIE); 400 raw_spin_unlock_irq(&die_lock); 401 402 oops_exit(); 403 404 if (in_interrupt()) 405 panic("Fatal exception in interrupt"); 406 407 if (panic_on_oops) { 408 printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); 409 ssleep(5); 410 panic("Fatal exception"); 411 } 412 413 if (regs && kexec_should_crash(current)) 414 crash_kexec(regs); 415 416 do_exit(sig); 417 } 418 419 extern struct exception_table_entry __start___dbe_table[]; 420 extern struct exception_table_entry __stop___dbe_table[]; 421 422 __asm__( 423 " .section __dbe_table, \"a\"\n" 424 " .previous \n"); 425 426 /* Given an address, look for it in the exception tables. */ 427 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 428 { 429 const struct exception_table_entry *e; 430 431 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 432 if (!e) 433 e = search_module_dbetables(addr); 434 return e; 435 } 436 437 asmlinkage void do_be(struct pt_regs *regs) 438 { 439 const int field = 2 * sizeof(unsigned long); 440 const struct exception_table_entry *fixup = NULL; 441 int data = regs->cp0_cause & 4; 442 int action = MIPS_BE_FATAL; 443 444 /* XXX For now. Fixme, this searches the wrong table ... */ 445 if (data && !user_mode(regs)) 446 fixup = search_dbe_tables(exception_epc(regs)); 447 448 if (fixup) 449 action = MIPS_BE_FIXUP; 450 451 if (board_be_handler) 452 action = board_be_handler(regs, fixup != NULL); 453 454 switch (action) { 455 case MIPS_BE_DISCARD: 456 return; 457 case MIPS_BE_FIXUP: 458 if (fixup) { 459 regs->cp0_epc = fixup->nextinsn; 460 return; 461 } 462 break; 463 default: 464 break; 465 } 466 467 /* 468 * Assume it would be too dangerous to continue ... 469 */ 470 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 471 data ? "Data" : "Instruction", 472 field, regs->cp0_epc, field, regs->regs[31]); 473 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) 474 == NOTIFY_STOP) 475 return; 476 477 die_if_kernel("Oops", regs); 478 force_sig(SIGBUS, current); 479 } 480 481 /* 482 * ll/sc, rdhwr, sync emulation 483 */ 484 485 #define OPCODE 0xfc000000 486 #define BASE 0x03e00000 487 #define RT 0x001f0000 488 #define OFFSET 0x0000ffff 489 #define LL 0xc0000000 490 #define SC 0xe0000000 491 #define SPEC0 0x00000000 492 #define SPEC3 0x7c000000 493 #define RD 0x0000f800 494 #define FUNC 0x0000003f 495 #define SYNC 0x0000000f 496 #define RDHWR 0x0000003b 497 498 /* 499 * The ll_bit is cleared by r*_switch.S 500 */ 501 502 unsigned int ll_bit; 503 struct task_struct *ll_task; 504 505 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 506 { 507 unsigned long value, __user *vaddr; 508 long offset; 509 510 /* 511 * analyse the ll instruction that just caused a ri exception 512 * and put the referenced address to addr. 513 */ 514 515 /* sign extend offset */ 516 offset = opcode & OFFSET; 517 offset <<= 16; 518 offset >>= 16; 519 520 vaddr = (unsigned long __user *) 521 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 522 523 if ((unsigned long)vaddr & 3) 524 return SIGBUS; 525 if (get_user(value, vaddr)) 526 return SIGSEGV; 527 528 preempt_disable(); 529 530 if (ll_task == NULL || ll_task == current) { 531 ll_bit = 1; 532 } else { 533 ll_bit = 0; 534 } 535 ll_task = current; 536 537 preempt_enable(); 538 539 regs->regs[(opcode & RT) >> 16] = value; 540 541 return 0; 542 } 543 544 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 545 { 546 unsigned long __user *vaddr; 547 unsigned long reg; 548 long offset; 549 550 /* 551 * analyse the sc instruction that just caused a ri exception 552 * and put the referenced address to addr. 553 */ 554 555 /* sign extend offset */ 556 offset = opcode & OFFSET; 557 offset <<= 16; 558 offset >>= 16; 559 560 vaddr = (unsigned long __user *) 561 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 562 reg = (opcode & RT) >> 16; 563 564 if ((unsigned long)vaddr & 3) 565 return SIGBUS; 566 567 preempt_disable(); 568 569 if (ll_bit == 0 || ll_task != current) { 570 regs->regs[reg] = 0; 571 preempt_enable(); 572 return 0; 573 } 574 575 preempt_enable(); 576 577 if (put_user(regs->regs[reg], vaddr)) 578 return SIGSEGV; 579 580 regs->regs[reg] = 1; 581 582 return 0; 583 } 584 585 /* 586 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 587 * opcodes are supposed to result in coprocessor unusable exceptions if 588 * executed on ll/sc-less processors. That's the theory. In practice a 589 * few processors such as NEC's VR4100 throw reserved instruction exceptions 590 * instead, so we're doing the emulation thing in both exception handlers. 591 */ 592 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 593 { 594 if ((opcode & OPCODE) == LL) { 595 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 596 1, regs, 0); 597 return simulate_ll(regs, opcode); 598 } 599 if ((opcode & OPCODE) == SC) { 600 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 601 1, regs, 0); 602 return simulate_sc(regs, opcode); 603 } 604 605 return -1; /* Must be something else ... */ 606 } 607 608 /* 609 * Simulate trapping 'rdhwr' instructions to provide user accessible 610 * registers not implemented in hardware. 611 */ 612 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) 613 { 614 struct thread_info *ti = task_thread_info(current); 615 616 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 617 int rd = (opcode & RD) >> 11; 618 int rt = (opcode & RT) >> 16; 619 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 620 1, regs, 0); 621 switch (rd) { 622 case 0: /* CPU number */ 623 regs->regs[rt] = smp_processor_id(); 624 return 0; 625 case 1: /* SYNCI length */ 626 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 627 current_cpu_data.icache.linesz); 628 return 0; 629 case 2: /* Read count register */ 630 regs->regs[rt] = read_c0_count(); 631 return 0; 632 case 3: /* Count register resolution */ 633 switch (current_cpu_data.cputype) { 634 case CPU_20KC: 635 case CPU_25KF: 636 regs->regs[rt] = 1; 637 break; 638 default: 639 regs->regs[rt] = 2; 640 } 641 return 0; 642 case 29: 643 regs->regs[rt] = ti->tp_value; 644 return 0; 645 default: 646 return -1; 647 } 648 } 649 650 /* Not ours. */ 651 return -1; 652 } 653 654 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 655 { 656 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 657 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 658 1, regs, 0); 659 return 0; 660 } 661 662 return -1; /* Must be something else ... */ 663 } 664 665 asmlinkage void do_ov(struct pt_regs *regs) 666 { 667 siginfo_t info; 668 669 die_if_kernel("Integer overflow", regs); 670 671 info.si_code = FPE_INTOVF; 672 info.si_signo = SIGFPE; 673 info.si_errno = 0; 674 info.si_addr = (void __user *) regs->cp0_epc; 675 force_sig_info(SIGFPE, &info, current); 676 } 677 678 static int process_fpemu_return(int sig, void __user *fault_addr) 679 { 680 if (sig == SIGSEGV || sig == SIGBUS) { 681 struct siginfo si = {0}; 682 si.si_addr = fault_addr; 683 si.si_signo = sig; 684 if (sig == SIGSEGV) { 685 if (find_vma(current->mm, (unsigned long)fault_addr)) 686 si.si_code = SEGV_ACCERR; 687 else 688 si.si_code = SEGV_MAPERR; 689 } else { 690 si.si_code = BUS_ADRERR; 691 } 692 force_sig_info(sig, &si, current); 693 return 1; 694 } else if (sig) { 695 force_sig(sig, current); 696 return 1; 697 } else { 698 return 0; 699 } 700 } 701 702 /* 703 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 704 */ 705 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 706 { 707 siginfo_t info = {0}; 708 709 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) 710 == NOTIFY_STOP) 711 return; 712 die_if_kernel("FP exception in kernel code", regs); 713 714 if (fcr31 & FPU_CSR_UNI_X) { 715 int sig; 716 void __user *fault_addr = NULL; 717 718 /* 719 * Unimplemented operation exception. If we've got the full 720 * software emulator on-board, let's use it... 721 * 722 * Force FPU to dump state into task/thread context. We're 723 * moving a lot of data here for what is probably a single 724 * instruction, but the alternative is to pre-decode the FP 725 * register operands before invoking the emulator, which seems 726 * a bit extreme for what should be an infrequent event. 727 */ 728 /* Ensure 'resume' not overwrite saved fp context again. */ 729 lose_fpu(1); 730 731 /* Run the emulator */ 732 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 733 &fault_addr); 734 735 /* 736 * We can't allow the emulated instruction to leave any of 737 * the cause bit set in $fcr31. 738 */ 739 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 740 741 /* Restore the hardware register state */ 742 own_fpu(1); /* Using the FPU again. */ 743 744 /* If something went wrong, signal */ 745 process_fpemu_return(sig, fault_addr); 746 747 return; 748 } else if (fcr31 & FPU_CSR_INV_X) 749 info.si_code = FPE_FLTINV; 750 else if (fcr31 & FPU_CSR_DIV_X) 751 info.si_code = FPE_FLTDIV; 752 else if (fcr31 & FPU_CSR_OVF_X) 753 info.si_code = FPE_FLTOVF; 754 else if (fcr31 & FPU_CSR_UDF_X) 755 info.si_code = FPE_FLTUND; 756 else if (fcr31 & FPU_CSR_INE_X) 757 info.si_code = FPE_FLTRES; 758 else 759 info.si_code = __SI_FAULT; 760 info.si_signo = SIGFPE; 761 info.si_errno = 0; 762 info.si_addr = (void __user *) regs->cp0_epc; 763 force_sig_info(SIGFPE, &info, current); 764 } 765 766 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 767 const char *str) 768 { 769 siginfo_t info; 770 char b[40]; 771 772 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 773 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 774 return; 775 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 776 777 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 778 return; 779 780 /* 781 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 782 * insns, even for trap and break codes that indicate arithmetic 783 * failures. Weird ... 784 * But should we continue the brokenness??? --macro 785 */ 786 switch (code) { 787 case BRK_OVERFLOW: 788 case BRK_DIVZERO: 789 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 790 die_if_kernel(b, regs); 791 if (code == BRK_DIVZERO) 792 info.si_code = FPE_INTDIV; 793 else 794 info.si_code = FPE_INTOVF; 795 info.si_signo = SIGFPE; 796 info.si_errno = 0; 797 info.si_addr = (void __user *) regs->cp0_epc; 798 force_sig_info(SIGFPE, &info, current); 799 break; 800 case BRK_BUG: 801 die_if_kernel("Kernel bug detected", regs); 802 force_sig(SIGTRAP, current); 803 break; 804 case BRK_MEMU: 805 /* 806 * Address errors may be deliberately induced by the FPU 807 * emulator to retake control of the CPU after executing the 808 * instruction in the delay slot of an emulated branch. 809 * 810 * Terminate if exception was recognized as a delay slot return 811 * otherwise handle as normal. 812 */ 813 if (do_dsemulret(regs)) 814 return; 815 816 die_if_kernel("Math emu break/trap", regs); 817 force_sig(SIGTRAP, current); 818 break; 819 default: 820 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 821 die_if_kernel(b, regs); 822 force_sig(SIGTRAP, current); 823 } 824 } 825 826 asmlinkage void do_bp(struct pt_regs *regs) 827 { 828 unsigned int opcode, bcode; 829 830 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 831 goto out_sigsegv; 832 833 /* 834 * There is the ancient bug in the MIPS assemblers that the break 835 * code starts left to bit 16 instead to bit 6 in the opcode. 836 * Gas is bug-compatible, but not always, grrr... 837 * We handle both cases with a simple heuristics. --macro 838 */ 839 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 840 if (bcode >= (1 << 10)) 841 bcode >>= 10; 842 843 /* 844 * notify the kprobe handlers, if instruction is likely to 845 * pertain to them. 846 */ 847 switch (bcode) { 848 case BRK_KPROBE_BP: 849 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 850 return; 851 else 852 break; 853 case BRK_KPROBE_SSTEPBP: 854 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 855 return; 856 else 857 break; 858 default: 859 break; 860 } 861 862 do_trap_or_bp(regs, bcode, "Break"); 863 return; 864 865 out_sigsegv: 866 force_sig(SIGSEGV, current); 867 } 868 869 asmlinkage void do_tr(struct pt_regs *regs) 870 { 871 unsigned int opcode, tcode = 0; 872 873 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 874 goto out_sigsegv; 875 876 /* Immediate versions don't provide a code. */ 877 if (!(opcode & OPCODE)) 878 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 879 880 do_trap_or_bp(regs, tcode, "Trap"); 881 return; 882 883 out_sigsegv: 884 force_sig(SIGSEGV, current); 885 } 886 887 asmlinkage void do_ri(struct pt_regs *regs) 888 { 889 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 890 unsigned long old_epc = regs->cp0_epc; 891 unsigned int opcode = 0; 892 int status = -1; 893 894 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) 895 == NOTIFY_STOP) 896 return; 897 898 die_if_kernel("Reserved instruction in kernel code", regs); 899 900 if (unlikely(compute_return_epc(regs) < 0)) 901 return; 902 903 if (unlikely(get_user(opcode, epc) < 0)) 904 status = SIGSEGV; 905 906 if (!cpu_has_llsc && status < 0) 907 status = simulate_llsc(regs, opcode); 908 909 if (status < 0) 910 status = simulate_rdhwr(regs, opcode); 911 912 if (status < 0) 913 status = simulate_sync(regs, opcode); 914 915 if (status < 0) 916 status = SIGILL; 917 918 if (unlikely(status > 0)) { 919 regs->cp0_epc = old_epc; /* Undo skip-over. */ 920 force_sig(status, current); 921 } 922 } 923 924 /* 925 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 926 * emulated more than some threshold number of instructions, force migration to 927 * a "CPU" that has FP support. 928 */ 929 static void mt_ase_fp_affinity(void) 930 { 931 #ifdef CONFIG_MIPS_MT_FPAFF 932 if (mt_fpemul_threshold > 0 && 933 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 934 /* 935 * If there's no FPU present, or if the application has already 936 * restricted the allowed set to exclude any CPUs with FPUs, 937 * we'll skip the procedure. 938 */ 939 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 940 cpumask_t tmask; 941 942 current->thread.user_cpus_allowed 943 = current->cpus_allowed; 944 cpus_and(tmask, current->cpus_allowed, 945 mt_fpu_cpumask); 946 set_cpus_allowed_ptr(current, &tmask); 947 set_thread_flag(TIF_FPUBOUND); 948 } 949 } 950 #endif /* CONFIG_MIPS_MT_FPAFF */ 951 } 952 953 /* 954 * No lock; only written during early bootup by CPU 0. 955 */ 956 static RAW_NOTIFIER_HEAD(cu2_chain); 957 958 int __ref register_cu2_notifier(struct notifier_block *nb) 959 { 960 return raw_notifier_chain_register(&cu2_chain, nb); 961 } 962 963 int cu2_notifier_call_chain(unsigned long val, void *v) 964 { 965 return raw_notifier_call_chain(&cu2_chain, val, v); 966 } 967 968 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 969 void *data) 970 { 971 struct pt_regs *regs = data; 972 973 switch (action) { 974 default: 975 die_if_kernel("Unhandled kernel unaligned access or invalid " 976 "instruction", regs); 977 /* Fall through */ 978 979 case CU2_EXCEPTION: 980 force_sig(SIGILL, current); 981 } 982 983 return NOTIFY_OK; 984 } 985 986 asmlinkage void do_cpu(struct pt_regs *regs) 987 { 988 unsigned int __user *epc; 989 unsigned long old_epc; 990 unsigned int opcode; 991 unsigned int cpid; 992 int status; 993 unsigned long __maybe_unused flags; 994 995 die_if_kernel("do_cpu invoked from kernel context!", regs); 996 997 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 998 999 switch (cpid) { 1000 case 0: 1001 epc = (unsigned int __user *)exception_epc(regs); 1002 old_epc = regs->cp0_epc; 1003 opcode = 0; 1004 status = -1; 1005 1006 if (unlikely(compute_return_epc(regs) < 0)) 1007 return; 1008 1009 if (unlikely(get_user(opcode, epc) < 0)) 1010 status = SIGSEGV; 1011 1012 if (!cpu_has_llsc && status < 0) 1013 status = simulate_llsc(regs, opcode); 1014 1015 if (status < 0) 1016 status = simulate_rdhwr(regs, opcode); 1017 1018 if (status < 0) 1019 status = SIGILL; 1020 1021 if (unlikely(status > 0)) { 1022 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1023 force_sig(status, current); 1024 } 1025 1026 return; 1027 1028 case 3: 1029 /* 1030 * Old (MIPS I and MIPS II) processors will set this code 1031 * for COP1X opcode instructions that replaced the original 1032 * COP3 space. We don't limit COP1 space instructions in 1033 * the emulator according to the CPU ISA, so we want to 1034 * treat COP1X instructions consistently regardless of which 1035 * code the CPU chose. Therefore we redirect this trap to 1036 * the FP emulator too. 1037 * 1038 * Then some newer FPU-less processors use this code 1039 * erroneously too, so they are covered by this choice 1040 * as well. 1041 */ 1042 if (raw_cpu_has_fpu) 1043 break; 1044 /* Fall through. */ 1045 1046 case 1: 1047 if (used_math()) /* Using the FPU again. */ 1048 own_fpu(1); 1049 else { /* First time FPU user. */ 1050 init_fpu(); 1051 set_used_math(); 1052 } 1053 1054 if (!raw_cpu_has_fpu) { 1055 int sig; 1056 void __user *fault_addr = NULL; 1057 sig = fpu_emulator_cop1Handler(regs, 1058 ¤t->thread.fpu, 1059 0, &fault_addr); 1060 if (!process_fpemu_return(sig, fault_addr)) 1061 mt_ase_fp_affinity(); 1062 } 1063 1064 return; 1065 1066 case 2: 1067 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1068 return; 1069 } 1070 1071 force_sig(SIGILL, current); 1072 } 1073 1074 asmlinkage void do_mdmx(struct pt_regs *regs) 1075 { 1076 force_sig(SIGILL, current); 1077 } 1078 1079 /* 1080 * Called with interrupts disabled. 1081 */ 1082 asmlinkage void do_watch(struct pt_regs *regs) 1083 { 1084 u32 cause; 1085 1086 /* 1087 * Clear WP (bit 22) bit of cause register so we don't loop 1088 * forever. 1089 */ 1090 cause = read_c0_cause(); 1091 cause &= ~(1 << 22); 1092 write_c0_cause(cause); 1093 1094 /* 1095 * If the current thread has the watch registers loaded, save 1096 * their values and send SIGTRAP. Otherwise another thread 1097 * left the registers set, clear them and continue. 1098 */ 1099 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1100 mips_read_watch_registers(); 1101 local_irq_enable(); 1102 force_sig(SIGTRAP, current); 1103 } else { 1104 mips_clear_watch_registers(); 1105 local_irq_enable(); 1106 } 1107 } 1108 1109 asmlinkage void do_mcheck(struct pt_regs *regs) 1110 { 1111 const int field = 2 * sizeof(unsigned long); 1112 int multi_match = regs->cp0_status & ST0_TS; 1113 1114 show_regs(regs); 1115 1116 if (multi_match) { 1117 printk("Index : %0x\n", read_c0_index()); 1118 printk("Pagemask: %0x\n", read_c0_pagemask()); 1119 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 1120 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 1121 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 1122 printk("\n"); 1123 dump_tlb_all(); 1124 } 1125 1126 show_code((unsigned int __user *) regs->cp0_epc); 1127 1128 /* 1129 * Some chips may have other causes of machine check (e.g. SB1 1130 * graduation timer) 1131 */ 1132 panic("Caught Machine Check exception - %scaused by multiple " 1133 "matching entries in the TLB.", 1134 (multi_match) ? "" : "not "); 1135 } 1136 1137 asmlinkage void do_mt(struct pt_regs *regs) 1138 { 1139 int subcode; 1140 1141 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1142 >> VPECONTROL_EXCPT_SHIFT; 1143 switch (subcode) { 1144 case 0: 1145 printk(KERN_DEBUG "Thread Underflow\n"); 1146 break; 1147 case 1: 1148 printk(KERN_DEBUG "Thread Overflow\n"); 1149 break; 1150 case 2: 1151 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1152 break; 1153 case 3: 1154 printk(KERN_DEBUG "Gating Storage Exception\n"); 1155 break; 1156 case 4: 1157 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1158 break; 1159 case 5: 1160 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1161 break; 1162 default: 1163 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1164 subcode); 1165 break; 1166 } 1167 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1168 1169 force_sig(SIGILL, current); 1170 } 1171 1172 1173 asmlinkage void do_dsp(struct pt_regs *regs) 1174 { 1175 if (cpu_has_dsp) 1176 panic("Unexpected DSP exception"); 1177 1178 force_sig(SIGILL, current); 1179 } 1180 1181 asmlinkage void do_reserved(struct pt_regs *regs) 1182 { 1183 /* 1184 * Game over - no way to handle this if it ever occurs. Most probably 1185 * caused by a new unknown cpu type or after another deadly 1186 * hard/software error. 1187 */ 1188 show_regs(regs); 1189 panic("Caught reserved exception %ld - should not happen.", 1190 (regs->cp0_cause & 0x7f) >> 2); 1191 } 1192 1193 static int __initdata l1parity = 1; 1194 static int __init nol1parity(char *s) 1195 { 1196 l1parity = 0; 1197 return 1; 1198 } 1199 __setup("nol1par", nol1parity); 1200 static int __initdata l2parity = 1; 1201 static int __init nol2parity(char *s) 1202 { 1203 l2parity = 0; 1204 return 1; 1205 } 1206 __setup("nol2par", nol2parity); 1207 1208 /* 1209 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1210 * it different ways. 1211 */ 1212 static inline void parity_protection_init(void) 1213 { 1214 switch (current_cpu_type()) { 1215 case CPU_24K: 1216 case CPU_34K: 1217 case CPU_74K: 1218 case CPU_1004K: 1219 { 1220 #define ERRCTL_PE 0x80000000 1221 #define ERRCTL_L2P 0x00800000 1222 unsigned long errctl; 1223 unsigned int l1parity_present, l2parity_present; 1224 1225 errctl = read_c0_ecc(); 1226 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1227 1228 /* probe L1 parity support */ 1229 write_c0_ecc(errctl | ERRCTL_PE); 1230 back_to_back_c0_hazard(); 1231 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1232 1233 /* probe L2 parity support */ 1234 write_c0_ecc(errctl|ERRCTL_L2P); 1235 back_to_back_c0_hazard(); 1236 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1237 1238 if (l1parity_present && l2parity_present) { 1239 if (l1parity) 1240 errctl |= ERRCTL_PE; 1241 if (l1parity ^ l2parity) 1242 errctl |= ERRCTL_L2P; 1243 } else if (l1parity_present) { 1244 if (l1parity) 1245 errctl |= ERRCTL_PE; 1246 } else if (l2parity_present) { 1247 if (l2parity) 1248 errctl |= ERRCTL_L2P; 1249 } else { 1250 /* No parity available */ 1251 } 1252 1253 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1254 1255 write_c0_ecc(errctl); 1256 back_to_back_c0_hazard(); 1257 errctl = read_c0_ecc(); 1258 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1259 1260 if (l1parity_present) 1261 printk(KERN_INFO "Cache parity protection %sabled\n", 1262 (errctl & ERRCTL_PE) ? "en" : "dis"); 1263 1264 if (l2parity_present) { 1265 if (l1parity_present && l1parity) 1266 errctl ^= ERRCTL_L2P; 1267 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1268 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1269 } 1270 } 1271 break; 1272 1273 case CPU_5KC: 1274 case CPU_5KE: 1275 case CPU_LOONGSON1: 1276 write_c0_ecc(0x80000000); 1277 back_to_back_c0_hazard(); 1278 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1279 printk(KERN_INFO "Cache parity protection %sabled\n", 1280 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1281 break; 1282 case CPU_20KC: 1283 case CPU_25KF: 1284 /* Clear the DE bit (bit 16) in the c0_status register. */ 1285 printk(KERN_INFO "Enable cache parity protection for " 1286 "MIPS 20KC/25KF CPUs.\n"); 1287 clear_c0_status(ST0_DE); 1288 break; 1289 default: 1290 break; 1291 } 1292 } 1293 1294 asmlinkage void cache_parity_error(void) 1295 { 1296 const int field = 2 * sizeof(unsigned long); 1297 unsigned int reg_val; 1298 1299 /* For the moment, report the problem and hang. */ 1300 printk("Cache error exception:\n"); 1301 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1302 reg_val = read_c0_cacheerr(); 1303 printk("c0_cacheerr == %08x\n", reg_val); 1304 1305 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1306 reg_val & (1<<30) ? "secondary" : "primary", 1307 reg_val & (1<<31) ? "data" : "insn"); 1308 printk("Error bits: %s%s%s%s%s%s%s\n", 1309 reg_val & (1<<29) ? "ED " : "", 1310 reg_val & (1<<28) ? "ET " : "", 1311 reg_val & (1<<26) ? "EE " : "", 1312 reg_val & (1<<25) ? "EB " : "", 1313 reg_val & (1<<24) ? "EI " : "", 1314 reg_val & (1<<23) ? "E1 " : "", 1315 reg_val & (1<<22) ? "E0 " : ""); 1316 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1317 1318 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1319 if (reg_val & (1<<22)) 1320 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1321 1322 if (reg_val & (1<<23)) 1323 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1324 #endif 1325 1326 panic("Can't handle the cache error!"); 1327 } 1328 1329 /* 1330 * SDBBP EJTAG debug exception handler. 1331 * We skip the instruction and return to the next instruction. 1332 */ 1333 void ejtag_exception_handler(struct pt_regs *regs) 1334 { 1335 const int field = 2 * sizeof(unsigned long); 1336 unsigned long depc, old_epc; 1337 unsigned int debug; 1338 1339 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1340 depc = read_c0_depc(); 1341 debug = read_c0_debug(); 1342 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1343 if (debug & 0x80000000) { 1344 /* 1345 * In branch delay slot. 1346 * We cheat a little bit here and use EPC to calculate the 1347 * debug return address (DEPC). EPC is restored after the 1348 * calculation. 1349 */ 1350 old_epc = regs->cp0_epc; 1351 regs->cp0_epc = depc; 1352 __compute_return_epc(regs); 1353 depc = regs->cp0_epc; 1354 regs->cp0_epc = old_epc; 1355 } else 1356 depc += 4; 1357 write_c0_depc(depc); 1358 1359 #if 0 1360 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1361 write_c0_debug(debug | 0x100); 1362 #endif 1363 } 1364 1365 /* 1366 * NMI exception handler. 1367 * No lock; only written during early bootup by CPU 0. 1368 */ 1369 static RAW_NOTIFIER_HEAD(nmi_chain); 1370 1371 int register_nmi_notifier(struct notifier_block *nb) 1372 { 1373 return raw_notifier_chain_register(&nmi_chain, nb); 1374 } 1375 1376 void __noreturn nmi_exception_handler(struct pt_regs *regs) 1377 { 1378 raw_notifier_call_chain(&nmi_chain, 0, regs); 1379 bust_spinlocks(1); 1380 printk("NMI taken!!!!\n"); 1381 die("NMI", regs); 1382 } 1383 1384 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1385 1386 unsigned long ebase; 1387 unsigned long exception_handlers[32]; 1388 unsigned long vi_handlers[64]; 1389 1390 void __init *set_except_vector(int n, void *addr) 1391 { 1392 unsigned long handler = (unsigned long) addr; 1393 unsigned long old_handler = exception_handlers[n]; 1394 1395 exception_handlers[n] = handler; 1396 if (n == 0 && cpu_has_divec) { 1397 unsigned long jump_mask = ~((1 << 28) - 1); 1398 u32 *buf = (u32 *)(ebase + 0x200); 1399 unsigned int k0 = 26; 1400 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 1401 uasm_i_j(&buf, handler & ~jump_mask); 1402 uasm_i_nop(&buf); 1403 } else { 1404 UASM_i_LA(&buf, k0, handler); 1405 uasm_i_jr(&buf, k0); 1406 uasm_i_nop(&buf); 1407 } 1408 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 1409 } 1410 return (void *)old_handler; 1411 } 1412 1413 static asmlinkage void do_default_vi(void) 1414 { 1415 show_regs(get_irq_regs()); 1416 panic("Caught unexpected vectored interrupt."); 1417 } 1418 1419 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1420 { 1421 unsigned long handler; 1422 unsigned long old_handler = vi_handlers[n]; 1423 int srssets = current_cpu_data.srsets; 1424 u32 *w; 1425 unsigned char *b; 1426 1427 BUG_ON(!cpu_has_veic && !cpu_has_vint); 1428 1429 if (addr == NULL) { 1430 handler = (unsigned long) do_default_vi; 1431 srs = 0; 1432 } else 1433 handler = (unsigned long) addr; 1434 vi_handlers[n] = (unsigned long) addr; 1435 1436 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1437 1438 if (srs >= srssets) 1439 panic("Shadow register set %d not supported", srs); 1440 1441 if (cpu_has_veic) { 1442 if (board_bind_eic_interrupt) 1443 board_bind_eic_interrupt(n, srs); 1444 } else if (cpu_has_vint) { 1445 /* SRSMap is only defined if shadow sets are implemented */ 1446 if (srssets > 1) 1447 change_c0_srsmap(0xf << n*4, srs << n*4); 1448 } 1449 1450 if (srs == 0) { 1451 /* 1452 * If no shadow set is selected then use the default handler 1453 * that does normal register saving and a standard interrupt exit 1454 */ 1455 1456 extern char except_vec_vi, except_vec_vi_lui; 1457 extern char except_vec_vi_ori, except_vec_vi_end; 1458 extern char rollback_except_vec_vi; 1459 char *vec_start = (cpu_wait == r4k_wait) ? 1460 &rollback_except_vec_vi : &except_vec_vi; 1461 #ifdef CONFIG_MIPS_MT_SMTC 1462 /* 1463 * We need to provide the SMTC vectored interrupt handler 1464 * not only with the address of the handler, but with the 1465 * Status.IM bit to be masked before going there. 1466 */ 1467 extern char except_vec_vi_mori; 1468 const int mori_offset = &except_vec_vi_mori - vec_start; 1469 #endif /* CONFIG_MIPS_MT_SMTC */ 1470 const int handler_len = &except_vec_vi_end - vec_start; 1471 const int lui_offset = &except_vec_vi_lui - vec_start; 1472 const int ori_offset = &except_vec_vi_ori - vec_start; 1473 1474 if (handler_len > VECTORSPACING) { 1475 /* 1476 * Sigh... panicing won't help as the console 1477 * is probably not configured :( 1478 */ 1479 panic("VECTORSPACING too small"); 1480 } 1481 1482 memcpy(b, vec_start, handler_len); 1483 #ifdef CONFIG_MIPS_MT_SMTC 1484 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1485 1486 w = (u32 *)(b + mori_offset); 1487 *w = (*w & 0xffff0000) | (0x100 << n); 1488 #endif /* CONFIG_MIPS_MT_SMTC */ 1489 w = (u32 *)(b + lui_offset); 1490 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1491 w = (u32 *)(b + ori_offset); 1492 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1493 local_flush_icache_range((unsigned long)b, 1494 (unsigned long)(b+handler_len)); 1495 } 1496 else { 1497 /* 1498 * In other cases jump directly to the interrupt handler 1499 * 1500 * It is the handlers responsibility to save registers if required 1501 * (eg hi/lo) and return from the exception using "eret" 1502 */ 1503 w = (u32 *)b; 1504 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1505 *w = 0; 1506 local_flush_icache_range((unsigned long)b, 1507 (unsigned long)(b+8)); 1508 } 1509 1510 return (void *)old_handler; 1511 } 1512 1513 void *set_vi_handler(int n, vi_handler_t addr) 1514 { 1515 return set_vi_srs_handler(n, addr, 0); 1516 } 1517 1518 extern void tlb_init(void); 1519 extern void flush_tlb_handlers(void); 1520 1521 /* 1522 * Timer interrupt 1523 */ 1524 int cp0_compare_irq; 1525 EXPORT_SYMBOL_GPL(cp0_compare_irq); 1526 int cp0_compare_irq_shift; 1527 1528 /* 1529 * Performance counter IRQ or -1 if shared with timer 1530 */ 1531 int cp0_perfcount_irq; 1532 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1533 1534 static int __cpuinitdata noulri; 1535 1536 static int __init ulri_disable(char *s) 1537 { 1538 pr_info("Disabling ulri\n"); 1539 noulri = 1; 1540 1541 return 1; 1542 } 1543 __setup("noulri", ulri_disable); 1544 1545 void __cpuinit per_cpu_trap_init(bool is_boot_cpu) 1546 { 1547 unsigned int cpu = smp_processor_id(); 1548 unsigned int status_set = ST0_CU0; 1549 unsigned int hwrena = cpu_hwrena_impl_bits; 1550 #ifdef CONFIG_MIPS_MT_SMTC 1551 int secondaryTC = 0; 1552 int bootTC = (cpu == 0); 1553 1554 /* 1555 * Only do per_cpu_trap_init() for first TC of Each VPE. 1556 * Note that this hack assumes that the SMTC init code 1557 * assigns TCs consecutively and in ascending order. 1558 */ 1559 1560 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1561 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1562 secondaryTC = 1; 1563 #endif /* CONFIG_MIPS_MT_SMTC */ 1564 1565 /* 1566 * Disable coprocessors and select 32-bit or 64-bit addressing 1567 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1568 * flag that some firmware may have left set and the TS bit (for 1569 * IP27). Set XX for ISA IV code to work. 1570 */ 1571 #ifdef CONFIG_64BIT 1572 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1573 #endif 1574 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1575 status_set |= ST0_XX; 1576 if (cpu_has_dsp) 1577 status_set |= ST0_MX; 1578 1579 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1580 status_set); 1581 1582 if (cpu_has_mips_r2) 1583 hwrena |= 0x0000000f; 1584 1585 if (!noulri && cpu_has_userlocal) 1586 hwrena |= (1 << 29); 1587 1588 if (hwrena) 1589 write_c0_hwrena(hwrena); 1590 1591 #ifdef CONFIG_MIPS_MT_SMTC 1592 if (!secondaryTC) { 1593 #endif /* CONFIG_MIPS_MT_SMTC */ 1594 1595 if (cpu_has_veic || cpu_has_vint) { 1596 unsigned long sr = set_c0_status(ST0_BEV); 1597 write_c0_ebase(ebase); 1598 write_c0_status(sr); 1599 /* Setting vector spacing enables EI/VI mode */ 1600 change_c0_intctl(0x3e0, VECTORSPACING); 1601 } 1602 if (cpu_has_divec) { 1603 if (cpu_has_mipsmt) { 1604 unsigned int vpflags = dvpe(); 1605 set_c0_cause(CAUSEF_IV); 1606 evpe(vpflags); 1607 } else 1608 set_c0_cause(CAUSEF_IV); 1609 } 1610 1611 /* 1612 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1613 * 1614 * o read IntCtl.IPTI to determine the timer interrupt 1615 * o read IntCtl.IPPCI to determine the performance counter interrupt 1616 */ 1617 if (cpu_has_mips_r2) { 1618 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 1619 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 1620 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 1621 if (cp0_perfcount_irq == cp0_compare_irq) 1622 cp0_perfcount_irq = -1; 1623 } else { 1624 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1625 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 1626 cp0_perfcount_irq = -1; 1627 } 1628 1629 #ifdef CONFIG_MIPS_MT_SMTC 1630 } 1631 #endif /* CONFIG_MIPS_MT_SMTC */ 1632 1633 if (!cpu_data[cpu].asid_cache) 1634 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1635 1636 atomic_inc(&init_mm.mm_count); 1637 current->active_mm = &init_mm; 1638 BUG_ON(current->mm); 1639 enter_lazy_tlb(&init_mm, current); 1640 1641 #ifdef CONFIG_MIPS_MT_SMTC 1642 if (bootTC) { 1643 #endif /* CONFIG_MIPS_MT_SMTC */ 1644 /* Boot CPU's cache setup in setup_arch(). */ 1645 if (!is_boot_cpu) 1646 cpu_cache_init(); 1647 tlb_init(); 1648 #ifdef CONFIG_MIPS_MT_SMTC 1649 } else if (!secondaryTC) { 1650 /* 1651 * First TC in non-boot VPE must do subset of tlb_init() 1652 * for MMU countrol registers. 1653 */ 1654 write_c0_pagemask(PM_DEFAULT_MASK); 1655 write_c0_wired(0); 1656 } 1657 #endif /* CONFIG_MIPS_MT_SMTC */ 1658 TLBMISS_HANDLER_SETUP(); 1659 } 1660 1661 /* Install CPU exception handler */ 1662 void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size) 1663 { 1664 memcpy((void *)(ebase + offset), addr, size); 1665 local_flush_icache_range(ebase + offset, ebase + offset + size); 1666 } 1667 1668 static char panic_null_cerr[] __cpuinitdata = 1669 "Trying to set NULL cache error exception handler"; 1670 1671 /* 1672 * Install uncached CPU exception handler. 1673 * This is suitable only for the cache error exception which is the only 1674 * exception handler that is being run uncached. 1675 */ 1676 void __cpuinit set_uncached_handler(unsigned long offset, void *addr, 1677 unsigned long size) 1678 { 1679 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 1680 1681 if (!addr) 1682 panic(panic_null_cerr); 1683 1684 memcpy((void *)(uncached_ebase + offset), addr, size); 1685 } 1686 1687 static int __initdata rdhwr_noopt; 1688 static int __init set_rdhwr_noopt(char *str) 1689 { 1690 rdhwr_noopt = 1; 1691 return 1; 1692 } 1693 1694 __setup("rdhwr_noopt", set_rdhwr_noopt); 1695 1696 void __init trap_init(void) 1697 { 1698 extern char except_vec3_generic, except_vec3_r4000; 1699 extern char except_vec4; 1700 unsigned long i; 1701 int rollback; 1702 1703 check_wait(); 1704 rollback = (cpu_wait == r4k_wait); 1705 1706 #if defined(CONFIG_KGDB) 1707 if (kgdb_early_setup) 1708 return; /* Already done */ 1709 #endif 1710 1711 if (cpu_has_veic || cpu_has_vint) { 1712 unsigned long size = 0x200 + VECTORSPACING*64; 1713 ebase = (unsigned long) 1714 __alloc_bootmem(size, 1 << fls(size), 0); 1715 } else { 1716 ebase = CKSEG0; 1717 if (cpu_has_mips_r2) 1718 ebase += (read_c0_ebase() & 0x3ffff000); 1719 } 1720 1721 if (board_ebase_setup) 1722 board_ebase_setup(); 1723 per_cpu_trap_init(true); 1724 1725 /* 1726 * Copy the generic exception handlers to their final destination. 1727 * This will be overriden later as suitable for a particular 1728 * configuration. 1729 */ 1730 set_handler(0x180, &except_vec3_generic, 0x80); 1731 1732 /* 1733 * Setup default vectors 1734 */ 1735 for (i = 0; i <= 31; i++) 1736 set_except_vector(i, handle_reserved); 1737 1738 /* 1739 * Copy the EJTAG debug exception vector handler code to it's final 1740 * destination. 1741 */ 1742 if (cpu_has_ejtag && board_ejtag_handler_setup) 1743 board_ejtag_handler_setup(); 1744 1745 /* 1746 * Only some CPUs have the watch exceptions. 1747 */ 1748 if (cpu_has_watch) 1749 set_except_vector(23, handle_watch); 1750 1751 /* 1752 * Initialise interrupt handlers 1753 */ 1754 if (cpu_has_veic || cpu_has_vint) { 1755 int nvec = cpu_has_veic ? 64 : 8; 1756 for (i = 0; i < nvec; i++) 1757 set_vi_handler(i, NULL); 1758 } 1759 else if (cpu_has_divec) 1760 set_handler(0x200, &except_vec4, 0x8); 1761 1762 /* 1763 * Some CPUs can enable/disable for cache parity detection, but does 1764 * it different ways. 1765 */ 1766 parity_protection_init(); 1767 1768 /* 1769 * The Data Bus Errors / Instruction Bus Errors are signaled 1770 * by external hardware. Therefore these two exceptions 1771 * may have board specific handlers. 1772 */ 1773 if (board_be_init) 1774 board_be_init(); 1775 1776 set_except_vector(0, rollback ? rollback_handle_int : handle_int); 1777 set_except_vector(1, handle_tlbm); 1778 set_except_vector(2, handle_tlbl); 1779 set_except_vector(3, handle_tlbs); 1780 1781 set_except_vector(4, handle_adel); 1782 set_except_vector(5, handle_ades); 1783 1784 set_except_vector(6, handle_ibe); 1785 set_except_vector(7, handle_dbe); 1786 1787 set_except_vector(8, handle_sys); 1788 set_except_vector(9, handle_bp); 1789 set_except_vector(10, rdhwr_noopt ? handle_ri : 1790 (cpu_has_vtag_icache ? 1791 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1792 set_except_vector(11, handle_cpu); 1793 set_except_vector(12, handle_ov); 1794 set_except_vector(13, handle_tr); 1795 1796 if (current_cpu_type() == CPU_R6000 || 1797 current_cpu_type() == CPU_R6000A) { 1798 /* 1799 * The R6000 is the only R-series CPU that features a machine 1800 * check exception (similar to the R4000 cache error) and 1801 * unaligned ldc1/sdc1 exception. The handlers have not been 1802 * written yet. Well, anyway there is no R6000 machine on the 1803 * current list of targets for Linux/MIPS. 1804 * (Duh, crap, there is someone with a triple R6k machine) 1805 */ 1806 //set_except_vector(14, handle_mc); 1807 //set_except_vector(15, handle_ndc); 1808 } 1809 1810 1811 if (board_nmi_handler_setup) 1812 board_nmi_handler_setup(); 1813 1814 if (cpu_has_fpu && !cpu_has_nofpuex) 1815 set_except_vector(15, handle_fpe); 1816 1817 set_except_vector(22, handle_mdmx); 1818 1819 if (cpu_has_mcheck) 1820 set_except_vector(24, handle_mcheck); 1821 1822 if (cpu_has_mipsmt) 1823 set_except_vector(25, handle_mt); 1824 1825 set_except_vector(26, handle_dsp); 1826 1827 if (board_cache_error_setup) 1828 board_cache_error_setup(); 1829 1830 if (cpu_has_vce) 1831 /* Special exception: R4[04]00 uses also the divec space. */ 1832 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); 1833 else if (cpu_has_4kex) 1834 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); 1835 else 1836 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); 1837 1838 local_flush_icache_range(ebase, ebase + 0x400); 1839 flush_tlb_handlers(); 1840 1841 sort_extable(__start___dbe_table, __stop___dbe_table); 1842 1843 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 1844 } 1845