1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki 13 */ 14 #include <linux/bug.h> 15 #include <linux/init.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/sched.h> 19 #include <linux/smp.h> 20 #include <linux/spinlock.h> 21 #include <linux/kallsyms.h> 22 #include <linux/bootmem.h> 23 #include <linux/interrupt.h> 24 25 #include <asm/bootinfo.h> 26 #include <asm/branch.h> 27 #include <asm/break.h> 28 #include <asm/cpu.h> 29 #include <asm/dsp.h> 30 #include <asm/fpu.h> 31 #include <asm/mipsregs.h> 32 #include <asm/mipsmtregs.h> 33 #include <asm/module.h> 34 #include <asm/pgtable.h> 35 #include <asm/ptrace.h> 36 #include <asm/sections.h> 37 #include <asm/system.h> 38 #include <asm/tlbdebug.h> 39 #include <asm/traps.h> 40 #include <asm/uaccess.h> 41 #include <asm/mmu_context.h> 42 #include <asm/types.h> 43 #include <asm/stacktrace.h> 44 45 extern asmlinkage void handle_int(void); 46 extern asmlinkage void handle_tlbm(void); 47 extern asmlinkage void handle_tlbl(void); 48 extern asmlinkage void handle_tlbs(void); 49 extern asmlinkage void handle_adel(void); 50 extern asmlinkage void handle_ades(void); 51 extern asmlinkage void handle_ibe(void); 52 extern asmlinkage void handle_dbe(void); 53 extern asmlinkage void handle_sys(void); 54 extern asmlinkage void handle_bp(void); 55 extern asmlinkage void handle_ri(void); 56 extern asmlinkage void handle_ri_rdhwr_vivt(void); 57 extern asmlinkage void handle_ri_rdhwr(void); 58 extern asmlinkage void handle_cpu(void); 59 extern asmlinkage void handle_ov(void); 60 extern asmlinkage void handle_tr(void); 61 extern asmlinkage void handle_fpe(void); 62 extern asmlinkage void handle_mdmx(void); 63 extern asmlinkage void handle_watch(void); 64 extern asmlinkage void handle_mt(void); 65 extern asmlinkage void handle_dsp(void); 66 extern asmlinkage void handle_mcheck(void); 67 extern asmlinkage void handle_reserved(void); 68 69 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 70 struct mips_fpu_struct *ctx, int has_fpu); 71 72 void (*board_watchpoint_handler)(struct pt_regs *regs); 73 void (*board_be_init)(void); 74 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 75 void (*board_nmi_handler_setup)(void); 76 void (*board_ejtag_handler_setup)(void); 77 void (*board_bind_eic_interrupt)(int irq, int regset); 78 79 80 static void show_raw_backtrace(unsigned long reg29) 81 { 82 unsigned long *sp = (unsigned long *)reg29; 83 unsigned long addr; 84 85 printk("Call Trace:"); 86 #ifdef CONFIG_KALLSYMS 87 printk("\n"); 88 #endif 89 while (!kstack_end(sp)) { 90 addr = *sp++; 91 if (__kernel_text_address(addr)) 92 print_ip_sym(addr); 93 } 94 printk("\n"); 95 } 96 97 #ifdef CONFIG_KALLSYMS 98 int raw_show_trace; 99 static int __init set_raw_show_trace(char *str) 100 { 101 raw_show_trace = 1; 102 return 1; 103 } 104 __setup("raw_show_trace", set_raw_show_trace); 105 #endif 106 107 static void show_backtrace(struct task_struct *task, struct pt_regs *regs) 108 { 109 unsigned long sp = regs->regs[29]; 110 unsigned long ra = regs->regs[31]; 111 unsigned long pc = regs->cp0_epc; 112 113 if (raw_show_trace || !__kernel_text_address(pc)) { 114 show_raw_backtrace(sp); 115 return; 116 } 117 printk("Call Trace:\n"); 118 do { 119 print_ip_sym(pc); 120 pc = unwind_stack(task, &sp, pc, &ra); 121 } while (pc); 122 printk("\n"); 123 } 124 125 /* 126 * This routine abuses get_user()/put_user() to reference pointers 127 * with at least a bit of error checking ... 128 */ 129 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs) 130 { 131 const int field = 2 * sizeof(unsigned long); 132 long stackdata; 133 int i; 134 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 135 136 printk("Stack :"); 137 i = 0; 138 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 139 if (i && ((i % (64 / field)) == 0)) 140 printk("\n "); 141 if (i > 39) { 142 printk(" ..."); 143 break; 144 } 145 146 if (__get_user(stackdata, sp++)) { 147 printk(" (Bad stack address)"); 148 break; 149 } 150 151 printk(" %0*lx", field, stackdata); 152 i++; 153 } 154 printk("\n"); 155 show_backtrace(task, regs); 156 } 157 158 void show_stack(struct task_struct *task, unsigned long *sp) 159 { 160 struct pt_regs regs; 161 if (sp) { 162 regs.regs[29] = (unsigned long)sp; 163 regs.regs[31] = 0; 164 regs.cp0_epc = 0; 165 } else { 166 if (task && task != current) { 167 regs.regs[29] = task->thread.reg29; 168 regs.regs[31] = 0; 169 regs.cp0_epc = task->thread.reg31; 170 } else { 171 prepare_frametrace(®s); 172 } 173 } 174 show_stacktrace(task, ®s); 175 } 176 177 /* 178 * The architecture-independent dump_stack generator 179 */ 180 void dump_stack(void) 181 { 182 struct pt_regs regs; 183 184 prepare_frametrace(®s); 185 show_backtrace(current, ®s); 186 } 187 188 EXPORT_SYMBOL(dump_stack); 189 190 static void show_code(unsigned int __user *pc) 191 { 192 long i; 193 194 printk("\nCode:"); 195 196 for(i = -3 ; i < 6 ; i++) { 197 unsigned int insn; 198 if (__get_user(insn, pc + i)) { 199 printk(" (Bad address in epc)\n"); 200 break; 201 } 202 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 203 } 204 } 205 206 void show_regs(struct pt_regs *regs) 207 { 208 const int field = 2 * sizeof(unsigned long); 209 unsigned int cause = regs->cp0_cause; 210 int i; 211 212 printk("Cpu %d\n", smp_processor_id()); 213 214 /* 215 * Saved main processor registers 216 */ 217 for (i = 0; i < 32; ) { 218 if ((i % 4) == 0) 219 printk("$%2d :", i); 220 if (i == 0) 221 printk(" %0*lx", field, 0UL); 222 else if (i == 26 || i == 27) 223 printk(" %*s", field, ""); 224 else 225 printk(" %0*lx", field, regs->regs[i]); 226 227 i++; 228 if ((i % 4) == 0) 229 printk("\n"); 230 } 231 232 #ifdef CONFIG_CPU_HAS_SMARTMIPS 233 printk("Acx : %0*lx\n", field, regs->acx); 234 #endif 235 printk("Hi : %0*lx\n", field, regs->hi); 236 printk("Lo : %0*lx\n", field, regs->lo); 237 238 /* 239 * Saved cp0 registers 240 */ 241 printk("epc : %0*lx ", field, regs->cp0_epc); 242 print_symbol("%s ", regs->cp0_epc); 243 printk(" %s\n", print_tainted()); 244 printk("ra : %0*lx ", field, regs->regs[31]); 245 print_symbol("%s\n", regs->regs[31]); 246 247 printk("Status: %08x ", (uint32_t) regs->cp0_status); 248 249 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 250 if (regs->cp0_status & ST0_KUO) 251 printk("KUo "); 252 if (regs->cp0_status & ST0_IEO) 253 printk("IEo "); 254 if (regs->cp0_status & ST0_KUP) 255 printk("KUp "); 256 if (regs->cp0_status & ST0_IEP) 257 printk("IEp "); 258 if (regs->cp0_status & ST0_KUC) 259 printk("KUc "); 260 if (regs->cp0_status & ST0_IEC) 261 printk("IEc "); 262 } else { 263 if (regs->cp0_status & ST0_KX) 264 printk("KX "); 265 if (regs->cp0_status & ST0_SX) 266 printk("SX "); 267 if (regs->cp0_status & ST0_UX) 268 printk("UX "); 269 switch (regs->cp0_status & ST0_KSU) { 270 case KSU_USER: 271 printk("USER "); 272 break; 273 case KSU_SUPERVISOR: 274 printk("SUPERVISOR "); 275 break; 276 case KSU_KERNEL: 277 printk("KERNEL "); 278 break; 279 default: 280 printk("BAD_MODE "); 281 break; 282 } 283 if (regs->cp0_status & ST0_ERL) 284 printk("ERL "); 285 if (regs->cp0_status & ST0_EXL) 286 printk("EXL "); 287 if (regs->cp0_status & ST0_IE) 288 printk("IE "); 289 } 290 printk("\n"); 291 292 printk("Cause : %08x\n", cause); 293 294 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 295 if (1 <= cause && cause <= 5) 296 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 297 298 printk("PrId : %08x\n", read_c0_prid()); 299 } 300 301 void show_registers(struct pt_regs *regs) 302 { 303 show_regs(regs); 304 print_modules(); 305 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 306 current->comm, current->pid, current_thread_info(), current); 307 show_stacktrace(current, regs); 308 show_code((unsigned int __user *) regs->cp0_epc); 309 printk("\n"); 310 } 311 312 static DEFINE_SPINLOCK(die_lock); 313 314 void __noreturn die(const char * str, struct pt_regs * regs) 315 { 316 static int die_counter; 317 #ifdef CONFIG_MIPS_MT_SMTC 318 unsigned long dvpret = dvpe(); 319 #endif /* CONFIG_MIPS_MT_SMTC */ 320 321 console_verbose(); 322 spin_lock_irq(&die_lock); 323 bust_spinlocks(1); 324 #ifdef CONFIG_MIPS_MT_SMTC 325 mips_mt_regdump(dvpret); 326 #endif /* CONFIG_MIPS_MT_SMTC */ 327 printk("%s[#%d]:\n", str, ++die_counter); 328 show_registers(regs); 329 add_taint(TAINT_DIE); 330 spin_unlock_irq(&die_lock); 331 332 if (in_interrupt()) 333 panic("Fatal exception in interrupt"); 334 335 if (panic_on_oops) { 336 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 337 ssleep(5); 338 panic("Fatal exception"); 339 } 340 341 do_exit(SIGSEGV); 342 } 343 344 extern const struct exception_table_entry __start___dbe_table[]; 345 extern const struct exception_table_entry __stop___dbe_table[]; 346 347 __asm__( 348 " .section __dbe_table, \"a\"\n" 349 " .previous \n"); 350 351 /* Given an address, look for it in the exception tables. */ 352 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 353 { 354 const struct exception_table_entry *e; 355 356 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 357 if (!e) 358 e = search_module_dbetables(addr); 359 return e; 360 } 361 362 asmlinkage void do_be(struct pt_regs *regs) 363 { 364 const int field = 2 * sizeof(unsigned long); 365 const struct exception_table_entry *fixup = NULL; 366 int data = regs->cp0_cause & 4; 367 int action = MIPS_BE_FATAL; 368 369 /* XXX For now. Fixme, this searches the wrong table ... */ 370 if (data && !user_mode(regs)) 371 fixup = search_dbe_tables(exception_epc(regs)); 372 373 if (fixup) 374 action = MIPS_BE_FIXUP; 375 376 if (board_be_handler) 377 action = board_be_handler(regs, fixup != NULL); 378 379 switch (action) { 380 case MIPS_BE_DISCARD: 381 return; 382 case MIPS_BE_FIXUP: 383 if (fixup) { 384 regs->cp0_epc = fixup->nextinsn; 385 return; 386 } 387 break; 388 default: 389 break; 390 } 391 392 /* 393 * Assume it would be too dangerous to continue ... 394 */ 395 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 396 data ? "Data" : "Instruction", 397 field, regs->cp0_epc, field, regs->regs[31]); 398 die_if_kernel("Oops", regs); 399 force_sig(SIGBUS, current); 400 } 401 402 /* 403 * ll/sc emulation 404 */ 405 406 #define OPCODE 0xfc000000 407 #define BASE 0x03e00000 408 #define RT 0x001f0000 409 #define OFFSET 0x0000ffff 410 #define LL 0xc0000000 411 #define SC 0xe0000000 412 #define SPEC3 0x7c000000 413 #define RD 0x0000f800 414 #define FUNC 0x0000003f 415 #define RDHWR 0x0000003b 416 417 /* 418 * The ll_bit is cleared by r*_switch.S 419 */ 420 421 unsigned long ll_bit; 422 423 static struct task_struct *ll_task = NULL; 424 425 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) 426 { 427 unsigned long value, __user *vaddr; 428 long offset; 429 int signal = 0; 430 431 /* 432 * analyse the ll instruction that just caused a ri exception 433 * and put the referenced address to addr. 434 */ 435 436 /* sign extend offset */ 437 offset = opcode & OFFSET; 438 offset <<= 16; 439 offset >>= 16; 440 441 vaddr = (unsigned long __user *) 442 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 443 444 if ((unsigned long)vaddr & 3) { 445 signal = SIGBUS; 446 goto sig; 447 } 448 if (get_user(value, vaddr)) { 449 signal = SIGSEGV; 450 goto sig; 451 } 452 453 preempt_disable(); 454 455 if (ll_task == NULL || ll_task == current) { 456 ll_bit = 1; 457 } else { 458 ll_bit = 0; 459 } 460 ll_task = current; 461 462 preempt_enable(); 463 464 compute_return_epc(regs); 465 466 regs->regs[(opcode & RT) >> 16] = value; 467 468 return; 469 470 sig: 471 force_sig(signal, current); 472 } 473 474 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) 475 { 476 unsigned long __user *vaddr; 477 unsigned long reg; 478 long offset; 479 int signal = 0; 480 481 /* 482 * analyse the sc instruction that just caused a ri exception 483 * and put the referenced address to addr. 484 */ 485 486 /* sign extend offset */ 487 offset = opcode & OFFSET; 488 offset <<= 16; 489 offset >>= 16; 490 491 vaddr = (unsigned long __user *) 492 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 493 reg = (opcode & RT) >> 16; 494 495 if ((unsigned long)vaddr & 3) { 496 signal = SIGBUS; 497 goto sig; 498 } 499 500 preempt_disable(); 501 502 if (ll_bit == 0 || ll_task != current) { 503 compute_return_epc(regs); 504 regs->regs[reg] = 0; 505 preempt_enable(); 506 return; 507 } 508 509 preempt_enable(); 510 511 if (put_user(regs->regs[reg], vaddr)) { 512 signal = SIGSEGV; 513 goto sig; 514 } 515 516 compute_return_epc(regs); 517 regs->regs[reg] = 1; 518 519 return; 520 521 sig: 522 force_sig(signal, current); 523 } 524 525 /* 526 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 527 * opcodes are supposed to result in coprocessor unusable exceptions if 528 * executed on ll/sc-less processors. That's the theory. In practice a 529 * few processors such as NEC's VR4100 throw reserved instruction exceptions 530 * instead, so we're doing the emulation thing in both exception handlers. 531 */ 532 static inline int simulate_llsc(struct pt_regs *regs) 533 { 534 unsigned int opcode; 535 536 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 537 goto out_sigsegv; 538 539 if ((opcode & OPCODE) == LL) { 540 simulate_ll(regs, opcode); 541 return 0; 542 } 543 if ((opcode & OPCODE) == SC) { 544 simulate_sc(regs, opcode); 545 return 0; 546 } 547 548 return -EFAULT; /* Strange things going on ... */ 549 550 out_sigsegv: 551 force_sig(SIGSEGV, current); 552 return -EFAULT; 553 } 554 555 /* 556 * Simulate trapping 'rdhwr' instructions to provide user accessible 557 * registers not implemented in hardware. The only current use of this 558 * is the thread area pointer. 559 */ 560 static inline int simulate_rdhwr(struct pt_regs *regs) 561 { 562 struct thread_info *ti = task_thread_info(current); 563 unsigned int opcode; 564 565 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 566 goto out_sigsegv; 567 568 if (unlikely(compute_return_epc(regs))) 569 return -EFAULT; 570 571 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 572 int rd = (opcode & RD) >> 11; 573 int rt = (opcode & RT) >> 16; 574 switch (rd) { 575 case 29: 576 regs->regs[rt] = ti->tp_value; 577 return 0; 578 default: 579 return -EFAULT; 580 } 581 } 582 583 /* Not ours. */ 584 return -EFAULT; 585 586 out_sigsegv: 587 force_sig(SIGSEGV, current); 588 return -EFAULT; 589 } 590 591 asmlinkage void do_ov(struct pt_regs *regs) 592 { 593 siginfo_t info; 594 595 die_if_kernel("Integer overflow", regs); 596 597 info.si_code = FPE_INTOVF; 598 info.si_signo = SIGFPE; 599 info.si_errno = 0; 600 info.si_addr = (void __user *) regs->cp0_epc; 601 force_sig_info(SIGFPE, &info, current); 602 } 603 604 /* 605 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 606 */ 607 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 608 { 609 die_if_kernel("FP exception in kernel code", regs); 610 611 if (fcr31 & FPU_CSR_UNI_X) { 612 int sig; 613 614 /* 615 * Unimplemented operation exception. If we've got the full 616 * software emulator on-board, let's use it... 617 * 618 * Force FPU to dump state into task/thread context. We're 619 * moving a lot of data here for what is probably a single 620 * instruction, but the alternative is to pre-decode the FP 621 * register operands before invoking the emulator, which seems 622 * a bit extreme for what should be an infrequent event. 623 */ 624 /* Ensure 'resume' not overwrite saved fp context again. */ 625 lose_fpu(1); 626 627 /* Run the emulator */ 628 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1); 629 630 /* 631 * We can't allow the emulated instruction to leave any of 632 * the cause bit set in $fcr31. 633 */ 634 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 635 636 /* Restore the hardware register state */ 637 own_fpu(1); /* Using the FPU again. */ 638 639 /* If something went wrong, signal */ 640 if (sig) 641 force_sig(sig, current); 642 643 return; 644 } 645 646 force_sig(SIGFPE, current); 647 } 648 649 asmlinkage void do_bp(struct pt_regs *regs) 650 { 651 unsigned int opcode, bcode; 652 siginfo_t info; 653 654 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 655 goto out_sigsegv; 656 657 /* 658 * There is the ancient bug in the MIPS assemblers that the break 659 * code starts left to bit 16 instead to bit 6 in the opcode. 660 * Gas is bug-compatible, but not always, grrr... 661 * We handle both cases with a simple heuristics. --macro 662 */ 663 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 664 if (bcode < (1 << 10)) 665 bcode <<= 10; 666 667 /* 668 * (A short test says that IRIX 5.3 sends SIGTRAP for all break 669 * insns, even for break codes that indicate arithmetic failures. 670 * Weird ...) 671 * But should we continue the brokenness??? --macro 672 */ 673 switch (bcode) { 674 case BRK_OVERFLOW << 10: 675 case BRK_DIVZERO << 10: 676 die_if_kernel("Break instruction in kernel code", regs); 677 if (bcode == (BRK_DIVZERO << 10)) 678 info.si_code = FPE_INTDIV; 679 else 680 info.si_code = FPE_INTOVF; 681 info.si_signo = SIGFPE; 682 info.si_errno = 0; 683 info.si_addr = (void __user *) regs->cp0_epc; 684 force_sig_info(SIGFPE, &info, current); 685 break; 686 case BRK_BUG: 687 die("Kernel bug detected", regs); 688 break; 689 default: 690 die_if_kernel("Break instruction in kernel code", regs); 691 force_sig(SIGTRAP, current); 692 } 693 return; 694 695 out_sigsegv: 696 force_sig(SIGSEGV, current); 697 } 698 699 asmlinkage void do_tr(struct pt_regs *regs) 700 { 701 unsigned int opcode, tcode = 0; 702 siginfo_t info; 703 704 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 705 goto out_sigsegv; 706 707 /* Immediate versions don't provide a code. */ 708 if (!(opcode & OPCODE)) 709 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 710 711 /* 712 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap 713 * insns, even for trap codes that indicate arithmetic failures. 714 * Weird ...) 715 * But should we continue the brokenness??? --macro 716 */ 717 switch (tcode) { 718 case BRK_OVERFLOW: 719 case BRK_DIVZERO: 720 die_if_kernel("Trap instruction in kernel code", regs); 721 if (tcode == BRK_DIVZERO) 722 info.si_code = FPE_INTDIV; 723 else 724 info.si_code = FPE_INTOVF; 725 info.si_signo = SIGFPE; 726 info.si_errno = 0; 727 info.si_addr = (void __user *) regs->cp0_epc; 728 force_sig_info(SIGFPE, &info, current); 729 break; 730 case BRK_BUG: 731 die("Kernel bug detected", regs); 732 break; 733 default: 734 die_if_kernel("Trap instruction in kernel code", regs); 735 force_sig(SIGTRAP, current); 736 } 737 return; 738 739 out_sigsegv: 740 force_sig(SIGSEGV, current); 741 } 742 743 asmlinkage void do_ri(struct pt_regs *regs) 744 { 745 die_if_kernel("Reserved instruction in kernel code", regs); 746 747 if (!cpu_has_llsc) 748 if (!simulate_llsc(regs)) 749 return; 750 751 if (!simulate_rdhwr(regs)) 752 return; 753 754 force_sig(SIGILL, current); 755 } 756 757 /* 758 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 759 * emulated more than some threshold number of instructions, force migration to 760 * a "CPU" that has FP support. 761 */ 762 static void mt_ase_fp_affinity(void) 763 { 764 #ifdef CONFIG_MIPS_MT_FPAFF 765 if (mt_fpemul_threshold > 0 && 766 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 767 /* 768 * If there's no FPU present, or if the application has already 769 * restricted the allowed set to exclude any CPUs with FPUs, 770 * we'll skip the procedure. 771 */ 772 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 773 cpumask_t tmask; 774 775 cpus_and(tmask, current->thread.user_cpus_allowed, 776 mt_fpu_cpumask); 777 set_cpus_allowed(current, tmask); 778 current->thread.mflags |= MF_FPUBOUND; 779 } 780 } 781 #endif /* CONFIG_MIPS_MT_FPAFF */ 782 } 783 784 asmlinkage void do_cpu(struct pt_regs *regs) 785 { 786 unsigned int cpid; 787 788 die_if_kernel("do_cpu invoked from kernel context!", regs); 789 790 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 791 792 switch (cpid) { 793 case 0: 794 if (!cpu_has_llsc) 795 if (!simulate_llsc(regs)) 796 return; 797 798 if (!simulate_rdhwr(regs)) 799 return; 800 801 break; 802 803 case 1: 804 if (used_math()) /* Using the FPU again. */ 805 own_fpu(1); 806 else { /* First time FPU user. */ 807 init_fpu(); 808 set_used_math(); 809 } 810 811 if (!raw_cpu_has_fpu) { 812 int sig; 813 sig = fpu_emulator_cop1Handler(regs, 814 ¤t->thread.fpu, 0); 815 if (sig) 816 force_sig(sig, current); 817 else 818 mt_ase_fp_affinity(); 819 } 820 821 return; 822 823 case 2: 824 case 3: 825 break; 826 } 827 828 force_sig(SIGILL, current); 829 } 830 831 asmlinkage void do_mdmx(struct pt_regs *regs) 832 { 833 force_sig(SIGILL, current); 834 } 835 836 asmlinkage void do_watch(struct pt_regs *regs) 837 { 838 if (board_watchpoint_handler) { 839 (*board_watchpoint_handler)(regs); 840 return; 841 } 842 843 /* 844 * We use the watch exception where available to detect stack 845 * overflows. 846 */ 847 dump_tlb_all(); 848 show_regs(regs); 849 panic("Caught WATCH exception - probably caused by stack overflow."); 850 } 851 852 asmlinkage void do_mcheck(struct pt_regs *regs) 853 { 854 const int field = 2 * sizeof(unsigned long); 855 int multi_match = regs->cp0_status & ST0_TS; 856 857 show_regs(regs); 858 859 if (multi_match) { 860 printk("Index : %0x\n", read_c0_index()); 861 printk("Pagemask: %0x\n", read_c0_pagemask()); 862 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 863 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 864 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 865 printk("\n"); 866 dump_tlb_all(); 867 } 868 869 show_code((unsigned int __user *) regs->cp0_epc); 870 871 /* 872 * Some chips may have other causes of machine check (e.g. SB1 873 * graduation timer) 874 */ 875 panic("Caught Machine Check exception - %scaused by multiple " 876 "matching entries in the TLB.", 877 (multi_match) ? "" : "not "); 878 } 879 880 asmlinkage void do_mt(struct pt_regs *regs) 881 { 882 int subcode; 883 884 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 885 >> VPECONTROL_EXCPT_SHIFT; 886 switch (subcode) { 887 case 0: 888 printk(KERN_DEBUG "Thread Underflow\n"); 889 break; 890 case 1: 891 printk(KERN_DEBUG "Thread Overflow\n"); 892 break; 893 case 2: 894 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 895 break; 896 case 3: 897 printk(KERN_DEBUG "Gating Storage Exception\n"); 898 break; 899 case 4: 900 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 901 break; 902 case 5: 903 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 904 break; 905 default: 906 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 907 subcode); 908 break; 909 } 910 die_if_kernel("MIPS MT Thread exception in kernel", regs); 911 912 force_sig(SIGILL, current); 913 } 914 915 916 asmlinkage void do_dsp(struct pt_regs *regs) 917 { 918 if (cpu_has_dsp) 919 panic("Unexpected DSP exception\n"); 920 921 force_sig(SIGILL, current); 922 } 923 924 asmlinkage void do_reserved(struct pt_regs *regs) 925 { 926 /* 927 * Game over - no way to handle this if it ever occurs. Most probably 928 * caused by a new unknown cpu type or after another deadly 929 * hard/software error. 930 */ 931 show_regs(regs); 932 panic("Caught reserved exception %ld - should not happen.", 933 (regs->cp0_cause & 0x7f) >> 2); 934 } 935 936 /* 937 * Some MIPS CPUs can enable/disable for cache parity detection, but do 938 * it different ways. 939 */ 940 static inline void parity_protection_init(void) 941 { 942 switch (current_cpu_data.cputype) { 943 case CPU_24K: 944 case CPU_34K: 945 case CPU_5KC: 946 write_c0_ecc(0x80000000); 947 back_to_back_c0_hazard(); 948 /* Set the PE bit (bit 31) in the c0_errctl register. */ 949 printk(KERN_INFO "Cache parity protection %sabled\n", 950 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 951 break; 952 case CPU_20KC: 953 case CPU_25KF: 954 /* Clear the DE bit (bit 16) in the c0_status register. */ 955 printk(KERN_INFO "Enable cache parity protection for " 956 "MIPS 20KC/25KF CPUs.\n"); 957 clear_c0_status(ST0_DE); 958 break; 959 default: 960 break; 961 } 962 } 963 964 asmlinkage void cache_parity_error(void) 965 { 966 const int field = 2 * sizeof(unsigned long); 967 unsigned int reg_val; 968 969 /* For the moment, report the problem and hang. */ 970 printk("Cache error exception:\n"); 971 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 972 reg_val = read_c0_cacheerr(); 973 printk("c0_cacheerr == %08x\n", reg_val); 974 975 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 976 reg_val & (1<<30) ? "secondary" : "primary", 977 reg_val & (1<<31) ? "data" : "insn"); 978 printk("Error bits: %s%s%s%s%s%s%s\n", 979 reg_val & (1<<29) ? "ED " : "", 980 reg_val & (1<<28) ? "ET " : "", 981 reg_val & (1<<26) ? "EE " : "", 982 reg_val & (1<<25) ? "EB " : "", 983 reg_val & (1<<24) ? "EI " : "", 984 reg_val & (1<<23) ? "E1 " : "", 985 reg_val & (1<<22) ? "E0 " : ""); 986 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 987 988 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 989 if (reg_val & (1<<22)) 990 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 991 992 if (reg_val & (1<<23)) 993 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 994 #endif 995 996 panic("Can't handle the cache error!"); 997 } 998 999 /* 1000 * SDBBP EJTAG debug exception handler. 1001 * We skip the instruction and return to the next instruction. 1002 */ 1003 void ejtag_exception_handler(struct pt_regs *regs) 1004 { 1005 const int field = 2 * sizeof(unsigned long); 1006 unsigned long depc, old_epc; 1007 unsigned int debug; 1008 1009 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1010 depc = read_c0_depc(); 1011 debug = read_c0_debug(); 1012 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1013 if (debug & 0x80000000) { 1014 /* 1015 * In branch delay slot. 1016 * We cheat a little bit here and use EPC to calculate the 1017 * debug return address (DEPC). EPC is restored after the 1018 * calculation. 1019 */ 1020 old_epc = regs->cp0_epc; 1021 regs->cp0_epc = depc; 1022 __compute_return_epc(regs); 1023 depc = regs->cp0_epc; 1024 regs->cp0_epc = old_epc; 1025 } else 1026 depc += 4; 1027 write_c0_depc(depc); 1028 1029 #if 0 1030 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1031 write_c0_debug(debug | 0x100); 1032 #endif 1033 } 1034 1035 /* 1036 * NMI exception handler. 1037 */ 1038 void nmi_exception_handler(struct pt_regs *regs) 1039 { 1040 #ifdef CONFIG_MIPS_MT_SMTC 1041 unsigned long dvpret = dvpe(); 1042 bust_spinlocks(1); 1043 printk("NMI taken!!!!\n"); 1044 mips_mt_regdump(dvpret); 1045 #else 1046 bust_spinlocks(1); 1047 printk("NMI taken!!!!\n"); 1048 #endif /* CONFIG_MIPS_MT_SMTC */ 1049 die("NMI", regs); 1050 while(1) ; 1051 } 1052 1053 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1054 1055 unsigned long ebase; 1056 unsigned long exception_handlers[32]; 1057 unsigned long vi_handlers[64]; 1058 1059 /* 1060 * As a side effect of the way this is implemented we're limited 1061 * to interrupt handlers in the address range from 1062 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... 1063 */ 1064 void *set_except_vector(int n, void *addr) 1065 { 1066 unsigned long handler = (unsigned long) addr; 1067 unsigned long old_handler = exception_handlers[n]; 1068 1069 exception_handlers[n] = handler; 1070 if (n == 0 && cpu_has_divec) { 1071 *(volatile u32 *)(ebase + 0x200) = 0x08000000 | 1072 (0x03ffffff & (handler >> 2)); 1073 flush_icache_range(ebase + 0x200, ebase + 0x204); 1074 } 1075 return (void *)old_handler; 1076 } 1077 1078 #ifdef CONFIG_CPU_MIPSR2_SRS 1079 /* 1080 * MIPSR2 shadow register set allocation 1081 * FIXME: SMP... 1082 */ 1083 1084 static struct shadow_registers { 1085 /* 1086 * Number of shadow register sets supported 1087 */ 1088 unsigned long sr_supported; 1089 /* 1090 * Bitmap of allocated shadow registers 1091 */ 1092 unsigned long sr_allocated; 1093 } shadow_registers; 1094 1095 static void mips_srs_init(void) 1096 { 1097 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1098 printk(KERN_INFO "%ld MIPSR2 register sets available\n", 1099 shadow_registers.sr_supported); 1100 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ 1101 } 1102 1103 int mips_srs_max(void) 1104 { 1105 return shadow_registers.sr_supported; 1106 } 1107 1108 int mips_srs_alloc(void) 1109 { 1110 struct shadow_registers *sr = &shadow_registers; 1111 int set; 1112 1113 again: 1114 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported); 1115 if (set >= sr->sr_supported) 1116 return -1; 1117 1118 if (test_and_set_bit(set, &sr->sr_allocated)) 1119 goto again; 1120 1121 return set; 1122 } 1123 1124 void mips_srs_free(int set) 1125 { 1126 struct shadow_registers *sr = &shadow_registers; 1127 1128 clear_bit(set, &sr->sr_allocated); 1129 } 1130 1131 static asmlinkage void do_default_vi(void) 1132 { 1133 show_regs(get_irq_regs()); 1134 panic("Caught unexpected vectored interrupt."); 1135 } 1136 1137 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1138 { 1139 unsigned long handler; 1140 unsigned long old_handler = vi_handlers[n]; 1141 u32 *w; 1142 unsigned char *b; 1143 1144 if (!cpu_has_veic && !cpu_has_vint) 1145 BUG(); 1146 1147 if (addr == NULL) { 1148 handler = (unsigned long) do_default_vi; 1149 srs = 0; 1150 } else 1151 handler = (unsigned long) addr; 1152 vi_handlers[n] = (unsigned long) addr; 1153 1154 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1155 1156 if (srs >= mips_srs_max()) 1157 panic("Shadow register set %d not supported", srs); 1158 1159 if (cpu_has_veic) { 1160 if (board_bind_eic_interrupt) 1161 board_bind_eic_interrupt (n, srs); 1162 } else if (cpu_has_vint) { 1163 /* SRSMap is only defined if shadow sets are implemented */ 1164 if (mips_srs_max() > 1) 1165 change_c0_srsmap (0xf << n*4, srs << n*4); 1166 } 1167 1168 if (srs == 0) { 1169 /* 1170 * If no shadow set is selected then use the default handler 1171 * that does normal register saving and a standard interrupt exit 1172 */ 1173 1174 extern char except_vec_vi, except_vec_vi_lui; 1175 extern char except_vec_vi_ori, except_vec_vi_end; 1176 #ifdef CONFIG_MIPS_MT_SMTC 1177 /* 1178 * We need to provide the SMTC vectored interrupt handler 1179 * not only with the address of the handler, but with the 1180 * Status.IM bit to be masked before going there. 1181 */ 1182 extern char except_vec_vi_mori; 1183 const int mori_offset = &except_vec_vi_mori - &except_vec_vi; 1184 #endif /* CONFIG_MIPS_MT_SMTC */ 1185 const int handler_len = &except_vec_vi_end - &except_vec_vi; 1186 const int lui_offset = &except_vec_vi_lui - &except_vec_vi; 1187 const int ori_offset = &except_vec_vi_ori - &except_vec_vi; 1188 1189 if (handler_len > VECTORSPACING) { 1190 /* 1191 * Sigh... panicing won't help as the console 1192 * is probably not configured :( 1193 */ 1194 panic ("VECTORSPACING too small"); 1195 } 1196 1197 memcpy (b, &except_vec_vi, handler_len); 1198 #ifdef CONFIG_MIPS_MT_SMTC 1199 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1200 1201 w = (u32 *)(b + mori_offset); 1202 *w = (*w & 0xffff0000) | (0x100 << n); 1203 #endif /* CONFIG_MIPS_MT_SMTC */ 1204 w = (u32 *)(b + lui_offset); 1205 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1206 w = (u32 *)(b + ori_offset); 1207 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1208 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); 1209 } 1210 else { 1211 /* 1212 * In other cases jump directly to the interrupt handler 1213 * 1214 * It is the handlers responsibility to save registers if required 1215 * (eg hi/lo) and return from the exception using "eret" 1216 */ 1217 w = (u32 *)b; 1218 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1219 *w = 0; 1220 flush_icache_range((unsigned long)b, (unsigned long)(b+8)); 1221 } 1222 1223 return (void *)old_handler; 1224 } 1225 1226 void *set_vi_handler(int n, vi_handler_t addr) 1227 { 1228 return set_vi_srs_handler(n, addr, 0); 1229 } 1230 1231 #else 1232 1233 static inline void mips_srs_init(void) 1234 { 1235 } 1236 1237 #endif /* CONFIG_CPU_MIPSR2_SRS */ 1238 1239 /* 1240 * This is used by native signal handling 1241 */ 1242 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); 1243 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); 1244 1245 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); 1246 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); 1247 1248 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); 1249 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); 1250 1251 #ifdef CONFIG_SMP 1252 static int smp_save_fp_context(struct sigcontext __user *sc) 1253 { 1254 return raw_cpu_has_fpu 1255 ? _save_fp_context(sc) 1256 : fpu_emulator_save_context(sc); 1257 } 1258 1259 static int smp_restore_fp_context(struct sigcontext __user *sc) 1260 { 1261 return raw_cpu_has_fpu 1262 ? _restore_fp_context(sc) 1263 : fpu_emulator_restore_context(sc); 1264 } 1265 #endif 1266 1267 static inline void signal_init(void) 1268 { 1269 #ifdef CONFIG_SMP 1270 /* For now just do the cpu_has_fpu check when the functions are invoked */ 1271 save_fp_context = smp_save_fp_context; 1272 restore_fp_context = smp_restore_fp_context; 1273 #else 1274 if (cpu_has_fpu) { 1275 save_fp_context = _save_fp_context; 1276 restore_fp_context = _restore_fp_context; 1277 } else { 1278 save_fp_context = fpu_emulator_save_context; 1279 restore_fp_context = fpu_emulator_restore_context; 1280 } 1281 #endif 1282 } 1283 1284 #ifdef CONFIG_MIPS32_COMPAT 1285 1286 /* 1287 * This is used by 32-bit signal stuff on the 64-bit kernel 1288 */ 1289 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); 1290 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); 1291 1292 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); 1293 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); 1294 1295 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); 1296 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); 1297 1298 static inline void signal32_init(void) 1299 { 1300 if (cpu_has_fpu) { 1301 save_fp_context32 = _save_fp_context32; 1302 restore_fp_context32 = _restore_fp_context32; 1303 } else { 1304 save_fp_context32 = fpu_emulator_save_context32; 1305 restore_fp_context32 = fpu_emulator_restore_context32; 1306 } 1307 } 1308 #endif 1309 1310 extern void cpu_cache_init(void); 1311 extern void tlb_init(void); 1312 extern void flush_tlb_handlers(void); 1313 1314 void __init per_cpu_trap_init(void) 1315 { 1316 unsigned int cpu = smp_processor_id(); 1317 unsigned int status_set = ST0_CU0; 1318 #ifdef CONFIG_MIPS_MT_SMTC 1319 int secondaryTC = 0; 1320 int bootTC = (cpu == 0); 1321 1322 /* 1323 * Only do per_cpu_trap_init() for first TC of Each VPE. 1324 * Note that this hack assumes that the SMTC init code 1325 * assigns TCs consecutively and in ascending order. 1326 */ 1327 1328 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1329 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1330 secondaryTC = 1; 1331 #endif /* CONFIG_MIPS_MT_SMTC */ 1332 1333 /* 1334 * Disable coprocessors and select 32-bit or 64-bit addressing 1335 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1336 * flag that some firmware may have left set and the TS bit (for 1337 * IP27). Set XX for ISA IV code to work. 1338 */ 1339 #ifdef CONFIG_64BIT 1340 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1341 #endif 1342 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1343 status_set |= ST0_XX; 1344 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1345 status_set); 1346 1347 if (cpu_has_dsp) 1348 set_c0_status(ST0_MX); 1349 1350 #ifdef CONFIG_CPU_MIPSR2 1351 if (cpu_has_mips_r2) { 1352 unsigned int enable = 0x0000000f; 1353 1354 if (cpu_has_userlocal) 1355 enable |= (1 << 29); 1356 1357 write_c0_hwrena(enable); 1358 } 1359 #endif 1360 1361 #ifdef CONFIG_MIPS_MT_SMTC 1362 if (!secondaryTC) { 1363 #endif /* CONFIG_MIPS_MT_SMTC */ 1364 1365 if (cpu_has_veic || cpu_has_vint) { 1366 write_c0_ebase (ebase); 1367 /* Setting vector spacing enables EI/VI mode */ 1368 change_c0_intctl (0x3e0, VECTORSPACING); 1369 } 1370 if (cpu_has_divec) { 1371 if (cpu_has_mipsmt) { 1372 unsigned int vpflags = dvpe(); 1373 set_c0_cause(CAUSEF_IV); 1374 evpe(vpflags); 1375 } else 1376 set_c0_cause(CAUSEF_IV); 1377 } 1378 1379 /* 1380 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1381 * 1382 * o read IntCtl.IPTI to determine the timer interrupt 1383 * o read IntCtl.IPPCI to determine the performance counter interrupt 1384 */ 1385 if (cpu_has_mips_r2) { 1386 cp0_compare_irq = (read_c0_intctl () >> 29) & 7; 1387 cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7; 1388 if (cp0_perfcount_irq == cp0_compare_irq) 1389 cp0_perfcount_irq = -1; 1390 } else { 1391 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1392 cp0_perfcount_irq = -1; 1393 } 1394 1395 #ifdef CONFIG_MIPS_MT_SMTC 1396 } 1397 #endif /* CONFIG_MIPS_MT_SMTC */ 1398 1399 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1400 TLBMISS_HANDLER_SETUP(); 1401 1402 atomic_inc(&init_mm.mm_count); 1403 current->active_mm = &init_mm; 1404 BUG_ON(current->mm); 1405 enter_lazy_tlb(&init_mm, current); 1406 1407 #ifdef CONFIG_MIPS_MT_SMTC 1408 if (bootTC) { 1409 #endif /* CONFIG_MIPS_MT_SMTC */ 1410 cpu_cache_init(); 1411 tlb_init(); 1412 #ifdef CONFIG_MIPS_MT_SMTC 1413 } else if (!secondaryTC) { 1414 /* 1415 * First TC in non-boot VPE must do subset of tlb_init() 1416 * for MMU countrol registers. 1417 */ 1418 write_c0_pagemask(PM_DEFAULT_MASK); 1419 write_c0_wired(0); 1420 } 1421 #endif /* CONFIG_MIPS_MT_SMTC */ 1422 } 1423 1424 /* Install CPU exception handler */ 1425 void __init set_handler (unsigned long offset, void *addr, unsigned long size) 1426 { 1427 memcpy((void *)(ebase + offset), addr, size); 1428 flush_icache_range(ebase + offset, ebase + offset + size); 1429 } 1430 1431 /* Install uncached CPU exception handler */ 1432 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) 1433 { 1434 #ifdef CONFIG_32BIT 1435 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1436 #endif 1437 #ifdef CONFIG_64BIT 1438 unsigned long uncached_ebase = TO_UNCAC(ebase); 1439 #endif 1440 1441 memcpy((void *)(uncached_ebase + offset), addr, size); 1442 } 1443 1444 static int __initdata rdhwr_noopt; 1445 static int __init set_rdhwr_noopt(char *str) 1446 { 1447 rdhwr_noopt = 1; 1448 return 1; 1449 } 1450 1451 __setup("rdhwr_noopt", set_rdhwr_noopt); 1452 1453 void __init trap_init(void) 1454 { 1455 extern char except_vec3_generic, except_vec3_r4000; 1456 extern char except_vec4; 1457 unsigned long i; 1458 1459 if (cpu_has_veic || cpu_has_vint) 1460 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); 1461 else 1462 ebase = CAC_BASE; 1463 1464 mips_srs_init(); 1465 1466 per_cpu_trap_init(); 1467 1468 /* 1469 * Copy the generic exception handlers to their final destination. 1470 * This will be overriden later as suitable for a particular 1471 * configuration. 1472 */ 1473 set_handler(0x180, &except_vec3_generic, 0x80); 1474 1475 /* 1476 * Setup default vectors 1477 */ 1478 for (i = 0; i <= 31; i++) 1479 set_except_vector(i, handle_reserved); 1480 1481 /* 1482 * Copy the EJTAG debug exception vector handler code to it's final 1483 * destination. 1484 */ 1485 if (cpu_has_ejtag && board_ejtag_handler_setup) 1486 board_ejtag_handler_setup (); 1487 1488 /* 1489 * Only some CPUs have the watch exceptions. 1490 */ 1491 if (cpu_has_watch) 1492 set_except_vector(23, handle_watch); 1493 1494 /* 1495 * Initialise interrupt handlers 1496 */ 1497 if (cpu_has_veic || cpu_has_vint) { 1498 int nvec = cpu_has_veic ? 64 : 8; 1499 for (i = 0; i < nvec; i++) 1500 set_vi_handler(i, NULL); 1501 } 1502 else if (cpu_has_divec) 1503 set_handler(0x200, &except_vec4, 0x8); 1504 1505 /* 1506 * Some CPUs can enable/disable for cache parity detection, but does 1507 * it different ways. 1508 */ 1509 parity_protection_init(); 1510 1511 /* 1512 * The Data Bus Errors / Instruction Bus Errors are signaled 1513 * by external hardware. Therefore these two exceptions 1514 * may have board specific handlers. 1515 */ 1516 if (board_be_init) 1517 board_be_init(); 1518 1519 set_except_vector(0, handle_int); 1520 set_except_vector(1, handle_tlbm); 1521 set_except_vector(2, handle_tlbl); 1522 set_except_vector(3, handle_tlbs); 1523 1524 set_except_vector(4, handle_adel); 1525 set_except_vector(5, handle_ades); 1526 1527 set_except_vector(6, handle_ibe); 1528 set_except_vector(7, handle_dbe); 1529 1530 set_except_vector(8, handle_sys); 1531 set_except_vector(9, handle_bp); 1532 set_except_vector(10, rdhwr_noopt ? handle_ri : 1533 (cpu_has_vtag_icache ? 1534 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1535 set_except_vector(11, handle_cpu); 1536 set_except_vector(12, handle_ov); 1537 set_except_vector(13, handle_tr); 1538 1539 if (current_cpu_data.cputype == CPU_R6000 || 1540 current_cpu_data.cputype == CPU_R6000A) { 1541 /* 1542 * The R6000 is the only R-series CPU that features a machine 1543 * check exception (similar to the R4000 cache error) and 1544 * unaligned ldc1/sdc1 exception. The handlers have not been 1545 * written yet. Well, anyway there is no R6000 machine on the 1546 * current list of targets for Linux/MIPS. 1547 * (Duh, crap, there is someone with a triple R6k machine) 1548 */ 1549 //set_except_vector(14, handle_mc); 1550 //set_except_vector(15, handle_ndc); 1551 } 1552 1553 1554 if (board_nmi_handler_setup) 1555 board_nmi_handler_setup(); 1556 1557 if (cpu_has_fpu && !cpu_has_nofpuex) 1558 set_except_vector(15, handle_fpe); 1559 1560 set_except_vector(22, handle_mdmx); 1561 1562 if (cpu_has_mcheck) 1563 set_except_vector(24, handle_mcheck); 1564 1565 if (cpu_has_mipsmt) 1566 set_except_vector(25, handle_mt); 1567 1568 set_except_vector(26, handle_dsp); 1569 1570 if (cpu_has_vce) 1571 /* Special exception: R4[04]00 uses also the divec space. */ 1572 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1573 else if (cpu_has_4kex) 1574 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1575 else 1576 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1577 1578 signal_init(); 1579 #ifdef CONFIG_MIPS32_COMPAT 1580 signal32_init(); 1581 #endif 1582 1583 flush_icache_range(ebase, ebase + 0x400); 1584 flush_tlb_handlers(); 1585 } 1586