1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki 13 */ 14 #include <linux/init.h> 15 #include <linux/mm.h> 16 #include <linux/module.h> 17 #include <linux/sched.h> 18 #include <linux/smp.h> 19 #include <linux/smp_lock.h> 20 #include <linux/spinlock.h> 21 #include <linux/kallsyms.h> 22 #include <linux/bootmem.h> 23 #include <linux/interrupt.h> 24 25 #include <asm/bootinfo.h> 26 #include <asm/branch.h> 27 #include <asm/break.h> 28 #include <asm/cpu.h> 29 #include <asm/dsp.h> 30 #include <asm/fpu.h> 31 #include <asm/mipsregs.h> 32 #include <asm/mipsmtregs.h> 33 #include <asm/module.h> 34 #include <asm/pgtable.h> 35 #include <asm/ptrace.h> 36 #include <asm/sections.h> 37 #include <asm/system.h> 38 #include <asm/tlbdebug.h> 39 #include <asm/traps.h> 40 #include <asm/uaccess.h> 41 #include <asm/mmu_context.h> 42 #include <asm/watch.h> 43 #include <asm/types.h> 44 #include <asm/stacktrace.h> 45 46 extern asmlinkage void handle_int(void); 47 extern asmlinkage void handle_tlbm(void); 48 extern asmlinkage void handle_tlbl(void); 49 extern asmlinkage void handle_tlbs(void); 50 extern asmlinkage void handle_adel(void); 51 extern asmlinkage void handle_ades(void); 52 extern asmlinkage void handle_ibe(void); 53 extern asmlinkage void handle_dbe(void); 54 extern asmlinkage void handle_sys(void); 55 extern asmlinkage void handle_bp(void); 56 extern asmlinkage void handle_ri(void); 57 extern asmlinkage void handle_ri_rdhwr_vivt(void); 58 extern asmlinkage void handle_ri_rdhwr(void); 59 extern asmlinkage void handle_cpu(void); 60 extern asmlinkage void handle_ov(void); 61 extern asmlinkage void handle_tr(void); 62 extern asmlinkage void handle_fpe(void); 63 extern asmlinkage void handle_mdmx(void); 64 extern asmlinkage void handle_watch(void); 65 extern asmlinkage void handle_mt(void); 66 extern asmlinkage void handle_dsp(void); 67 extern asmlinkage void handle_mcheck(void); 68 extern asmlinkage void handle_reserved(void); 69 70 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 71 struct mips_fpu_struct *ctx, int has_fpu); 72 73 void (*board_be_init)(void); 74 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 75 void (*board_nmi_handler_setup)(void); 76 void (*board_ejtag_handler_setup)(void); 77 void (*board_bind_eic_interrupt)(int irq, int regset); 78 79 80 static void show_raw_backtrace(unsigned long reg29) 81 { 82 unsigned long *sp = (unsigned long *)reg29; 83 unsigned long addr; 84 85 printk("Call Trace:"); 86 #ifdef CONFIG_KALLSYMS 87 printk("\n"); 88 #endif 89 while (!kstack_end(sp)) { 90 addr = *sp++; 91 if (__kernel_text_address(addr)) 92 print_ip_sym(addr); 93 } 94 printk("\n"); 95 } 96 97 #ifdef CONFIG_KALLSYMS 98 int raw_show_trace; 99 static int __init set_raw_show_trace(char *str) 100 { 101 raw_show_trace = 1; 102 return 1; 103 } 104 __setup("raw_show_trace", set_raw_show_trace); 105 #endif 106 107 static void show_backtrace(struct task_struct *task, struct pt_regs *regs) 108 { 109 unsigned long sp = regs->regs[29]; 110 unsigned long ra = regs->regs[31]; 111 unsigned long pc = regs->cp0_epc; 112 113 if (raw_show_trace || !__kernel_text_address(pc)) { 114 show_raw_backtrace(sp); 115 return; 116 } 117 printk("Call Trace:\n"); 118 do { 119 print_ip_sym(pc); 120 pc = unwind_stack(task, &sp, pc, &ra); 121 } while (pc); 122 printk("\n"); 123 } 124 125 /* 126 * This routine abuses get_user()/put_user() to reference pointers 127 * with at least a bit of error checking ... 128 */ 129 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs) 130 { 131 const int field = 2 * sizeof(unsigned long); 132 long stackdata; 133 int i; 134 unsigned long *sp = (unsigned long *)regs->regs[29]; 135 136 printk("Stack :"); 137 i = 0; 138 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 139 if (i && ((i % (64 / field)) == 0)) 140 printk("\n "); 141 if (i > 39) { 142 printk(" ..."); 143 break; 144 } 145 146 if (__get_user(stackdata, sp++)) { 147 printk(" (Bad stack address)"); 148 break; 149 } 150 151 printk(" %0*lx", field, stackdata); 152 i++; 153 } 154 printk("\n"); 155 show_backtrace(task, regs); 156 } 157 158 void show_stack(struct task_struct *task, unsigned long *sp) 159 { 160 struct pt_regs regs; 161 if (sp) { 162 regs.regs[29] = (unsigned long)sp; 163 regs.regs[31] = 0; 164 regs.cp0_epc = 0; 165 } else { 166 if (task && task != current) { 167 regs.regs[29] = task->thread.reg29; 168 regs.regs[31] = 0; 169 regs.cp0_epc = task->thread.reg31; 170 } else { 171 prepare_frametrace(®s); 172 } 173 } 174 show_stacktrace(task, ®s); 175 } 176 177 /* 178 * The architecture-independent dump_stack generator 179 */ 180 void dump_stack(void) 181 { 182 struct pt_regs regs; 183 184 prepare_frametrace(®s); 185 show_backtrace(current, ®s); 186 } 187 188 EXPORT_SYMBOL(dump_stack); 189 190 void show_code(unsigned int *pc) 191 { 192 long i; 193 194 printk("\nCode:"); 195 196 for(i = -3 ; i < 6 ; i++) { 197 unsigned int insn; 198 if (__get_user(insn, pc + i)) { 199 printk(" (Bad address in epc)\n"); 200 break; 201 } 202 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 203 } 204 } 205 206 void show_regs(struct pt_regs *regs) 207 { 208 const int field = 2 * sizeof(unsigned long); 209 unsigned int cause = regs->cp0_cause; 210 int i; 211 212 printk("Cpu %d\n", smp_processor_id()); 213 214 /* 215 * Saved main processor registers 216 */ 217 for (i = 0; i < 32; ) { 218 if ((i % 4) == 0) 219 printk("$%2d :", i); 220 if (i == 0) 221 printk(" %0*lx", field, 0UL); 222 else if (i == 26 || i == 27) 223 printk(" %*s", field, ""); 224 else 225 printk(" %0*lx", field, regs->regs[i]); 226 227 i++; 228 if ((i % 4) == 0) 229 printk("\n"); 230 } 231 232 #ifdef CONFIG_CPU_HAS_SMARTMIPS 233 printk("Acx : %0*lx\n", field, regs->acx); 234 #endif 235 printk("Hi : %0*lx\n", field, regs->hi); 236 printk("Lo : %0*lx\n", field, regs->lo); 237 238 /* 239 * Saved cp0 registers 240 */ 241 printk("epc : %0*lx ", field, regs->cp0_epc); 242 print_symbol("%s ", regs->cp0_epc); 243 printk(" %s\n", print_tainted()); 244 printk("ra : %0*lx ", field, regs->regs[31]); 245 print_symbol("%s\n", regs->regs[31]); 246 247 printk("Status: %08x ", (uint32_t) regs->cp0_status); 248 249 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 250 if (regs->cp0_status & ST0_KUO) 251 printk("KUo "); 252 if (regs->cp0_status & ST0_IEO) 253 printk("IEo "); 254 if (regs->cp0_status & ST0_KUP) 255 printk("KUp "); 256 if (regs->cp0_status & ST0_IEP) 257 printk("IEp "); 258 if (regs->cp0_status & ST0_KUC) 259 printk("KUc "); 260 if (regs->cp0_status & ST0_IEC) 261 printk("IEc "); 262 } else { 263 if (regs->cp0_status & ST0_KX) 264 printk("KX "); 265 if (regs->cp0_status & ST0_SX) 266 printk("SX "); 267 if (regs->cp0_status & ST0_UX) 268 printk("UX "); 269 switch (regs->cp0_status & ST0_KSU) { 270 case KSU_USER: 271 printk("USER "); 272 break; 273 case KSU_SUPERVISOR: 274 printk("SUPERVISOR "); 275 break; 276 case KSU_KERNEL: 277 printk("KERNEL "); 278 break; 279 default: 280 printk("BAD_MODE "); 281 break; 282 } 283 if (regs->cp0_status & ST0_ERL) 284 printk("ERL "); 285 if (regs->cp0_status & ST0_EXL) 286 printk("EXL "); 287 if (regs->cp0_status & ST0_IE) 288 printk("IE "); 289 } 290 printk("\n"); 291 292 printk("Cause : %08x\n", cause); 293 294 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 295 if (1 <= cause && cause <= 5) 296 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 297 298 printk("PrId : %08x\n", read_c0_prid()); 299 } 300 301 void show_registers(struct pt_regs *regs) 302 { 303 show_regs(regs); 304 print_modules(); 305 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 306 current->comm, current->pid, current_thread_info(), current); 307 show_stacktrace(current, regs); 308 show_code((unsigned int *) regs->cp0_epc); 309 printk("\n"); 310 } 311 312 static DEFINE_SPINLOCK(die_lock); 313 314 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs) 315 { 316 static int die_counter; 317 #ifdef CONFIG_MIPS_MT_SMTC 318 unsigned long dvpret = dvpe(); 319 #endif /* CONFIG_MIPS_MT_SMTC */ 320 321 console_verbose(); 322 spin_lock_irq(&die_lock); 323 bust_spinlocks(1); 324 #ifdef CONFIG_MIPS_MT_SMTC 325 mips_mt_regdump(dvpret); 326 #endif /* CONFIG_MIPS_MT_SMTC */ 327 printk("%s[#%d]:\n", str, ++die_counter); 328 show_registers(regs); 329 spin_unlock_irq(&die_lock); 330 331 if (in_interrupt()) 332 panic("Fatal exception in interrupt"); 333 334 if (panic_on_oops) { 335 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 336 ssleep(5); 337 panic("Fatal exception"); 338 } 339 340 do_exit(SIGSEGV); 341 } 342 343 extern const struct exception_table_entry __start___dbe_table[]; 344 extern const struct exception_table_entry __stop___dbe_table[]; 345 346 __asm__( 347 " .section __dbe_table, \"a\"\n" 348 " .previous \n"); 349 350 /* Given an address, look for it in the exception tables. */ 351 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 352 { 353 const struct exception_table_entry *e; 354 355 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 356 if (!e) 357 e = search_module_dbetables(addr); 358 return e; 359 } 360 361 asmlinkage void do_be(struct pt_regs *regs) 362 { 363 const int field = 2 * sizeof(unsigned long); 364 const struct exception_table_entry *fixup = NULL; 365 int data = regs->cp0_cause & 4; 366 int action = MIPS_BE_FATAL; 367 368 /* XXX For now. Fixme, this searches the wrong table ... */ 369 if (data && !user_mode(regs)) 370 fixup = search_dbe_tables(exception_epc(regs)); 371 372 if (fixup) 373 action = MIPS_BE_FIXUP; 374 375 if (board_be_handler) 376 action = board_be_handler(regs, fixup != 0); 377 378 switch (action) { 379 case MIPS_BE_DISCARD: 380 return; 381 case MIPS_BE_FIXUP: 382 if (fixup) { 383 regs->cp0_epc = fixup->nextinsn; 384 return; 385 } 386 break; 387 default: 388 break; 389 } 390 391 /* 392 * Assume it would be too dangerous to continue ... 393 */ 394 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 395 data ? "Data" : "Instruction", 396 field, regs->cp0_epc, field, regs->regs[31]); 397 die_if_kernel("Oops", regs); 398 force_sig(SIGBUS, current); 399 } 400 401 /* 402 * ll/sc emulation 403 */ 404 405 #define OPCODE 0xfc000000 406 #define BASE 0x03e00000 407 #define RT 0x001f0000 408 #define OFFSET 0x0000ffff 409 #define LL 0xc0000000 410 #define SC 0xe0000000 411 #define SPEC3 0x7c000000 412 #define RD 0x0000f800 413 #define FUNC 0x0000003f 414 #define RDHWR 0x0000003b 415 416 /* 417 * The ll_bit is cleared by r*_switch.S 418 */ 419 420 unsigned long ll_bit; 421 422 static struct task_struct *ll_task = NULL; 423 424 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) 425 { 426 unsigned long value, __user *vaddr; 427 long offset; 428 int signal = 0; 429 430 /* 431 * analyse the ll instruction that just caused a ri exception 432 * and put the referenced address to addr. 433 */ 434 435 /* sign extend offset */ 436 offset = opcode & OFFSET; 437 offset <<= 16; 438 offset >>= 16; 439 440 vaddr = (unsigned long __user *) 441 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 442 443 if ((unsigned long)vaddr & 3) { 444 signal = SIGBUS; 445 goto sig; 446 } 447 if (get_user(value, vaddr)) { 448 signal = SIGSEGV; 449 goto sig; 450 } 451 452 preempt_disable(); 453 454 if (ll_task == NULL || ll_task == current) { 455 ll_bit = 1; 456 } else { 457 ll_bit = 0; 458 } 459 ll_task = current; 460 461 preempt_enable(); 462 463 compute_return_epc(regs); 464 465 regs->regs[(opcode & RT) >> 16] = value; 466 467 return; 468 469 sig: 470 force_sig(signal, current); 471 } 472 473 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) 474 { 475 unsigned long __user *vaddr; 476 unsigned long reg; 477 long offset; 478 int signal = 0; 479 480 /* 481 * analyse the sc instruction that just caused a ri exception 482 * and put the referenced address to addr. 483 */ 484 485 /* sign extend offset */ 486 offset = opcode & OFFSET; 487 offset <<= 16; 488 offset >>= 16; 489 490 vaddr = (unsigned long __user *) 491 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 492 reg = (opcode & RT) >> 16; 493 494 if ((unsigned long)vaddr & 3) { 495 signal = SIGBUS; 496 goto sig; 497 } 498 499 preempt_disable(); 500 501 if (ll_bit == 0 || ll_task != current) { 502 compute_return_epc(regs); 503 regs->regs[reg] = 0; 504 preempt_enable(); 505 return; 506 } 507 508 preempt_enable(); 509 510 if (put_user(regs->regs[reg], vaddr)) { 511 signal = SIGSEGV; 512 goto sig; 513 } 514 515 compute_return_epc(regs); 516 regs->regs[reg] = 1; 517 518 return; 519 520 sig: 521 force_sig(signal, current); 522 } 523 524 /* 525 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 526 * opcodes are supposed to result in coprocessor unusable exceptions if 527 * executed on ll/sc-less processors. That's the theory. In practice a 528 * few processors such as NEC's VR4100 throw reserved instruction exceptions 529 * instead, so we're doing the emulation thing in both exception handlers. 530 */ 531 static inline int simulate_llsc(struct pt_regs *regs) 532 { 533 unsigned int opcode; 534 535 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 536 goto out_sigsegv; 537 538 if ((opcode & OPCODE) == LL) { 539 simulate_ll(regs, opcode); 540 return 0; 541 } 542 if ((opcode & OPCODE) == SC) { 543 simulate_sc(regs, opcode); 544 return 0; 545 } 546 547 return -EFAULT; /* Strange things going on ... */ 548 549 out_sigsegv: 550 force_sig(SIGSEGV, current); 551 return -EFAULT; 552 } 553 554 /* 555 * Simulate trapping 'rdhwr' instructions to provide user accessible 556 * registers not implemented in hardware. The only current use of this 557 * is the thread area pointer. 558 */ 559 static inline int simulate_rdhwr(struct pt_regs *regs) 560 { 561 struct thread_info *ti = task_thread_info(current); 562 unsigned int opcode; 563 564 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 565 goto out_sigsegv; 566 567 if (unlikely(compute_return_epc(regs))) 568 return -EFAULT; 569 570 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 571 int rd = (opcode & RD) >> 11; 572 int rt = (opcode & RT) >> 16; 573 switch (rd) { 574 case 29: 575 regs->regs[rt] = ti->tp_value; 576 return 0; 577 default: 578 return -EFAULT; 579 } 580 } 581 582 /* Not ours. */ 583 return -EFAULT; 584 585 out_sigsegv: 586 force_sig(SIGSEGV, current); 587 return -EFAULT; 588 } 589 590 asmlinkage void do_ov(struct pt_regs *regs) 591 { 592 siginfo_t info; 593 594 die_if_kernel("Integer overflow", regs); 595 596 info.si_code = FPE_INTOVF; 597 info.si_signo = SIGFPE; 598 info.si_errno = 0; 599 info.si_addr = (void __user *) regs->cp0_epc; 600 force_sig_info(SIGFPE, &info, current); 601 } 602 603 /* 604 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 605 */ 606 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 607 { 608 die_if_kernel("FP exception in kernel code", regs); 609 610 if (fcr31 & FPU_CSR_UNI_X) { 611 int sig; 612 613 /* 614 * Unimplemented operation exception. If we've got the full 615 * software emulator on-board, let's use it... 616 * 617 * Force FPU to dump state into task/thread context. We're 618 * moving a lot of data here for what is probably a single 619 * instruction, but the alternative is to pre-decode the FP 620 * register operands before invoking the emulator, which seems 621 * a bit extreme for what should be an infrequent event. 622 */ 623 /* Ensure 'resume' not overwrite saved fp context again. */ 624 lose_fpu(1); 625 626 /* Run the emulator */ 627 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1); 628 629 /* 630 * We can't allow the emulated instruction to leave any of 631 * the cause bit set in $fcr31. 632 */ 633 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 634 635 /* Restore the hardware register state */ 636 own_fpu(1); /* Using the FPU again. */ 637 638 /* If something went wrong, signal */ 639 if (sig) 640 force_sig(sig, current); 641 642 return; 643 } 644 645 force_sig(SIGFPE, current); 646 } 647 648 asmlinkage void do_bp(struct pt_regs *regs) 649 { 650 unsigned int opcode, bcode; 651 siginfo_t info; 652 653 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 654 goto out_sigsegv; 655 656 /* 657 * There is the ancient bug in the MIPS assemblers that the break 658 * code starts left to bit 16 instead to bit 6 in the opcode. 659 * Gas is bug-compatible, but not always, grrr... 660 * We handle both cases with a simple heuristics. --macro 661 */ 662 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 663 if (bcode < (1 << 10)) 664 bcode <<= 10; 665 666 /* 667 * (A short test says that IRIX 5.3 sends SIGTRAP for all break 668 * insns, even for break codes that indicate arithmetic failures. 669 * Weird ...) 670 * But should we continue the brokenness??? --macro 671 */ 672 switch (bcode) { 673 case BRK_OVERFLOW << 10: 674 case BRK_DIVZERO << 10: 675 die_if_kernel("Break instruction in kernel code", regs); 676 if (bcode == (BRK_DIVZERO << 10)) 677 info.si_code = FPE_INTDIV; 678 else 679 info.si_code = FPE_INTOVF; 680 info.si_signo = SIGFPE; 681 info.si_errno = 0; 682 info.si_addr = (void __user *) regs->cp0_epc; 683 force_sig_info(SIGFPE, &info, current); 684 break; 685 case BRK_BUG: 686 die("Kernel bug detected", regs); 687 break; 688 default: 689 die_if_kernel("Break instruction in kernel code", regs); 690 force_sig(SIGTRAP, current); 691 } 692 return; 693 694 out_sigsegv: 695 force_sig(SIGSEGV, current); 696 } 697 698 asmlinkage void do_tr(struct pt_regs *regs) 699 { 700 unsigned int opcode, tcode = 0; 701 siginfo_t info; 702 703 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 704 goto out_sigsegv; 705 706 /* Immediate versions don't provide a code. */ 707 if (!(opcode & OPCODE)) 708 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 709 710 /* 711 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap 712 * insns, even for trap codes that indicate arithmetic failures. 713 * Weird ...) 714 * But should we continue the brokenness??? --macro 715 */ 716 switch (tcode) { 717 case BRK_OVERFLOW: 718 case BRK_DIVZERO: 719 die_if_kernel("Trap instruction in kernel code", regs); 720 if (tcode == BRK_DIVZERO) 721 info.si_code = FPE_INTDIV; 722 else 723 info.si_code = FPE_INTOVF; 724 info.si_signo = SIGFPE; 725 info.si_errno = 0; 726 info.si_addr = (void __user *) regs->cp0_epc; 727 force_sig_info(SIGFPE, &info, current); 728 break; 729 case BRK_BUG: 730 die("Kernel bug detected", regs); 731 break; 732 default: 733 die_if_kernel("Trap instruction in kernel code", regs); 734 force_sig(SIGTRAP, current); 735 } 736 return; 737 738 out_sigsegv: 739 force_sig(SIGSEGV, current); 740 } 741 742 asmlinkage void do_ri(struct pt_regs *regs) 743 { 744 die_if_kernel("Reserved instruction in kernel code", regs); 745 746 if (!cpu_has_llsc) 747 if (!simulate_llsc(regs)) 748 return; 749 750 if (!simulate_rdhwr(regs)) 751 return; 752 753 force_sig(SIGILL, current); 754 } 755 756 asmlinkage void do_cpu(struct pt_regs *regs) 757 { 758 unsigned int cpid; 759 760 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 761 762 switch (cpid) { 763 case 0: 764 die_if_kernel("do_cpu invoked from kernel context!", regs); 765 if (!cpu_has_llsc) 766 if (!simulate_llsc(regs)) 767 return; 768 769 if (!simulate_rdhwr(regs)) 770 return; 771 772 break; 773 774 case 1: 775 if (!test_thread_flag(TIF_ALLOW_FP_IN_KERNEL)) 776 die_if_kernel("do_cpu invoked from kernel context!", 777 regs); 778 if (used_math()) /* Using the FPU again. */ 779 own_fpu(1); 780 else { /* First time FPU user. */ 781 init_fpu(); 782 set_used_math(); 783 } 784 785 if (raw_cpu_has_fpu) { 786 if (test_thread_flag(TIF_ALLOW_FP_IN_KERNEL)) { 787 local_irq_disable(); 788 if (cpu_has_fpu) 789 regs->cp0_status |= ST0_CU1; 790 /* 791 * We must return without enabling 792 * interrupts to ensure keep FPU 793 * ownership until resume. 794 */ 795 return; 796 } 797 } else { 798 int sig; 799 sig = fpu_emulator_cop1Handler(regs, 800 ¤t->thread.fpu, 0); 801 if (sig) 802 force_sig(sig, current); 803 #ifdef CONFIG_MIPS_MT_FPAFF 804 else { 805 /* 806 * MIPS MT processors may have fewer FPU contexts 807 * than CPU threads. If we've emulated more than 808 * some threshold number of instructions, force 809 * migration to a "CPU" that has FP support. 810 */ 811 if(mt_fpemul_threshold > 0 812 && ((current->thread.emulated_fp++ 813 > mt_fpemul_threshold))) { 814 /* 815 * If there's no FPU present, or if the 816 * application has already restricted 817 * the allowed set to exclude any CPUs 818 * with FPUs, we'll skip the procedure. 819 */ 820 if (cpus_intersects(current->cpus_allowed, 821 mt_fpu_cpumask)) { 822 cpumask_t tmask; 823 824 cpus_and(tmask, 825 current->thread.user_cpus_allowed, 826 mt_fpu_cpumask); 827 set_cpus_allowed(current, tmask); 828 current->thread.mflags |= MF_FPUBOUND; 829 } 830 } 831 } 832 #endif /* CONFIG_MIPS_MT_FPAFF */ 833 } 834 835 return; 836 837 case 2: 838 case 3: 839 die_if_kernel("do_cpu invoked from kernel context!", regs); 840 break; 841 } 842 843 force_sig(SIGILL, current); 844 } 845 846 asmlinkage void do_mdmx(struct pt_regs *regs) 847 { 848 force_sig(SIGILL, current); 849 } 850 851 asmlinkage void do_watch(struct pt_regs *regs) 852 { 853 /* 854 * We use the watch exception where available to detect stack 855 * overflows. 856 */ 857 dump_tlb_all(); 858 show_regs(regs); 859 panic("Caught WATCH exception - probably caused by stack overflow."); 860 } 861 862 asmlinkage void do_mcheck(struct pt_regs *regs) 863 { 864 const int field = 2 * sizeof(unsigned long); 865 int multi_match = regs->cp0_status & ST0_TS; 866 867 show_regs(regs); 868 869 if (multi_match) { 870 printk("Index : %0x\n", read_c0_index()); 871 printk("Pagemask: %0x\n", read_c0_pagemask()); 872 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 873 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 874 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 875 printk("\n"); 876 dump_tlb_all(); 877 } 878 879 show_code((unsigned int *) regs->cp0_epc); 880 881 /* 882 * Some chips may have other causes of machine check (e.g. SB1 883 * graduation timer) 884 */ 885 panic("Caught Machine Check exception - %scaused by multiple " 886 "matching entries in the TLB.", 887 (multi_match) ? "" : "not "); 888 } 889 890 asmlinkage void do_mt(struct pt_regs *regs) 891 { 892 int subcode; 893 894 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 895 >> VPECONTROL_EXCPT_SHIFT; 896 switch (subcode) { 897 case 0: 898 printk(KERN_DEBUG "Thread Underflow\n"); 899 break; 900 case 1: 901 printk(KERN_DEBUG "Thread Overflow\n"); 902 break; 903 case 2: 904 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 905 break; 906 case 3: 907 printk(KERN_DEBUG "Gating Storage Exception\n"); 908 break; 909 case 4: 910 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 911 break; 912 case 5: 913 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 914 break; 915 default: 916 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 917 subcode); 918 break; 919 } 920 die_if_kernel("MIPS MT Thread exception in kernel", regs); 921 922 force_sig(SIGILL, current); 923 } 924 925 926 asmlinkage void do_dsp(struct pt_regs *regs) 927 { 928 if (cpu_has_dsp) 929 panic("Unexpected DSP exception\n"); 930 931 force_sig(SIGILL, current); 932 } 933 934 asmlinkage void do_reserved(struct pt_regs *regs) 935 { 936 /* 937 * Game over - no way to handle this if it ever occurs. Most probably 938 * caused by a new unknown cpu type or after another deadly 939 * hard/software error. 940 */ 941 show_regs(regs); 942 panic("Caught reserved exception %ld - should not happen.", 943 (regs->cp0_cause & 0x7f) >> 2); 944 } 945 946 asmlinkage void do_default_vi(struct pt_regs *regs) 947 { 948 show_regs(regs); 949 panic("Caught unexpected vectored interrupt."); 950 } 951 952 /* 953 * Some MIPS CPUs can enable/disable for cache parity detection, but do 954 * it different ways. 955 */ 956 static inline void parity_protection_init(void) 957 { 958 switch (current_cpu_data.cputype) { 959 case CPU_24K: 960 case CPU_34K: 961 case CPU_5KC: 962 write_c0_ecc(0x80000000); 963 back_to_back_c0_hazard(); 964 /* Set the PE bit (bit 31) in the c0_errctl register. */ 965 printk(KERN_INFO "Cache parity protection %sabled\n", 966 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 967 break; 968 case CPU_20KC: 969 case CPU_25KF: 970 /* Clear the DE bit (bit 16) in the c0_status register. */ 971 printk(KERN_INFO "Enable cache parity protection for " 972 "MIPS 20KC/25KF CPUs.\n"); 973 clear_c0_status(ST0_DE); 974 break; 975 default: 976 break; 977 } 978 } 979 980 asmlinkage void cache_parity_error(void) 981 { 982 const int field = 2 * sizeof(unsigned long); 983 unsigned int reg_val; 984 985 /* For the moment, report the problem and hang. */ 986 printk("Cache error exception:\n"); 987 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 988 reg_val = read_c0_cacheerr(); 989 printk("c0_cacheerr == %08x\n", reg_val); 990 991 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 992 reg_val & (1<<30) ? "secondary" : "primary", 993 reg_val & (1<<31) ? "data" : "insn"); 994 printk("Error bits: %s%s%s%s%s%s%s\n", 995 reg_val & (1<<29) ? "ED " : "", 996 reg_val & (1<<28) ? "ET " : "", 997 reg_val & (1<<26) ? "EE " : "", 998 reg_val & (1<<25) ? "EB " : "", 999 reg_val & (1<<24) ? "EI " : "", 1000 reg_val & (1<<23) ? "E1 " : "", 1001 reg_val & (1<<22) ? "E0 " : ""); 1002 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1003 1004 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1005 if (reg_val & (1<<22)) 1006 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1007 1008 if (reg_val & (1<<23)) 1009 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1010 #endif 1011 1012 panic("Can't handle the cache error!"); 1013 } 1014 1015 /* 1016 * SDBBP EJTAG debug exception handler. 1017 * We skip the instruction and return to the next instruction. 1018 */ 1019 void ejtag_exception_handler(struct pt_regs *regs) 1020 { 1021 const int field = 2 * sizeof(unsigned long); 1022 unsigned long depc, old_epc; 1023 unsigned int debug; 1024 1025 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1026 depc = read_c0_depc(); 1027 debug = read_c0_debug(); 1028 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1029 if (debug & 0x80000000) { 1030 /* 1031 * In branch delay slot. 1032 * We cheat a little bit here and use EPC to calculate the 1033 * debug return address (DEPC). EPC is restored after the 1034 * calculation. 1035 */ 1036 old_epc = regs->cp0_epc; 1037 regs->cp0_epc = depc; 1038 __compute_return_epc(regs); 1039 depc = regs->cp0_epc; 1040 regs->cp0_epc = old_epc; 1041 } else 1042 depc += 4; 1043 write_c0_depc(depc); 1044 1045 #if 0 1046 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1047 write_c0_debug(debug | 0x100); 1048 #endif 1049 } 1050 1051 /* 1052 * NMI exception handler. 1053 */ 1054 void nmi_exception_handler(struct pt_regs *regs) 1055 { 1056 #ifdef CONFIG_MIPS_MT_SMTC 1057 unsigned long dvpret = dvpe(); 1058 bust_spinlocks(1); 1059 printk("NMI taken!!!!\n"); 1060 mips_mt_regdump(dvpret); 1061 #else 1062 bust_spinlocks(1); 1063 printk("NMI taken!!!!\n"); 1064 #endif /* CONFIG_MIPS_MT_SMTC */ 1065 die("NMI", regs); 1066 while(1) ; 1067 } 1068 1069 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1070 1071 unsigned long ebase; 1072 unsigned long exception_handlers[32]; 1073 unsigned long vi_handlers[64]; 1074 1075 /* 1076 * As a side effect of the way this is implemented we're limited 1077 * to interrupt handlers in the address range from 1078 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... 1079 */ 1080 void *set_except_vector(int n, void *addr) 1081 { 1082 unsigned long handler = (unsigned long) addr; 1083 unsigned long old_handler = exception_handlers[n]; 1084 1085 exception_handlers[n] = handler; 1086 if (n == 0 && cpu_has_divec) { 1087 *(volatile u32 *)(ebase + 0x200) = 0x08000000 | 1088 (0x03ffffff & (handler >> 2)); 1089 flush_icache_range(ebase + 0x200, ebase + 0x204); 1090 } 1091 return (void *)old_handler; 1092 } 1093 1094 #ifdef CONFIG_CPU_MIPSR2_SRS 1095 /* 1096 * MIPSR2 shadow register set allocation 1097 * FIXME: SMP... 1098 */ 1099 1100 static struct shadow_registers { 1101 /* 1102 * Number of shadow register sets supported 1103 */ 1104 unsigned long sr_supported; 1105 /* 1106 * Bitmap of allocated shadow registers 1107 */ 1108 unsigned long sr_allocated; 1109 } shadow_registers; 1110 1111 static void mips_srs_init(void) 1112 { 1113 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1114 printk(KERN_INFO "%ld MIPSR2 register sets available\n", 1115 shadow_registers.sr_supported); 1116 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ 1117 } 1118 1119 int mips_srs_max(void) 1120 { 1121 return shadow_registers.sr_supported; 1122 } 1123 1124 int mips_srs_alloc(void) 1125 { 1126 struct shadow_registers *sr = &shadow_registers; 1127 int set; 1128 1129 again: 1130 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported); 1131 if (set >= sr->sr_supported) 1132 return -1; 1133 1134 if (test_and_set_bit(set, &sr->sr_allocated)) 1135 goto again; 1136 1137 return set; 1138 } 1139 1140 void mips_srs_free(int set) 1141 { 1142 struct shadow_registers *sr = &shadow_registers; 1143 1144 clear_bit(set, &sr->sr_allocated); 1145 } 1146 1147 static void *set_vi_srs_handler(int n, void *addr, int srs) 1148 { 1149 unsigned long handler; 1150 unsigned long old_handler = vi_handlers[n]; 1151 u32 *w; 1152 unsigned char *b; 1153 1154 if (!cpu_has_veic && !cpu_has_vint) 1155 BUG(); 1156 1157 if (addr == NULL) { 1158 handler = (unsigned long) do_default_vi; 1159 srs = 0; 1160 } else 1161 handler = (unsigned long) addr; 1162 vi_handlers[n] = (unsigned long) addr; 1163 1164 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1165 1166 if (srs >= mips_srs_max()) 1167 panic("Shadow register set %d not supported", srs); 1168 1169 if (cpu_has_veic) { 1170 if (board_bind_eic_interrupt) 1171 board_bind_eic_interrupt (n, srs); 1172 } else if (cpu_has_vint) { 1173 /* SRSMap is only defined if shadow sets are implemented */ 1174 if (mips_srs_max() > 1) 1175 change_c0_srsmap (0xf << n*4, srs << n*4); 1176 } 1177 1178 if (srs == 0) { 1179 /* 1180 * If no shadow set is selected then use the default handler 1181 * that does normal register saving and a standard interrupt exit 1182 */ 1183 1184 extern char except_vec_vi, except_vec_vi_lui; 1185 extern char except_vec_vi_ori, except_vec_vi_end; 1186 #ifdef CONFIG_MIPS_MT_SMTC 1187 /* 1188 * We need to provide the SMTC vectored interrupt handler 1189 * not only with the address of the handler, but with the 1190 * Status.IM bit to be masked before going there. 1191 */ 1192 extern char except_vec_vi_mori; 1193 const int mori_offset = &except_vec_vi_mori - &except_vec_vi; 1194 #endif /* CONFIG_MIPS_MT_SMTC */ 1195 const int handler_len = &except_vec_vi_end - &except_vec_vi; 1196 const int lui_offset = &except_vec_vi_lui - &except_vec_vi; 1197 const int ori_offset = &except_vec_vi_ori - &except_vec_vi; 1198 1199 if (handler_len > VECTORSPACING) { 1200 /* 1201 * Sigh... panicing won't help as the console 1202 * is probably not configured :( 1203 */ 1204 panic ("VECTORSPACING too small"); 1205 } 1206 1207 memcpy (b, &except_vec_vi, handler_len); 1208 #ifdef CONFIG_MIPS_MT_SMTC 1209 if (n > 7) 1210 printk("Vector index %d exceeds SMTC maximum\n", n); 1211 w = (u32 *)(b + mori_offset); 1212 *w = (*w & 0xffff0000) | (0x100 << n); 1213 #endif /* CONFIG_MIPS_MT_SMTC */ 1214 w = (u32 *)(b + lui_offset); 1215 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1216 w = (u32 *)(b + ori_offset); 1217 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1218 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); 1219 } 1220 else { 1221 /* 1222 * In other cases jump directly to the interrupt handler 1223 * 1224 * It is the handlers responsibility to save registers if required 1225 * (eg hi/lo) and return from the exception using "eret" 1226 */ 1227 w = (u32 *)b; 1228 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1229 *w = 0; 1230 flush_icache_range((unsigned long)b, (unsigned long)(b+8)); 1231 } 1232 1233 return (void *)old_handler; 1234 } 1235 1236 void *set_vi_handler(int n, void *addr) 1237 { 1238 return set_vi_srs_handler(n, addr, 0); 1239 } 1240 1241 #else 1242 1243 static inline void mips_srs_init(void) 1244 { 1245 } 1246 1247 #endif /* CONFIG_CPU_MIPSR2_SRS */ 1248 1249 /* 1250 * This is used by native signal handling 1251 */ 1252 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); 1253 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); 1254 1255 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); 1256 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); 1257 1258 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); 1259 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); 1260 1261 #ifdef CONFIG_SMP 1262 static int smp_save_fp_context(struct sigcontext __user *sc) 1263 { 1264 return raw_cpu_has_fpu 1265 ? _save_fp_context(sc) 1266 : fpu_emulator_save_context(sc); 1267 } 1268 1269 static int smp_restore_fp_context(struct sigcontext __user *sc) 1270 { 1271 return raw_cpu_has_fpu 1272 ? _restore_fp_context(sc) 1273 : fpu_emulator_restore_context(sc); 1274 } 1275 #endif 1276 1277 static inline void signal_init(void) 1278 { 1279 #ifdef CONFIG_SMP 1280 /* For now just do the cpu_has_fpu check when the functions are invoked */ 1281 save_fp_context = smp_save_fp_context; 1282 restore_fp_context = smp_restore_fp_context; 1283 #else 1284 if (cpu_has_fpu) { 1285 save_fp_context = _save_fp_context; 1286 restore_fp_context = _restore_fp_context; 1287 } else { 1288 save_fp_context = fpu_emulator_save_context; 1289 restore_fp_context = fpu_emulator_restore_context; 1290 } 1291 #endif 1292 } 1293 1294 #ifdef CONFIG_MIPS32_COMPAT 1295 1296 /* 1297 * This is used by 32-bit signal stuff on the 64-bit kernel 1298 */ 1299 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); 1300 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); 1301 1302 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); 1303 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); 1304 1305 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); 1306 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); 1307 1308 static inline void signal32_init(void) 1309 { 1310 if (cpu_has_fpu) { 1311 save_fp_context32 = _save_fp_context32; 1312 restore_fp_context32 = _restore_fp_context32; 1313 } else { 1314 save_fp_context32 = fpu_emulator_save_context32; 1315 restore_fp_context32 = fpu_emulator_restore_context32; 1316 } 1317 } 1318 #endif 1319 1320 extern void cpu_cache_init(void); 1321 extern void tlb_init(void); 1322 extern void flush_tlb_handlers(void); 1323 1324 void __init per_cpu_trap_init(void) 1325 { 1326 unsigned int cpu = smp_processor_id(); 1327 unsigned int status_set = ST0_CU0; 1328 #ifdef CONFIG_MIPS_MT_SMTC 1329 int secondaryTC = 0; 1330 int bootTC = (cpu == 0); 1331 1332 /* 1333 * Only do per_cpu_trap_init() for first TC of Each VPE. 1334 * Note that this hack assumes that the SMTC init code 1335 * assigns TCs consecutively and in ascending order. 1336 */ 1337 1338 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1339 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1340 secondaryTC = 1; 1341 #endif /* CONFIG_MIPS_MT_SMTC */ 1342 1343 /* 1344 * Disable coprocessors and select 32-bit or 64-bit addressing 1345 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1346 * flag that some firmware may have left set and the TS bit (for 1347 * IP27). Set XX for ISA IV code to work. 1348 */ 1349 #ifdef CONFIG_64BIT 1350 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1351 #endif 1352 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1353 status_set |= ST0_XX; 1354 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1355 status_set); 1356 1357 if (cpu_has_dsp) 1358 set_c0_status(ST0_MX); 1359 1360 #ifdef CONFIG_CPU_MIPSR2 1361 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */ 1362 #endif 1363 1364 #ifdef CONFIG_MIPS_MT_SMTC 1365 if (!secondaryTC) { 1366 #endif /* CONFIG_MIPS_MT_SMTC */ 1367 1368 /* 1369 * Interrupt handling. 1370 */ 1371 if (cpu_has_veic || cpu_has_vint) { 1372 write_c0_ebase (ebase); 1373 /* Setting vector spacing enables EI/VI mode */ 1374 change_c0_intctl (0x3e0, VECTORSPACING); 1375 } 1376 if (cpu_has_divec) { 1377 if (cpu_has_mipsmt) { 1378 unsigned int vpflags = dvpe(); 1379 set_c0_cause(CAUSEF_IV); 1380 evpe(vpflags); 1381 } else 1382 set_c0_cause(CAUSEF_IV); 1383 } 1384 #ifdef CONFIG_MIPS_MT_SMTC 1385 } 1386 #endif /* CONFIG_MIPS_MT_SMTC */ 1387 1388 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1389 TLBMISS_HANDLER_SETUP(); 1390 1391 atomic_inc(&init_mm.mm_count); 1392 current->active_mm = &init_mm; 1393 BUG_ON(current->mm); 1394 enter_lazy_tlb(&init_mm, current); 1395 1396 #ifdef CONFIG_MIPS_MT_SMTC 1397 if (bootTC) { 1398 #endif /* CONFIG_MIPS_MT_SMTC */ 1399 cpu_cache_init(); 1400 tlb_init(); 1401 #ifdef CONFIG_MIPS_MT_SMTC 1402 } 1403 #endif /* CONFIG_MIPS_MT_SMTC */ 1404 } 1405 1406 /* Install CPU exception handler */ 1407 void __init set_handler (unsigned long offset, void *addr, unsigned long size) 1408 { 1409 memcpy((void *)(ebase + offset), addr, size); 1410 flush_icache_range(ebase + offset, ebase + offset + size); 1411 } 1412 1413 /* Install uncached CPU exception handler */ 1414 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) 1415 { 1416 #ifdef CONFIG_32BIT 1417 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1418 #endif 1419 #ifdef CONFIG_64BIT 1420 unsigned long uncached_ebase = TO_UNCAC(ebase); 1421 #endif 1422 1423 memcpy((void *)(uncached_ebase + offset), addr, size); 1424 } 1425 1426 static int __initdata rdhwr_noopt; 1427 static int __init set_rdhwr_noopt(char *str) 1428 { 1429 rdhwr_noopt = 1; 1430 return 1; 1431 } 1432 1433 __setup("rdhwr_noopt", set_rdhwr_noopt); 1434 1435 void __init trap_init(void) 1436 { 1437 extern char except_vec3_generic, except_vec3_r4000; 1438 extern char except_vec4; 1439 unsigned long i; 1440 1441 if (cpu_has_veic || cpu_has_vint) 1442 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); 1443 else 1444 ebase = CAC_BASE; 1445 1446 mips_srs_init(); 1447 1448 per_cpu_trap_init(); 1449 1450 /* 1451 * Copy the generic exception handlers to their final destination. 1452 * This will be overriden later as suitable for a particular 1453 * configuration. 1454 */ 1455 set_handler(0x180, &except_vec3_generic, 0x80); 1456 1457 /* 1458 * Setup default vectors 1459 */ 1460 for (i = 0; i <= 31; i++) 1461 set_except_vector(i, handle_reserved); 1462 1463 /* 1464 * Copy the EJTAG debug exception vector handler code to it's final 1465 * destination. 1466 */ 1467 if (cpu_has_ejtag && board_ejtag_handler_setup) 1468 board_ejtag_handler_setup (); 1469 1470 /* 1471 * Only some CPUs have the watch exceptions. 1472 */ 1473 if (cpu_has_watch) 1474 set_except_vector(23, handle_watch); 1475 1476 /* 1477 * Initialise interrupt handlers 1478 */ 1479 if (cpu_has_veic || cpu_has_vint) { 1480 int nvec = cpu_has_veic ? 64 : 8; 1481 for (i = 0; i < nvec; i++) 1482 set_vi_handler(i, NULL); 1483 } 1484 else if (cpu_has_divec) 1485 set_handler(0x200, &except_vec4, 0x8); 1486 1487 /* 1488 * Some CPUs can enable/disable for cache parity detection, but does 1489 * it different ways. 1490 */ 1491 parity_protection_init(); 1492 1493 /* 1494 * The Data Bus Errors / Instruction Bus Errors are signaled 1495 * by external hardware. Therefore these two exceptions 1496 * may have board specific handlers. 1497 */ 1498 if (board_be_init) 1499 board_be_init(); 1500 1501 set_except_vector(0, handle_int); 1502 set_except_vector(1, handle_tlbm); 1503 set_except_vector(2, handle_tlbl); 1504 set_except_vector(3, handle_tlbs); 1505 1506 set_except_vector(4, handle_adel); 1507 set_except_vector(5, handle_ades); 1508 1509 set_except_vector(6, handle_ibe); 1510 set_except_vector(7, handle_dbe); 1511 1512 set_except_vector(8, handle_sys); 1513 set_except_vector(9, handle_bp); 1514 set_except_vector(10, rdhwr_noopt ? handle_ri : 1515 (cpu_has_vtag_icache ? 1516 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1517 set_except_vector(11, handle_cpu); 1518 set_except_vector(12, handle_ov); 1519 set_except_vector(13, handle_tr); 1520 1521 if (current_cpu_data.cputype == CPU_R6000 || 1522 current_cpu_data.cputype == CPU_R6000A) { 1523 /* 1524 * The R6000 is the only R-series CPU that features a machine 1525 * check exception (similar to the R4000 cache error) and 1526 * unaligned ldc1/sdc1 exception. The handlers have not been 1527 * written yet. Well, anyway there is no R6000 machine on the 1528 * current list of targets for Linux/MIPS. 1529 * (Duh, crap, there is someone with a triple R6k machine) 1530 */ 1531 //set_except_vector(14, handle_mc); 1532 //set_except_vector(15, handle_ndc); 1533 } 1534 1535 1536 if (board_nmi_handler_setup) 1537 board_nmi_handler_setup(); 1538 1539 if (cpu_has_fpu && !cpu_has_nofpuex) 1540 set_except_vector(15, handle_fpe); 1541 1542 set_except_vector(22, handle_mdmx); 1543 1544 if (cpu_has_mcheck) 1545 set_except_vector(24, handle_mcheck); 1546 1547 if (cpu_has_mipsmt) 1548 set_except_vector(25, handle_mt); 1549 1550 if (cpu_has_dsp) 1551 set_except_vector(26, handle_dsp); 1552 1553 if (cpu_has_vce) 1554 /* Special exception: R4[04]00 uses also the divec space. */ 1555 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1556 else if (cpu_has_4kex) 1557 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1558 else 1559 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1560 1561 signal_init(); 1562 #ifdef CONFIG_MIPS32_COMPAT 1563 signal32_init(); 1564 #endif 1565 1566 flush_icache_range(ebase, ebase + 0x400); 1567 flush_tlb_handlers(); 1568 } 1569