1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. 13 * Copyright (C) 2014, Imagination Technologies Ltd. 14 */ 15 #include <linux/bitops.h> 16 #include <linux/bug.h> 17 #include <linux/compiler.h> 18 #include <linux/context_tracking.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/kexec.h> 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/extable.h> 25 #include <linux/mm.h> 26 #include <linux/sched/mm.h> 27 #include <linux/sched/debug.h> 28 #include <linux/smp.h> 29 #include <linux/spinlock.h> 30 #include <linux/kallsyms.h> 31 #include <linux/memblock.h> 32 #include <linux/interrupt.h> 33 #include <linux/ptrace.h> 34 #include <linux/kgdb.h> 35 #include <linux/kdebug.h> 36 #include <linux/kprobes.h> 37 #include <linux/notifier.h> 38 #include <linux/kdb.h> 39 #include <linux/irq.h> 40 #include <linux/perf_event.h> 41 42 #include <asm/addrspace.h> 43 #include <asm/bootinfo.h> 44 #include <asm/branch.h> 45 #include <asm/break.h> 46 #include <asm/cop2.h> 47 #include <asm/cpu.h> 48 #include <asm/cpu-type.h> 49 #include <asm/dsp.h> 50 #include <asm/fpu.h> 51 #include <asm/fpu_emulator.h> 52 #include <asm/idle.h> 53 #include <asm/isa-rev.h> 54 #include <asm/mips-cps.h> 55 #include <asm/mips-r2-to-r6-emul.h> 56 #include <asm/mipsregs.h> 57 #include <asm/mipsmtregs.h> 58 #include <asm/module.h> 59 #include <asm/msa.h> 60 #include <asm/ptrace.h> 61 #include <asm/sections.h> 62 #include <asm/siginfo.h> 63 #include <asm/tlbdebug.h> 64 #include <asm/traps.h> 65 #include <linux/uaccess.h> 66 #include <asm/watch.h> 67 #include <asm/mmu_context.h> 68 #include <asm/types.h> 69 #include <asm/stacktrace.h> 70 #include <asm/tlbex.h> 71 #include <asm/uasm.h> 72 73 #include <asm/mach-loongson64/cpucfg-emul.h> 74 75 extern void check_wait(void); 76 extern asmlinkage void rollback_handle_int(void); 77 extern asmlinkage void handle_int(void); 78 extern asmlinkage void handle_adel(void); 79 extern asmlinkage void handle_ades(void); 80 extern asmlinkage void handle_ibe(void); 81 extern asmlinkage void handle_dbe(void); 82 extern asmlinkage void handle_sys(void); 83 extern asmlinkage void handle_bp(void); 84 extern asmlinkage void handle_ri(void); 85 extern asmlinkage void handle_ri_rdhwr_tlbp(void); 86 extern asmlinkage void handle_ri_rdhwr(void); 87 extern asmlinkage void handle_cpu(void); 88 extern asmlinkage void handle_ov(void); 89 extern asmlinkage void handle_tr(void); 90 extern asmlinkage void handle_msa_fpe(void); 91 extern asmlinkage void handle_fpe(void); 92 extern asmlinkage void handle_ftlb(void); 93 extern asmlinkage void handle_gsexc(void); 94 extern asmlinkage void handle_msa(void); 95 extern asmlinkage void handle_mdmx(void); 96 extern asmlinkage void handle_watch(void); 97 extern asmlinkage void handle_mt(void); 98 extern asmlinkage void handle_dsp(void); 99 extern asmlinkage void handle_mcheck(void); 100 extern asmlinkage void handle_reserved(void); 101 extern void tlb_do_page_fault_0(void); 102 103 void (*board_be_init)(void); 104 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 105 void (*board_nmi_handler_setup)(void); 106 void (*board_ejtag_handler_setup)(void); 107 void (*board_bind_eic_interrupt)(int irq, int regset); 108 void (*board_ebase_setup)(void); 109 void(*board_cache_error_setup)(void); 110 111 static void show_raw_backtrace(unsigned long reg29, const char *loglvl) 112 { 113 unsigned long *sp = (unsigned long *)(reg29 & ~3); 114 unsigned long addr; 115 116 printk("%sCall Trace:", loglvl); 117 #ifdef CONFIG_KALLSYMS 118 printk("%s\n", loglvl); 119 #endif 120 while (!kstack_end(sp)) { 121 unsigned long __user *p = 122 (unsigned long __user *)(unsigned long)sp++; 123 if (__get_user(addr, p)) { 124 printk("%s (Bad stack address)", loglvl); 125 break; 126 } 127 if (__kernel_text_address(addr)) 128 print_ip_sym(loglvl, addr); 129 } 130 printk("%s\n", loglvl); 131 } 132 133 #ifdef CONFIG_KALLSYMS 134 int raw_show_trace; 135 static int __init set_raw_show_trace(char *str) 136 { 137 raw_show_trace = 1; 138 return 1; 139 } 140 __setup("raw_show_trace", set_raw_show_trace); 141 #endif 142 143 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs, 144 const char *loglvl) 145 { 146 unsigned long sp = regs->regs[29]; 147 unsigned long ra = regs->regs[31]; 148 unsigned long pc = regs->cp0_epc; 149 150 if (!task) 151 task = current; 152 153 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) { 154 show_raw_backtrace(sp, loglvl); 155 return; 156 } 157 printk("%sCall Trace:\n", loglvl); 158 do { 159 print_ip_sym(loglvl, pc); 160 pc = unwind_stack(task, &sp, pc, &ra); 161 } while (pc); 162 pr_cont("\n"); 163 } 164 165 /* 166 * This routine abuses get_user()/put_user() to reference pointers 167 * with at least a bit of error checking ... 168 */ 169 static void show_stacktrace(struct task_struct *task, 170 const struct pt_regs *regs, const char *loglvl) 171 { 172 const int field = 2 * sizeof(unsigned long); 173 long stackdata; 174 int i; 175 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 176 177 printk("%sStack :", loglvl); 178 i = 0; 179 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 180 if (i && ((i % (64 / field)) == 0)) { 181 pr_cont("\n"); 182 printk("%s ", loglvl); 183 } 184 if (i > 39) { 185 pr_cont(" ..."); 186 break; 187 } 188 189 if (__get_user(stackdata, sp++)) { 190 pr_cont(" (Bad stack address)"); 191 break; 192 } 193 194 pr_cont(" %0*lx", field, stackdata); 195 i++; 196 } 197 pr_cont("\n"); 198 show_backtrace(task, regs, loglvl); 199 } 200 201 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl) 202 { 203 struct pt_regs regs; 204 mm_segment_t old_fs = get_fs(); 205 206 regs.cp0_status = KSU_KERNEL; 207 if (sp) { 208 regs.regs[29] = (unsigned long)sp; 209 regs.regs[31] = 0; 210 regs.cp0_epc = 0; 211 } else { 212 if (task && task != current) { 213 regs.regs[29] = task->thread.reg29; 214 regs.regs[31] = 0; 215 regs.cp0_epc = task->thread.reg31; 216 } else { 217 prepare_frametrace(®s); 218 } 219 } 220 /* 221 * show_stack() deals exclusively with kernel mode, so be sure to access 222 * the stack in the kernel (not user) address space. 223 */ 224 set_fs(KERNEL_DS); 225 show_stacktrace(task, ®s, loglvl); 226 set_fs(old_fs); 227 } 228 229 static void show_code(unsigned int __user *pc) 230 { 231 long i; 232 unsigned short __user *pc16 = NULL; 233 234 printk("Code:"); 235 236 if ((unsigned long)pc & 1) 237 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 238 for(i = -3 ; i < 6 ; i++) { 239 unsigned int insn; 240 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 241 pr_cont(" (Bad address in epc)\n"); 242 break; 243 } 244 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 245 } 246 pr_cont("\n"); 247 } 248 249 static void __show_regs(const struct pt_regs *regs) 250 { 251 const int field = 2 * sizeof(unsigned long); 252 unsigned int cause = regs->cp0_cause; 253 unsigned int exccode; 254 int i; 255 256 show_regs_print_info(KERN_DEFAULT); 257 258 /* 259 * Saved main processor registers 260 */ 261 for (i = 0; i < 32; ) { 262 if ((i % 4) == 0) 263 printk("$%2d :", i); 264 if (i == 0) 265 pr_cont(" %0*lx", field, 0UL); 266 else if (i == 26 || i == 27) 267 pr_cont(" %*s", field, ""); 268 else 269 pr_cont(" %0*lx", field, regs->regs[i]); 270 271 i++; 272 if ((i % 4) == 0) 273 pr_cont("\n"); 274 } 275 276 #ifdef CONFIG_CPU_HAS_SMARTMIPS 277 printk("Acx : %0*lx\n", field, regs->acx); 278 #endif 279 if (MIPS_ISA_REV < 6) { 280 printk("Hi : %0*lx\n", field, regs->hi); 281 printk("Lo : %0*lx\n", field, regs->lo); 282 } 283 284 /* 285 * Saved cp0 registers 286 */ 287 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 288 (void *) regs->cp0_epc); 289 printk("ra : %0*lx %pS\n", field, regs->regs[31], 290 (void *) regs->regs[31]); 291 292 printk("Status: %08x ", (uint32_t) regs->cp0_status); 293 294 if (cpu_has_3kex) { 295 if (regs->cp0_status & ST0_KUO) 296 pr_cont("KUo "); 297 if (regs->cp0_status & ST0_IEO) 298 pr_cont("IEo "); 299 if (regs->cp0_status & ST0_KUP) 300 pr_cont("KUp "); 301 if (regs->cp0_status & ST0_IEP) 302 pr_cont("IEp "); 303 if (regs->cp0_status & ST0_KUC) 304 pr_cont("KUc "); 305 if (regs->cp0_status & ST0_IEC) 306 pr_cont("IEc "); 307 } else if (cpu_has_4kex) { 308 if (regs->cp0_status & ST0_KX) 309 pr_cont("KX "); 310 if (regs->cp0_status & ST0_SX) 311 pr_cont("SX "); 312 if (regs->cp0_status & ST0_UX) 313 pr_cont("UX "); 314 switch (regs->cp0_status & ST0_KSU) { 315 case KSU_USER: 316 pr_cont("USER "); 317 break; 318 case KSU_SUPERVISOR: 319 pr_cont("SUPERVISOR "); 320 break; 321 case KSU_KERNEL: 322 pr_cont("KERNEL "); 323 break; 324 default: 325 pr_cont("BAD_MODE "); 326 break; 327 } 328 if (regs->cp0_status & ST0_ERL) 329 pr_cont("ERL "); 330 if (regs->cp0_status & ST0_EXL) 331 pr_cont("EXL "); 332 if (regs->cp0_status & ST0_IE) 333 pr_cont("IE "); 334 } 335 pr_cont("\n"); 336 337 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 338 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode); 339 340 if (1 <= exccode && exccode <= 5) 341 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 342 343 printk("PrId : %08x (%s)\n", read_c0_prid(), 344 cpu_name_string()); 345 } 346 347 /* 348 * FIXME: really the generic show_regs should take a const pointer argument. 349 */ 350 void show_regs(struct pt_regs *regs) 351 { 352 __show_regs(regs); 353 dump_stack(); 354 } 355 356 void show_registers(struct pt_regs *regs) 357 { 358 const int field = 2 * sizeof(unsigned long); 359 mm_segment_t old_fs = get_fs(); 360 361 __show_regs(regs); 362 print_modules(); 363 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 364 current->comm, current->pid, current_thread_info(), current, 365 field, current_thread_info()->tp_value); 366 if (cpu_has_userlocal) { 367 unsigned long tls; 368 369 tls = read_c0_userlocal(); 370 if (tls != current_thread_info()->tp_value) 371 printk("*HwTLS: %0*lx\n", field, tls); 372 } 373 374 if (!user_mode(regs)) 375 /* Necessary for getting the correct stack content */ 376 set_fs(KERNEL_DS); 377 show_stacktrace(current, regs, KERN_DEFAULT); 378 show_code((unsigned int __user *) regs->cp0_epc); 379 printk("\n"); 380 set_fs(old_fs); 381 } 382 383 static DEFINE_RAW_SPINLOCK(die_lock); 384 385 void __noreturn die(const char *str, struct pt_regs *regs) 386 { 387 static int die_counter; 388 int sig = SIGSEGV; 389 390 oops_enter(); 391 392 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, 393 SIGSEGV) == NOTIFY_STOP) 394 sig = 0; 395 396 console_verbose(); 397 raw_spin_lock_irq(&die_lock); 398 bust_spinlocks(1); 399 400 printk("%s[#%d]:\n", str, ++die_counter); 401 show_registers(regs); 402 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 403 raw_spin_unlock_irq(&die_lock); 404 405 oops_exit(); 406 407 if (in_interrupt()) 408 panic("Fatal exception in interrupt"); 409 410 if (panic_on_oops) 411 panic("Fatal exception"); 412 413 if (regs && kexec_should_crash(current)) 414 crash_kexec(regs); 415 416 do_exit(sig); 417 } 418 419 extern struct exception_table_entry __start___dbe_table[]; 420 extern struct exception_table_entry __stop___dbe_table[]; 421 422 __asm__( 423 " .section __dbe_table, \"a\"\n" 424 " .previous \n"); 425 426 /* Given an address, look for it in the exception tables. */ 427 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 428 { 429 const struct exception_table_entry *e; 430 431 e = search_extable(__start___dbe_table, 432 __stop___dbe_table - __start___dbe_table, addr); 433 if (!e) 434 e = search_module_dbetables(addr); 435 return e; 436 } 437 438 asmlinkage void do_be(struct pt_regs *regs) 439 { 440 const int field = 2 * sizeof(unsigned long); 441 const struct exception_table_entry *fixup = NULL; 442 int data = regs->cp0_cause & 4; 443 int action = MIPS_BE_FATAL; 444 enum ctx_state prev_state; 445 446 prev_state = exception_enter(); 447 /* XXX For now. Fixme, this searches the wrong table ... */ 448 if (data && !user_mode(regs)) 449 fixup = search_dbe_tables(exception_epc(regs)); 450 451 if (fixup) 452 action = MIPS_BE_FIXUP; 453 454 if (board_be_handler) 455 action = board_be_handler(regs, fixup != NULL); 456 else 457 mips_cm_error_report(); 458 459 switch (action) { 460 case MIPS_BE_DISCARD: 461 goto out; 462 case MIPS_BE_FIXUP: 463 if (fixup) { 464 regs->cp0_epc = fixup->nextinsn; 465 goto out; 466 } 467 break; 468 default: 469 break; 470 } 471 472 /* 473 * Assume it would be too dangerous to continue ... 474 */ 475 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 476 data ? "Data" : "Instruction", 477 field, regs->cp0_epc, field, regs->regs[31]); 478 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr, 479 SIGBUS) == NOTIFY_STOP) 480 goto out; 481 482 die_if_kernel("Oops", regs); 483 force_sig(SIGBUS); 484 485 out: 486 exception_exit(prev_state); 487 } 488 489 /* 490 * ll/sc, rdhwr, sync emulation 491 */ 492 493 #define OPCODE 0xfc000000 494 #define BASE 0x03e00000 495 #define RT 0x001f0000 496 #define OFFSET 0x0000ffff 497 #define LL 0xc0000000 498 #define SC 0xe0000000 499 #define SPEC0 0x00000000 500 #define SPEC3 0x7c000000 501 #define RD 0x0000f800 502 #define FUNC 0x0000003f 503 #define SYNC 0x0000000f 504 #define RDHWR 0x0000003b 505 506 /* microMIPS definitions */ 507 #define MM_POOL32A_FUNC 0xfc00ffff 508 #define MM_RDHWR 0x00006b3c 509 #define MM_RS 0x001f0000 510 #define MM_RT 0x03e00000 511 512 /* 513 * The ll_bit is cleared by r*_switch.S 514 */ 515 516 unsigned int ll_bit; 517 struct task_struct *ll_task; 518 519 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 520 { 521 unsigned long value, __user *vaddr; 522 long offset; 523 524 /* 525 * analyse the ll instruction that just caused a ri exception 526 * and put the referenced address to addr. 527 */ 528 529 /* sign extend offset */ 530 offset = opcode & OFFSET; 531 offset <<= 16; 532 offset >>= 16; 533 534 vaddr = (unsigned long __user *) 535 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 536 537 if ((unsigned long)vaddr & 3) 538 return SIGBUS; 539 if (get_user(value, vaddr)) 540 return SIGSEGV; 541 542 preempt_disable(); 543 544 if (ll_task == NULL || ll_task == current) { 545 ll_bit = 1; 546 } else { 547 ll_bit = 0; 548 } 549 ll_task = current; 550 551 preempt_enable(); 552 553 regs->regs[(opcode & RT) >> 16] = value; 554 555 return 0; 556 } 557 558 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 559 { 560 unsigned long __user *vaddr; 561 unsigned long reg; 562 long offset; 563 564 /* 565 * analyse the sc instruction that just caused a ri exception 566 * and put the referenced address to addr. 567 */ 568 569 /* sign extend offset */ 570 offset = opcode & OFFSET; 571 offset <<= 16; 572 offset >>= 16; 573 574 vaddr = (unsigned long __user *) 575 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 576 reg = (opcode & RT) >> 16; 577 578 if ((unsigned long)vaddr & 3) 579 return SIGBUS; 580 581 preempt_disable(); 582 583 if (ll_bit == 0 || ll_task != current) { 584 regs->regs[reg] = 0; 585 preempt_enable(); 586 return 0; 587 } 588 589 preempt_enable(); 590 591 if (put_user(regs->regs[reg], vaddr)) 592 return SIGSEGV; 593 594 regs->regs[reg] = 1; 595 596 return 0; 597 } 598 599 /* 600 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 601 * opcodes are supposed to result in coprocessor unusable exceptions if 602 * executed on ll/sc-less processors. That's the theory. In practice a 603 * few processors such as NEC's VR4100 throw reserved instruction exceptions 604 * instead, so we're doing the emulation thing in both exception handlers. 605 */ 606 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 607 { 608 if ((opcode & OPCODE) == LL) { 609 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 610 1, regs, 0); 611 return simulate_ll(regs, opcode); 612 } 613 if ((opcode & OPCODE) == SC) { 614 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 615 1, regs, 0); 616 return simulate_sc(regs, opcode); 617 } 618 619 return -1; /* Must be something else ... */ 620 } 621 622 /* 623 * Simulate trapping 'rdhwr' instructions to provide user accessible 624 * registers not implemented in hardware. 625 */ 626 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) 627 { 628 struct thread_info *ti = task_thread_info(current); 629 630 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 631 1, regs, 0); 632 switch (rd) { 633 case MIPS_HWR_CPUNUM: /* CPU number */ 634 regs->regs[rt] = smp_processor_id(); 635 return 0; 636 case MIPS_HWR_SYNCISTEP: /* SYNCI length */ 637 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 638 current_cpu_data.icache.linesz); 639 return 0; 640 case MIPS_HWR_CC: /* Read count register */ 641 regs->regs[rt] = read_c0_count(); 642 return 0; 643 case MIPS_HWR_CCRES: /* Count register resolution */ 644 switch (current_cpu_type()) { 645 case CPU_20KC: 646 case CPU_25KF: 647 regs->regs[rt] = 1; 648 break; 649 default: 650 regs->regs[rt] = 2; 651 } 652 return 0; 653 case MIPS_HWR_ULR: /* Read UserLocal register */ 654 regs->regs[rt] = ti->tp_value; 655 return 0; 656 default: 657 return -1; 658 } 659 } 660 661 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) 662 { 663 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 664 int rd = (opcode & RD) >> 11; 665 int rt = (opcode & RT) >> 16; 666 667 simulate_rdhwr(regs, rd, rt); 668 return 0; 669 } 670 671 /* Not ours. */ 672 return -1; 673 } 674 675 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode) 676 { 677 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { 678 int rd = (opcode & MM_RS) >> 16; 679 int rt = (opcode & MM_RT) >> 21; 680 simulate_rdhwr(regs, rd, rt); 681 return 0; 682 } 683 684 /* Not ours. */ 685 return -1; 686 } 687 688 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 689 { 690 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 691 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 692 1, regs, 0); 693 return 0; 694 } 695 696 return -1; /* Must be something else ... */ 697 } 698 699 /* 700 * Loongson-3 CSR instructions emulation 701 */ 702 703 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION 704 705 #define LWC2 0xc8000000 706 #define RS BASE 707 #define CSR_OPCODE2 0x00000118 708 #define CSR_OPCODE2_MASK 0x000007ff 709 #define CSR_FUNC_MASK RT 710 #define CSR_FUNC_CPUCFG 0x8 711 712 static int simulate_loongson3_cpucfg(struct pt_regs *regs, 713 unsigned int opcode) 714 { 715 int op = opcode & OPCODE; 716 int op2 = opcode & CSR_OPCODE2_MASK; 717 int csr_func = (opcode & CSR_FUNC_MASK) >> 16; 718 719 if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) { 720 int rd = (opcode & RD) >> 11; 721 int rs = (opcode & RS) >> 21; 722 __u64 sel = regs->regs[rs]; 723 724 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); 725 726 /* Do not emulate on unsupported core models. */ 727 preempt_disable(); 728 if (!loongson3_cpucfg_emulation_enabled(¤t_cpu_data)) { 729 preempt_enable(); 730 return -1; 731 } 732 regs->regs[rd] = loongson3_cpucfg_read_synthesized( 733 ¤t_cpu_data, sel); 734 preempt_enable(); 735 return 0; 736 } 737 738 /* Not ours. */ 739 return -1; 740 } 741 #endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */ 742 743 asmlinkage void do_ov(struct pt_regs *regs) 744 { 745 enum ctx_state prev_state; 746 747 prev_state = exception_enter(); 748 die_if_kernel("Integer overflow", regs); 749 750 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc); 751 exception_exit(prev_state); 752 } 753 754 #ifdef CONFIG_MIPS_FP_SUPPORT 755 756 /* 757 * Send SIGFPE according to FCSR Cause bits, which must have already 758 * been masked against Enable bits. This is impotant as Inexact can 759 * happen together with Overflow or Underflow, and `ptrace' can set 760 * any bits. 761 */ 762 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr, 763 struct task_struct *tsk) 764 { 765 int si_code = FPE_FLTUNK; 766 767 if (fcr31 & FPU_CSR_INV_X) 768 si_code = FPE_FLTINV; 769 else if (fcr31 & FPU_CSR_DIV_X) 770 si_code = FPE_FLTDIV; 771 else if (fcr31 & FPU_CSR_OVF_X) 772 si_code = FPE_FLTOVF; 773 else if (fcr31 & FPU_CSR_UDF_X) 774 si_code = FPE_FLTUND; 775 else if (fcr31 & FPU_CSR_INE_X) 776 si_code = FPE_FLTRES; 777 778 force_sig_fault_to_task(SIGFPE, si_code, fault_addr, tsk); 779 } 780 781 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31) 782 { 783 int si_code; 784 struct vm_area_struct *vma; 785 786 switch (sig) { 787 case 0: 788 return 0; 789 790 case SIGFPE: 791 force_fcr31_sig(fcr31, fault_addr, current); 792 return 1; 793 794 case SIGBUS: 795 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr); 796 return 1; 797 798 case SIGSEGV: 799 mmap_read_lock(current->mm); 800 vma = find_vma(current->mm, (unsigned long)fault_addr); 801 if (vma && (vma->vm_start <= (unsigned long)fault_addr)) 802 si_code = SEGV_ACCERR; 803 else 804 si_code = SEGV_MAPERR; 805 mmap_read_unlock(current->mm); 806 force_sig_fault(SIGSEGV, si_code, fault_addr); 807 return 1; 808 809 default: 810 force_sig(sig); 811 return 1; 812 } 813 } 814 815 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 816 unsigned long old_epc, unsigned long old_ra) 817 { 818 union mips_instruction inst = { .word = opcode }; 819 void __user *fault_addr; 820 unsigned long fcr31; 821 int sig; 822 823 /* If it's obviously not an FP instruction, skip it */ 824 switch (inst.i_format.opcode) { 825 case cop1_op: 826 case cop1x_op: 827 case lwc1_op: 828 case ldc1_op: 829 case swc1_op: 830 case sdc1_op: 831 break; 832 833 default: 834 return -1; 835 } 836 837 /* 838 * do_ri skipped over the instruction via compute_return_epc, undo 839 * that for the FPU emulator. 840 */ 841 regs->cp0_epc = old_epc; 842 regs->regs[31] = old_ra; 843 844 /* Run the emulator */ 845 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 846 &fault_addr); 847 848 /* 849 * We can't allow the emulated instruction to leave any 850 * enabled Cause bits set in $fcr31. 851 */ 852 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 853 current->thread.fpu.fcr31 &= ~fcr31; 854 855 /* Restore the hardware register state */ 856 own_fpu(1); 857 858 /* Send a signal if required. */ 859 process_fpemu_return(sig, fault_addr, fcr31); 860 861 return 0; 862 } 863 864 /* 865 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 866 */ 867 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 868 { 869 enum ctx_state prev_state; 870 void __user *fault_addr; 871 int sig; 872 873 prev_state = exception_enter(); 874 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, 875 SIGFPE) == NOTIFY_STOP) 876 goto out; 877 878 /* Clear FCSR.Cause before enabling interrupts */ 879 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31)); 880 local_irq_enable(); 881 882 die_if_kernel("FP exception in kernel code", regs); 883 884 if (fcr31 & FPU_CSR_UNI_X) { 885 /* 886 * Unimplemented operation exception. If we've got the full 887 * software emulator on-board, let's use it... 888 * 889 * Force FPU to dump state into task/thread context. We're 890 * moving a lot of data here for what is probably a single 891 * instruction, but the alternative is to pre-decode the FP 892 * register operands before invoking the emulator, which seems 893 * a bit extreme for what should be an infrequent event. 894 */ 895 896 /* Run the emulator */ 897 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 898 &fault_addr); 899 900 /* 901 * We can't allow the emulated instruction to leave any 902 * enabled Cause bits set in $fcr31. 903 */ 904 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 905 current->thread.fpu.fcr31 &= ~fcr31; 906 907 /* Restore the hardware register state */ 908 own_fpu(1); /* Using the FPU again. */ 909 } else { 910 sig = SIGFPE; 911 fault_addr = (void __user *) regs->cp0_epc; 912 } 913 914 /* Send a signal if required. */ 915 process_fpemu_return(sig, fault_addr, fcr31); 916 917 out: 918 exception_exit(prev_state); 919 } 920 921 /* 922 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 923 * emulated more than some threshold number of instructions, force migration to 924 * a "CPU" that has FP support. 925 */ 926 static void mt_ase_fp_affinity(void) 927 { 928 #ifdef CONFIG_MIPS_MT_FPAFF 929 if (mt_fpemul_threshold > 0 && 930 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 931 /* 932 * If there's no FPU present, or if the application has already 933 * restricted the allowed set to exclude any CPUs with FPUs, 934 * we'll skip the procedure. 935 */ 936 if (cpumask_intersects(¤t->cpus_mask, &mt_fpu_cpumask)) { 937 cpumask_t tmask; 938 939 current->thread.user_cpus_allowed 940 = current->cpus_mask; 941 cpumask_and(&tmask, ¤t->cpus_mask, 942 &mt_fpu_cpumask); 943 set_cpus_allowed_ptr(current, &tmask); 944 set_thread_flag(TIF_FPUBOUND); 945 } 946 } 947 #endif /* CONFIG_MIPS_MT_FPAFF */ 948 } 949 950 #else /* !CONFIG_MIPS_FP_SUPPORT */ 951 952 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 953 unsigned long old_epc, unsigned long old_ra) 954 { 955 return -1; 956 } 957 958 #endif /* !CONFIG_MIPS_FP_SUPPORT */ 959 960 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code, 961 const char *str) 962 { 963 char b[40]; 964 965 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 966 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr, 967 SIGTRAP) == NOTIFY_STOP) 968 return; 969 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 970 971 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr, 972 SIGTRAP) == NOTIFY_STOP) 973 return; 974 975 /* 976 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 977 * insns, even for trap and break codes that indicate arithmetic 978 * failures. Weird ... 979 * But should we continue the brokenness??? --macro 980 */ 981 switch (code) { 982 case BRK_OVERFLOW: 983 case BRK_DIVZERO: 984 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 985 die_if_kernel(b, regs); 986 force_sig_fault(SIGFPE, 987 code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF, 988 (void __user *) regs->cp0_epc); 989 break; 990 case BRK_BUG: 991 die_if_kernel("Kernel bug detected", regs); 992 force_sig(SIGTRAP); 993 break; 994 case BRK_MEMU: 995 /* 996 * This breakpoint code is used by the FPU emulator to retake 997 * control of the CPU after executing the instruction from the 998 * delay slot of an emulated branch. 999 * 1000 * Terminate if exception was recognized as a delay slot return 1001 * otherwise handle as normal. 1002 */ 1003 if (do_dsemulret(regs)) 1004 return; 1005 1006 die_if_kernel("Math emu break/trap", regs); 1007 force_sig(SIGTRAP); 1008 break; 1009 default: 1010 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 1011 die_if_kernel(b, regs); 1012 if (si_code) { 1013 force_sig_fault(SIGTRAP, si_code, NULL); 1014 } else { 1015 force_sig(SIGTRAP); 1016 } 1017 } 1018 } 1019 1020 asmlinkage void do_bp(struct pt_regs *regs) 1021 { 1022 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 1023 unsigned int opcode, bcode; 1024 enum ctx_state prev_state; 1025 mm_segment_t seg; 1026 1027 seg = get_fs(); 1028 if (!user_mode(regs)) 1029 set_fs(KERNEL_DS); 1030 1031 prev_state = exception_enter(); 1032 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1033 if (get_isa16_mode(regs->cp0_epc)) { 1034 u16 instr[2]; 1035 1036 if (__get_user(instr[0], (u16 __user *)epc)) 1037 goto out_sigsegv; 1038 1039 if (!cpu_has_mmips) { 1040 /* MIPS16e mode */ 1041 bcode = (instr[0] >> 5) & 0x3f; 1042 } else if (mm_insn_16bit(instr[0])) { 1043 /* 16-bit microMIPS BREAK */ 1044 bcode = instr[0] & 0xf; 1045 } else { 1046 /* 32-bit microMIPS BREAK */ 1047 if (__get_user(instr[1], (u16 __user *)(epc + 2))) 1048 goto out_sigsegv; 1049 opcode = (instr[0] << 16) | instr[1]; 1050 bcode = (opcode >> 6) & ((1 << 20) - 1); 1051 } 1052 } else { 1053 if (__get_user(opcode, (unsigned int __user *)epc)) 1054 goto out_sigsegv; 1055 bcode = (opcode >> 6) & ((1 << 20) - 1); 1056 } 1057 1058 /* 1059 * There is the ancient bug in the MIPS assemblers that the break 1060 * code starts left to bit 16 instead to bit 6 in the opcode. 1061 * Gas is bug-compatible, but not always, grrr... 1062 * We handle both cases with a simple heuristics. --macro 1063 */ 1064 if (bcode >= (1 << 10)) 1065 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10); 1066 1067 /* 1068 * notify the kprobe handlers, if instruction is likely to 1069 * pertain to them. 1070 */ 1071 switch (bcode) { 1072 case BRK_UPROBE: 1073 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode, 1074 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1075 goto out; 1076 else 1077 break; 1078 case BRK_UPROBE_XOL: 1079 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode, 1080 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1081 goto out; 1082 else 1083 break; 1084 case BRK_KPROBE_BP: 1085 if (notify_die(DIE_BREAK, "debug", regs, bcode, 1086 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1087 goto out; 1088 else 1089 break; 1090 case BRK_KPROBE_SSTEPBP: 1091 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 1092 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1093 goto out; 1094 else 1095 break; 1096 default: 1097 break; 1098 } 1099 1100 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break"); 1101 1102 out: 1103 set_fs(seg); 1104 exception_exit(prev_state); 1105 return; 1106 1107 out_sigsegv: 1108 force_sig(SIGSEGV); 1109 goto out; 1110 } 1111 1112 asmlinkage void do_tr(struct pt_regs *regs) 1113 { 1114 u32 opcode, tcode = 0; 1115 enum ctx_state prev_state; 1116 u16 instr[2]; 1117 mm_segment_t seg; 1118 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 1119 1120 seg = get_fs(); 1121 if (!user_mode(regs)) 1122 set_fs(KERNEL_DS); 1123 1124 prev_state = exception_enter(); 1125 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1126 if (get_isa16_mode(regs->cp0_epc)) { 1127 if (__get_user(instr[0], (u16 __user *)(epc + 0)) || 1128 __get_user(instr[1], (u16 __user *)(epc + 2))) 1129 goto out_sigsegv; 1130 opcode = (instr[0] << 16) | instr[1]; 1131 /* Immediate versions don't provide a code. */ 1132 if (!(opcode & OPCODE)) 1133 tcode = (opcode >> 12) & ((1 << 4) - 1); 1134 } else { 1135 if (__get_user(opcode, (u32 __user *)epc)) 1136 goto out_sigsegv; 1137 /* Immediate versions don't provide a code. */ 1138 if (!(opcode & OPCODE)) 1139 tcode = (opcode >> 6) & ((1 << 10) - 1); 1140 } 1141 1142 do_trap_or_bp(regs, tcode, 0, "Trap"); 1143 1144 out: 1145 set_fs(seg); 1146 exception_exit(prev_state); 1147 return; 1148 1149 out_sigsegv: 1150 force_sig(SIGSEGV); 1151 goto out; 1152 } 1153 1154 asmlinkage void do_ri(struct pt_regs *regs) 1155 { 1156 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 1157 unsigned long old_epc = regs->cp0_epc; 1158 unsigned long old31 = regs->regs[31]; 1159 enum ctx_state prev_state; 1160 unsigned int opcode = 0; 1161 int status = -1; 1162 1163 /* 1164 * Avoid any kernel code. Just emulate the R2 instruction 1165 * as quickly as possible. 1166 */ 1167 if (mipsr2_emulation && cpu_has_mips_r6 && 1168 likely(user_mode(regs)) && 1169 likely(get_user(opcode, epc) >= 0)) { 1170 unsigned long fcr31 = 0; 1171 1172 status = mipsr2_decoder(regs, opcode, &fcr31); 1173 switch (status) { 1174 case 0: 1175 case SIGEMT: 1176 return; 1177 case SIGILL: 1178 goto no_r2_instr; 1179 default: 1180 process_fpemu_return(status, 1181 ¤t->thread.cp0_baduaddr, 1182 fcr31); 1183 return; 1184 } 1185 } 1186 1187 no_r2_instr: 1188 1189 prev_state = exception_enter(); 1190 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1191 1192 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, 1193 SIGILL) == NOTIFY_STOP) 1194 goto out; 1195 1196 die_if_kernel("Reserved instruction in kernel code", regs); 1197 1198 if (unlikely(compute_return_epc(regs) < 0)) 1199 goto out; 1200 1201 if (!get_isa16_mode(regs->cp0_epc)) { 1202 if (unlikely(get_user(opcode, epc) < 0)) 1203 status = SIGSEGV; 1204 1205 if (!cpu_has_llsc && status < 0) 1206 status = simulate_llsc(regs, opcode); 1207 1208 if (status < 0) 1209 status = simulate_rdhwr_normal(regs, opcode); 1210 1211 if (status < 0) 1212 status = simulate_sync(regs, opcode); 1213 1214 if (status < 0) 1215 status = simulate_fp(regs, opcode, old_epc, old31); 1216 1217 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION 1218 if (status < 0) 1219 status = simulate_loongson3_cpucfg(regs, opcode); 1220 #endif 1221 } else if (cpu_has_mmips) { 1222 unsigned short mmop[2] = { 0 }; 1223 1224 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0)) 1225 status = SIGSEGV; 1226 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0)) 1227 status = SIGSEGV; 1228 opcode = mmop[0]; 1229 opcode = (opcode << 16) | mmop[1]; 1230 1231 if (status < 0) 1232 status = simulate_rdhwr_mm(regs, opcode); 1233 } 1234 1235 if (status < 0) 1236 status = SIGILL; 1237 1238 if (unlikely(status > 0)) { 1239 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1240 regs->regs[31] = old31; 1241 force_sig(status); 1242 } 1243 1244 out: 1245 exception_exit(prev_state); 1246 } 1247 1248 /* 1249 * No lock; only written during early bootup by CPU 0. 1250 */ 1251 static RAW_NOTIFIER_HEAD(cu2_chain); 1252 1253 int __ref register_cu2_notifier(struct notifier_block *nb) 1254 { 1255 return raw_notifier_chain_register(&cu2_chain, nb); 1256 } 1257 1258 int cu2_notifier_call_chain(unsigned long val, void *v) 1259 { 1260 return raw_notifier_call_chain(&cu2_chain, val, v); 1261 } 1262 1263 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 1264 void *data) 1265 { 1266 struct pt_regs *regs = data; 1267 1268 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " 1269 "instruction", regs); 1270 force_sig(SIGILL); 1271 1272 return NOTIFY_OK; 1273 } 1274 1275 #ifdef CONFIG_MIPS_FP_SUPPORT 1276 1277 static int enable_restore_fp_context(int msa) 1278 { 1279 int err, was_fpu_owner, prior_msa; 1280 bool first_fp; 1281 1282 /* Initialize context if it hasn't been used already */ 1283 first_fp = init_fp_ctx(current); 1284 1285 if (first_fp) { 1286 preempt_disable(); 1287 err = own_fpu_inatomic(1); 1288 if (msa && !err) { 1289 enable_msa(); 1290 /* 1291 * with MSA enabled, userspace can see MSACSR 1292 * and MSA regs, but the values in them are from 1293 * other task before current task, restore them 1294 * from saved fp/msa context 1295 */ 1296 write_msa_csr(current->thread.fpu.msacsr); 1297 /* 1298 * own_fpu_inatomic(1) just restore low 64bit, 1299 * fix the high 64bit 1300 */ 1301 init_msa_upper(); 1302 set_thread_flag(TIF_USEDMSA); 1303 set_thread_flag(TIF_MSA_CTX_LIVE); 1304 } 1305 preempt_enable(); 1306 return err; 1307 } 1308 1309 /* 1310 * This task has formerly used the FP context. 1311 * 1312 * If this thread has no live MSA vector context then we can simply 1313 * restore the scalar FP context. If it has live MSA vector context 1314 * (that is, it has or may have used MSA since last performing a 1315 * function call) then we'll need to restore the vector context. This 1316 * applies even if we're currently only executing a scalar FP 1317 * instruction. This is because if we were to later execute an MSA 1318 * instruction then we'd either have to: 1319 * 1320 * - Restore the vector context & clobber any registers modified by 1321 * scalar FP instructions between now & then. 1322 * 1323 * or 1324 * 1325 * - Not restore the vector context & lose the most significant bits 1326 * of all vector registers. 1327 * 1328 * Neither of those options is acceptable. We cannot restore the least 1329 * significant bits of the registers now & only restore the most 1330 * significant bits later because the most significant bits of any 1331 * vector registers whose aliased FP register is modified now will have 1332 * been zeroed. We'd have no way to know that when restoring the vector 1333 * context & thus may load an outdated value for the most significant 1334 * bits of a vector register. 1335 */ 1336 if (!msa && !thread_msa_context_live()) 1337 return own_fpu(1); 1338 1339 /* 1340 * This task is using or has previously used MSA. Thus we require 1341 * that Status.FR == 1. 1342 */ 1343 preempt_disable(); 1344 was_fpu_owner = is_fpu_owner(); 1345 err = own_fpu_inatomic(0); 1346 if (err) 1347 goto out; 1348 1349 enable_msa(); 1350 write_msa_csr(current->thread.fpu.msacsr); 1351 set_thread_flag(TIF_USEDMSA); 1352 1353 /* 1354 * If this is the first time that the task is using MSA and it has 1355 * previously used scalar FP in this time slice then we already nave 1356 * FP context which we shouldn't clobber. We do however need to clear 1357 * the upper 64b of each vector register so that this task has no 1358 * opportunity to see data left behind by another. 1359 */ 1360 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); 1361 if (!prior_msa && was_fpu_owner) { 1362 init_msa_upper(); 1363 1364 goto out; 1365 } 1366 1367 if (!prior_msa) { 1368 /* 1369 * Restore the least significant 64b of each vector register 1370 * from the existing scalar FP context. 1371 */ 1372 _restore_fp(current); 1373 1374 /* 1375 * The task has not formerly used MSA, so clear the upper 64b 1376 * of each vector register such that it cannot see data left 1377 * behind by another task. 1378 */ 1379 init_msa_upper(); 1380 } else { 1381 /* We need to restore the vector context. */ 1382 restore_msa(current); 1383 1384 /* Restore the scalar FP control & status register */ 1385 if (!was_fpu_owner) 1386 write_32bit_cp1_register(CP1_STATUS, 1387 current->thread.fpu.fcr31); 1388 } 1389 1390 out: 1391 preempt_enable(); 1392 1393 return 0; 1394 } 1395 1396 #else /* !CONFIG_MIPS_FP_SUPPORT */ 1397 1398 static int enable_restore_fp_context(int msa) 1399 { 1400 return SIGILL; 1401 } 1402 1403 #endif /* CONFIG_MIPS_FP_SUPPORT */ 1404 1405 asmlinkage void do_cpu(struct pt_regs *regs) 1406 { 1407 enum ctx_state prev_state; 1408 unsigned int __user *epc; 1409 unsigned long old_epc, old31; 1410 unsigned int opcode; 1411 unsigned int cpid; 1412 int status; 1413 1414 prev_state = exception_enter(); 1415 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1416 1417 if (cpid != 2) 1418 die_if_kernel("do_cpu invoked from kernel context!", regs); 1419 1420 switch (cpid) { 1421 case 0: 1422 epc = (unsigned int __user *)exception_epc(regs); 1423 old_epc = regs->cp0_epc; 1424 old31 = regs->regs[31]; 1425 opcode = 0; 1426 status = -1; 1427 1428 if (unlikely(compute_return_epc(regs) < 0)) 1429 break; 1430 1431 if (!get_isa16_mode(regs->cp0_epc)) { 1432 if (unlikely(get_user(opcode, epc) < 0)) 1433 status = SIGSEGV; 1434 1435 if (!cpu_has_llsc && status < 0) 1436 status = simulate_llsc(regs, opcode); 1437 } 1438 1439 if (status < 0) 1440 status = SIGILL; 1441 1442 if (unlikely(status > 0)) { 1443 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1444 regs->regs[31] = old31; 1445 force_sig(status); 1446 } 1447 1448 break; 1449 1450 #ifdef CONFIG_MIPS_FP_SUPPORT 1451 case 3: 1452 /* 1453 * The COP3 opcode space and consequently the CP0.Status.CU3 1454 * bit and the CP0.Cause.CE=3 encoding have been removed as 1455 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs 1456 * up the space has been reused for COP1X instructions, that 1457 * are enabled by the CP0.Status.CU1 bit and consequently 1458 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable 1459 * exceptions. Some FPU-less processors that implement one 1460 * of these ISAs however use this code erroneously for COP1X 1461 * instructions. Therefore we redirect this trap to the FP 1462 * emulator too. 1463 */ 1464 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) { 1465 force_sig(SIGILL); 1466 break; 1467 } 1468 fallthrough; 1469 case 1: { 1470 void __user *fault_addr; 1471 unsigned long fcr31; 1472 int err, sig; 1473 1474 err = enable_restore_fp_context(0); 1475 1476 if (raw_cpu_has_fpu && !err) 1477 break; 1478 1479 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, 1480 &fault_addr); 1481 1482 /* 1483 * We can't allow the emulated instruction to leave 1484 * any enabled Cause bits set in $fcr31. 1485 */ 1486 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 1487 current->thread.fpu.fcr31 &= ~fcr31; 1488 1489 /* Send a signal if required. */ 1490 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err) 1491 mt_ase_fp_affinity(); 1492 1493 break; 1494 } 1495 #else /* CONFIG_MIPS_FP_SUPPORT */ 1496 case 1: 1497 case 3: 1498 force_sig(SIGILL); 1499 break; 1500 #endif /* CONFIG_MIPS_FP_SUPPORT */ 1501 1502 case 2: 1503 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1504 break; 1505 } 1506 1507 exception_exit(prev_state); 1508 } 1509 1510 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr) 1511 { 1512 enum ctx_state prev_state; 1513 1514 prev_state = exception_enter(); 1515 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1516 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0, 1517 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP) 1518 goto out; 1519 1520 /* Clear MSACSR.Cause before enabling interrupts */ 1521 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF); 1522 local_irq_enable(); 1523 1524 die_if_kernel("do_msa_fpe invoked from kernel context!", regs); 1525 force_sig(SIGFPE); 1526 out: 1527 exception_exit(prev_state); 1528 } 1529 1530 asmlinkage void do_msa(struct pt_regs *regs) 1531 { 1532 enum ctx_state prev_state; 1533 int err; 1534 1535 prev_state = exception_enter(); 1536 1537 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { 1538 force_sig(SIGILL); 1539 goto out; 1540 } 1541 1542 die_if_kernel("do_msa invoked from kernel context!", regs); 1543 1544 err = enable_restore_fp_context(1); 1545 if (err) 1546 force_sig(SIGILL); 1547 out: 1548 exception_exit(prev_state); 1549 } 1550 1551 asmlinkage void do_mdmx(struct pt_regs *regs) 1552 { 1553 enum ctx_state prev_state; 1554 1555 prev_state = exception_enter(); 1556 force_sig(SIGILL); 1557 exception_exit(prev_state); 1558 } 1559 1560 /* 1561 * Called with interrupts disabled. 1562 */ 1563 asmlinkage void do_watch(struct pt_regs *regs) 1564 { 1565 enum ctx_state prev_state; 1566 1567 prev_state = exception_enter(); 1568 /* 1569 * Clear WP (bit 22) bit of cause register so we don't loop 1570 * forever. 1571 */ 1572 clear_c0_cause(CAUSEF_WP); 1573 1574 /* 1575 * If the current thread has the watch registers loaded, save 1576 * their values and send SIGTRAP. Otherwise another thread 1577 * left the registers set, clear them and continue. 1578 */ 1579 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1580 mips_read_watch_registers(); 1581 local_irq_enable(); 1582 force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL); 1583 } else { 1584 mips_clear_watch_registers(); 1585 local_irq_enable(); 1586 } 1587 exception_exit(prev_state); 1588 } 1589 1590 asmlinkage void do_mcheck(struct pt_regs *regs) 1591 { 1592 int multi_match = regs->cp0_status & ST0_TS; 1593 enum ctx_state prev_state; 1594 mm_segment_t old_fs = get_fs(); 1595 1596 prev_state = exception_enter(); 1597 show_regs(regs); 1598 1599 if (multi_match) { 1600 dump_tlb_regs(); 1601 pr_info("\n"); 1602 dump_tlb_all(); 1603 } 1604 1605 if (!user_mode(regs)) 1606 set_fs(KERNEL_DS); 1607 1608 show_code((unsigned int __user *) regs->cp0_epc); 1609 1610 set_fs(old_fs); 1611 1612 /* 1613 * Some chips may have other causes of machine check (e.g. SB1 1614 * graduation timer) 1615 */ 1616 panic("Caught Machine Check exception - %scaused by multiple " 1617 "matching entries in the TLB.", 1618 (multi_match) ? "" : "not "); 1619 } 1620 1621 asmlinkage void do_mt(struct pt_regs *regs) 1622 { 1623 int subcode; 1624 1625 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1626 >> VPECONTROL_EXCPT_SHIFT; 1627 switch (subcode) { 1628 case 0: 1629 printk(KERN_DEBUG "Thread Underflow\n"); 1630 break; 1631 case 1: 1632 printk(KERN_DEBUG "Thread Overflow\n"); 1633 break; 1634 case 2: 1635 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1636 break; 1637 case 3: 1638 printk(KERN_DEBUG "Gating Storage Exception\n"); 1639 break; 1640 case 4: 1641 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1642 break; 1643 case 5: 1644 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1645 break; 1646 default: 1647 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1648 subcode); 1649 break; 1650 } 1651 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1652 1653 force_sig(SIGILL); 1654 } 1655 1656 1657 asmlinkage void do_dsp(struct pt_regs *regs) 1658 { 1659 if (cpu_has_dsp) 1660 panic("Unexpected DSP exception"); 1661 1662 force_sig(SIGILL); 1663 } 1664 1665 asmlinkage void do_reserved(struct pt_regs *regs) 1666 { 1667 /* 1668 * Game over - no way to handle this if it ever occurs. Most probably 1669 * caused by a new unknown cpu type or after another deadly 1670 * hard/software error. 1671 */ 1672 show_regs(regs); 1673 panic("Caught reserved exception %ld - should not happen.", 1674 (regs->cp0_cause & 0x7f) >> 2); 1675 } 1676 1677 static int __initdata l1parity = 1; 1678 static int __init nol1parity(char *s) 1679 { 1680 l1parity = 0; 1681 return 1; 1682 } 1683 __setup("nol1par", nol1parity); 1684 static int __initdata l2parity = 1; 1685 static int __init nol2parity(char *s) 1686 { 1687 l2parity = 0; 1688 return 1; 1689 } 1690 __setup("nol2par", nol2parity); 1691 1692 /* 1693 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1694 * it different ways. 1695 */ 1696 static inline __init void parity_protection_init(void) 1697 { 1698 #define ERRCTL_PE 0x80000000 1699 #define ERRCTL_L2P 0x00800000 1700 1701 if (mips_cm_revision() >= CM_REV_CM3) { 1702 ulong gcr_ectl, cp0_ectl; 1703 1704 /* 1705 * With CM3 systems we need to ensure that the L1 & L2 1706 * parity enables are set to the same value, since this 1707 * is presumed by the hardware engineers. 1708 * 1709 * If the user disabled either of L1 or L2 ECC checking, 1710 * disable both. 1711 */ 1712 l1parity &= l2parity; 1713 l2parity &= l1parity; 1714 1715 /* Probe L1 ECC support */ 1716 cp0_ectl = read_c0_ecc(); 1717 write_c0_ecc(cp0_ectl | ERRCTL_PE); 1718 back_to_back_c0_hazard(); 1719 cp0_ectl = read_c0_ecc(); 1720 1721 /* Probe L2 ECC support */ 1722 gcr_ectl = read_gcr_err_control(); 1723 1724 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) || 1725 !(cp0_ectl & ERRCTL_PE)) { 1726 /* 1727 * One of L1 or L2 ECC checking isn't supported, 1728 * so we cannot enable either. 1729 */ 1730 l1parity = l2parity = 0; 1731 } 1732 1733 /* Configure L1 ECC checking */ 1734 if (l1parity) 1735 cp0_ectl |= ERRCTL_PE; 1736 else 1737 cp0_ectl &= ~ERRCTL_PE; 1738 write_c0_ecc(cp0_ectl); 1739 back_to_back_c0_hazard(); 1740 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity); 1741 1742 /* Configure L2 ECC checking */ 1743 if (l2parity) 1744 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN; 1745 else 1746 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN; 1747 write_gcr_err_control(gcr_ectl); 1748 gcr_ectl = read_gcr_err_control(); 1749 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN; 1750 WARN_ON(!!gcr_ectl != l2parity); 1751 1752 pr_info("Cache parity protection %sabled\n", 1753 l1parity ? "en" : "dis"); 1754 return; 1755 } 1756 1757 switch (current_cpu_type()) { 1758 case CPU_24K: 1759 case CPU_34K: 1760 case CPU_74K: 1761 case CPU_1004K: 1762 case CPU_1074K: 1763 case CPU_INTERAPTIV: 1764 case CPU_PROAPTIV: 1765 case CPU_P5600: 1766 case CPU_QEMU_GENERIC: 1767 case CPU_P6600: 1768 { 1769 unsigned long errctl; 1770 unsigned int l1parity_present, l2parity_present; 1771 1772 errctl = read_c0_ecc(); 1773 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1774 1775 /* probe L1 parity support */ 1776 write_c0_ecc(errctl | ERRCTL_PE); 1777 back_to_back_c0_hazard(); 1778 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1779 1780 /* probe L2 parity support */ 1781 write_c0_ecc(errctl|ERRCTL_L2P); 1782 back_to_back_c0_hazard(); 1783 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1784 1785 if (l1parity_present && l2parity_present) { 1786 if (l1parity) 1787 errctl |= ERRCTL_PE; 1788 if (l1parity ^ l2parity) 1789 errctl |= ERRCTL_L2P; 1790 } else if (l1parity_present) { 1791 if (l1parity) 1792 errctl |= ERRCTL_PE; 1793 } else if (l2parity_present) { 1794 if (l2parity) 1795 errctl |= ERRCTL_L2P; 1796 } else { 1797 /* No parity available */ 1798 } 1799 1800 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1801 1802 write_c0_ecc(errctl); 1803 back_to_back_c0_hazard(); 1804 errctl = read_c0_ecc(); 1805 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1806 1807 if (l1parity_present) 1808 printk(KERN_INFO "Cache parity protection %sabled\n", 1809 (errctl & ERRCTL_PE) ? "en" : "dis"); 1810 1811 if (l2parity_present) { 1812 if (l1parity_present && l1parity) 1813 errctl ^= ERRCTL_L2P; 1814 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1815 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1816 } 1817 } 1818 break; 1819 1820 case CPU_5KC: 1821 case CPU_5KE: 1822 case CPU_LOONGSON32: 1823 write_c0_ecc(0x80000000); 1824 back_to_back_c0_hazard(); 1825 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1826 printk(KERN_INFO "Cache parity protection %sabled\n", 1827 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1828 break; 1829 case CPU_20KC: 1830 case CPU_25KF: 1831 /* Clear the DE bit (bit 16) in the c0_status register. */ 1832 printk(KERN_INFO "Enable cache parity protection for " 1833 "MIPS 20KC/25KF CPUs.\n"); 1834 clear_c0_status(ST0_DE); 1835 break; 1836 default: 1837 break; 1838 } 1839 } 1840 1841 asmlinkage void cache_parity_error(void) 1842 { 1843 const int field = 2 * sizeof(unsigned long); 1844 unsigned int reg_val; 1845 1846 /* For the moment, report the problem and hang. */ 1847 printk("Cache error exception:\n"); 1848 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1849 reg_val = read_c0_cacheerr(); 1850 printk("c0_cacheerr == %08x\n", reg_val); 1851 1852 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1853 reg_val & (1<<30) ? "secondary" : "primary", 1854 reg_val & (1<<31) ? "data" : "insn"); 1855 if ((cpu_has_mips_r2_r6) && 1856 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1857 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1858 reg_val & (1<<29) ? "ED " : "", 1859 reg_val & (1<<28) ? "ET " : "", 1860 reg_val & (1<<27) ? "ES " : "", 1861 reg_val & (1<<26) ? "EE " : "", 1862 reg_val & (1<<25) ? "EB " : "", 1863 reg_val & (1<<24) ? "EI " : "", 1864 reg_val & (1<<23) ? "E1 " : "", 1865 reg_val & (1<<22) ? "E0 " : ""); 1866 } else { 1867 pr_err("Error bits: %s%s%s%s%s%s%s\n", 1868 reg_val & (1<<29) ? "ED " : "", 1869 reg_val & (1<<28) ? "ET " : "", 1870 reg_val & (1<<26) ? "EE " : "", 1871 reg_val & (1<<25) ? "EB " : "", 1872 reg_val & (1<<24) ? "EI " : "", 1873 reg_val & (1<<23) ? "E1 " : "", 1874 reg_val & (1<<22) ? "E0 " : ""); 1875 } 1876 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1877 1878 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1879 if (reg_val & (1<<22)) 1880 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1881 1882 if (reg_val & (1<<23)) 1883 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1884 #endif 1885 1886 panic("Can't handle the cache error!"); 1887 } 1888 1889 asmlinkage void do_ftlb(void) 1890 { 1891 const int field = 2 * sizeof(unsigned long); 1892 unsigned int reg_val; 1893 1894 /* For the moment, report the problem and hang. */ 1895 if ((cpu_has_mips_r2_r6) && 1896 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) || 1897 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) { 1898 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1899 read_c0_ecc()); 1900 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1901 reg_val = read_c0_cacheerr(); 1902 pr_err("c0_cacheerr == %08x\n", reg_val); 1903 1904 if ((reg_val & 0xc0000000) == 0xc0000000) { 1905 pr_err("Decoded c0_cacheerr: FTLB parity error\n"); 1906 } else { 1907 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1908 reg_val & (1<<30) ? "secondary" : "primary", 1909 reg_val & (1<<31) ? "data" : "insn"); 1910 } 1911 } else { 1912 pr_err("FTLB error exception\n"); 1913 } 1914 /* Just print the cacheerr bits for now */ 1915 cache_parity_error(); 1916 } 1917 1918 asmlinkage void do_gsexc(struct pt_regs *regs, u32 diag1) 1919 { 1920 u32 exccode = (diag1 & LOONGSON_DIAG1_EXCCODE) >> 1921 LOONGSON_DIAG1_EXCCODE_SHIFT; 1922 enum ctx_state prev_state; 1923 1924 prev_state = exception_enter(); 1925 1926 switch (exccode) { 1927 case 0x08: 1928 /* Undocumented exception, will trigger on certain 1929 * also-undocumented instructions accessible from userspace. 1930 * Processor state is not otherwise corrupted, but currently 1931 * we don't know how to proceed. Maybe there is some 1932 * undocumented control flag to enable the instructions? 1933 */ 1934 force_sig(SIGILL); 1935 break; 1936 1937 default: 1938 /* None of the other exceptions, documented or not, have 1939 * further details given; none are encountered in the wild 1940 * either. Panic in case some of them turn out to be fatal. 1941 */ 1942 show_regs(regs); 1943 panic("Unhandled Loongson exception - GSCause = %08x", diag1); 1944 } 1945 1946 exception_exit(prev_state); 1947 } 1948 1949 /* 1950 * SDBBP EJTAG debug exception handler. 1951 * We skip the instruction and return to the next instruction. 1952 */ 1953 void ejtag_exception_handler(struct pt_regs *regs) 1954 { 1955 const int field = 2 * sizeof(unsigned long); 1956 unsigned long depc, old_epc, old_ra; 1957 unsigned int debug; 1958 1959 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1960 depc = read_c0_depc(); 1961 debug = read_c0_debug(); 1962 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1963 if (debug & 0x80000000) { 1964 /* 1965 * In branch delay slot. 1966 * We cheat a little bit here and use EPC to calculate the 1967 * debug return address (DEPC). EPC is restored after the 1968 * calculation. 1969 */ 1970 old_epc = regs->cp0_epc; 1971 old_ra = regs->regs[31]; 1972 regs->cp0_epc = depc; 1973 compute_return_epc(regs); 1974 depc = regs->cp0_epc; 1975 regs->cp0_epc = old_epc; 1976 regs->regs[31] = old_ra; 1977 } else 1978 depc += 4; 1979 write_c0_depc(depc); 1980 1981 #if 0 1982 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1983 write_c0_debug(debug | 0x100); 1984 #endif 1985 } 1986 1987 /* 1988 * NMI exception handler. 1989 * No lock; only written during early bootup by CPU 0. 1990 */ 1991 static RAW_NOTIFIER_HEAD(nmi_chain); 1992 1993 int register_nmi_notifier(struct notifier_block *nb) 1994 { 1995 return raw_notifier_chain_register(&nmi_chain, nb); 1996 } 1997 1998 void __noreturn nmi_exception_handler(struct pt_regs *regs) 1999 { 2000 char str[100]; 2001 2002 nmi_enter(); 2003 raw_notifier_call_chain(&nmi_chain, 0, regs); 2004 bust_spinlocks(1); 2005 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", 2006 smp_processor_id(), regs->cp0_epc); 2007 regs->cp0_epc = read_c0_errorepc(); 2008 die(str, regs); 2009 nmi_exit(); 2010 } 2011 2012 #define VECTORSPACING 0x100 /* for EI/VI mode */ 2013 2014 unsigned long ebase; 2015 EXPORT_SYMBOL_GPL(ebase); 2016 unsigned long exception_handlers[32]; 2017 unsigned long vi_handlers[64]; 2018 2019 void __init *set_except_vector(int n, void *addr) 2020 { 2021 unsigned long handler = (unsigned long) addr; 2022 unsigned long old_handler; 2023 2024 #ifdef CONFIG_CPU_MICROMIPS 2025 /* 2026 * Only the TLB handlers are cache aligned with an even 2027 * address. All other handlers are on an odd address and 2028 * require no modification. Otherwise, MIPS32 mode will 2029 * be entered when handling any TLB exceptions. That 2030 * would be bad...since we must stay in microMIPS mode. 2031 */ 2032 if (!(handler & 0x1)) 2033 handler |= 1; 2034 #endif 2035 old_handler = xchg(&exception_handlers[n], handler); 2036 2037 if (n == 0 && cpu_has_divec) { 2038 #ifdef CONFIG_CPU_MICROMIPS 2039 unsigned long jump_mask = ~((1 << 27) - 1); 2040 #else 2041 unsigned long jump_mask = ~((1 << 28) - 1); 2042 #endif 2043 u32 *buf = (u32 *)(ebase + 0x200); 2044 unsigned int k0 = 26; 2045 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 2046 uasm_i_j(&buf, handler & ~jump_mask); 2047 uasm_i_nop(&buf); 2048 } else { 2049 UASM_i_LA(&buf, k0, handler); 2050 uasm_i_jr(&buf, k0); 2051 uasm_i_nop(&buf); 2052 } 2053 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 2054 } 2055 return (void *)old_handler; 2056 } 2057 2058 static void do_default_vi(void) 2059 { 2060 show_regs(get_irq_regs()); 2061 panic("Caught unexpected vectored interrupt."); 2062 } 2063 2064 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 2065 { 2066 unsigned long handler; 2067 unsigned long old_handler = vi_handlers[n]; 2068 int srssets = current_cpu_data.srsets; 2069 u16 *h; 2070 unsigned char *b; 2071 2072 BUG_ON(!cpu_has_veic && !cpu_has_vint); 2073 2074 if (addr == NULL) { 2075 handler = (unsigned long) do_default_vi; 2076 srs = 0; 2077 } else 2078 handler = (unsigned long) addr; 2079 vi_handlers[n] = handler; 2080 2081 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 2082 2083 if (srs >= srssets) 2084 panic("Shadow register set %d not supported", srs); 2085 2086 if (cpu_has_veic) { 2087 if (board_bind_eic_interrupt) 2088 board_bind_eic_interrupt(n, srs); 2089 } else if (cpu_has_vint) { 2090 /* SRSMap is only defined if shadow sets are implemented */ 2091 if (srssets > 1) 2092 change_c0_srsmap(0xf << n*4, srs << n*4); 2093 } 2094 2095 if (srs == 0) { 2096 /* 2097 * If no shadow set is selected then use the default handler 2098 * that does normal register saving and standard interrupt exit 2099 */ 2100 extern char except_vec_vi, except_vec_vi_lui; 2101 extern char except_vec_vi_ori, except_vec_vi_end; 2102 extern char rollback_except_vec_vi; 2103 char *vec_start = using_rollback_handler() ? 2104 &rollback_except_vec_vi : &except_vec_vi; 2105 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) 2106 const int lui_offset = &except_vec_vi_lui - vec_start + 2; 2107 const int ori_offset = &except_vec_vi_ori - vec_start + 2; 2108 #else 2109 const int lui_offset = &except_vec_vi_lui - vec_start; 2110 const int ori_offset = &except_vec_vi_ori - vec_start; 2111 #endif 2112 const int handler_len = &except_vec_vi_end - vec_start; 2113 2114 if (handler_len > VECTORSPACING) { 2115 /* 2116 * Sigh... panicing won't help as the console 2117 * is probably not configured :( 2118 */ 2119 panic("VECTORSPACING too small"); 2120 } 2121 2122 set_handler(((unsigned long)b - ebase), vec_start, 2123 #ifdef CONFIG_CPU_MICROMIPS 2124 (handler_len - 1)); 2125 #else 2126 handler_len); 2127 #endif 2128 h = (u16 *)(b + lui_offset); 2129 *h = (handler >> 16) & 0xffff; 2130 h = (u16 *)(b + ori_offset); 2131 *h = (handler & 0xffff); 2132 local_flush_icache_range((unsigned long)b, 2133 (unsigned long)(b+handler_len)); 2134 } 2135 else { 2136 /* 2137 * In other cases jump directly to the interrupt handler. It 2138 * is the handler's responsibility to save registers if required 2139 * (eg hi/lo) and return from the exception using "eret". 2140 */ 2141 u32 insn; 2142 2143 h = (u16 *)b; 2144 /* j handler */ 2145 #ifdef CONFIG_CPU_MICROMIPS 2146 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); 2147 #else 2148 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); 2149 #endif 2150 h[0] = (insn >> 16) & 0xffff; 2151 h[1] = insn & 0xffff; 2152 h[2] = 0; 2153 h[3] = 0; 2154 local_flush_icache_range((unsigned long)b, 2155 (unsigned long)(b+8)); 2156 } 2157 2158 return (void *)old_handler; 2159 } 2160 2161 void *set_vi_handler(int n, vi_handler_t addr) 2162 { 2163 return set_vi_srs_handler(n, addr, 0); 2164 } 2165 2166 extern void tlb_init(void); 2167 2168 /* 2169 * Timer interrupt 2170 */ 2171 int cp0_compare_irq; 2172 EXPORT_SYMBOL_GPL(cp0_compare_irq); 2173 int cp0_compare_irq_shift; 2174 2175 /* 2176 * Performance counter IRQ or -1 if shared with timer 2177 */ 2178 int cp0_perfcount_irq; 2179 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 2180 2181 /* 2182 * Fast debug channel IRQ or -1 if not present 2183 */ 2184 int cp0_fdc_irq; 2185 EXPORT_SYMBOL_GPL(cp0_fdc_irq); 2186 2187 static int noulri; 2188 2189 static int __init ulri_disable(char *s) 2190 { 2191 pr_info("Disabling ulri\n"); 2192 noulri = 1; 2193 2194 return 1; 2195 } 2196 __setup("noulri", ulri_disable); 2197 2198 /* configure STATUS register */ 2199 static void configure_status(void) 2200 { 2201 /* 2202 * Disable coprocessors and select 32-bit or 64-bit addressing 2203 * and the 16/32 or 32/32 FPR register model. Reset the BEV 2204 * flag that some firmware may have left set and the TS bit (for 2205 * IP27). Set XX for ISA IV code to work. 2206 */ 2207 unsigned int status_set = ST0_KERNEL_CUMASK; 2208 #ifdef CONFIG_64BIT 2209 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 2210 #endif 2211 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) 2212 status_set |= ST0_XX; 2213 if (cpu_has_dsp) 2214 status_set |= ST0_MX; 2215 2216 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 2217 status_set); 2218 back_to_back_c0_hazard(); 2219 } 2220 2221 unsigned int hwrena; 2222 EXPORT_SYMBOL_GPL(hwrena); 2223 2224 /* configure HWRENA register */ 2225 static void configure_hwrena(void) 2226 { 2227 hwrena = cpu_hwrena_impl_bits; 2228 2229 if (cpu_has_mips_r2_r6) 2230 hwrena |= MIPS_HWRENA_CPUNUM | 2231 MIPS_HWRENA_SYNCISTEP | 2232 MIPS_HWRENA_CC | 2233 MIPS_HWRENA_CCRES; 2234 2235 if (!noulri && cpu_has_userlocal) 2236 hwrena |= MIPS_HWRENA_ULR; 2237 2238 if (hwrena) 2239 write_c0_hwrena(hwrena); 2240 } 2241 2242 static void configure_exception_vector(void) 2243 { 2244 if (cpu_has_mips_r2_r6) { 2245 unsigned long sr = set_c0_status(ST0_BEV); 2246 /* If available, use WG to set top bits of EBASE */ 2247 if (cpu_has_ebase_wg) { 2248 #ifdef CONFIG_64BIT 2249 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 2250 #else 2251 write_c0_ebase(ebase | MIPS_EBASE_WG); 2252 #endif 2253 } 2254 write_c0_ebase(ebase); 2255 write_c0_status(sr); 2256 } 2257 if (cpu_has_veic || cpu_has_vint) { 2258 /* Setting vector spacing enables EI/VI mode */ 2259 change_c0_intctl(0x3e0, VECTORSPACING); 2260 } 2261 if (cpu_has_divec) { 2262 if (cpu_has_mipsmt) { 2263 unsigned int vpflags = dvpe(); 2264 set_c0_cause(CAUSEF_IV); 2265 evpe(vpflags); 2266 } else 2267 set_c0_cause(CAUSEF_IV); 2268 } 2269 } 2270 2271 void per_cpu_trap_init(bool is_boot_cpu) 2272 { 2273 unsigned int cpu = smp_processor_id(); 2274 2275 configure_status(); 2276 configure_hwrena(); 2277 2278 configure_exception_vector(); 2279 2280 /* 2281 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 2282 * 2283 * o read IntCtl.IPTI to determine the timer interrupt 2284 * o read IntCtl.IPPCI to determine the performance counter interrupt 2285 * o read IntCtl.IPFDC to determine the fast debug channel interrupt 2286 */ 2287 if (cpu_has_mips_r2_r6) { 2288 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 2289 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 2290 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 2291 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7; 2292 if (!cp0_fdc_irq) 2293 cp0_fdc_irq = -1; 2294 2295 } else { 2296 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 2297 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 2298 cp0_perfcount_irq = -1; 2299 cp0_fdc_irq = -1; 2300 } 2301 2302 if (cpu_has_mmid) 2303 cpu_data[cpu].asid_cache = 0; 2304 else if (!cpu_data[cpu].asid_cache) 2305 cpu_data[cpu].asid_cache = asid_first_version(cpu); 2306 2307 mmgrab(&init_mm); 2308 current->active_mm = &init_mm; 2309 BUG_ON(current->mm); 2310 enter_lazy_tlb(&init_mm, current); 2311 2312 /* Boot CPU's cache setup in setup_arch(). */ 2313 if (!is_boot_cpu) 2314 cpu_cache_init(); 2315 tlb_init(); 2316 TLBMISS_HANDLER_SETUP(); 2317 } 2318 2319 /* Install CPU exception handler */ 2320 void set_handler(unsigned long offset, void *addr, unsigned long size) 2321 { 2322 #ifdef CONFIG_CPU_MICROMIPS 2323 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); 2324 #else 2325 memcpy((void *)(ebase + offset), addr, size); 2326 #endif 2327 local_flush_icache_range(ebase + offset, ebase + offset + size); 2328 } 2329 2330 static const char panic_null_cerr[] = 2331 "Trying to set NULL cache error exception handler\n"; 2332 2333 /* 2334 * Install uncached CPU exception handler. 2335 * This is suitable only for the cache error exception which is the only 2336 * exception handler that is being run uncached. 2337 */ 2338 void set_uncached_handler(unsigned long offset, void *addr, 2339 unsigned long size) 2340 { 2341 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 2342 2343 if (!addr) 2344 panic(panic_null_cerr); 2345 2346 memcpy((void *)(uncached_ebase + offset), addr, size); 2347 } 2348 2349 static int __initdata rdhwr_noopt; 2350 static int __init set_rdhwr_noopt(char *str) 2351 { 2352 rdhwr_noopt = 1; 2353 return 1; 2354 } 2355 2356 __setup("rdhwr_noopt", set_rdhwr_noopt); 2357 2358 void __init trap_init(void) 2359 { 2360 extern char except_vec3_generic; 2361 extern char except_vec4; 2362 extern char except_vec3_r4000; 2363 unsigned long i, vec_size; 2364 phys_addr_t ebase_pa; 2365 2366 check_wait(); 2367 2368 if (!cpu_has_mips_r2_r6) { 2369 ebase = CAC_BASE; 2370 ebase_pa = virt_to_phys((void *)ebase); 2371 vec_size = 0x400; 2372 2373 memblock_reserve(ebase_pa, vec_size); 2374 } else { 2375 if (cpu_has_veic || cpu_has_vint) 2376 vec_size = 0x200 + VECTORSPACING*64; 2377 else 2378 vec_size = PAGE_SIZE; 2379 2380 ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); 2381 if (!ebase_pa) 2382 panic("%s: Failed to allocate %lu bytes align=0x%x\n", 2383 __func__, vec_size, 1 << fls(vec_size)); 2384 2385 /* 2386 * Try to ensure ebase resides in KSeg0 if possible. 2387 * 2388 * It shouldn't generally be in XKPhys on MIPS64 to avoid 2389 * hitting a poorly defined exception base for Cache Errors. 2390 * The allocation is likely to be in the low 512MB of physical, 2391 * in which case we should be able to convert to KSeg0. 2392 * 2393 * EVA is special though as it allows segments to be rearranged 2394 * and to become uncached during cache error handling. 2395 */ 2396 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) 2397 ebase = CKSEG0ADDR(ebase_pa); 2398 else 2399 ebase = (unsigned long)phys_to_virt(ebase_pa); 2400 } 2401 2402 if (cpu_has_mmips) { 2403 unsigned int config3 = read_c0_config3(); 2404 2405 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) 2406 write_c0_config3(config3 | MIPS_CONF3_ISA_OE); 2407 else 2408 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); 2409 } 2410 2411 if (board_ebase_setup) 2412 board_ebase_setup(); 2413 per_cpu_trap_init(true); 2414 memblock_set_bottom_up(false); 2415 2416 /* 2417 * Copy the generic exception handlers to their final destination. 2418 * This will be overridden later as suitable for a particular 2419 * configuration. 2420 */ 2421 set_handler(0x180, &except_vec3_generic, 0x80); 2422 2423 /* 2424 * Setup default vectors 2425 */ 2426 for (i = 0; i <= 31; i++) 2427 set_except_vector(i, handle_reserved); 2428 2429 /* 2430 * Copy the EJTAG debug exception vector handler code to it's final 2431 * destination. 2432 */ 2433 if (cpu_has_ejtag && board_ejtag_handler_setup) 2434 board_ejtag_handler_setup(); 2435 2436 /* 2437 * Only some CPUs have the watch exceptions. 2438 */ 2439 if (cpu_has_watch) 2440 set_except_vector(EXCCODE_WATCH, handle_watch); 2441 2442 /* 2443 * Initialise interrupt handlers 2444 */ 2445 if (cpu_has_veic || cpu_has_vint) { 2446 int nvec = cpu_has_veic ? 64 : 8; 2447 for (i = 0; i < nvec; i++) 2448 set_vi_handler(i, NULL); 2449 } 2450 else if (cpu_has_divec) 2451 set_handler(0x200, &except_vec4, 0x8); 2452 2453 /* 2454 * Some CPUs can enable/disable for cache parity detection, but does 2455 * it different ways. 2456 */ 2457 parity_protection_init(); 2458 2459 /* 2460 * The Data Bus Errors / Instruction Bus Errors are signaled 2461 * by external hardware. Therefore these two exceptions 2462 * may have board specific handlers. 2463 */ 2464 if (board_be_init) 2465 board_be_init(); 2466 2467 set_except_vector(EXCCODE_INT, using_rollback_handler() ? 2468 rollback_handle_int : handle_int); 2469 set_except_vector(EXCCODE_MOD, handle_tlbm); 2470 set_except_vector(EXCCODE_TLBL, handle_tlbl); 2471 set_except_vector(EXCCODE_TLBS, handle_tlbs); 2472 2473 set_except_vector(EXCCODE_ADEL, handle_adel); 2474 set_except_vector(EXCCODE_ADES, handle_ades); 2475 2476 set_except_vector(EXCCODE_IBE, handle_ibe); 2477 set_except_vector(EXCCODE_DBE, handle_dbe); 2478 2479 set_except_vector(EXCCODE_SYS, handle_sys); 2480 set_except_vector(EXCCODE_BP, handle_bp); 2481 2482 if (rdhwr_noopt) 2483 set_except_vector(EXCCODE_RI, handle_ri); 2484 else { 2485 if (cpu_has_vtag_icache) 2486 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 2487 else if (current_cpu_type() == CPU_LOONGSON64) 2488 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 2489 else 2490 set_except_vector(EXCCODE_RI, handle_ri_rdhwr); 2491 } 2492 2493 set_except_vector(EXCCODE_CPU, handle_cpu); 2494 set_except_vector(EXCCODE_OV, handle_ov); 2495 set_except_vector(EXCCODE_TR, handle_tr); 2496 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe); 2497 2498 if (board_nmi_handler_setup) 2499 board_nmi_handler_setup(); 2500 2501 if (cpu_has_fpu && !cpu_has_nofpuex) 2502 set_except_vector(EXCCODE_FPE, handle_fpe); 2503 2504 if (cpu_has_ftlbparex) 2505 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); 2506 2507 if (cpu_has_gsexcex) 2508 set_except_vector(LOONGSON_EXCCODE_GSEXC, handle_gsexc); 2509 2510 if (cpu_has_rixiex) { 2511 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0); 2512 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0); 2513 } 2514 2515 set_except_vector(EXCCODE_MSADIS, handle_msa); 2516 set_except_vector(EXCCODE_MDMX, handle_mdmx); 2517 2518 if (cpu_has_mcheck) 2519 set_except_vector(EXCCODE_MCHECK, handle_mcheck); 2520 2521 if (cpu_has_mipsmt) 2522 set_except_vector(EXCCODE_THREAD, handle_mt); 2523 2524 set_except_vector(EXCCODE_DSPDIS, handle_dsp); 2525 2526 if (board_cache_error_setup) 2527 board_cache_error_setup(); 2528 2529 if (cpu_has_vce) 2530 /* Special exception: R4[04]00 uses also the divec space. */ 2531 set_handler(0x180, &except_vec3_r4000, 0x100); 2532 else if (cpu_has_4kex) 2533 set_handler(0x180, &except_vec3_generic, 0x80); 2534 else 2535 set_handler(0x080, &except_vec3_generic, 0x80); 2536 2537 local_flush_icache_range(ebase, ebase + vec_size); 2538 2539 sort_extable(__start___dbe_table, __stop___dbe_table); 2540 2541 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 2542 } 2543 2544 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, 2545 void *v) 2546 { 2547 switch (cmd) { 2548 case CPU_PM_ENTER_FAILED: 2549 case CPU_PM_EXIT: 2550 configure_status(); 2551 configure_hwrena(); 2552 configure_exception_vector(); 2553 2554 /* Restore register with CPU number for TLB handlers */ 2555 TLBMISS_HANDLER_RESTORE(); 2556 2557 break; 2558 } 2559 2560 return NOTIFY_OK; 2561 } 2562 2563 static struct notifier_block trap_pm_notifier_block = { 2564 .notifier_call = trap_pm_notifier, 2565 }; 2566 2567 static int __init trap_pm_init(void) 2568 { 2569 return cpu_pm_register_notifier(&trap_pm_notifier_block); 2570 } 2571 arch_initcall(trap_pm_init); 2572