1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 13 */ 14 #include <linux/bug.h> 15 #include <linux/compiler.h> 16 #include <linux/init.h> 17 #include <linux/mm.h> 18 #include <linux/module.h> 19 #include <linux/sched.h> 20 #include <linux/smp.h> 21 #include <linux/spinlock.h> 22 #include <linux/kallsyms.h> 23 #include <linux/bootmem.h> 24 #include <linux/interrupt.h> 25 26 #include <asm/bootinfo.h> 27 #include <asm/branch.h> 28 #include <asm/break.h> 29 #include <asm/cpu.h> 30 #include <asm/dsp.h> 31 #include <asm/fpu.h> 32 #include <asm/mipsregs.h> 33 #include <asm/mipsmtregs.h> 34 #include <asm/module.h> 35 #include <asm/pgtable.h> 36 #include <asm/ptrace.h> 37 #include <asm/sections.h> 38 #include <asm/system.h> 39 #include <asm/tlbdebug.h> 40 #include <asm/traps.h> 41 #include <asm/uaccess.h> 42 #include <asm/mmu_context.h> 43 #include <asm/types.h> 44 #include <asm/stacktrace.h> 45 46 extern asmlinkage void handle_int(void); 47 extern asmlinkage void handle_tlbm(void); 48 extern asmlinkage void handle_tlbl(void); 49 extern asmlinkage void handle_tlbs(void); 50 extern asmlinkage void handle_adel(void); 51 extern asmlinkage void handle_ades(void); 52 extern asmlinkage void handle_ibe(void); 53 extern asmlinkage void handle_dbe(void); 54 extern asmlinkage void handle_sys(void); 55 extern asmlinkage void handle_bp(void); 56 extern asmlinkage void handle_ri(void); 57 extern asmlinkage void handle_ri_rdhwr_vivt(void); 58 extern asmlinkage void handle_ri_rdhwr(void); 59 extern asmlinkage void handle_cpu(void); 60 extern asmlinkage void handle_ov(void); 61 extern asmlinkage void handle_tr(void); 62 extern asmlinkage void handle_fpe(void); 63 extern asmlinkage void handle_mdmx(void); 64 extern asmlinkage void handle_watch(void); 65 extern asmlinkage void handle_mt(void); 66 extern asmlinkage void handle_dsp(void); 67 extern asmlinkage void handle_mcheck(void); 68 extern asmlinkage void handle_reserved(void); 69 70 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 71 struct mips_fpu_struct *ctx, int has_fpu); 72 73 void (*board_watchpoint_handler)(struct pt_regs *regs); 74 void (*board_be_init)(void); 75 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 76 void (*board_nmi_handler_setup)(void); 77 void (*board_ejtag_handler_setup)(void); 78 void (*board_bind_eic_interrupt)(int irq, int regset); 79 80 81 static void show_raw_backtrace(unsigned long reg29) 82 { 83 unsigned long *sp = (unsigned long *)reg29; 84 unsigned long addr; 85 86 printk("Call Trace:"); 87 #ifdef CONFIG_KALLSYMS 88 printk("\n"); 89 #endif 90 while (!kstack_end(sp)) { 91 addr = *sp++; 92 if (__kernel_text_address(addr)) 93 print_ip_sym(addr); 94 } 95 printk("\n"); 96 } 97 98 #ifdef CONFIG_KALLSYMS 99 int raw_show_trace; 100 static int __init set_raw_show_trace(char *str) 101 { 102 raw_show_trace = 1; 103 return 1; 104 } 105 __setup("raw_show_trace", set_raw_show_trace); 106 #endif 107 108 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 109 { 110 unsigned long sp = regs->regs[29]; 111 unsigned long ra = regs->regs[31]; 112 unsigned long pc = regs->cp0_epc; 113 114 if (raw_show_trace || !__kernel_text_address(pc)) { 115 show_raw_backtrace(sp); 116 return; 117 } 118 printk("Call Trace:\n"); 119 do { 120 print_ip_sym(pc); 121 pc = unwind_stack(task, &sp, pc, &ra); 122 } while (pc); 123 printk("\n"); 124 } 125 126 /* 127 * This routine abuses get_user()/put_user() to reference pointers 128 * with at least a bit of error checking ... 129 */ 130 static void show_stacktrace(struct task_struct *task, 131 const struct pt_regs *regs) 132 { 133 const int field = 2 * sizeof(unsigned long); 134 long stackdata; 135 int i; 136 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 137 138 printk("Stack :"); 139 i = 0; 140 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 141 if (i && ((i % (64 / field)) == 0)) 142 printk("\n "); 143 if (i > 39) { 144 printk(" ..."); 145 break; 146 } 147 148 if (__get_user(stackdata, sp++)) { 149 printk(" (Bad stack address)"); 150 break; 151 } 152 153 printk(" %0*lx", field, stackdata); 154 i++; 155 } 156 printk("\n"); 157 show_backtrace(task, regs); 158 } 159 160 void show_stack(struct task_struct *task, unsigned long *sp) 161 { 162 struct pt_regs regs; 163 if (sp) { 164 regs.regs[29] = (unsigned long)sp; 165 regs.regs[31] = 0; 166 regs.cp0_epc = 0; 167 } else { 168 if (task && task != current) { 169 regs.regs[29] = task->thread.reg29; 170 regs.regs[31] = 0; 171 regs.cp0_epc = task->thread.reg31; 172 } else { 173 prepare_frametrace(®s); 174 } 175 } 176 show_stacktrace(task, ®s); 177 } 178 179 /* 180 * The architecture-independent dump_stack generator 181 */ 182 void dump_stack(void) 183 { 184 struct pt_regs regs; 185 186 prepare_frametrace(®s); 187 show_backtrace(current, ®s); 188 } 189 190 EXPORT_SYMBOL(dump_stack); 191 192 static void show_code(unsigned int __user *pc) 193 { 194 long i; 195 196 printk("\nCode:"); 197 198 for(i = -3 ; i < 6 ; i++) { 199 unsigned int insn; 200 if (__get_user(insn, pc + i)) { 201 printk(" (Bad address in epc)\n"); 202 break; 203 } 204 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 205 } 206 } 207 208 static void __show_regs(const struct pt_regs *regs) 209 { 210 const int field = 2 * sizeof(unsigned long); 211 unsigned int cause = regs->cp0_cause; 212 int i; 213 214 printk("Cpu %d\n", smp_processor_id()); 215 216 /* 217 * Saved main processor registers 218 */ 219 for (i = 0; i < 32; ) { 220 if ((i % 4) == 0) 221 printk("$%2d :", i); 222 if (i == 0) 223 printk(" %0*lx", field, 0UL); 224 else if (i == 26 || i == 27) 225 printk(" %*s", field, ""); 226 else 227 printk(" %0*lx", field, regs->regs[i]); 228 229 i++; 230 if ((i % 4) == 0) 231 printk("\n"); 232 } 233 234 #ifdef CONFIG_CPU_HAS_SMARTMIPS 235 printk("Acx : %0*lx\n", field, regs->acx); 236 #endif 237 printk("Hi : %0*lx\n", field, regs->hi); 238 printk("Lo : %0*lx\n", field, regs->lo); 239 240 /* 241 * Saved cp0 registers 242 */ 243 printk("epc : %0*lx ", field, regs->cp0_epc); 244 print_symbol("%s ", regs->cp0_epc); 245 printk(" %s\n", print_tainted()); 246 printk("ra : %0*lx ", field, regs->regs[31]); 247 print_symbol("%s\n", regs->regs[31]); 248 249 printk("Status: %08x ", (uint32_t) regs->cp0_status); 250 251 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 252 if (regs->cp0_status & ST0_KUO) 253 printk("KUo "); 254 if (regs->cp0_status & ST0_IEO) 255 printk("IEo "); 256 if (regs->cp0_status & ST0_KUP) 257 printk("KUp "); 258 if (regs->cp0_status & ST0_IEP) 259 printk("IEp "); 260 if (regs->cp0_status & ST0_KUC) 261 printk("KUc "); 262 if (regs->cp0_status & ST0_IEC) 263 printk("IEc "); 264 } else { 265 if (regs->cp0_status & ST0_KX) 266 printk("KX "); 267 if (regs->cp0_status & ST0_SX) 268 printk("SX "); 269 if (regs->cp0_status & ST0_UX) 270 printk("UX "); 271 switch (regs->cp0_status & ST0_KSU) { 272 case KSU_USER: 273 printk("USER "); 274 break; 275 case KSU_SUPERVISOR: 276 printk("SUPERVISOR "); 277 break; 278 case KSU_KERNEL: 279 printk("KERNEL "); 280 break; 281 default: 282 printk("BAD_MODE "); 283 break; 284 } 285 if (regs->cp0_status & ST0_ERL) 286 printk("ERL "); 287 if (regs->cp0_status & ST0_EXL) 288 printk("EXL "); 289 if (regs->cp0_status & ST0_IE) 290 printk("IE "); 291 } 292 printk("\n"); 293 294 printk("Cause : %08x\n", cause); 295 296 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 297 if (1 <= cause && cause <= 5) 298 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 299 300 printk("PrId : %08x (%s)\n", read_c0_prid(), 301 cpu_name_string()); 302 } 303 304 /* 305 * FIXME: really the generic show_regs should take a const pointer argument. 306 */ 307 void show_regs(struct pt_regs *regs) 308 { 309 __show_regs((struct pt_regs *)regs); 310 } 311 312 void show_registers(const struct pt_regs *regs) 313 { 314 __show_regs(regs); 315 print_modules(); 316 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 317 current->comm, task_pid_nr(current), current_thread_info(), current); 318 show_stacktrace(current, regs); 319 show_code((unsigned int __user *) regs->cp0_epc); 320 printk("\n"); 321 } 322 323 static DEFINE_SPINLOCK(die_lock); 324 325 void __noreturn die(const char * str, const struct pt_regs * regs) 326 { 327 static int die_counter; 328 #ifdef CONFIG_MIPS_MT_SMTC 329 unsigned long dvpret = dvpe(); 330 #endif /* CONFIG_MIPS_MT_SMTC */ 331 332 console_verbose(); 333 spin_lock_irq(&die_lock); 334 bust_spinlocks(1); 335 #ifdef CONFIG_MIPS_MT_SMTC 336 mips_mt_regdump(dvpret); 337 #endif /* CONFIG_MIPS_MT_SMTC */ 338 printk("%s[#%d]:\n", str, ++die_counter); 339 show_registers(regs); 340 add_taint(TAINT_DIE); 341 spin_unlock_irq(&die_lock); 342 343 if (in_interrupt()) 344 panic("Fatal exception in interrupt"); 345 346 if (panic_on_oops) { 347 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 348 ssleep(5); 349 panic("Fatal exception"); 350 } 351 352 do_exit(SIGSEGV); 353 } 354 355 extern const struct exception_table_entry __start___dbe_table[]; 356 extern const struct exception_table_entry __stop___dbe_table[]; 357 358 __asm__( 359 " .section __dbe_table, \"a\"\n" 360 " .previous \n"); 361 362 /* Given an address, look for it in the exception tables. */ 363 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 364 { 365 const struct exception_table_entry *e; 366 367 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 368 if (!e) 369 e = search_module_dbetables(addr); 370 return e; 371 } 372 373 asmlinkage void do_be(struct pt_regs *regs) 374 { 375 const int field = 2 * sizeof(unsigned long); 376 const struct exception_table_entry *fixup = NULL; 377 int data = regs->cp0_cause & 4; 378 int action = MIPS_BE_FATAL; 379 380 /* XXX For now. Fixme, this searches the wrong table ... */ 381 if (data && !user_mode(regs)) 382 fixup = search_dbe_tables(exception_epc(regs)); 383 384 if (fixup) 385 action = MIPS_BE_FIXUP; 386 387 if (board_be_handler) 388 action = board_be_handler(regs, fixup != NULL); 389 390 switch (action) { 391 case MIPS_BE_DISCARD: 392 return; 393 case MIPS_BE_FIXUP: 394 if (fixup) { 395 regs->cp0_epc = fixup->nextinsn; 396 return; 397 } 398 break; 399 default: 400 break; 401 } 402 403 /* 404 * Assume it would be too dangerous to continue ... 405 */ 406 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 407 data ? "Data" : "Instruction", 408 field, regs->cp0_epc, field, regs->regs[31]); 409 die_if_kernel("Oops", regs); 410 force_sig(SIGBUS, current); 411 } 412 413 /* 414 * ll/sc, rdhwr, sync emulation 415 */ 416 417 #define OPCODE 0xfc000000 418 #define BASE 0x03e00000 419 #define RT 0x001f0000 420 #define OFFSET 0x0000ffff 421 #define LL 0xc0000000 422 #define SC 0xe0000000 423 #define SPEC0 0x00000000 424 #define SPEC3 0x7c000000 425 #define RD 0x0000f800 426 #define FUNC 0x0000003f 427 #define SYNC 0x0000000f 428 #define RDHWR 0x0000003b 429 430 /* 431 * The ll_bit is cleared by r*_switch.S 432 */ 433 434 unsigned long ll_bit; 435 436 static struct task_struct *ll_task = NULL; 437 438 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 439 { 440 unsigned long value, __user *vaddr; 441 long offset; 442 443 /* 444 * analyse the ll instruction that just caused a ri exception 445 * and put the referenced address to addr. 446 */ 447 448 /* sign extend offset */ 449 offset = opcode & OFFSET; 450 offset <<= 16; 451 offset >>= 16; 452 453 vaddr = (unsigned long __user *) 454 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 455 456 if ((unsigned long)vaddr & 3) 457 return SIGBUS; 458 if (get_user(value, vaddr)) 459 return SIGSEGV; 460 461 preempt_disable(); 462 463 if (ll_task == NULL || ll_task == current) { 464 ll_bit = 1; 465 } else { 466 ll_bit = 0; 467 } 468 ll_task = current; 469 470 preempt_enable(); 471 472 regs->regs[(opcode & RT) >> 16] = value; 473 474 return 0; 475 } 476 477 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 478 { 479 unsigned long __user *vaddr; 480 unsigned long reg; 481 long offset; 482 483 /* 484 * analyse the sc instruction that just caused a ri exception 485 * and put the referenced address to addr. 486 */ 487 488 /* sign extend offset */ 489 offset = opcode & OFFSET; 490 offset <<= 16; 491 offset >>= 16; 492 493 vaddr = (unsigned long __user *) 494 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 495 reg = (opcode & RT) >> 16; 496 497 if ((unsigned long)vaddr & 3) 498 return SIGBUS; 499 500 preempt_disable(); 501 502 if (ll_bit == 0 || ll_task != current) { 503 regs->regs[reg] = 0; 504 preempt_enable(); 505 return 0; 506 } 507 508 preempt_enable(); 509 510 if (put_user(regs->regs[reg], vaddr)) 511 return SIGSEGV; 512 513 regs->regs[reg] = 1; 514 515 return 0; 516 } 517 518 /* 519 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 520 * opcodes are supposed to result in coprocessor unusable exceptions if 521 * executed on ll/sc-less processors. That's the theory. In practice a 522 * few processors such as NEC's VR4100 throw reserved instruction exceptions 523 * instead, so we're doing the emulation thing in both exception handlers. 524 */ 525 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 526 { 527 if ((opcode & OPCODE) == LL) 528 return simulate_ll(regs, opcode); 529 if ((opcode & OPCODE) == SC) 530 return simulate_sc(regs, opcode); 531 532 return -1; /* Must be something else ... */ 533 } 534 535 /* 536 * Simulate trapping 'rdhwr' instructions to provide user accessible 537 * registers not implemented in hardware. 538 */ 539 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) 540 { 541 struct thread_info *ti = task_thread_info(current); 542 543 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 544 int rd = (opcode & RD) >> 11; 545 int rt = (opcode & RT) >> 16; 546 switch (rd) { 547 case 0: /* CPU number */ 548 regs->regs[rt] = smp_processor_id(); 549 return 0; 550 case 1: /* SYNCI length */ 551 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 552 current_cpu_data.icache.linesz); 553 return 0; 554 case 2: /* Read count register */ 555 regs->regs[rt] = read_c0_count(); 556 return 0; 557 case 3: /* Count register resolution */ 558 switch (current_cpu_data.cputype) { 559 case CPU_20KC: 560 case CPU_25KF: 561 regs->regs[rt] = 1; 562 break; 563 default: 564 regs->regs[rt] = 2; 565 } 566 return 0; 567 case 29: 568 regs->regs[rt] = ti->tp_value; 569 return 0; 570 default: 571 return -1; 572 } 573 } 574 575 /* Not ours. */ 576 return -1; 577 } 578 579 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 580 { 581 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) 582 return 0; 583 584 return -1; /* Must be something else ... */ 585 } 586 587 asmlinkage void do_ov(struct pt_regs *regs) 588 { 589 siginfo_t info; 590 591 die_if_kernel("Integer overflow", regs); 592 593 info.si_code = FPE_INTOVF; 594 info.si_signo = SIGFPE; 595 info.si_errno = 0; 596 info.si_addr = (void __user *) regs->cp0_epc; 597 force_sig_info(SIGFPE, &info, current); 598 } 599 600 /* 601 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 602 */ 603 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 604 { 605 siginfo_t info; 606 607 die_if_kernel("FP exception in kernel code", regs); 608 609 if (fcr31 & FPU_CSR_UNI_X) { 610 int sig; 611 612 /* 613 * Unimplemented operation exception. If we've got the full 614 * software emulator on-board, let's use it... 615 * 616 * Force FPU to dump state into task/thread context. We're 617 * moving a lot of data here for what is probably a single 618 * instruction, but the alternative is to pre-decode the FP 619 * register operands before invoking the emulator, which seems 620 * a bit extreme for what should be an infrequent event. 621 */ 622 /* Ensure 'resume' not overwrite saved fp context again. */ 623 lose_fpu(1); 624 625 /* Run the emulator */ 626 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); 627 628 /* 629 * We can't allow the emulated instruction to leave any of 630 * the cause bit set in $fcr31. 631 */ 632 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 633 634 /* Restore the hardware register state */ 635 own_fpu(1); /* Using the FPU again. */ 636 637 /* If something went wrong, signal */ 638 if (sig) 639 force_sig(sig, current); 640 641 return; 642 } else if (fcr31 & FPU_CSR_INV_X) 643 info.si_code = FPE_FLTINV; 644 else if (fcr31 & FPU_CSR_DIV_X) 645 info.si_code = FPE_FLTDIV; 646 else if (fcr31 & FPU_CSR_OVF_X) 647 info.si_code = FPE_FLTOVF; 648 else if (fcr31 & FPU_CSR_UDF_X) 649 info.si_code = FPE_FLTUND; 650 else if (fcr31 & FPU_CSR_INE_X) 651 info.si_code = FPE_FLTRES; 652 else 653 info.si_code = __SI_FAULT; 654 info.si_signo = SIGFPE; 655 info.si_errno = 0; 656 info.si_addr = (void __user *) regs->cp0_epc; 657 force_sig_info(SIGFPE, &info, current); 658 } 659 660 asmlinkage void do_bp(struct pt_regs *regs) 661 { 662 unsigned int opcode, bcode; 663 siginfo_t info; 664 665 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 666 goto out_sigsegv; 667 668 /* 669 * There is the ancient bug in the MIPS assemblers that the break 670 * code starts left to bit 16 instead to bit 6 in the opcode. 671 * Gas is bug-compatible, but not always, grrr... 672 * We handle both cases with a simple heuristics. --macro 673 */ 674 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 675 if (bcode < (1 << 10)) 676 bcode <<= 10; 677 678 /* 679 * (A short test says that IRIX 5.3 sends SIGTRAP for all break 680 * insns, even for break codes that indicate arithmetic failures. 681 * Weird ...) 682 * But should we continue the brokenness??? --macro 683 */ 684 switch (bcode) { 685 case BRK_OVERFLOW << 10: 686 case BRK_DIVZERO << 10: 687 die_if_kernel("Break instruction in kernel code", regs); 688 if (bcode == (BRK_DIVZERO << 10)) 689 info.si_code = FPE_INTDIV; 690 else 691 info.si_code = FPE_INTOVF; 692 info.si_signo = SIGFPE; 693 info.si_errno = 0; 694 info.si_addr = (void __user *) regs->cp0_epc; 695 force_sig_info(SIGFPE, &info, current); 696 break; 697 case BRK_BUG: 698 die("Kernel bug detected", regs); 699 break; 700 default: 701 die_if_kernel("Break instruction in kernel code", regs); 702 force_sig(SIGTRAP, current); 703 } 704 return; 705 706 out_sigsegv: 707 force_sig(SIGSEGV, current); 708 } 709 710 asmlinkage void do_tr(struct pt_regs *regs) 711 { 712 unsigned int opcode, tcode = 0; 713 siginfo_t info; 714 715 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 716 goto out_sigsegv; 717 718 /* Immediate versions don't provide a code. */ 719 if (!(opcode & OPCODE)) 720 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 721 722 /* 723 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap 724 * insns, even for trap codes that indicate arithmetic failures. 725 * Weird ...) 726 * But should we continue the brokenness??? --macro 727 */ 728 switch (tcode) { 729 case BRK_OVERFLOW: 730 case BRK_DIVZERO: 731 die_if_kernel("Trap instruction in kernel code", regs); 732 if (tcode == BRK_DIVZERO) 733 info.si_code = FPE_INTDIV; 734 else 735 info.si_code = FPE_INTOVF; 736 info.si_signo = SIGFPE; 737 info.si_errno = 0; 738 info.si_addr = (void __user *) regs->cp0_epc; 739 force_sig_info(SIGFPE, &info, current); 740 break; 741 case BRK_BUG: 742 die("Kernel bug detected", regs); 743 break; 744 default: 745 die_if_kernel("Trap instruction in kernel code", regs); 746 force_sig(SIGTRAP, current); 747 } 748 return; 749 750 out_sigsegv: 751 force_sig(SIGSEGV, current); 752 } 753 754 asmlinkage void do_ri(struct pt_regs *regs) 755 { 756 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 757 unsigned long old_epc = regs->cp0_epc; 758 unsigned int opcode = 0; 759 int status = -1; 760 761 die_if_kernel("Reserved instruction in kernel code", regs); 762 763 if (unlikely(compute_return_epc(regs) < 0)) 764 return; 765 766 if (unlikely(get_user(opcode, epc) < 0)) 767 status = SIGSEGV; 768 769 if (!cpu_has_llsc && status < 0) 770 status = simulate_llsc(regs, opcode); 771 772 if (status < 0) 773 status = simulate_rdhwr(regs, opcode); 774 775 if (status < 0) 776 status = simulate_sync(regs, opcode); 777 778 if (status < 0) 779 status = SIGILL; 780 781 if (unlikely(status > 0)) { 782 regs->cp0_epc = old_epc; /* Undo skip-over. */ 783 force_sig(status, current); 784 } 785 } 786 787 /* 788 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 789 * emulated more than some threshold number of instructions, force migration to 790 * a "CPU" that has FP support. 791 */ 792 static void mt_ase_fp_affinity(void) 793 { 794 #ifdef CONFIG_MIPS_MT_FPAFF 795 if (mt_fpemul_threshold > 0 && 796 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 797 /* 798 * If there's no FPU present, or if the application has already 799 * restricted the allowed set to exclude any CPUs with FPUs, 800 * we'll skip the procedure. 801 */ 802 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 803 cpumask_t tmask; 804 805 cpus_and(tmask, current->thread.user_cpus_allowed, 806 mt_fpu_cpumask); 807 set_cpus_allowed(current, tmask); 808 set_thread_flag(TIF_FPUBOUND); 809 } 810 } 811 #endif /* CONFIG_MIPS_MT_FPAFF */ 812 } 813 814 asmlinkage void do_cpu(struct pt_regs *regs) 815 { 816 unsigned int __user *epc; 817 unsigned long old_epc; 818 unsigned int opcode; 819 unsigned int cpid; 820 int status; 821 822 die_if_kernel("do_cpu invoked from kernel context!", regs); 823 824 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 825 826 switch (cpid) { 827 case 0: 828 epc = (unsigned int __user *)exception_epc(regs); 829 old_epc = regs->cp0_epc; 830 opcode = 0; 831 status = -1; 832 833 if (unlikely(compute_return_epc(regs) < 0)) 834 return; 835 836 if (unlikely(get_user(opcode, epc) < 0)) 837 status = SIGSEGV; 838 839 if (!cpu_has_llsc && status < 0) 840 status = simulate_llsc(regs, opcode); 841 842 if (status < 0) 843 status = simulate_rdhwr(regs, opcode); 844 845 if (status < 0) 846 status = SIGILL; 847 848 if (unlikely(status > 0)) { 849 regs->cp0_epc = old_epc; /* Undo skip-over. */ 850 force_sig(status, current); 851 } 852 853 return; 854 855 case 1: 856 if (used_math()) /* Using the FPU again. */ 857 own_fpu(1); 858 else { /* First time FPU user. */ 859 init_fpu(); 860 set_used_math(); 861 } 862 863 if (!raw_cpu_has_fpu) { 864 int sig; 865 sig = fpu_emulator_cop1Handler(regs, 866 ¤t->thread.fpu, 0); 867 if (sig) 868 force_sig(sig, current); 869 else 870 mt_ase_fp_affinity(); 871 } 872 873 return; 874 875 case 2: 876 case 3: 877 break; 878 } 879 880 force_sig(SIGILL, current); 881 } 882 883 asmlinkage void do_mdmx(struct pt_regs *regs) 884 { 885 force_sig(SIGILL, current); 886 } 887 888 asmlinkage void do_watch(struct pt_regs *regs) 889 { 890 if (board_watchpoint_handler) { 891 (*board_watchpoint_handler)(regs); 892 return; 893 } 894 895 /* 896 * We use the watch exception where available to detect stack 897 * overflows. 898 */ 899 dump_tlb_all(); 900 show_regs(regs); 901 panic("Caught WATCH exception - probably caused by stack overflow."); 902 } 903 904 asmlinkage void do_mcheck(struct pt_regs *regs) 905 { 906 const int field = 2 * sizeof(unsigned long); 907 int multi_match = regs->cp0_status & ST0_TS; 908 909 show_regs(regs); 910 911 if (multi_match) { 912 printk("Index : %0x\n", read_c0_index()); 913 printk("Pagemask: %0x\n", read_c0_pagemask()); 914 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 915 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 916 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 917 printk("\n"); 918 dump_tlb_all(); 919 } 920 921 show_code((unsigned int __user *) regs->cp0_epc); 922 923 /* 924 * Some chips may have other causes of machine check (e.g. SB1 925 * graduation timer) 926 */ 927 panic("Caught Machine Check exception - %scaused by multiple " 928 "matching entries in the TLB.", 929 (multi_match) ? "" : "not "); 930 } 931 932 asmlinkage void do_mt(struct pt_regs *regs) 933 { 934 int subcode; 935 936 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 937 >> VPECONTROL_EXCPT_SHIFT; 938 switch (subcode) { 939 case 0: 940 printk(KERN_DEBUG "Thread Underflow\n"); 941 break; 942 case 1: 943 printk(KERN_DEBUG "Thread Overflow\n"); 944 break; 945 case 2: 946 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 947 break; 948 case 3: 949 printk(KERN_DEBUG "Gating Storage Exception\n"); 950 break; 951 case 4: 952 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 953 break; 954 case 5: 955 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 956 break; 957 default: 958 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 959 subcode); 960 break; 961 } 962 die_if_kernel("MIPS MT Thread exception in kernel", regs); 963 964 force_sig(SIGILL, current); 965 } 966 967 968 asmlinkage void do_dsp(struct pt_regs *regs) 969 { 970 if (cpu_has_dsp) 971 panic("Unexpected DSP exception\n"); 972 973 force_sig(SIGILL, current); 974 } 975 976 asmlinkage void do_reserved(struct pt_regs *regs) 977 { 978 /* 979 * Game over - no way to handle this if it ever occurs. Most probably 980 * caused by a new unknown cpu type or after another deadly 981 * hard/software error. 982 */ 983 show_regs(regs); 984 panic("Caught reserved exception %ld - should not happen.", 985 (regs->cp0_cause & 0x7f) >> 2); 986 } 987 988 /* 989 * Some MIPS CPUs can enable/disable for cache parity detection, but do 990 * it different ways. 991 */ 992 static inline void parity_protection_init(void) 993 { 994 switch (current_cpu_type()) { 995 case CPU_24K: 996 case CPU_34K: 997 case CPU_5KC: 998 write_c0_ecc(0x80000000); 999 back_to_back_c0_hazard(); 1000 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1001 printk(KERN_INFO "Cache parity protection %sabled\n", 1002 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1003 break; 1004 case CPU_20KC: 1005 case CPU_25KF: 1006 /* Clear the DE bit (bit 16) in the c0_status register. */ 1007 printk(KERN_INFO "Enable cache parity protection for " 1008 "MIPS 20KC/25KF CPUs.\n"); 1009 clear_c0_status(ST0_DE); 1010 break; 1011 default: 1012 break; 1013 } 1014 } 1015 1016 asmlinkage void cache_parity_error(void) 1017 { 1018 const int field = 2 * sizeof(unsigned long); 1019 unsigned int reg_val; 1020 1021 /* For the moment, report the problem and hang. */ 1022 printk("Cache error exception:\n"); 1023 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1024 reg_val = read_c0_cacheerr(); 1025 printk("c0_cacheerr == %08x\n", reg_val); 1026 1027 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1028 reg_val & (1<<30) ? "secondary" : "primary", 1029 reg_val & (1<<31) ? "data" : "insn"); 1030 printk("Error bits: %s%s%s%s%s%s%s\n", 1031 reg_val & (1<<29) ? "ED " : "", 1032 reg_val & (1<<28) ? "ET " : "", 1033 reg_val & (1<<26) ? "EE " : "", 1034 reg_val & (1<<25) ? "EB " : "", 1035 reg_val & (1<<24) ? "EI " : "", 1036 reg_val & (1<<23) ? "E1 " : "", 1037 reg_val & (1<<22) ? "E0 " : ""); 1038 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1039 1040 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1041 if (reg_val & (1<<22)) 1042 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1043 1044 if (reg_val & (1<<23)) 1045 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1046 #endif 1047 1048 panic("Can't handle the cache error!"); 1049 } 1050 1051 /* 1052 * SDBBP EJTAG debug exception handler. 1053 * We skip the instruction and return to the next instruction. 1054 */ 1055 void ejtag_exception_handler(struct pt_regs *regs) 1056 { 1057 const int field = 2 * sizeof(unsigned long); 1058 unsigned long depc, old_epc; 1059 unsigned int debug; 1060 1061 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1062 depc = read_c0_depc(); 1063 debug = read_c0_debug(); 1064 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1065 if (debug & 0x80000000) { 1066 /* 1067 * In branch delay slot. 1068 * We cheat a little bit here and use EPC to calculate the 1069 * debug return address (DEPC). EPC is restored after the 1070 * calculation. 1071 */ 1072 old_epc = regs->cp0_epc; 1073 regs->cp0_epc = depc; 1074 __compute_return_epc(regs); 1075 depc = regs->cp0_epc; 1076 regs->cp0_epc = old_epc; 1077 } else 1078 depc += 4; 1079 write_c0_depc(depc); 1080 1081 #if 0 1082 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1083 write_c0_debug(debug | 0x100); 1084 #endif 1085 } 1086 1087 /* 1088 * NMI exception handler. 1089 */ 1090 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) 1091 { 1092 bust_spinlocks(1); 1093 printk("NMI taken!!!!\n"); 1094 die("NMI", regs); 1095 } 1096 1097 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1098 1099 unsigned long ebase; 1100 unsigned long exception_handlers[32]; 1101 unsigned long vi_handlers[64]; 1102 1103 /* 1104 * As a side effect of the way this is implemented we're limited 1105 * to interrupt handlers in the address range from 1106 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... 1107 */ 1108 void *set_except_vector(int n, void *addr) 1109 { 1110 unsigned long handler = (unsigned long) addr; 1111 unsigned long old_handler = exception_handlers[n]; 1112 1113 exception_handlers[n] = handler; 1114 if (n == 0 && cpu_has_divec) { 1115 *(u32 *)(ebase + 0x200) = 0x08000000 | 1116 (0x03ffffff & (handler >> 2)); 1117 flush_icache_range(ebase + 0x200, ebase + 0x204); 1118 } 1119 return (void *)old_handler; 1120 } 1121 1122 static asmlinkage void do_default_vi(void) 1123 { 1124 show_regs(get_irq_regs()); 1125 panic("Caught unexpected vectored interrupt."); 1126 } 1127 1128 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1129 { 1130 unsigned long handler; 1131 unsigned long old_handler = vi_handlers[n]; 1132 int srssets = current_cpu_data.srsets; 1133 u32 *w; 1134 unsigned char *b; 1135 1136 if (!cpu_has_veic && !cpu_has_vint) 1137 BUG(); 1138 1139 if (addr == NULL) { 1140 handler = (unsigned long) do_default_vi; 1141 srs = 0; 1142 } else 1143 handler = (unsigned long) addr; 1144 vi_handlers[n] = (unsigned long) addr; 1145 1146 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1147 1148 if (srs >= srssets) 1149 panic("Shadow register set %d not supported", srs); 1150 1151 if (cpu_has_veic) { 1152 if (board_bind_eic_interrupt) 1153 board_bind_eic_interrupt(n, srs); 1154 } else if (cpu_has_vint) { 1155 /* SRSMap is only defined if shadow sets are implemented */ 1156 if (srssets > 1) 1157 change_c0_srsmap(0xf << n*4, srs << n*4); 1158 } 1159 1160 if (srs == 0) { 1161 /* 1162 * If no shadow set is selected then use the default handler 1163 * that does normal register saving and a standard interrupt exit 1164 */ 1165 1166 extern char except_vec_vi, except_vec_vi_lui; 1167 extern char except_vec_vi_ori, except_vec_vi_end; 1168 #ifdef CONFIG_MIPS_MT_SMTC 1169 /* 1170 * We need to provide the SMTC vectored interrupt handler 1171 * not only with the address of the handler, but with the 1172 * Status.IM bit to be masked before going there. 1173 */ 1174 extern char except_vec_vi_mori; 1175 const int mori_offset = &except_vec_vi_mori - &except_vec_vi; 1176 #endif /* CONFIG_MIPS_MT_SMTC */ 1177 const int handler_len = &except_vec_vi_end - &except_vec_vi; 1178 const int lui_offset = &except_vec_vi_lui - &except_vec_vi; 1179 const int ori_offset = &except_vec_vi_ori - &except_vec_vi; 1180 1181 if (handler_len > VECTORSPACING) { 1182 /* 1183 * Sigh... panicing won't help as the console 1184 * is probably not configured :( 1185 */ 1186 panic("VECTORSPACING too small"); 1187 } 1188 1189 memcpy(b, &except_vec_vi, handler_len); 1190 #ifdef CONFIG_MIPS_MT_SMTC 1191 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1192 1193 w = (u32 *)(b + mori_offset); 1194 *w = (*w & 0xffff0000) | (0x100 << n); 1195 #endif /* CONFIG_MIPS_MT_SMTC */ 1196 w = (u32 *)(b + lui_offset); 1197 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1198 w = (u32 *)(b + ori_offset); 1199 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1200 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); 1201 } 1202 else { 1203 /* 1204 * In other cases jump directly to the interrupt handler 1205 * 1206 * It is the handlers responsibility to save registers if required 1207 * (eg hi/lo) and return from the exception using "eret" 1208 */ 1209 w = (u32 *)b; 1210 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1211 *w = 0; 1212 flush_icache_range((unsigned long)b, (unsigned long)(b+8)); 1213 } 1214 1215 return (void *)old_handler; 1216 } 1217 1218 void *set_vi_handler(int n, vi_handler_t addr) 1219 { 1220 return set_vi_srs_handler(n, addr, 0); 1221 } 1222 1223 /* 1224 * This is used by native signal handling 1225 */ 1226 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); 1227 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); 1228 1229 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); 1230 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); 1231 1232 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); 1233 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); 1234 1235 #ifdef CONFIG_SMP 1236 static int smp_save_fp_context(struct sigcontext __user *sc) 1237 { 1238 return raw_cpu_has_fpu 1239 ? _save_fp_context(sc) 1240 : fpu_emulator_save_context(sc); 1241 } 1242 1243 static int smp_restore_fp_context(struct sigcontext __user *sc) 1244 { 1245 return raw_cpu_has_fpu 1246 ? _restore_fp_context(sc) 1247 : fpu_emulator_restore_context(sc); 1248 } 1249 #endif 1250 1251 static inline void signal_init(void) 1252 { 1253 #ifdef CONFIG_SMP 1254 /* For now just do the cpu_has_fpu check when the functions are invoked */ 1255 save_fp_context = smp_save_fp_context; 1256 restore_fp_context = smp_restore_fp_context; 1257 #else 1258 if (cpu_has_fpu) { 1259 save_fp_context = _save_fp_context; 1260 restore_fp_context = _restore_fp_context; 1261 } else { 1262 save_fp_context = fpu_emulator_save_context; 1263 restore_fp_context = fpu_emulator_restore_context; 1264 } 1265 #endif 1266 } 1267 1268 #ifdef CONFIG_MIPS32_COMPAT 1269 1270 /* 1271 * This is used by 32-bit signal stuff on the 64-bit kernel 1272 */ 1273 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); 1274 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); 1275 1276 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); 1277 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); 1278 1279 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); 1280 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); 1281 1282 static inline void signal32_init(void) 1283 { 1284 if (cpu_has_fpu) { 1285 save_fp_context32 = _save_fp_context32; 1286 restore_fp_context32 = _restore_fp_context32; 1287 } else { 1288 save_fp_context32 = fpu_emulator_save_context32; 1289 restore_fp_context32 = fpu_emulator_restore_context32; 1290 } 1291 } 1292 #endif 1293 1294 extern void cpu_cache_init(void); 1295 extern void tlb_init(void); 1296 extern void flush_tlb_handlers(void); 1297 1298 /* 1299 * Timer interrupt 1300 */ 1301 int cp0_compare_irq; 1302 1303 /* 1304 * Performance counter IRQ or -1 if shared with timer 1305 */ 1306 int cp0_perfcount_irq; 1307 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1308 1309 void __cpuinit per_cpu_trap_init(void) 1310 { 1311 unsigned int cpu = smp_processor_id(); 1312 unsigned int status_set = ST0_CU0; 1313 #ifdef CONFIG_MIPS_MT_SMTC 1314 int secondaryTC = 0; 1315 int bootTC = (cpu == 0); 1316 1317 /* 1318 * Only do per_cpu_trap_init() for first TC of Each VPE. 1319 * Note that this hack assumes that the SMTC init code 1320 * assigns TCs consecutively and in ascending order. 1321 */ 1322 1323 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1324 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1325 secondaryTC = 1; 1326 #endif /* CONFIG_MIPS_MT_SMTC */ 1327 1328 /* 1329 * Disable coprocessors and select 32-bit or 64-bit addressing 1330 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1331 * flag that some firmware may have left set and the TS bit (for 1332 * IP27). Set XX for ISA IV code to work. 1333 */ 1334 #ifdef CONFIG_64BIT 1335 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1336 #endif 1337 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1338 status_set |= ST0_XX; 1339 if (cpu_has_dsp) 1340 status_set |= ST0_MX; 1341 1342 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1343 status_set); 1344 1345 #ifdef CONFIG_CPU_MIPSR2 1346 if (cpu_has_mips_r2) { 1347 unsigned int enable = 0x0000000f; 1348 1349 if (cpu_has_userlocal) 1350 enable |= (1 << 29); 1351 1352 write_c0_hwrena(enable); 1353 } 1354 #endif 1355 1356 #ifdef CONFIG_MIPS_MT_SMTC 1357 if (!secondaryTC) { 1358 #endif /* CONFIG_MIPS_MT_SMTC */ 1359 1360 if (cpu_has_veic || cpu_has_vint) { 1361 write_c0_ebase(ebase); 1362 /* Setting vector spacing enables EI/VI mode */ 1363 change_c0_intctl(0x3e0, VECTORSPACING); 1364 } 1365 if (cpu_has_divec) { 1366 if (cpu_has_mipsmt) { 1367 unsigned int vpflags = dvpe(); 1368 set_c0_cause(CAUSEF_IV); 1369 evpe(vpflags); 1370 } else 1371 set_c0_cause(CAUSEF_IV); 1372 } 1373 1374 /* 1375 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1376 * 1377 * o read IntCtl.IPTI to determine the timer interrupt 1378 * o read IntCtl.IPPCI to determine the performance counter interrupt 1379 */ 1380 if (cpu_has_mips_r2) { 1381 cp0_compare_irq = (read_c0_intctl() >> 29) & 7; 1382 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; 1383 if (cp0_perfcount_irq == cp0_compare_irq) 1384 cp0_perfcount_irq = -1; 1385 } else { 1386 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1387 cp0_perfcount_irq = -1; 1388 } 1389 1390 #ifdef CONFIG_MIPS_MT_SMTC 1391 } 1392 #endif /* CONFIG_MIPS_MT_SMTC */ 1393 1394 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1395 TLBMISS_HANDLER_SETUP(); 1396 1397 atomic_inc(&init_mm.mm_count); 1398 current->active_mm = &init_mm; 1399 BUG_ON(current->mm); 1400 enter_lazy_tlb(&init_mm, current); 1401 1402 #ifdef CONFIG_MIPS_MT_SMTC 1403 if (bootTC) { 1404 #endif /* CONFIG_MIPS_MT_SMTC */ 1405 cpu_cache_init(); 1406 tlb_init(); 1407 #ifdef CONFIG_MIPS_MT_SMTC 1408 } else if (!secondaryTC) { 1409 /* 1410 * First TC in non-boot VPE must do subset of tlb_init() 1411 * for MMU countrol registers. 1412 */ 1413 write_c0_pagemask(PM_DEFAULT_MASK); 1414 write_c0_wired(0); 1415 } 1416 #endif /* CONFIG_MIPS_MT_SMTC */ 1417 } 1418 1419 /* Install CPU exception handler */ 1420 void __init set_handler(unsigned long offset, void *addr, unsigned long size) 1421 { 1422 memcpy((void *)(ebase + offset), addr, size); 1423 flush_icache_range(ebase + offset, ebase + offset + size); 1424 } 1425 1426 static char panic_null_cerr[] __cpuinitdata = 1427 "Trying to set NULL cache error exception handler"; 1428 1429 /* Install uncached CPU exception handler */ 1430 void __cpuinit set_uncached_handler(unsigned long offset, void *addr, 1431 unsigned long size) 1432 { 1433 #ifdef CONFIG_32BIT 1434 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1435 #endif 1436 #ifdef CONFIG_64BIT 1437 unsigned long uncached_ebase = TO_UNCAC(ebase); 1438 #endif 1439 1440 if (!addr) 1441 panic(panic_null_cerr); 1442 1443 memcpy((void *)(uncached_ebase + offset), addr, size); 1444 } 1445 1446 static int __initdata rdhwr_noopt; 1447 static int __init set_rdhwr_noopt(char *str) 1448 { 1449 rdhwr_noopt = 1; 1450 return 1; 1451 } 1452 1453 __setup("rdhwr_noopt", set_rdhwr_noopt); 1454 1455 void __init trap_init(void) 1456 { 1457 extern char except_vec3_generic, except_vec3_r4000; 1458 extern char except_vec4; 1459 unsigned long i; 1460 1461 if (cpu_has_veic || cpu_has_vint) 1462 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); 1463 else 1464 ebase = CAC_BASE; 1465 1466 per_cpu_trap_init(); 1467 1468 /* 1469 * Copy the generic exception handlers to their final destination. 1470 * This will be overriden later as suitable for a particular 1471 * configuration. 1472 */ 1473 set_handler(0x180, &except_vec3_generic, 0x80); 1474 1475 /* 1476 * Setup default vectors 1477 */ 1478 for (i = 0; i <= 31; i++) 1479 set_except_vector(i, handle_reserved); 1480 1481 /* 1482 * Copy the EJTAG debug exception vector handler code to it's final 1483 * destination. 1484 */ 1485 if (cpu_has_ejtag && board_ejtag_handler_setup) 1486 board_ejtag_handler_setup(); 1487 1488 /* 1489 * Only some CPUs have the watch exceptions. 1490 */ 1491 if (cpu_has_watch) 1492 set_except_vector(23, handle_watch); 1493 1494 /* 1495 * Initialise interrupt handlers 1496 */ 1497 if (cpu_has_veic || cpu_has_vint) { 1498 int nvec = cpu_has_veic ? 64 : 8; 1499 for (i = 0; i < nvec; i++) 1500 set_vi_handler(i, NULL); 1501 } 1502 else if (cpu_has_divec) 1503 set_handler(0x200, &except_vec4, 0x8); 1504 1505 /* 1506 * Some CPUs can enable/disable for cache parity detection, but does 1507 * it different ways. 1508 */ 1509 parity_protection_init(); 1510 1511 /* 1512 * The Data Bus Errors / Instruction Bus Errors are signaled 1513 * by external hardware. Therefore these two exceptions 1514 * may have board specific handlers. 1515 */ 1516 if (board_be_init) 1517 board_be_init(); 1518 1519 set_except_vector(0, handle_int); 1520 set_except_vector(1, handle_tlbm); 1521 set_except_vector(2, handle_tlbl); 1522 set_except_vector(3, handle_tlbs); 1523 1524 set_except_vector(4, handle_adel); 1525 set_except_vector(5, handle_ades); 1526 1527 set_except_vector(6, handle_ibe); 1528 set_except_vector(7, handle_dbe); 1529 1530 set_except_vector(8, handle_sys); 1531 set_except_vector(9, handle_bp); 1532 set_except_vector(10, rdhwr_noopt ? handle_ri : 1533 (cpu_has_vtag_icache ? 1534 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1535 set_except_vector(11, handle_cpu); 1536 set_except_vector(12, handle_ov); 1537 set_except_vector(13, handle_tr); 1538 1539 if (current_cpu_type() == CPU_R6000 || 1540 current_cpu_type() == CPU_R6000A) { 1541 /* 1542 * The R6000 is the only R-series CPU that features a machine 1543 * check exception (similar to the R4000 cache error) and 1544 * unaligned ldc1/sdc1 exception. The handlers have not been 1545 * written yet. Well, anyway there is no R6000 machine on the 1546 * current list of targets for Linux/MIPS. 1547 * (Duh, crap, there is someone with a triple R6k machine) 1548 */ 1549 //set_except_vector(14, handle_mc); 1550 //set_except_vector(15, handle_ndc); 1551 } 1552 1553 1554 if (board_nmi_handler_setup) 1555 board_nmi_handler_setup(); 1556 1557 if (cpu_has_fpu && !cpu_has_nofpuex) 1558 set_except_vector(15, handle_fpe); 1559 1560 set_except_vector(22, handle_mdmx); 1561 1562 if (cpu_has_mcheck) 1563 set_except_vector(24, handle_mcheck); 1564 1565 if (cpu_has_mipsmt) 1566 set_except_vector(25, handle_mt); 1567 1568 set_except_vector(26, handle_dsp); 1569 1570 if (cpu_has_vce) 1571 /* Special exception: R4[04]00 uses also the divec space. */ 1572 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1573 else if (cpu_has_4kex) 1574 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1575 else 1576 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1577 1578 signal_init(); 1579 #ifdef CONFIG_MIPS32_COMPAT 1580 signal32_init(); 1581 #endif 1582 1583 flush_icache_range(ebase, ebase + 0x400); 1584 flush_tlb_handlers(); 1585 } 1586