1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. 13 * Copyright (C) 2014, Imagination Technologies Ltd. 14 */ 15 #include <linux/bug.h> 16 #include <linux/compiler.h> 17 #include <linux/context_tracking.h> 18 #include <linux/kexec.h> 19 #include <linux/init.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/mm.h> 23 #include <linux/sched.h> 24 #include <linux/smp.h> 25 #include <linux/spinlock.h> 26 #include <linux/kallsyms.h> 27 #include <linux/bootmem.h> 28 #include <linux/interrupt.h> 29 #include <linux/ptrace.h> 30 #include <linux/kgdb.h> 31 #include <linux/kdebug.h> 32 #include <linux/kprobes.h> 33 #include <linux/notifier.h> 34 #include <linux/kdb.h> 35 #include <linux/irq.h> 36 #include <linux/perf_event.h> 37 38 #include <asm/bootinfo.h> 39 #include <asm/branch.h> 40 #include <asm/break.h> 41 #include <asm/cop2.h> 42 #include <asm/cpu.h> 43 #include <asm/cpu-type.h> 44 #include <asm/dsp.h> 45 #include <asm/fpu.h> 46 #include <asm/fpu_emulator.h> 47 #include <asm/idle.h> 48 #include <asm/mipsregs.h> 49 #include <asm/mipsmtregs.h> 50 #include <asm/module.h> 51 #include <asm/msa.h> 52 #include <asm/pgtable.h> 53 #include <asm/ptrace.h> 54 #include <asm/sections.h> 55 #include <asm/tlbdebug.h> 56 #include <asm/traps.h> 57 #include <asm/uaccess.h> 58 #include <asm/watch.h> 59 #include <asm/mmu_context.h> 60 #include <asm/types.h> 61 #include <asm/stacktrace.h> 62 #include <asm/uasm.h> 63 64 extern void check_wait(void); 65 extern asmlinkage void rollback_handle_int(void); 66 extern asmlinkage void handle_int(void); 67 extern u32 handle_tlbl[]; 68 extern u32 handle_tlbs[]; 69 extern u32 handle_tlbm[]; 70 extern asmlinkage void handle_adel(void); 71 extern asmlinkage void handle_ades(void); 72 extern asmlinkage void handle_ibe(void); 73 extern asmlinkage void handle_dbe(void); 74 extern asmlinkage void handle_sys(void); 75 extern asmlinkage void handle_bp(void); 76 extern asmlinkage void handle_ri(void); 77 extern asmlinkage void handle_ri_rdhwr_vivt(void); 78 extern asmlinkage void handle_ri_rdhwr(void); 79 extern asmlinkage void handle_cpu(void); 80 extern asmlinkage void handle_ov(void); 81 extern asmlinkage void handle_tr(void); 82 extern asmlinkage void handle_msa_fpe(void); 83 extern asmlinkage void handle_fpe(void); 84 extern asmlinkage void handle_ftlb(void); 85 extern asmlinkage void handle_msa(void); 86 extern asmlinkage void handle_mdmx(void); 87 extern asmlinkage void handle_watch(void); 88 extern asmlinkage void handle_mt(void); 89 extern asmlinkage void handle_dsp(void); 90 extern asmlinkage void handle_mcheck(void); 91 extern asmlinkage void handle_reserved(void); 92 93 void (*board_be_init)(void); 94 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 95 void (*board_nmi_handler_setup)(void); 96 void (*board_ejtag_handler_setup)(void); 97 void (*board_bind_eic_interrupt)(int irq, int regset); 98 void (*board_ebase_setup)(void); 99 void(*board_cache_error_setup)(void); 100 101 static void show_raw_backtrace(unsigned long reg29) 102 { 103 unsigned long *sp = (unsigned long *)(reg29 & ~3); 104 unsigned long addr; 105 106 printk("Call Trace:"); 107 #ifdef CONFIG_KALLSYMS 108 printk("\n"); 109 #endif 110 while (!kstack_end(sp)) { 111 unsigned long __user *p = 112 (unsigned long __user *)(unsigned long)sp++; 113 if (__get_user(addr, p)) { 114 printk(" (Bad stack address)"); 115 break; 116 } 117 if (__kernel_text_address(addr)) 118 print_ip_sym(addr); 119 } 120 printk("\n"); 121 } 122 123 #ifdef CONFIG_KALLSYMS 124 int raw_show_trace; 125 static int __init set_raw_show_trace(char *str) 126 { 127 raw_show_trace = 1; 128 return 1; 129 } 130 __setup("raw_show_trace", set_raw_show_trace); 131 #endif 132 133 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 134 { 135 unsigned long sp = regs->regs[29]; 136 unsigned long ra = regs->regs[31]; 137 unsigned long pc = regs->cp0_epc; 138 139 if (!task) 140 task = current; 141 142 if (raw_show_trace || !__kernel_text_address(pc)) { 143 show_raw_backtrace(sp); 144 return; 145 } 146 printk("Call Trace:\n"); 147 do { 148 print_ip_sym(pc); 149 pc = unwind_stack(task, &sp, pc, &ra); 150 } while (pc); 151 printk("\n"); 152 } 153 154 /* 155 * This routine abuses get_user()/put_user() to reference pointers 156 * with at least a bit of error checking ... 157 */ 158 static void show_stacktrace(struct task_struct *task, 159 const struct pt_regs *regs) 160 { 161 const int field = 2 * sizeof(unsigned long); 162 long stackdata; 163 int i; 164 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 165 166 printk("Stack :"); 167 i = 0; 168 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 169 if (i && ((i % (64 / field)) == 0)) 170 printk("\n "); 171 if (i > 39) { 172 printk(" ..."); 173 break; 174 } 175 176 if (__get_user(stackdata, sp++)) { 177 printk(" (Bad stack address)"); 178 break; 179 } 180 181 printk(" %0*lx", field, stackdata); 182 i++; 183 } 184 printk("\n"); 185 show_backtrace(task, regs); 186 } 187 188 void show_stack(struct task_struct *task, unsigned long *sp) 189 { 190 struct pt_regs regs; 191 if (sp) { 192 regs.regs[29] = (unsigned long)sp; 193 regs.regs[31] = 0; 194 regs.cp0_epc = 0; 195 } else { 196 if (task && task != current) { 197 regs.regs[29] = task->thread.reg29; 198 regs.regs[31] = 0; 199 regs.cp0_epc = task->thread.reg31; 200 #ifdef CONFIG_KGDB_KDB 201 } else if (atomic_read(&kgdb_active) != -1 && 202 kdb_current_regs) { 203 memcpy(®s, kdb_current_regs, sizeof(regs)); 204 #endif /* CONFIG_KGDB_KDB */ 205 } else { 206 prepare_frametrace(®s); 207 } 208 } 209 show_stacktrace(task, ®s); 210 } 211 212 static void show_code(unsigned int __user *pc) 213 { 214 long i; 215 unsigned short __user *pc16 = NULL; 216 217 printk("\nCode:"); 218 219 if ((unsigned long)pc & 1) 220 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 221 for(i = -3 ; i < 6 ; i++) { 222 unsigned int insn; 223 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 224 printk(" (Bad address in epc)\n"); 225 break; 226 } 227 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 228 } 229 } 230 231 static void __show_regs(const struct pt_regs *regs) 232 { 233 const int field = 2 * sizeof(unsigned long); 234 unsigned int cause = regs->cp0_cause; 235 int i; 236 237 show_regs_print_info(KERN_DEFAULT); 238 239 /* 240 * Saved main processor registers 241 */ 242 for (i = 0; i < 32; ) { 243 if ((i % 4) == 0) 244 printk("$%2d :", i); 245 if (i == 0) 246 printk(" %0*lx", field, 0UL); 247 else if (i == 26 || i == 27) 248 printk(" %*s", field, ""); 249 else 250 printk(" %0*lx", field, regs->regs[i]); 251 252 i++; 253 if ((i % 4) == 0) 254 printk("\n"); 255 } 256 257 #ifdef CONFIG_CPU_HAS_SMARTMIPS 258 printk("Acx : %0*lx\n", field, regs->acx); 259 #endif 260 printk("Hi : %0*lx\n", field, regs->hi); 261 printk("Lo : %0*lx\n", field, regs->lo); 262 263 /* 264 * Saved cp0 registers 265 */ 266 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 267 (void *) regs->cp0_epc); 268 printk(" %s\n", print_tainted()); 269 printk("ra : %0*lx %pS\n", field, regs->regs[31], 270 (void *) regs->regs[31]); 271 272 printk("Status: %08x ", (uint32_t) regs->cp0_status); 273 274 if (cpu_has_3kex) { 275 if (regs->cp0_status & ST0_KUO) 276 printk("KUo "); 277 if (regs->cp0_status & ST0_IEO) 278 printk("IEo "); 279 if (regs->cp0_status & ST0_KUP) 280 printk("KUp "); 281 if (regs->cp0_status & ST0_IEP) 282 printk("IEp "); 283 if (regs->cp0_status & ST0_KUC) 284 printk("KUc "); 285 if (regs->cp0_status & ST0_IEC) 286 printk("IEc "); 287 } else if (cpu_has_4kex) { 288 if (regs->cp0_status & ST0_KX) 289 printk("KX "); 290 if (regs->cp0_status & ST0_SX) 291 printk("SX "); 292 if (regs->cp0_status & ST0_UX) 293 printk("UX "); 294 switch (regs->cp0_status & ST0_KSU) { 295 case KSU_USER: 296 printk("USER "); 297 break; 298 case KSU_SUPERVISOR: 299 printk("SUPERVISOR "); 300 break; 301 case KSU_KERNEL: 302 printk("KERNEL "); 303 break; 304 default: 305 printk("BAD_MODE "); 306 break; 307 } 308 if (regs->cp0_status & ST0_ERL) 309 printk("ERL "); 310 if (regs->cp0_status & ST0_EXL) 311 printk("EXL "); 312 if (regs->cp0_status & ST0_IE) 313 printk("IE "); 314 } 315 printk("\n"); 316 317 printk("Cause : %08x\n", cause); 318 319 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 320 if (1 <= cause && cause <= 5) 321 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 322 323 printk("PrId : %08x (%s)\n", read_c0_prid(), 324 cpu_name_string()); 325 } 326 327 /* 328 * FIXME: really the generic show_regs should take a const pointer argument. 329 */ 330 void show_regs(struct pt_regs *regs) 331 { 332 __show_regs((struct pt_regs *)regs); 333 } 334 335 void show_registers(struct pt_regs *regs) 336 { 337 const int field = 2 * sizeof(unsigned long); 338 mm_segment_t old_fs = get_fs(); 339 340 __show_regs(regs); 341 print_modules(); 342 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 343 current->comm, current->pid, current_thread_info(), current, 344 field, current_thread_info()->tp_value); 345 if (cpu_has_userlocal) { 346 unsigned long tls; 347 348 tls = read_c0_userlocal(); 349 if (tls != current_thread_info()->tp_value) 350 printk("*HwTLS: %0*lx\n", field, tls); 351 } 352 353 if (!user_mode(regs)) 354 /* Necessary for getting the correct stack content */ 355 set_fs(KERNEL_DS); 356 show_stacktrace(current, regs); 357 show_code((unsigned int __user *) regs->cp0_epc); 358 printk("\n"); 359 set_fs(old_fs); 360 } 361 362 static int regs_to_trapnr(struct pt_regs *regs) 363 { 364 return (regs->cp0_cause >> 2) & 0x1f; 365 } 366 367 static DEFINE_RAW_SPINLOCK(die_lock); 368 369 void __noreturn die(const char *str, struct pt_regs *regs) 370 { 371 static int die_counter; 372 int sig = SIGSEGV; 373 #ifdef CONFIG_MIPS_MT_SMTC 374 unsigned long dvpret; 375 #endif /* CONFIG_MIPS_MT_SMTC */ 376 377 oops_enter(); 378 379 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), 380 SIGSEGV) == NOTIFY_STOP) 381 sig = 0; 382 383 console_verbose(); 384 raw_spin_lock_irq(&die_lock); 385 #ifdef CONFIG_MIPS_MT_SMTC 386 dvpret = dvpe(); 387 #endif /* CONFIG_MIPS_MT_SMTC */ 388 bust_spinlocks(1); 389 #ifdef CONFIG_MIPS_MT_SMTC 390 mips_mt_regdump(dvpret); 391 #endif /* CONFIG_MIPS_MT_SMTC */ 392 393 printk("%s[#%d]:\n", str, ++die_counter); 394 show_registers(regs); 395 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 396 raw_spin_unlock_irq(&die_lock); 397 398 oops_exit(); 399 400 if (in_interrupt()) 401 panic("Fatal exception in interrupt"); 402 403 if (panic_on_oops) { 404 printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); 405 ssleep(5); 406 panic("Fatal exception"); 407 } 408 409 if (regs && kexec_should_crash(current)) 410 crash_kexec(regs); 411 412 do_exit(sig); 413 } 414 415 extern struct exception_table_entry __start___dbe_table[]; 416 extern struct exception_table_entry __stop___dbe_table[]; 417 418 __asm__( 419 " .section __dbe_table, \"a\"\n" 420 " .previous \n"); 421 422 /* Given an address, look for it in the exception tables. */ 423 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 424 { 425 const struct exception_table_entry *e; 426 427 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 428 if (!e) 429 e = search_module_dbetables(addr); 430 return e; 431 } 432 433 asmlinkage void do_be(struct pt_regs *regs) 434 { 435 const int field = 2 * sizeof(unsigned long); 436 const struct exception_table_entry *fixup = NULL; 437 int data = regs->cp0_cause & 4; 438 int action = MIPS_BE_FATAL; 439 enum ctx_state prev_state; 440 441 prev_state = exception_enter(); 442 /* XXX For now. Fixme, this searches the wrong table ... */ 443 if (data && !user_mode(regs)) 444 fixup = search_dbe_tables(exception_epc(regs)); 445 446 if (fixup) 447 action = MIPS_BE_FIXUP; 448 449 if (board_be_handler) 450 action = board_be_handler(regs, fixup != NULL); 451 452 switch (action) { 453 case MIPS_BE_DISCARD: 454 goto out; 455 case MIPS_BE_FIXUP: 456 if (fixup) { 457 regs->cp0_epc = fixup->nextinsn; 458 goto out; 459 } 460 break; 461 default: 462 break; 463 } 464 465 /* 466 * Assume it would be too dangerous to continue ... 467 */ 468 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 469 data ? "Data" : "Instruction", 470 field, regs->cp0_epc, field, regs->regs[31]); 471 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), 472 SIGBUS) == NOTIFY_STOP) 473 goto out; 474 475 die_if_kernel("Oops", regs); 476 force_sig(SIGBUS, current); 477 478 out: 479 exception_exit(prev_state); 480 } 481 482 /* 483 * ll/sc, rdhwr, sync emulation 484 */ 485 486 #define OPCODE 0xfc000000 487 #define BASE 0x03e00000 488 #define RT 0x001f0000 489 #define OFFSET 0x0000ffff 490 #define LL 0xc0000000 491 #define SC 0xe0000000 492 #define SPEC0 0x00000000 493 #define SPEC3 0x7c000000 494 #define RD 0x0000f800 495 #define FUNC 0x0000003f 496 #define SYNC 0x0000000f 497 #define RDHWR 0x0000003b 498 499 /* microMIPS definitions */ 500 #define MM_POOL32A_FUNC 0xfc00ffff 501 #define MM_RDHWR 0x00006b3c 502 #define MM_RS 0x001f0000 503 #define MM_RT 0x03e00000 504 505 /* 506 * The ll_bit is cleared by r*_switch.S 507 */ 508 509 unsigned int ll_bit; 510 struct task_struct *ll_task; 511 512 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 513 { 514 unsigned long value, __user *vaddr; 515 long offset; 516 517 /* 518 * analyse the ll instruction that just caused a ri exception 519 * and put the referenced address to addr. 520 */ 521 522 /* sign extend offset */ 523 offset = opcode & OFFSET; 524 offset <<= 16; 525 offset >>= 16; 526 527 vaddr = (unsigned long __user *) 528 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 529 530 if ((unsigned long)vaddr & 3) 531 return SIGBUS; 532 if (get_user(value, vaddr)) 533 return SIGSEGV; 534 535 preempt_disable(); 536 537 if (ll_task == NULL || ll_task == current) { 538 ll_bit = 1; 539 } else { 540 ll_bit = 0; 541 } 542 ll_task = current; 543 544 preempt_enable(); 545 546 regs->regs[(opcode & RT) >> 16] = value; 547 548 return 0; 549 } 550 551 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 552 { 553 unsigned long __user *vaddr; 554 unsigned long reg; 555 long offset; 556 557 /* 558 * analyse the sc instruction that just caused a ri exception 559 * and put the referenced address to addr. 560 */ 561 562 /* sign extend offset */ 563 offset = opcode & OFFSET; 564 offset <<= 16; 565 offset >>= 16; 566 567 vaddr = (unsigned long __user *) 568 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 569 reg = (opcode & RT) >> 16; 570 571 if ((unsigned long)vaddr & 3) 572 return SIGBUS; 573 574 preempt_disable(); 575 576 if (ll_bit == 0 || ll_task != current) { 577 regs->regs[reg] = 0; 578 preempt_enable(); 579 return 0; 580 } 581 582 preempt_enable(); 583 584 if (put_user(regs->regs[reg], vaddr)) 585 return SIGSEGV; 586 587 regs->regs[reg] = 1; 588 589 return 0; 590 } 591 592 /* 593 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 594 * opcodes are supposed to result in coprocessor unusable exceptions if 595 * executed on ll/sc-less processors. That's the theory. In practice a 596 * few processors such as NEC's VR4100 throw reserved instruction exceptions 597 * instead, so we're doing the emulation thing in both exception handlers. 598 */ 599 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 600 { 601 if ((opcode & OPCODE) == LL) { 602 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 603 1, regs, 0); 604 return simulate_ll(regs, opcode); 605 } 606 if ((opcode & OPCODE) == SC) { 607 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 608 1, regs, 0); 609 return simulate_sc(regs, opcode); 610 } 611 612 return -1; /* Must be something else ... */ 613 } 614 615 /* 616 * Simulate trapping 'rdhwr' instructions to provide user accessible 617 * registers not implemented in hardware. 618 */ 619 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) 620 { 621 struct thread_info *ti = task_thread_info(current); 622 623 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 624 1, regs, 0); 625 switch (rd) { 626 case 0: /* CPU number */ 627 regs->regs[rt] = smp_processor_id(); 628 return 0; 629 case 1: /* SYNCI length */ 630 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 631 current_cpu_data.icache.linesz); 632 return 0; 633 case 2: /* Read count register */ 634 regs->regs[rt] = read_c0_count(); 635 return 0; 636 case 3: /* Count register resolution */ 637 switch (current_cpu_type()) { 638 case CPU_20KC: 639 case CPU_25KF: 640 regs->regs[rt] = 1; 641 break; 642 default: 643 regs->regs[rt] = 2; 644 } 645 return 0; 646 case 29: 647 regs->regs[rt] = ti->tp_value; 648 return 0; 649 default: 650 return -1; 651 } 652 } 653 654 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) 655 { 656 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 657 int rd = (opcode & RD) >> 11; 658 int rt = (opcode & RT) >> 16; 659 660 simulate_rdhwr(regs, rd, rt); 661 return 0; 662 } 663 664 /* Not ours. */ 665 return -1; 666 } 667 668 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) 669 { 670 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { 671 int rd = (opcode & MM_RS) >> 16; 672 int rt = (opcode & MM_RT) >> 21; 673 simulate_rdhwr(regs, rd, rt); 674 return 0; 675 } 676 677 /* Not ours. */ 678 return -1; 679 } 680 681 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 682 { 683 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 684 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 685 1, regs, 0); 686 return 0; 687 } 688 689 return -1; /* Must be something else ... */ 690 } 691 692 asmlinkage void do_ov(struct pt_regs *regs) 693 { 694 enum ctx_state prev_state; 695 siginfo_t info; 696 697 prev_state = exception_enter(); 698 die_if_kernel("Integer overflow", regs); 699 700 info.si_code = FPE_INTOVF; 701 info.si_signo = SIGFPE; 702 info.si_errno = 0; 703 info.si_addr = (void __user *) regs->cp0_epc; 704 force_sig_info(SIGFPE, &info, current); 705 exception_exit(prev_state); 706 } 707 708 int process_fpemu_return(int sig, void __user *fault_addr) 709 { 710 if (sig == SIGSEGV || sig == SIGBUS) { 711 struct siginfo si = {0}; 712 si.si_addr = fault_addr; 713 si.si_signo = sig; 714 if (sig == SIGSEGV) { 715 if (find_vma(current->mm, (unsigned long)fault_addr)) 716 si.si_code = SEGV_ACCERR; 717 else 718 si.si_code = SEGV_MAPERR; 719 } else { 720 si.si_code = BUS_ADRERR; 721 } 722 force_sig_info(sig, &si, current); 723 return 1; 724 } else if (sig) { 725 force_sig(sig, current); 726 return 1; 727 } else { 728 return 0; 729 } 730 } 731 732 /* 733 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 734 */ 735 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 736 { 737 enum ctx_state prev_state; 738 siginfo_t info = {0}; 739 740 prev_state = exception_enter(); 741 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), 742 SIGFPE) == NOTIFY_STOP) 743 goto out; 744 die_if_kernel("FP exception in kernel code", regs); 745 746 if (fcr31 & FPU_CSR_UNI_X) { 747 int sig; 748 void __user *fault_addr = NULL; 749 750 /* 751 * Unimplemented operation exception. If we've got the full 752 * software emulator on-board, let's use it... 753 * 754 * Force FPU to dump state into task/thread context. We're 755 * moving a lot of data here for what is probably a single 756 * instruction, but the alternative is to pre-decode the FP 757 * register operands before invoking the emulator, which seems 758 * a bit extreme for what should be an infrequent event. 759 */ 760 /* Ensure 'resume' not overwrite saved fp context again. */ 761 lose_fpu(1); 762 763 /* Run the emulator */ 764 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 765 &fault_addr); 766 767 /* 768 * We can't allow the emulated instruction to leave any of 769 * the cause bit set in $fcr31. 770 */ 771 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 772 773 /* Restore the hardware register state */ 774 own_fpu(1); /* Using the FPU again. */ 775 776 /* If something went wrong, signal */ 777 process_fpemu_return(sig, fault_addr); 778 779 goto out; 780 } else if (fcr31 & FPU_CSR_INV_X) 781 info.si_code = FPE_FLTINV; 782 else if (fcr31 & FPU_CSR_DIV_X) 783 info.si_code = FPE_FLTDIV; 784 else if (fcr31 & FPU_CSR_OVF_X) 785 info.si_code = FPE_FLTOVF; 786 else if (fcr31 & FPU_CSR_UDF_X) 787 info.si_code = FPE_FLTUND; 788 else if (fcr31 & FPU_CSR_INE_X) 789 info.si_code = FPE_FLTRES; 790 else 791 info.si_code = __SI_FAULT; 792 info.si_signo = SIGFPE; 793 info.si_errno = 0; 794 info.si_addr = (void __user *) regs->cp0_epc; 795 force_sig_info(SIGFPE, &info, current); 796 797 out: 798 exception_exit(prev_state); 799 } 800 801 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 802 const char *str) 803 { 804 siginfo_t info; 805 char b[40]; 806 807 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 808 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 809 return; 810 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 811 812 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), 813 SIGTRAP) == NOTIFY_STOP) 814 return; 815 816 /* 817 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 818 * insns, even for trap and break codes that indicate arithmetic 819 * failures. Weird ... 820 * But should we continue the brokenness??? --macro 821 */ 822 switch (code) { 823 case BRK_OVERFLOW: 824 case BRK_DIVZERO: 825 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 826 die_if_kernel(b, regs); 827 if (code == BRK_DIVZERO) 828 info.si_code = FPE_INTDIV; 829 else 830 info.si_code = FPE_INTOVF; 831 info.si_signo = SIGFPE; 832 info.si_errno = 0; 833 info.si_addr = (void __user *) regs->cp0_epc; 834 force_sig_info(SIGFPE, &info, current); 835 break; 836 case BRK_BUG: 837 die_if_kernel("Kernel bug detected", regs); 838 force_sig(SIGTRAP, current); 839 break; 840 case BRK_MEMU: 841 /* 842 * Address errors may be deliberately induced by the FPU 843 * emulator to retake control of the CPU after executing the 844 * instruction in the delay slot of an emulated branch. 845 * 846 * Terminate if exception was recognized as a delay slot return 847 * otherwise handle as normal. 848 */ 849 if (do_dsemulret(regs)) 850 return; 851 852 die_if_kernel("Math emu break/trap", regs); 853 force_sig(SIGTRAP, current); 854 break; 855 default: 856 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 857 die_if_kernel(b, regs); 858 force_sig(SIGTRAP, current); 859 } 860 } 861 862 asmlinkage void do_bp(struct pt_regs *regs) 863 { 864 unsigned int opcode, bcode; 865 enum ctx_state prev_state; 866 unsigned long epc; 867 u16 instr[2]; 868 mm_segment_t seg; 869 870 seg = get_fs(); 871 if (!user_mode(regs)) 872 set_fs(KERNEL_DS); 873 874 prev_state = exception_enter(); 875 if (get_isa16_mode(regs->cp0_epc)) { 876 /* Calculate EPC. */ 877 epc = exception_epc(regs); 878 if (cpu_has_mmips) { 879 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) || 880 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))) 881 goto out_sigsegv; 882 opcode = (instr[0] << 16) | instr[1]; 883 } else { 884 /* MIPS16e mode */ 885 if (__get_user(instr[0], 886 (u16 __user *)msk_isa16_mode(epc))) 887 goto out_sigsegv; 888 bcode = (instr[0] >> 6) & 0x3f; 889 do_trap_or_bp(regs, bcode, "Break"); 890 goto out; 891 } 892 } else { 893 if (__get_user(opcode, 894 (unsigned int __user *) exception_epc(regs))) 895 goto out_sigsegv; 896 } 897 898 /* 899 * There is the ancient bug in the MIPS assemblers that the break 900 * code starts left to bit 16 instead to bit 6 in the opcode. 901 * Gas is bug-compatible, but not always, grrr... 902 * We handle both cases with a simple heuristics. --macro 903 */ 904 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 905 if (bcode >= (1 << 10)) 906 bcode >>= 10; 907 908 /* 909 * notify the kprobe handlers, if instruction is likely to 910 * pertain to them. 911 */ 912 switch (bcode) { 913 case BRK_KPROBE_BP: 914 if (notify_die(DIE_BREAK, "debug", regs, bcode, 915 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 916 goto out; 917 else 918 break; 919 case BRK_KPROBE_SSTEPBP: 920 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 921 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 922 goto out; 923 else 924 break; 925 default: 926 break; 927 } 928 929 do_trap_or_bp(regs, bcode, "Break"); 930 931 out: 932 set_fs(seg); 933 exception_exit(prev_state); 934 return; 935 936 out_sigsegv: 937 force_sig(SIGSEGV, current); 938 goto out; 939 } 940 941 asmlinkage void do_tr(struct pt_regs *regs) 942 { 943 u32 opcode, tcode = 0; 944 enum ctx_state prev_state; 945 u16 instr[2]; 946 mm_segment_t seg; 947 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 948 949 seg = get_fs(); 950 if (!user_mode(regs)) 951 set_fs(get_ds()); 952 953 prev_state = exception_enter(); 954 if (get_isa16_mode(regs->cp0_epc)) { 955 if (__get_user(instr[0], (u16 __user *)(epc + 0)) || 956 __get_user(instr[1], (u16 __user *)(epc + 2))) 957 goto out_sigsegv; 958 opcode = (instr[0] << 16) | instr[1]; 959 /* Immediate versions don't provide a code. */ 960 if (!(opcode & OPCODE)) 961 tcode = (opcode >> 12) & ((1 << 4) - 1); 962 } else { 963 if (__get_user(opcode, (u32 __user *)epc)) 964 goto out_sigsegv; 965 /* Immediate versions don't provide a code. */ 966 if (!(opcode & OPCODE)) 967 tcode = (opcode >> 6) & ((1 << 10) - 1); 968 } 969 970 do_trap_or_bp(regs, tcode, "Trap"); 971 972 out: 973 set_fs(seg); 974 exception_exit(prev_state); 975 return; 976 977 out_sigsegv: 978 force_sig(SIGSEGV, current); 979 goto out; 980 } 981 982 asmlinkage void do_ri(struct pt_regs *regs) 983 { 984 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 985 unsigned long old_epc = regs->cp0_epc; 986 unsigned long old31 = regs->regs[31]; 987 enum ctx_state prev_state; 988 unsigned int opcode = 0; 989 int status = -1; 990 991 prev_state = exception_enter(); 992 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), 993 SIGILL) == NOTIFY_STOP) 994 goto out; 995 996 die_if_kernel("Reserved instruction in kernel code", regs); 997 998 if (unlikely(compute_return_epc(regs) < 0)) 999 goto out; 1000 1001 if (get_isa16_mode(regs->cp0_epc)) { 1002 unsigned short mmop[2] = { 0 }; 1003 1004 if (unlikely(get_user(mmop[0], epc) < 0)) 1005 status = SIGSEGV; 1006 if (unlikely(get_user(mmop[1], epc) < 0)) 1007 status = SIGSEGV; 1008 opcode = (mmop[0] << 16) | mmop[1]; 1009 1010 if (status < 0) 1011 status = simulate_rdhwr_mm(regs, opcode); 1012 } else { 1013 if (unlikely(get_user(opcode, epc) < 0)) 1014 status = SIGSEGV; 1015 1016 if (!cpu_has_llsc && status < 0) 1017 status = simulate_llsc(regs, opcode); 1018 1019 if (status < 0) 1020 status = simulate_rdhwr_normal(regs, opcode); 1021 1022 if (status < 0) 1023 status = simulate_sync(regs, opcode); 1024 } 1025 1026 if (status < 0) 1027 status = SIGILL; 1028 1029 if (unlikely(status > 0)) { 1030 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1031 regs->regs[31] = old31; 1032 force_sig(status, current); 1033 } 1034 1035 out: 1036 exception_exit(prev_state); 1037 } 1038 1039 /* 1040 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 1041 * emulated more than some threshold number of instructions, force migration to 1042 * a "CPU" that has FP support. 1043 */ 1044 static void mt_ase_fp_affinity(void) 1045 { 1046 #ifdef CONFIG_MIPS_MT_FPAFF 1047 if (mt_fpemul_threshold > 0 && 1048 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 1049 /* 1050 * If there's no FPU present, or if the application has already 1051 * restricted the allowed set to exclude any CPUs with FPUs, 1052 * we'll skip the procedure. 1053 */ 1054 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 1055 cpumask_t tmask; 1056 1057 current->thread.user_cpus_allowed 1058 = current->cpus_allowed; 1059 cpus_and(tmask, current->cpus_allowed, 1060 mt_fpu_cpumask); 1061 set_cpus_allowed_ptr(current, &tmask); 1062 set_thread_flag(TIF_FPUBOUND); 1063 } 1064 } 1065 #endif /* CONFIG_MIPS_MT_FPAFF */ 1066 } 1067 1068 /* 1069 * No lock; only written during early bootup by CPU 0. 1070 */ 1071 static RAW_NOTIFIER_HEAD(cu2_chain); 1072 1073 int __ref register_cu2_notifier(struct notifier_block *nb) 1074 { 1075 return raw_notifier_chain_register(&cu2_chain, nb); 1076 } 1077 1078 int cu2_notifier_call_chain(unsigned long val, void *v) 1079 { 1080 return raw_notifier_call_chain(&cu2_chain, val, v); 1081 } 1082 1083 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 1084 void *data) 1085 { 1086 struct pt_regs *regs = data; 1087 1088 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " 1089 "instruction", regs); 1090 force_sig(SIGILL, current); 1091 1092 return NOTIFY_OK; 1093 } 1094 1095 static int enable_restore_fp_context(int msa) 1096 { 1097 int err, was_fpu_owner; 1098 1099 if (!used_math()) { 1100 /* First time FP context user. */ 1101 err = init_fpu(); 1102 if (msa && !err) 1103 enable_msa(); 1104 if (!err) 1105 set_used_math(); 1106 return err; 1107 } 1108 1109 /* 1110 * This task has formerly used the FP context. 1111 * 1112 * If this thread has no live MSA vector context then we can simply 1113 * restore the scalar FP context. If it has live MSA vector context 1114 * (that is, it has or may have used MSA since last performing a 1115 * function call) then we'll need to restore the vector context. This 1116 * applies even if we're currently only executing a scalar FP 1117 * instruction. This is because if we were to later execute an MSA 1118 * instruction then we'd either have to: 1119 * 1120 * - Restore the vector context & clobber any registers modified by 1121 * scalar FP instructions between now & then. 1122 * 1123 * or 1124 * 1125 * - Not restore the vector context & lose the most significant bits 1126 * of all vector registers. 1127 * 1128 * Neither of those options is acceptable. We cannot restore the least 1129 * significant bits of the registers now & only restore the most 1130 * significant bits later because the most significant bits of any 1131 * vector registers whose aliased FP register is modified now will have 1132 * been zeroed. We'd have no way to know that when restoring the vector 1133 * context & thus may load an outdated value for the most significant 1134 * bits of a vector register. 1135 */ 1136 if (!msa && !thread_msa_context_live()) 1137 return own_fpu(1); 1138 1139 /* 1140 * This task is using or has previously used MSA. Thus we require 1141 * that Status.FR == 1. 1142 */ 1143 was_fpu_owner = is_fpu_owner(); 1144 err = own_fpu(0); 1145 if (err) 1146 return err; 1147 1148 enable_msa(); 1149 write_msa_csr(current->thread.fpu.msacsr); 1150 set_thread_flag(TIF_USEDMSA); 1151 1152 /* 1153 * If this is the first time that the task is using MSA and it has 1154 * previously used scalar FP in this time slice then we already nave 1155 * FP context which we shouldn't clobber. 1156 */ 1157 if (!test_and_set_thread_flag(TIF_MSA_CTX_LIVE) && was_fpu_owner) 1158 return 0; 1159 1160 /* We need to restore the vector context. */ 1161 restore_msa(current); 1162 return 0; 1163 } 1164 1165 asmlinkage void do_cpu(struct pt_regs *regs) 1166 { 1167 enum ctx_state prev_state; 1168 unsigned int __user *epc; 1169 unsigned long old_epc, old31; 1170 unsigned int opcode; 1171 unsigned int cpid; 1172 int status, err; 1173 unsigned long __maybe_unused flags; 1174 1175 prev_state = exception_enter(); 1176 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1177 1178 if (cpid != 2) 1179 die_if_kernel("do_cpu invoked from kernel context!", regs); 1180 1181 switch (cpid) { 1182 case 0: 1183 epc = (unsigned int __user *)exception_epc(regs); 1184 old_epc = regs->cp0_epc; 1185 old31 = regs->regs[31]; 1186 opcode = 0; 1187 status = -1; 1188 1189 if (unlikely(compute_return_epc(regs) < 0)) 1190 goto out; 1191 1192 if (get_isa16_mode(regs->cp0_epc)) { 1193 unsigned short mmop[2] = { 0 }; 1194 1195 if (unlikely(get_user(mmop[0], epc) < 0)) 1196 status = SIGSEGV; 1197 if (unlikely(get_user(mmop[1], epc) < 0)) 1198 status = SIGSEGV; 1199 opcode = (mmop[0] << 16) | mmop[1]; 1200 1201 if (status < 0) 1202 status = simulate_rdhwr_mm(regs, opcode); 1203 } else { 1204 if (unlikely(get_user(opcode, epc) < 0)) 1205 status = SIGSEGV; 1206 1207 if (!cpu_has_llsc && status < 0) 1208 status = simulate_llsc(regs, opcode); 1209 1210 if (status < 0) 1211 status = simulate_rdhwr_normal(regs, opcode); 1212 } 1213 1214 if (status < 0) 1215 status = SIGILL; 1216 1217 if (unlikely(status > 0)) { 1218 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1219 regs->regs[31] = old31; 1220 force_sig(status, current); 1221 } 1222 1223 goto out; 1224 1225 case 3: 1226 /* 1227 * Old (MIPS I and MIPS II) processors will set this code 1228 * for COP1X opcode instructions that replaced the original 1229 * COP3 space. We don't limit COP1 space instructions in 1230 * the emulator according to the CPU ISA, so we want to 1231 * treat COP1X instructions consistently regardless of which 1232 * code the CPU chose. Therefore we redirect this trap to 1233 * the FP emulator too. 1234 * 1235 * Then some newer FPU-less processors use this code 1236 * erroneously too, so they are covered by this choice 1237 * as well. 1238 */ 1239 if (raw_cpu_has_fpu) 1240 break; 1241 /* Fall through. */ 1242 1243 case 1: 1244 err = enable_restore_fp_context(0); 1245 1246 if (!raw_cpu_has_fpu || err) { 1247 int sig; 1248 void __user *fault_addr = NULL; 1249 sig = fpu_emulator_cop1Handler(regs, 1250 ¤t->thread.fpu, 1251 0, &fault_addr); 1252 if (!process_fpemu_return(sig, fault_addr) && !err) 1253 mt_ase_fp_affinity(); 1254 } 1255 1256 goto out; 1257 1258 case 2: 1259 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1260 goto out; 1261 } 1262 1263 force_sig(SIGILL, current); 1264 1265 out: 1266 exception_exit(prev_state); 1267 } 1268 1269 asmlinkage void do_msa_fpe(struct pt_regs *regs) 1270 { 1271 enum ctx_state prev_state; 1272 1273 prev_state = exception_enter(); 1274 die_if_kernel("do_msa_fpe invoked from kernel context!", regs); 1275 force_sig(SIGFPE, current); 1276 exception_exit(prev_state); 1277 } 1278 1279 asmlinkage void do_msa(struct pt_regs *regs) 1280 { 1281 enum ctx_state prev_state; 1282 int err; 1283 1284 prev_state = exception_enter(); 1285 1286 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { 1287 force_sig(SIGILL, current); 1288 goto out; 1289 } 1290 1291 die_if_kernel("do_msa invoked from kernel context!", regs); 1292 1293 err = enable_restore_fp_context(1); 1294 if (err) 1295 force_sig(SIGILL, current); 1296 out: 1297 exception_exit(prev_state); 1298 } 1299 1300 asmlinkage void do_mdmx(struct pt_regs *regs) 1301 { 1302 enum ctx_state prev_state; 1303 1304 prev_state = exception_enter(); 1305 force_sig(SIGILL, current); 1306 exception_exit(prev_state); 1307 } 1308 1309 /* 1310 * Called with interrupts disabled. 1311 */ 1312 asmlinkage void do_watch(struct pt_regs *regs) 1313 { 1314 enum ctx_state prev_state; 1315 u32 cause; 1316 1317 prev_state = exception_enter(); 1318 /* 1319 * Clear WP (bit 22) bit of cause register so we don't loop 1320 * forever. 1321 */ 1322 cause = read_c0_cause(); 1323 cause &= ~(1 << 22); 1324 write_c0_cause(cause); 1325 1326 /* 1327 * If the current thread has the watch registers loaded, save 1328 * their values and send SIGTRAP. Otherwise another thread 1329 * left the registers set, clear them and continue. 1330 */ 1331 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1332 mips_read_watch_registers(); 1333 local_irq_enable(); 1334 force_sig(SIGTRAP, current); 1335 } else { 1336 mips_clear_watch_registers(); 1337 local_irq_enable(); 1338 } 1339 exception_exit(prev_state); 1340 } 1341 1342 asmlinkage void do_mcheck(struct pt_regs *regs) 1343 { 1344 const int field = 2 * sizeof(unsigned long); 1345 int multi_match = regs->cp0_status & ST0_TS; 1346 enum ctx_state prev_state; 1347 1348 prev_state = exception_enter(); 1349 show_regs(regs); 1350 1351 if (multi_match) { 1352 printk("Index : %0x\n", read_c0_index()); 1353 printk("Pagemask: %0x\n", read_c0_pagemask()); 1354 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 1355 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 1356 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 1357 printk("\n"); 1358 dump_tlb_all(); 1359 } 1360 1361 show_code((unsigned int __user *) regs->cp0_epc); 1362 1363 /* 1364 * Some chips may have other causes of machine check (e.g. SB1 1365 * graduation timer) 1366 */ 1367 panic("Caught Machine Check exception - %scaused by multiple " 1368 "matching entries in the TLB.", 1369 (multi_match) ? "" : "not "); 1370 } 1371 1372 asmlinkage void do_mt(struct pt_regs *regs) 1373 { 1374 int subcode; 1375 1376 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1377 >> VPECONTROL_EXCPT_SHIFT; 1378 switch (subcode) { 1379 case 0: 1380 printk(KERN_DEBUG "Thread Underflow\n"); 1381 break; 1382 case 1: 1383 printk(KERN_DEBUG "Thread Overflow\n"); 1384 break; 1385 case 2: 1386 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1387 break; 1388 case 3: 1389 printk(KERN_DEBUG "Gating Storage Exception\n"); 1390 break; 1391 case 4: 1392 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1393 break; 1394 case 5: 1395 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1396 break; 1397 default: 1398 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1399 subcode); 1400 break; 1401 } 1402 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1403 1404 force_sig(SIGILL, current); 1405 } 1406 1407 1408 asmlinkage void do_dsp(struct pt_regs *regs) 1409 { 1410 if (cpu_has_dsp) 1411 panic("Unexpected DSP exception"); 1412 1413 force_sig(SIGILL, current); 1414 } 1415 1416 asmlinkage void do_reserved(struct pt_regs *regs) 1417 { 1418 /* 1419 * Game over - no way to handle this if it ever occurs. Most probably 1420 * caused by a new unknown cpu type or after another deadly 1421 * hard/software error. 1422 */ 1423 show_regs(regs); 1424 panic("Caught reserved exception %ld - should not happen.", 1425 (regs->cp0_cause & 0x7f) >> 2); 1426 } 1427 1428 static int __initdata l1parity = 1; 1429 static int __init nol1parity(char *s) 1430 { 1431 l1parity = 0; 1432 return 1; 1433 } 1434 __setup("nol1par", nol1parity); 1435 static int __initdata l2parity = 1; 1436 static int __init nol2parity(char *s) 1437 { 1438 l2parity = 0; 1439 return 1; 1440 } 1441 __setup("nol2par", nol2parity); 1442 1443 /* 1444 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1445 * it different ways. 1446 */ 1447 static inline void parity_protection_init(void) 1448 { 1449 switch (current_cpu_type()) { 1450 case CPU_24K: 1451 case CPU_34K: 1452 case CPU_74K: 1453 case CPU_1004K: 1454 case CPU_1074K: 1455 case CPU_INTERAPTIV: 1456 case CPU_PROAPTIV: 1457 case CPU_P5600: 1458 { 1459 #define ERRCTL_PE 0x80000000 1460 #define ERRCTL_L2P 0x00800000 1461 unsigned long errctl; 1462 unsigned int l1parity_present, l2parity_present; 1463 1464 errctl = read_c0_ecc(); 1465 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1466 1467 /* probe L1 parity support */ 1468 write_c0_ecc(errctl | ERRCTL_PE); 1469 back_to_back_c0_hazard(); 1470 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1471 1472 /* probe L2 parity support */ 1473 write_c0_ecc(errctl|ERRCTL_L2P); 1474 back_to_back_c0_hazard(); 1475 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1476 1477 if (l1parity_present && l2parity_present) { 1478 if (l1parity) 1479 errctl |= ERRCTL_PE; 1480 if (l1parity ^ l2parity) 1481 errctl |= ERRCTL_L2P; 1482 } else if (l1parity_present) { 1483 if (l1parity) 1484 errctl |= ERRCTL_PE; 1485 } else if (l2parity_present) { 1486 if (l2parity) 1487 errctl |= ERRCTL_L2P; 1488 } else { 1489 /* No parity available */ 1490 } 1491 1492 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1493 1494 write_c0_ecc(errctl); 1495 back_to_back_c0_hazard(); 1496 errctl = read_c0_ecc(); 1497 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1498 1499 if (l1parity_present) 1500 printk(KERN_INFO "Cache parity protection %sabled\n", 1501 (errctl & ERRCTL_PE) ? "en" : "dis"); 1502 1503 if (l2parity_present) { 1504 if (l1parity_present && l1parity) 1505 errctl ^= ERRCTL_L2P; 1506 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1507 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1508 } 1509 } 1510 break; 1511 1512 case CPU_5KC: 1513 case CPU_5KE: 1514 case CPU_LOONGSON1: 1515 write_c0_ecc(0x80000000); 1516 back_to_back_c0_hazard(); 1517 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1518 printk(KERN_INFO "Cache parity protection %sabled\n", 1519 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1520 break; 1521 case CPU_20KC: 1522 case CPU_25KF: 1523 /* Clear the DE bit (bit 16) in the c0_status register. */ 1524 printk(KERN_INFO "Enable cache parity protection for " 1525 "MIPS 20KC/25KF CPUs.\n"); 1526 clear_c0_status(ST0_DE); 1527 break; 1528 default: 1529 break; 1530 } 1531 } 1532 1533 asmlinkage void cache_parity_error(void) 1534 { 1535 const int field = 2 * sizeof(unsigned long); 1536 unsigned int reg_val; 1537 1538 /* For the moment, report the problem and hang. */ 1539 printk("Cache error exception:\n"); 1540 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1541 reg_val = read_c0_cacheerr(); 1542 printk("c0_cacheerr == %08x\n", reg_val); 1543 1544 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1545 reg_val & (1<<30) ? "secondary" : "primary", 1546 reg_val & (1<<31) ? "data" : "insn"); 1547 if (cpu_has_mips_r2 && 1548 ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { 1549 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1550 reg_val & (1<<29) ? "ED " : "", 1551 reg_val & (1<<28) ? "ET " : "", 1552 reg_val & (1<<27) ? "ES " : "", 1553 reg_val & (1<<26) ? "EE " : "", 1554 reg_val & (1<<25) ? "EB " : "", 1555 reg_val & (1<<24) ? "EI " : "", 1556 reg_val & (1<<23) ? "E1 " : "", 1557 reg_val & (1<<22) ? "E0 " : ""); 1558 } else { 1559 pr_err("Error bits: %s%s%s%s%s%s%s\n", 1560 reg_val & (1<<29) ? "ED " : "", 1561 reg_val & (1<<28) ? "ET " : "", 1562 reg_val & (1<<26) ? "EE " : "", 1563 reg_val & (1<<25) ? "EB " : "", 1564 reg_val & (1<<24) ? "EI " : "", 1565 reg_val & (1<<23) ? "E1 " : "", 1566 reg_val & (1<<22) ? "E0 " : ""); 1567 } 1568 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1569 1570 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1571 if (reg_val & (1<<22)) 1572 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1573 1574 if (reg_val & (1<<23)) 1575 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1576 #endif 1577 1578 panic("Can't handle the cache error!"); 1579 } 1580 1581 asmlinkage void do_ftlb(void) 1582 { 1583 const int field = 2 * sizeof(unsigned long); 1584 unsigned int reg_val; 1585 1586 /* For the moment, report the problem and hang. */ 1587 if (cpu_has_mips_r2 && 1588 ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { 1589 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1590 read_c0_ecc()); 1591 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1592 reg_val = read_c0_cacheerr(); 1593 pr_err("c0_cacheerr == %08x\n", reg_val); 1594 1595 if ((reg_val & 0xc0000000) == 0xc0000000) { 1596 pr_err("Decoded c0_cacheerr: FTLB parity error\n"); 1597 } else { 1598 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1599 reg_val & (1<<30) ? "secondary" : "primary", 1600 reg_val & (1<<31) ? "data" : "insn"); 1601 } 1602 } else { 1603 pr_err("FTLB error exception\n"); 1604 } 1605 /* Just print the cacheerr bits for now */ 1606 cache_parity_error(); 1607 } 1608 1609 /* 1610 * SDBBP EJTAG debug exception handler. 1611 * We skip the instruction and return to the next instruction. 1612 */ 1613 void ejtag_exception_handler(struct pt_regs *regs) 1614 { 1615 const int field = 2 * sizeof(unsigned long); 1616 unsigned long depc, old_epc, old_ra; 1617 unsigned int debug; 1618 1619 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1620 depc = read_c0_depc(); 1621 debug = read_c0_debug(); 1622 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1623 if (debug & 0x80000000) { 1624 /* 1625 * In branch delay slot. 1626 * We cheat a little bit here and use EPC to calculate the 1627 * debug return address (DEPC). EPC is restored after the 1628 * calculation. 1629 */ 1630 old_epc = regs->cp0_epc; 1631 old_ra = regs->regs[31]; 1632 regs->cp0_epc = depc; 1633 compute_return_epc(regs); 1634 depc = regs->cp0_epc; 1635 regs->cp0_epc = old_epc; 1636 regs->regs[31] = old_ra; 1637 } else 1638 depc += 4; 1639 write_c0_depc(depc); 1640 1641 #if 0 1642 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1643 write_c0_debug(debug | 0x100); 1644 #endif 1645 } 1646 1647 /* 1648 * NMI exception handler. 1649 * No lock; only written during early bootup by CPU 0. 1650 */ 1651 static RAW_NOTIFIER_HEAD(nmi_chain); 1652 1653 int register_nmi_notifier(struct notifier_block *nb) 1654 { 1655 return raw_notifier_chain_register(&nmi_chain, nb); 1656 } 1657 1658 void __noreturn nmi_exception_handler(struct pt_regs *regs) 1659 { 1660 char str[100]; 1661 1662 raw_notifier_call_chain(&nmi_chain, 0, regs); 1663 bust_spinlocks(1); 1664 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", 1665 smp_processor_id(), regs->cp0_epc); 1666 regs->cp0_epc = read_c0_errorepc(); 1667 die(str, regs); 1668 } 1669 1670 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1671 1672 unsigned long ebase; 1673 unsigned long exception_handlers[32]; 1674 unsigned long vi_handlers[64]; 1675 1676 void __init *set_except_vector(int n, void *addr) 1677 { 1678 unsigned long handler = (unsigned long) addr; 1679 unsigned long old_handler; 1680 1681 #ifdef CONFIG_CPU_MICROMIPS 1682 /* 1683 * Only the TLB handlers are cache aligned with an even 1684 * address. All other handlers are on an odd address and 1685 * require no modification. Otherwise, MIPS32 mode will 1686 * be entered when handling any TLB exceptions. That 1687 * would be bad...since we must stay in microMIPS mode. 1688 */ 1689 if (!(handler & 0x1)) 1690 handler |= 1; 1691 #endif 1692 old_handler = xchg(&exception_handlers[n], handler); 1693 1694 if (n == 0 && cpu_has_divec) { 1695 #ifdef CONFIG_CPU_MICROMIPS 1696 unsigned long jump_mask = ~((1 << 27) - 1); 1697 #else 1698 unsigned long jump_mask = ~((1 << 28) - 1); 1699 #endif 1700 u32 *buf = (u32 *)(ebase + 0x200); 1701 unsigned int k0 = 26; 1702 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 1703 uasm_i_j(&buf, handler & ~jump_mask); 1704 uasm_i_nop(&buf); 1705 } else { 1706 UASM_i_LA(&buf, k0, handler); 1707 uasm_i_jr(&buf, k0); 1708 uasm_i_nop(&buf); 1709 } 1710 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 1711 } 1712 return (void *)old_handler; 1713 } 1714 1715 static void do_default_vi(void) 1716 { 1717 show_regs(get_irq_regs()); 1718 panic("Caught unexpected vectored interrupt."); 1719 } 1720 1721 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1722 { 1723 unsigned long handler; 1724 unsigned long old_handler = vi_handlers[n]; 1725 int srssets = current_cpu_data.srsets; 1726 u16 *h; 1727 unsigned char *b; 1728 1729 BUG_ON(!cpu_has_veic && !cpu_has_vint); 1730 1731 if (addr == NULL) { 1732 handler = (unsigned long) do_default_vi; 1733 srs = 0; 1734 } else 1735 handler = (unsigned long) addr; 1736 vi_handlers[n] = handler; 1737 1738 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1739 1740 if (srs >= srssets) 1741 panic("Shadow register set %d not supported", srs); 1742 1743 if (cpu_has_veic) { 1744 if (board_bind_eic_interrupt) 1745 board_bind_eic_interrupt(n, srs); 1746 } else if (cpu_has_vint) { 1747 /* SRSMap is only defined if shadow sets are implemented */ 1748 if (srssets > 1) 1749 change_c0_srsmap(0xf << n*4, srs << n*4); 1750 } 1751 1752 if (srs == 0) { 1753 /* 1754 * If no shadow set is selected then use the default handler 1755 * that does normal register saving and standard interrupt exit 1756 */ 1757 extern char except_vec_vi, except_vec_vi_lui; 1758 extern char except_vec_vi_ori, except_vec_vi_end; 1759 extern char rollback_except_vec_vi; 1760 char *vec_start = using_rollback_handler() ? 1761 &rollback_except_vec_vi : &except_vec_vi; 1762 #ifdef CONFIG_MIPS_MT_SMTC 1763 /* 1764 * We need to provide the SMTC vectored interrupt handler 1765 * not only with the address of the handler, but with the 1766 * Status.IM bit to be masked before going there. 1767 */ 1768 extern char except_vec_vi_mori; 1769 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) 1770 const int mori_offset = &except_vec_vi_mori - vec_start + 2; 1771 #else 1772 const int mori_offset = &except_vec_vi_mori - vec_start; 1773 #endif 1774 #endif /* CONFIG_MIPS_MT_SMTC */ 1775 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) 1776 const int lui_offset = &except_vec_vi_lui - vec_start + 2; 1777 const int ori_offset = &except_vec_vi_ori - vec_start + 2; 1778 #else 1779 const int lui_offset = &except_vec_vi_lui - vec_start; 1780 const int ori_offset = &except_vec_vi_ori - vec_start; 1781 #endif 1782 const int handler_len = &except_vec_vi_end - vec_start; 1783 1784 if (handler_len > VECTORSPACING) { 1785 /* 1786 * Sigh... panicing won't help as the console 1787 * is probably not configured :( 1788 */ 1789 panic("VECTORSPACING too small"); 1790 } 1791 1792 set_handler(((unsigned long)b - ebase), vec_start, 1793 #ifdef CONFIG_CPU_MICROMIPS 1794 (handler_len - 1)); 1795 #else 1796 handler_len); 1797 #endif 1798 #ifdef CONFIG_MIPS_MT_SMTC 1799 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1800 1801 h = (u16 *)(b + mori_offset); 1802 *h = (0x100 << n); 1803 #endif /* CONFIG_MIPS_MT_SMTC */ 1804 h = (u16 *)(b + lui_offset); 1805 *h = (handler >> 16) & 0xffff; 1806 h = (u16 *)(b + ori_offset); 1807 *h = (handler & 0xffff); 1808 local_flush_icache_range((unsigned long)b, 1809 (unsigned long)(b+handler_len)); 1810 } 1811 else { 1812 /* 1813 * In other cases jump directly to the interrupt handler. It 1814 * is the handler's responsibility to save registers if required 1815 * (eg hi/lo) and return from the exception using "eret". 1816 */ 1817 u32 insn; 1818 1819 h = (u16 *)b; 1820 /* j handler */ 1821 #ifdef CONFIG_CPU_MICROMIPS 1822 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); 1823 #else 1824 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); 1825 #endif 1826 h[0] = (insn >> 16) & 0xffff; 1827 h[1] = insn & 0xffff; 1828 h[2] = 0; 1829 h[3] = 0; 1830 local_flush_icache_range((unsigned long)b, 1831 (unsigned long)(b+8)); 1832 } 1833 1834 return (void *)old_handler; 1835 } 1836 1837 void *set_vi_handler(int n, vi_handler_t addr) 1838 { 1839 return set_vi_srs_handler(n, addr, 0); 1840 } 1841 1842 extern void tlb_init(void); 1843 1844 /* 1845 * Timer interrupt 1846 */ 1847 int cp0_compare_irq; 1848 EXPORT_SYMBOL_GPL(cp0_compare_irq); 1849 int cp0_compare_irq_shift; 1850 1851 /* 1852 * Performance counter IRQ or -1 if shared with timer 1853 */ 1854 int cp0_perfcount_irq; 1855 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1856 1857 static int noulri; 1858 1859 static int __init ulri_disable(char *s) 1860 { 1861 pr_info("Disabling ulri\n"); 1862 noulri = 1; 1863 1864 return 1; 1865 } 1866 __setup("noulri", ulri_disable); 1867 1868 void per_cpu_trap_init(bool is_boot_cpu) 1869 { 1870 unsigned int cpu = smp_processor_id(); 1871 unsigned int status_set = ST0_CU0; 1872 unsigned int hwrena = cpu_hwrena_impl_bits; 1873 #ifdef CONFIG_MIPS_MT_SMTC 1874 int secondaryTC = 0; 1875 int bootTC = (cpu == 0); 1876 1877 /* 1878 * Only do per_cpu_trap_init() for first TC of Each VPE. 1879 * Note that this hack assumes that the SMTC init code 1880 * assigns TCs consecutively and in ascending order. 1881 */ 1882 1883 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1884 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1885 secondaryTC = 1; 1886 #endif /* CONFIG_MIPS_MT_SMTC */ 1887 1888 /* 1889 * Disable coprocessors and select 32-bit or 64-bit addressing 1890 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1891 * flag that some firmware may have left set and the TS bit (for 1892 * IP27). Set XX for ISA IV code to work. 1893 */ 1894 #ifdef CONFIG_64BIT 1895 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1896 #endif 1897 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) 1898 status_set |= ST0_XX; 1899 if (cpu_has_dsp) 1900 status_set |= ST0_MX; 1901 1902 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1903 status_set); 1904 1905 if (cpu_has_mips_r2) 1906 hwrena |= 0x0000000f; 1907 1908 if (!noulri && cpu_has_userlocal) 1909 hwrena |= (1 << 29); 1910 1911 if (hwrena) 1912 write_c0_hwrena(hwrena); 1913 1914 #ifdef CONFIG_MIPS_MT_SMTC 1915 if (!secondaryTC) { 1916 #endif /* CONFIG_MIPS_MT_SMTC */ 1917 1918 if (cpu_has_veic || cpu_has_vint) { 1919 unsigned long sr = set_c0_status(ST0_BEV); 1920 write_c0_ebase(ebase); 1921 write_c0_status(sr); 1922 /* Setting vector spacing enables EI/VI mode */ 1923 change_c0_intctl(0x3e0, VECTORSPACING); 1924 } 1925 if (cpu_has_divec) { 1926 if (cpu_has_mipsmt) { 1927 unsigned int vpflags = dvpe(); 1928 set_c0_cause(CAUSEF_IV); 1929 evpe(vpflags); 1930 } else 1931 set_c0_cause(CAUSEF_IV); 1932 } 1933 1934 /* 1935 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1936 * 1937 * o read IntCtl.IPTI to determine the timer interrupt 1938 * o read IntCtl.IPPCI to determine the performance counter interrupt 1939 */ 1940 if (cpu_has_mips_r2) { 1941 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 1942 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 1943 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 1944 if (cp0_perfcount_irq == cp0_compare_irq) 1945 cp0_perfcount_irq = -1; 1946 } else { 1947 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1948 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 1949 cp0_perfcount_irq = -1; 1950 } 1951 1952 #ifdef CONFIG_MIPS_MT_SMTC 1953 } 1954 #endif /* CONFIG_MIPS_MT_SMTC */ 1955 1956 if (!cpu_data[cpu].asid_cache) 1957 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1958 1959 atomic_inc(&init_mm.mm_count); 1960 current->active_mm = &init_mm; 1961 BUG_ON(current->mm); 1962 enter_lazy_tlb(&init_mm, current); 1963 1964 #ifdef CONFIG_MIPS_MT_SMTC 1965 if (bootTC) { 1966 #endif /* CONFIG_MIPS_MT_SMTC */ 1967 /* Boot CPU's cache setup in setup_arch(). */ 1968 if (!is_boot_cpu) 1969 cpu_cache_init(); 1970 tlb_init(); 1971 #ifdef CONFIG_MIPS_MT_SMTC 1972 } else if (!secondaryTC) { 1973 /* 1974 * First TC in non-boot VPE must do subset of tlb_init() 1975 * for MMU countrol registers. 1976 */ 1977 write_c0_pagemask(PM_DEFAULT_MASK); 1978 write_c0_wired(0); 1979 } 1980 #endif /* CONFIG_MIPS_MT_SMTC */ 1981 TLBMISS_HANDLER_SETUP(); 1982 } 1983 1984 /* Install CPU exception handler */ 1985 void set_handler(unsigned long offset, void *addr, unsigned long size) 1986 { 1987 #ifdef CONFIG_CPU_MICROMIPS 1988 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); 1989 #else 1990 memcpy((void *)(ebase + offset), addr, size); 1991 #endif 1992 local_flush_icache_range(ebase + offset, ebase + offset + size); 1993 } 1994 1995 static char panic_null_cerr[] = 1996 "Trying to set NULL cache error exception handler"; 1997 1998 /* 1999 * Install uncached CPU exception handler. 2000 * This is suitable only for the cache error exception which is the only 2001 * exception handler that is being run uncached. 2002 */ 2003 void set_uncached_handler(unsigned long offset, void *addr, 2004 unsigned long size) 2005 { 2006 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 2007 2008 if (!addr) 2009 panic(panic_null_cerr); 2010 2011 memcpy((void *)(uncached_ebase + offset), addr, size); 2012 } 2013 2014 static int __initdata rdhwr_noopt; 2015 static int __init set_rdhwr_noopt(char *str) 2016 { 2017 rdhwr_noopt = 1; 2018 return 1; 2019 } 2020 2021 __setup("rdhwr_noopt", set_rdhwr_noopt); 2022 2023 void __init trap_init(void) 2024 { 2025 extern char except_vec3_generic; 2026 extern char except_vec4; 2027 extern char except_vec3_r4000; 2028 unsigned long i; 2029 2030 check_wait(); 2031 2032 #if defined(CONFIG_KGDB) 2033 if (kgdb_early_setup) 2034 return; /* Already done */ 2035 #endif 2036 2037 if (cpu_has_veic || cpu_has_vint) { 2038 unsigned long size = 0x200 + VECTORSPACING*64; 2039 ebase = (unsigned long) 2040 __alloc_bootmem(size, 1 << fls(size), 0); 2041 } else { 2042 #ifdef CONFIG_KVM_GUEST 2043 #define KVM_GUEST_KSEG0 0x40000000 2044 ebase = KVM_GUEST_KSEG0; 2045 #else 2046 ebase = CKSEG0; 2047 #endif 2048 if (cpu_has_mips_r2) 2049 ebase += (read_c0_ebase() & 0x3ffff000); 2050 } 2051 2052 if (cpu_has_mmips) { 2053 unsigned int config3 = read_c0_config3(); 2054 2055 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) 2056 write_c0_config3(config3 | MIPS_CONF3_ISA_OE); 2057 else 2058 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); 2059 } 2060 2061 if (board_ebase_setup) 2062 board_ebase_setup(); 2063 per_cpu_trap_init(true); 2064 2065 /* 2066 * Copy the generic exception handlers to their final destination. 2067 * This will be overriden later as suitable for a particular 2068 * configuration. 2069 */ 2070 set_handler(0x180, &except_vec3_generic, 0x80); 2071 2072 /* 2073 * Setup default vectors 2074 */ 2075 for (i = 0; i <= 31; i++) 2076 set_except_vector(i, handle_reserved); 2077 2078 /* 2079 * Copy the EJTAG debug exception vector handler code to it's final 2080 * destination. 2081 */ 2082 if (cpu_has_ejtag && board_ejtag_handler_setup) 2083 board_ejtag_handler_setup(); 2084 2085 /* 2086 * Only some CPUs have the watch exceptions. 2087 */ 2088 if (cpu_has_watch) 2089 set_except_vector(23, handle_watch); 2090 2091 /* 2092 * Initialise interrupt handlers 2093 */ 2094 if (cpu_has_veic || cpu_has_vint) { 2095 int nvec = cpu_has_veic ? 64 : 8; 2096 for (i = 0; i < nvec; i++) 2097 set_vi_handler(i, NULL); 2098 } 2099 else if (cpu_has_divec) 2100 set_handler(0x200, &except_vec4, 0x8); 2101 2102 /* 2103 * Some CPUs can enable/disable for cache parity detection, but does 2104 * it different ways. 2105 */ 2106 parity_protection_init(); 2107 2108 /* 2109 * The Data Bus Errors / Instruction Bus Errors are signaled 2110 * by external hardware. Therefore these two exceptions 2111 * may have board specific handlers. 2112 */ 2113 if (board_be_init) 2114 board_be_init(); 2115 2116 set_except_vector(0, using_rollback_handler() ? rollback_handle_int 2117 : handle_int); 2118 set_except_vector(1, handle_tlbm); 2119 set_except_vector(2, handle_tlbl); 2120 set_except_vector(3, handle_tlbs); 2121 2122 set_except_vector(4, handle_adel); 2123 set_except_vector(5, handle_ades); 2124 2125 set_except_vector(6, handle_ibe); 2126 set_except_vector(7, handle_dbe); 2127 2128 set_except_vector(8, handle_sys); 2129 set_except_vector(9, handle_bp); 2130 set_except_vector(10, rdhwr_noopt ? handle_ri : 2131 (cpu_has_vtag_icache ? 2132 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 2133 set_except_vector(11, handle_cpu); 2134 set_except_vector(12, handle_ov); 2135 set_except_vector(13, handle_tr); 2136 set_except_vector(14, handle_msa_fpe); 2137 2138 if (current_cpu_type() == CPU_R6000 || 2139 current_cpu_type() == CPU_R6000A) { 2140 /* 2141 * The R6000 is the only R-series CPU that features a machine 2142 * check exception (similar to the R4000 cache error) and 2143 * unaligned ldc1/sdc1 exception. The handlers have not been 2144 * written yet. Well, anyway there is no R6000 machine on the 2145 * current list of targets for Linux/MIPS. 2146 * (Duh, crap, there is someone with a triple R6k machine) 2147 */ 2148 //set_except_vector(14, handle_mc); 2149 //set_except_vector(15, handle_ndc); 2150 } 2151 2152 2153 if (board_nmi_handler_setup) 2154 board_nmi_handler_setup(); 2155 2156 if (cpu_has_fpu && !cpu_has_nofpuex) 2157 set_except_vector(15, handle_fpe); 2158 2159 set_except_vector(16, handle_ftlb); 2160 set_except_vector(21, handle_msa); 2161 set_except_vector(22, handle_mdmx); 2162 2163 if (cpu_has_mcheck) 2164 set_except_vector(24, handle_mcheck); 2165 2166 if (cpu_has_mipsmt) 2167 set_except_vector(25, handle_mt); 2168 2169 set_except_vector(26, handle_dsp); 2170 2171 if (board_cache_error_setup) 2172 board_cache_error_setup(); 2173 2174 if (cpu_has_vce) 2175 /* Special exception: R4[04]00 uses also the divec space. */ 2176 set_handler(0x180, &except_vec3_r4000, 0x100); 2177 else if (cpu_has_4kex) 2178 set_handler(0x180, &except_vec3_generic, 0x80); 2179 else 2180 set_handler(0x080, &except_vec3_generic, 0x80); 2181 2182 local_flush_icache_range(ebase, ebase + 0x400); 2183 2184 sort_extable(__start___dbe_table, __stop___dbe_table); 2185 2186 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 2187 } 2188