1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. 13 * Copyright (C) 2014, Imagination Technologies Ltd. 14 */ 15 #include <linux/bitops.h> 16 #include <linux/bug.h> 17 #include <linux/compiler.h> 18 #include <linux/context_tracking.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/kexec.h> 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/extable.h> 25 #include <linux/mm.h> 26 #include <linux/sched/mm.h> 27 #include <linux/sched/debug.h> 28 #include <linux/smp.h> 29 #include <linux/spinlock.h> 30 #include <linux/kallsyms.h> 31 #include <linux/memblock.h> 32 #include <linux/interrupt.h> 33 #include <linux/ptrace.h> 34 #include <linux/kgdb.h> 35 #include <linux/kdebug.h> 36 #include <linux/kprobes.h> 37 #include <linux/notifier.h> 38 #include <linux/kdb.h> 39 #include <linux/irq.h> 40 #include <linux/perf_event.h> 41 42 #include <asm/addrspace.h> 43 #include <asm/bootinfo.h> 44 #include <asm/branch.h> 45 #include <asm/break.h> 46 #include <asm/cop2.h> 47 #include <asm/cpu.h> 48 #include <asm/cpu-type.h> 49 #include <asm/dsp.h> 50 #include <asm/fpu.h> 51 #include <asm/fpu_emulator.h> 52 #include <asm/idle.h> 53 #include <asm/isa-rev.h> 54 #include <asm/mips-cps.h> 55 #include <asm/mips-r2-to-r6-emul.h> 56 #include <asm/mipsregs.h> 57 #include <asm/mipsmtregs.h> 58 #include <asm/module.h> 59 #include <asm/msa.h> 60 #include <asm/pgtable.h> 61 #include <asm/ptrace.h> 62 #include <asm/sections.h> 63 #include <asm/siginfo.h> 64 #include <asm/tlbdebug.h> 65 #include <asm/traps.h> 66 #include <linux/uaccess.h> 67 #include <asm/watch.h> 68 #include <asm/mmu_context.h> 69 #include <asm/types.h> 70 #include <asm/stacktrace.h> 71 #include <asm/tlbex.h> 72 #include <asm/uasm.h> 73 74 #include <asm/mach-loongson64/cpucfg-emul.h> 75 76 extern void check_wait(void); 77 extern asmlinkage void rollback_handle_int(void); 78 extern asmlinkage void handle_int(void); 79 extern asmlinkage void handle_adel(void); 80 extern asmlinkage void handle_ades(void); 81 extern asmlinkage void handle_ibe(void); 82 extern asmlinkage void handle_dbe(void); 83 extern asmlinkage void handle_sys(void); 84 extern asmlinkage void handle_bp(void); 85 extern asmlinkage void handle_ri(void); 86 extern asmlinkage void handle_ri_rdhwr_tlbp(void); 87 extern asmlinkage void handle_ri_rdhwr(void); 88 extern asmlinkage void handle_cpu(void); 89 extern asmlinkage void handle_ov(void); 90 extern asmlinkage void handle_tr(void); 91 extern asmlinkage void handle_msa_fpe(void); 92 extern asmlinkage void handle_fpe(void); 93 extern asmlinkage void handle_ftlb(void); 94 extern asmlinkage void handle_msa(void); 95 extern asmlinkage void handle_mdmx(void); 96 extern asmlinkage void handle_watch(void); 97 extern asmlinkage void handle_mt(void); 98 extern asmlinkage void handle_dsp(void); 99 extern asmlinkage void handle_mcheck(void); 100 extern asmlinkage void handle_reserved(void); 101 extern void tlb_do_page_fault_0(void); 102 103 void (*board_be_init)(void); 104 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 105 void (*board_nmi_handler_setup)(void); 106 void (*board_ejtag_handler_setup)(void); 107 void (*board_bind_eic_interrupt)(int irq, int regset); 108 void (*board_ebase_setup)(void); 109 void(*board_cache_error_setup)(void); 110 111 static void show_raw_backtrace(unsigned long reg29) 112 { 113 unsigned long *sp = (unsigned long *)(reg29 & ~3); 114 unsigned long addr; 115 116 printk("Call Trace:"); 117 #ifdef CONFIG_KALLSYMS 118 printk("\n"); 119 #endif 120 while (!kstack_end(sp)) { 121 unsigned long __user *p = 122 (unsigned long __user *)(unsigned long)sp++; 123 if (__get_user(addr, p)) { 124 printk(" (Bad stack address)"); 125 break; 126 } 127 if (__kernel_text_address(addr)) 128 print_ip_sym(addr); 129 } 130 printk("\n"); 131 } 132 133 #ifdef CONFIG_KALLSYMS 134 int raw_show_trace; 135 static int __init set_raw_show_trace(char *str) 136 { 137 raw_show_trace = 1; 138 return 1; 139 } 140 __setup("raw_show_trace", set_raw_show_trace); 141 #endif 142 143 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 144 { 145 unsigned long sp = regs->regs[29]; 146 unsigned long ra = regs->regs[31]; 147 unsigned long pc = regs->cp0_epc; 148 149 if (!task) 150 task = current; 151 152 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) { 153 show_raw_backtrace(sp); 154 return; 155 } 156 printk("Call Trace:\n"); 157 do { 158 print_ip_sym(pc); 159 pc = unwind_stack(task, &sp, pc, &ra); 160 } while (pc); 161 pr_cont("\n"); 162 } 163 164 /* 165 * This routine abuses get_user()/put_user() to reference pointers 166 * with at least a bit of error checking ... 167 */ 168 static void show_stacktrace(struct task_struct *task, 169 const struct pt_regs *regs) 170 { 171 const int field = 2 * sizeof(unsigned long); 172 long stackdata; 173 int i; 174 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 175 176 printk("Stack :"); 177 i = 0; 178 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 179 if (i && ((i % (64 / field)) == 0)) { 180 pr_cont("\n"); 181 printk(" "); 182 } 183 if (i > 39) { 184 pr_cont(" ..."); 185 break; 186 } 187 188 if (__get_user(stackdata, sp++)) { 189 pr_cont(" (Bad stack address)"); 190 break; 191 } 192 193 pr_cont(" %0*lx", field, stackdata); 194 i++; 195 } 196 pr_cont("\n"); 197 show_backtrace(task, regs); 198 } 199 200 void show_stack(struct task_struct *task, unsigned long *sp) 201 { 202 struct pt_regs regs; 203 mm_segment_t old_fs = get_fs(); 204 205 regs.cp0_status = KSU_KERNEL; 206 if (sp) { 207 regs.regs[29] = (unsigned long)sp; 208 regs.regs[31] = 0; 209 regs.cp0_epc = 0; 210 } else { 211 if (task && task != current) { 212 regs.regs[29] = task->thread.reg29; 213 regs.regs[31] = 0; 214 regs.cp0_epc = task->thread.reg31; 215 } else { 216 prepare_frametrace(®s); 217 } 218 } 219 /* 220 * show_stack() deals exclusively with kernel mode, so be sure to access 221 * the stack in the kernel (not user) address space. 222 */ 223 set_fs(KERNEL_DS); 224 show_stacktrace(task, ®s); 225 set_fs(old_fs); 226 } 227 228 static void show_code(unsigned int __user *pc) 229 { 230 long i; 231 unsigned short __user *pc16 = NULL; 232 233 printk("Code:"); 234 235 if ((unsigned long)pc & 1) 236 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 237 for(i = -3 ; i < 6 ; i++) { 238 unsigned int insn; 239 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 240 pr_cont(" (Bad address in epc)\n"); 241 break; 242 } 243 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 244 } 245 pr_cont("\n"); 246 } 247 248 static void __show_regs(const struct pt_regs *regs) 249 { 250 const int field = 2 * sizeof(unsigned long); 251 unsigned int cause = regs->cp0_cause; 252 unsigned int exccode; 253 int i; 254 255 show_regs_print_info(KERN_DEFAULT); 256 257 /* 258 * Saved main processor registers 259 */ 260 for (i = 0; i < 32; ) { 261 if ((i % 4) == 0) 262 printk("$%2d :", i); 263 if (i == 0) 264 pr_cont(" %0*lx", field, 0UL); 265 else if (i == 26 || i == 27) 266 pr_cont(" %*s", field, ""); 267 else 268 pr_cont(" %0*lx", field, regs->regs[i]); 269 270 i++; 271 if ((i % 4) == 0) 272 pr_cont("\n"); 273 } 274 275 #ifdef CONFIG_CPU_HAS_SMARTMIPS 276 printk("Acx : %0*lx\n", field, regs->acx); 277 #endif 278 if (MIPS_ISA_REV < 6) { 279 printk("Hi : %0*lx\n", field, regs->hi); 280 printk("Lo : %0*lx\n", field, regs->lo); 281 } 282 283 /* 284 * Saved cp0 registers 285 */ 286 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 287 (void *) regs->cp0_epc); 288 printk("ra : %0*lx %pS\n", field, regs->regs[31], 289 (void *) regs->regs[31]); 290 291 printk("Status: %08x ", (uint32_t) regs->cp0_status); 292 293 if (cpu_has_3kex) { 294 if (regs->cp0_status & ST0_KUO) 295 pr_cont("KUo "); 296 if (regs->cp0_status & ST0_IEO) 297 pr_cont("IEo "); 298 if (regs->cp0_status & ST0_KUP) 299 pr_cont("KUp "); 300 if (regs->cp0_status & ST0_IEP) 301 pr_cont("IEp "); 302 if (regs->cp0_status & ST0_KUC) 303 pr_cont("KUc "); 304 if (regs->cp0_status & ST0_IEC) 305 pr_cont("IEc "); 306 } else if (cpu_has_4kex) { 307 if (regs->cp0_status & ST0_KX) 308 pr_cont("KX "); 309 if (regs->cp0_status & ST0_SX) 310 pr_cont("SX "); 311 if (regs->cp0_status & ST0_UX) 312 pr_cont("UX "); 313 switch (regs->cp0_status & ST0_KSU) { 314 case KSU_USER: 315 pr_cont("USER "); 316 break; 317 case KSU_SUPERVISOR: 318 pr_cont("SUPERVISOR "); 319 break; 320 case KSU_KERNEL: 321 pr_cont("KERNEL "); 322 break; 323 default: 324 pr_cont("BAD_MODE "); 325 break; 326 } 327 if (regs->cp0_status & ST0_ERL) 328 pr_cont("ERL "); 329 if (regs->cp0_status & ST0_EXL) 330 pr_cont("EXL "); 331 if (regs->cp0_status & ST0_IE) 332 pr_cont("IE "); 333 } 334 pr_cont("\n"); 335 336 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 337 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode); 338 339 if (1 <= exccode && exccode <= 5) 340 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 341 342 printk("PrId : %08x (%s)\n", read_c0_prid(), 343 cpu_name_string()); 344 } 345 346 /* 347 * FIXME: really the generic show_regs should take a const pointer argument. 348 */ 349 void show_regs(struct pt_regs *regs) 350 { 351 __show_regs(regs); 352 dump_stack(); 353 } 354 355 void show_registers(struct pt_regs *regs) 356 { 357 const int field = 2 * sizeof(unsigned long); 358 mm_segment_t old_fs = get_fs(); 359 360 __show_regs(regs); 361 print_modules(); 362 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 363 current->comm, current->pid, current_thread_info(), current, 364 field, current_thread_info()->tp_value); 365 if (cpu_has_userlocal) { 366 unsigned long tls; 367 368 tls = read_c0_userlocal(); 369 if (tls != current_thread_info()->tp_value) 370 printk("*HwTLS: %0*lx\n", field, tls); 371 } 372 373 if (!user_mode(regs)) 374 /* Necessary for getting the correct stack content */ 375 set_fs(KERNEL_DS); 376 show_stacktrace(current, regs); 377 show_code((unsigned int __user *) regs->cp0_epc); 378 printk("\n"); 379 set_fs(old_fs); 380 } 381 382 static DEFINE_RAW_SPINLOCK(die_lock); 383 384 void __noreturn die(const char *str, struct pt_regs *regs) 385 { 386 static int die_counter; 387 int sig = SIGSEGV; 388 389 oops_enter(); 390 391 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, 392 SIGSEGV) == NOTIFY_STOP) 393 sig = 0; 394 395 console_verbose(); 396 raw_spin_lock_irq(&die_lock); 397 bust_spinlocks(1); 398 399 printk("%s[#%d]:\n", str, ++die_counter); 400 show_registers(regs); 401 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 402 raw_spin_unlock_irq(&die_lock); 403 404 oops_exit(); 405 406 if (in_interrupt()) 407 panic("Fatal exception in interrupt"); 408 409 if (panic_on_oops) 410 panic("Fatal exception"); 411 412 if (regs && kexec_should_crash(current)) 413 crash_kexec(regs); 414 415 do_exit(sig); 416 } 417 418 extern struct exception_table_entry __start___dbe_table[]; 419 extern struct exception_table_entry __stop___dbe_table[]; 420 421 __asm__( 422 " .section __dbe_table, \"a\"\n" 423 " .previous \n"); 424 425 /* Given an address, look for it in the exception tables. */ 426 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 427 { 428 const struct exception_table_entry *e; 429 430 e = search_extable(__start___dbe_table, 431 __stop___dbe_table - __start___dbe_table, addr); 432 if (!e) 433 e = search_module_dbetables(addr); 434 return e; 435 } 436 437 asmlinkage void do_be(struct pt_regs *regs) 438 { 439 const int field = 2 * sizeof(unsigned long); 440 const struct exception_table_entry *fixup = NULL; 441 int data = regs->cp0_cause & 4; 442 int action = MIPS_BE_FATAL; 443 enum ctx_state prev_state; 444 445 prev_state = exception_enter(); 446 /* XXX For now. Fixme, this searches the wrong table ... */ 447 if (data && !user_mode(regs)) 448 fixup = search_dbe_tables(exception_epc(regs)); 449 450 if (fixup) 451 action = MIPS_BE_FIXUP; 452 453 if (board_be_handler) 454 action = board_be_handler(regs, fixup != NULL); 455 else 456 mips_cm_error_report(); 457 458 switch (action) { 459 case MIPS_BE_DISCARD: 460 goto out; 461 case MIPS_BE_FIXUP: 462 if (fixup) { 463 regs->cp0_epc = fixup->nextinsn; 464 goto out; 465 } 466 break; 467 default: 468 break; 469 } 470 471 /* 472 * Assume it would be too dangerous to continue ... 473 */ 474 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 475 data ? "Data" : "Instruction", 476 field, regs->cp0_epc, field, regs->regs[31]); 477 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr, 478 SIGBUS) == NOTIFY_STOP) 479 goto out; 480 481 die_if_kernel("Oops", regs); 482 force_sig(SIGBUS); 483 484 out: 485 exception_exit(prev_state); 486 } 487 488 /* 489 * ll/sc, rdhwr, sync emulation 490 */ 491 492 #define OPCODE 0xfc000000 493 #define BASE 0x03e00000 494 #define RT 0x001f0000 495 #define OFFSET 0x0000ffff 496 #define LL 0xc0000000 497 #define SC 0xe0000000 498 #define SPEC0 0x00000000 499 #define SPEC3 0x7c000000 500 #define RD 0x0000f800 501 #define FUNC 0x0000003f 502 #define SYNC 0x0000000f 503 #define RDHWR 0x0000003b 504 505 /* microMIPS definitions */ 506 #define MM_POOL32A_FUNC 0xfc00ffff 507 #define MM_RDHWR 0x00006b3c 508 #define MM_RS 0x001f0000 509 #define MM_RT 0x03e00000 510 511 /* 512 * The ll_bit is cleared by r*_switch.S 513 */ 514 515 unsigned int ll_bit; 516 struct task_struct *ll_task; 517 518 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 519 { 520 unsigned long value, __user *vaddr; 521 long offset; 522 523 /* 524 * analyse the ll instruction that just caused a ri exception 525 * and put the referenced address to addr. 526 */ 527 528 /* sign extend offset */ 529 offset = opcode & OFFSET; 530 offset <<= 16; 531 offset >>= 16; 532 533 vaddr = (unsigned long __user *) 534 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 535 536 if ((unsigned long)vaddr & 3) 537 return SIGBUS; 538 if (get_user(value, vaddr)) 539 return SIGSEGV; 540 541 preempt_disable(); 542 543 if (ll_task == NULL || ll_task == current) { 544 ll_bit = 1; 545 } else { 546 ll_bit = 0; 547 } 548 ll_task = current; 549 550 preempt_enable(); 551 552 regs->regs[(opcode & RT) >> 16] = value; 553 554 return 0; 555 } 556 557 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 558 { 559 unsigned long __user *vaddr; 560 unsigned long reg; 561 long offset; 562 563 /* 564 * analyse the sc instruction that just caused a ri exception 565 * and put the referenced address to addr. 566 */ 567 568 /* sign extend offset */ 569 offset = opcode & OFFSET; 570 offset <<= 16; 571 offset >>= 16; 572 573 vaddr = (unsigned long __user *) 574 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 575 reg = (opcode & RT) >> 16; 576 577 if ((unsigned long)vaddr & 3) 578 return SIGBUS; 579 580 preempt_disable(); 581 582 if (ll_bit == 0 || ll_task != current) { 583 regs->regs[reg] = 0; 584 preempt_enable(); 585 return 0; 586 } 587 588 preempt_enable(); 589 590 if (put_user(regs->regs[reg], vaddr)) 591 return SIGSEGV; 592 593 regs->regs[reg] = 1; 594 595 return 0; 596 } 597 598 /* 599 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 600 * opcodes are supposed to result in coprocessor unusable exceptions if 601 * executed on ll/sc-less processors. That's the theory. In practice a 602 * few processors such as NEC's VR4100 throw reserved instruction exceptions 603 * instead, so we're doing the emulation thing in both exception handlers. 604 */ 605 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 606 { 607 if ((opcode & OPCODE) == LL) { 608 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 609 1, regs, 0); 610 return simulate_ll(regs, opcode); 611 } 612 if ((opcode & OPCODE) == SC) { 613 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 614 1, regs, 0); 615 return simulate_sc(regs, opcode); 616 } 617 618 return -1; /* Must be something else ... */ 619 } 620 621 /* 622 * Simulate trapping 'rdhwr' instructions to provide user accessible 623 * registers not implemented in hardware. 624 */ 625 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) 626 { 627 struct thread_info *ti = task_thread_info(current); 628 629 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 630 1, regs, 0); 631 switch (rd) { 632 case MIPS_HWR_CPUNUM: /* CPU number */ 633 regs->regs[rt] = smp_processor_id(); 634 return 0; 635 case MIPS_HWR_SYNCISTEP: /* SYNCI length */ 636 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 637 current_cpu_data.icache.linesz); 638 return 0; 639 case MIPS_HWR_CC: /* Read count register */ 640 regs->regs[rt] = read_c0_count(); 641 return 0; 642 case MIPS_HWR_CCRES: /* Count register resolution */ 643 switch (current_cpu_type()) { 644 case CPU_20KC: 645 case CPU_25KF: 646 regs->regs[rt] = 1; 647 break; 648 default: 649 regs->regs[rt] = 2; 650 } 651 return 0; 652 case MIPS_HWR_ULR: /* Read UserLocal register */ 653 regs->regs[rt] = ti->tp_value; 654 return 0; 655 default: 656 return -1; 657 } 658 } 659 660 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) 661 { 662 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 663 int rd = (opcode & RD) >> 11; 664 int rt = (opcode & RT) >> 16; 665 666 simulate_rdhwr(regs, rd, rt); 667 return 0; 668 } 669 670 /* Not ours. */ 671 return -1; 672 } 673 674 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode) 675 { 676 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { 677 int rd = (opcode & MM_RS) >> 16; 678 int rt = (opcode & MM_RT) >> 21; 679 simulate_rdhwr(regs, rd, rt); 680 return 0; 681 } 682 683 /* Not ours. */ 684 return -1; 685 } 686 687 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 688 { 689 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 690 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 691 1, regs, 0); 692 return 0; 693 } 694 695 return -1; /* Must be something else ... */ 696 } 697 698 /* 699 * Loongson-3 CSR instructions emulation 700 */ 701 702 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION 703 704 #define LWC2 0xc8000000 705 #define RS BASE 706 #define CSR_OPCODE2 0x00000118 707 #define CSR_OPCODE2_MASK 0x000007ff 708 #define CSR_FUNC_MASK RT 709 #define CSR_FUNC_CPUCFG 0x8 710 711 static int simulate_loongson3_cpucfg(struct pt_regs *regs, 712 unsigned int opcode) 713 { 714 int op = opcode & OPCODE; 715 int op2 = opcode & CSR_OPCODE2_MASK; 716 int csr_func = (opcode & CSR_FUNC_MASK) >> 16; 717 718 if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) { 719 int rd = (opcode & RD) >> 11; 720 int rs = (opcode & RS) >> 21; 721 __u64 sel = regs->regs[rs]; 722 723 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); 724 725 /* Do not emulate on unsupported core models. */ 726 if (!loongson3_cpucfg_emulation_enabled(¤t_cpu_data)) 727 return -1; 728 729 regs->regs[rd] = loongson3_cpucfg_read_synthesized( 730 ¤t_cpu_data, sel); 731 732 return 0; 733 } 734 735 /* Not ours. */ 736 return -1; 737 } 738 #endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */ 739 740 asmlinkage void do_ov(struct pt_regs *regs) 741 { 742 enum ctx_state prev_state; 743 744 prev_state = exception_enter(); 745 die_if_kernel("Integer overflow", regs); 746 747 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc); 748 exception_exit(prev_state); 749 } 750 751 #ifdef CONFIG_MIPS_FP_SUPPORT 752 753 /* 754 * Send SIGFPE according to FCSR Cause bits, which must have already 755 * been masked against Enable bits. This is impotant as Inexact can 756 * happen together with Overflow or Underflow, and `ptrace' can set 757 * any bits. 758 */ 759 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr, 760 struct task_struct *tsk) 761 { 762 int si_code = FPE_FLTUNK; 763 764 if (fcr31 & FPU_CSR_INV_X) 765 si_code = FPE_FLTINV; 766 else if (fcr31 & FPU_CSR_DIV_X) 767 si_code = FPE_FLTDIV; 768 else if (fcr31 & FPU_CSR_OVF_X) 769 si_code = FPE_FLTOVF; 770 else if (fcr31 & FPU_CSR_UDF_X) 771 si_code = FPE_FLTUND; 772 else if (fcr31 & FPU_CSR_INE_X) 773 si_code = FPE_FLTRES; 774 775 force_sig_fault_to_task(SIGFPE, si_code, fault_addr, tsk); 776 } 777 778 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31) 779 { 780 int si_code; 781 struct vm_area_struct *vma; 782 783 switch (sig) { 784 case 0: 785 return 0; 786 787 case SIGFPE: 788 force_fcr31_sig(fcr31, fault_addr, current); 789 return 1; 790 791 case SIGBUS: 792 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr); 793 return 1; 794 795 case SIGSEGV: 796 down_read(¤t->mm->mmap_sem); 797 vma = find_vma(current->mm, (unsigned long)fault_addr); 798 if (vma && (vma->vm_start <= (unsigned long)fault_addr)) 799 si_code = SEGV_ACCERR; 800 else 801 si_code = SEGV_MAPERR; 802 up_read(¤t->mm->mmap_sem); 803 force_sig_fault(SIGSEGV, si_code, fault_addr); 804 return 1; 805 806 default: 807 force_sig(sig); 808 return 1; 809 } 810 } 811 812 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 813 unsigned long old_epc, unsigned long old_ra) 814 { 815 union mips_instruction inst = { .word = opcode }; 816 void __user *fault_addr; 817 unsigned long fcr31; 818 int sig; 819 820 /* If it's obviously not an FP instruction, skip it */ 821 switch (inst.i_format.opcode) { 822 case cop1_op: 823 case cop1x_op: 824 case lwc1_op: 825 case ldc1_op: 826 case swc1_op: 827 case sdc1_op: 828 break; 829 830 default: 831 return -1; 832 } 833 834 /* 835 * do_ri skipped over the instruction via compute_return_epc, undo 836 * that for the FPU emulator. 837 */ 838 regs->cp0_epc = old_epc; 839 regs->regs[31] = old_ra; 840 841 /* Run the emulator */ 842 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 843 &fault_addr); 844 845 /* 846 * We can't allow the emulated instruction to leave any 847 * enabled Cause bits set in $fcr31. 848 */ 849 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 850 current->thread.fpu.fcr31 &= ~fcr31; 851 852 /* Restore the hardware register state */ 853 own_fpu(1); 854 855 /* Send a signal if required. */ 856 process_fpemu_return(sig, fault_addr, fcr31); 857 858 return 0; 859 } 860 861 /* 862 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 863 */ 864 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 865 { 866 enum ctx_state prev_state; 867 void __user *fault_addr; 868 int sig; 869 870 prev_state = exception_enter(); 871 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, 872 SIGFPE) == NOTIFY_STOP) 873 goto out; 874 875 /* Clear FCSR.Cause before enabling interrupts */ 876 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31)); 877 local_irq_enable(); 878 879 die_if_kernel("FP exception in kernel code", regs); 880 881 if (fcr31 & FPU_CSR_UNI_X) { 882 /* 883 * Unimplemented operation exception. If we've got the full 884 * software emulator on-board, let's use it... 885 * 886 * Force FPU to dump state into task/thread context. We're 887 * moving a lot of data here for what is probably a single 888 * instruction, but the alternative is to pre-decode the FP 889 * register operands before invoking the emulator, which seems 890 * a bit extreme for what should be an infrequent event. 891 */ 892 893 /* Run the emulator */ 894 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 895 &fault_addr); 896 897 /* 898 * We can't allow the emulated instruction to leave any 899 * enabled Cause bits set in $fcr31. 900 */ 901 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 902 current->thread.fpu.fcr31 &= ~fcr31; 903 904 /* Restore the hardware register state */ 905 own_fpu(1); /* Using the FPU again. */ 906 } else { 907 sig = SIGFPE; 908 fault_addr = (void __user *) regs->cp0_epc; 909 } 910 911 /* Send a signal if required. */ 912 process_fpemu_return(sig, fault_addr, fcr31); 913 914 out: 915 exception_exit(prev_state); 916 } 917 918 /* 919 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 920 * emulated more than some threshold number of instructions, force migration to 921 * a "CPU" that has FP support. 922 */ 923 static void mt_ase_fp_affinity(void) 924 { 925 #ifdef CONFIG_MIPS_MT_FPAFF 926 if (mt_fpemul_threshold > 0 && 927 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 928 /* 929 * If there's no FPU present, or if the application has already 930 * restricted the allowed set to exclude any CPUs with FPUs, 931 * we'll skip the procedure. 932 */ 933 if (cpumask_intersects(¤t->cpus_mask, &mt_fpu_cpumask)) { 934 cpumask_t tmask; 935 936 current->thread.user_cpus_allowed 937 = current->cpus_mask; 938 cpumask_and(&tmask, ¤t->cpus_mask, 939 &mt_fpu_cpumask); 940 set_cpus_allowed_ptr(current, &tmask); 941 set_thread_flag(TIF_FPUBOUND); 942 } 943 } 944 #endif /* CONFIG_MIPS_MT_FPAFF */ 945 } 946 947 #else /* !CONFIG_MIPS_FP_SUPPORT */ 948 949 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 950 unsigned long old_epc, unsigned long old_ra) 951 { 952 return -1; 953 } 954 955 #endif /* !CONFIG_MIPS_FP_SUPPORT */ 956 957 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code, 958 const char *str) 959 { 960 char b[40]; 961 962 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 963 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr, 964 SIGTRAP) == NOTIFY_STOP) 965 return; 966 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 967 968 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr, 969 SIGTRAP) == NOTIFY_STOP) 970 return; 971 972 /* 973 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 974 * insns, even for trap and break codes that indicate arithmetic 975 * failures. Weird ... 976 * But should we continue the brokenness??? --macro 977 */ 978 switch (code) { 979 case BRK_OVERFLOW: 980 case BRK_DIVZERO: 981 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 982 die_if_kernel(b, regs); 983 force_sig_fault(SIGFPE, 984 code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF, 985 (void __user *) regs->cp0_epc); 986 break; 987 case BRK_BUG: 988 die_if_kernel("Kernel bug detected", regs); 989 force_sig(SIGTRAP); 990 break; 991 case BRK_MEMU: 992 /* 993 * This breakpoint code is used by the FPU emulator to retake 994 * control of the CPU after executing the instruction from the 995 * delay slot of an emulated branch. 996 * 997 * Terminate if exception was recognized as a delay slot return 998 * otherwise handle as normal. 999 */ 1000 if (do_dsemulret(regs)) 1001 return; 1002 1003 die_if_kernel("Math emu break/trap", regs); 1004 force_sig(SIGTRAP); 1005 break; 1006 default: 1007 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 1008 die_if_kernel(b, regs); 1009 if (si_code) { 1010 force_sig_fault(SIGTRAP, si_code, NULL); 1011 } else { 1012 force_sig(SIGTRAP); 1013 } 1014 } 1015 } 1016 1017 asmlinkage void do_bp(struct pt_regs *regs) 1018 { 1019 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 1020 unsigned int opcode, bcode; 1021 enum ctx_state prev_state; 1022 mm_segment_t seg; 1023 1024 seg = get_fs(); 1025 if (!user_mode(regs)) 1026 set_fs(KERNEL_DS); 1027 1028 prev_state = exception_enter(); 1029 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1030 if (get_isa16_mode(regs->cp0_epc)) { 1031 u16 instr[2]; 1032 1033 if (__get_user(instr[0], (u16 __user *)epc)) 1034 goto out_sigsegv; 1035 1036 if (!cpu_has_mmips) { 1037 /* MIPS16e mode */ 1038 bcode = (instr[0] >> 5) & 0x3f; 1039 } else if (mm_insn_16bit(instr[0])) { 1040 /* 16-bit microMIPS BREAK */ 1041 bcode = instr[0] & 0xf; 1042 } else { 1043 /* 32-bit microMIPS BREAK */ 1044 if (__get_user(instr[1], (u16 __user *)(epc + 2))) 1045 goto out_sigsegv; 1046 opcode = (instr[0] << 16) | instr[1]; 1047 bcode = (opcode >> 6) & ((1 << 20) - 1); 1048 } 1049 } else { 1050 if (__get_user(opcode, (unsigned int __user *)epc)) 1051 goto out_sigsegv; 1052 bcode = (opcode >> 6) & ((1 << 20) - 1); 1053 } 1054 1055 /* 1056 * There is the ancient bug in the MIPS assemblers that the break 1057 * code starts left to bit 16 instead to bit 6 in the opcode. 1058 * Gas is bug-compatible, but not always, grrr... 1059 * We handle both cases with a simple heuristics. --macro 1060 */ 1061 if (bcode >= (1 << 10)) 1062 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10); 1063 1064 /* 1065 * notify the kprobe handlers, if instruction is likely to 1066 * pertain to them. 1067 */ 1068 switch (bcode) { 1069 case BRK_UPROBE: 1070 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode, 1071 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1072 goto out; 1073 else 1074 break; 1075 case BRK_UPROBE_XOL: 1076 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode, 1077 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1078 goto out; 1079 else 1080 break; 1081 case BRK_KPROBE_BP: 1082 if (notify_die(DIE_BREAK, "debug", regs, bcode, 1083 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1084 goto out; 1085 else 1086 break; 1087 case BRK_KPROBE_SSTEPBP: 1088 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 1089 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1090 goto out; 1091 else 1092 break; 1093 default: 1094 break; 1095 } 1096 1097 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break"); 1098 1099 out: 1100 set_fs(seg); 1101 exception_exit(prev_state); 1102 return; 1103 1104 out_sigsegv: 1105 force_sig(SIGSEGV); 1106 goto out; 1107 } 1108 1109 asmlinkage void do_tr(struct pt_regs *regs) 1110 { 1111 u32 opcode, tcode = 0; 1112 enum ctx_state prev_state; 1113 u16 instr[2]; 1114 mm_segment_t seg; 1115 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 1116 1117 seg = get_fs(); 1118 if (!user_mode(regs)) 1119 set_fs(KERNEL_DS); 1120 1121 prev_state = exception_enter(); 1122 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1123 if (get_isa16_mode(regs->cp0_epc)) { 1124 if (__get_user(instr[0], (u16 __user *)(epc + 0)) || 1125 __get_user(instr[1], (u16 __user *)(epc + 2))) 1126 goto out_sigsegv; 1127 opcode = (instr[0] << 16) | instr[1]; 1128 /* Immediate versions don't provide a code. */ 1129 if (!(opcode & OPCODE)) 1130 tcode = (opcode >> 12) & ((1 << 4) - 1); 1131 } else { 1132 if (__get_user(opcode, (u32 __user *)epc)) 1133 goto out_sigsegv; 1134 /* Immediate versions don't provide a code. */ 1135 if (!(opcode & OPCODE)) 1136 tcode = (opcode >> 6) & ((1 << 10) - 1); 1137 } 1138 1139 do_trap_or_bp(regs, tcode, 0, "Trap"); 1140 1141 out: 1142 set_fs(seg); 1143 exception_exit(prev_state); 1144 return; 1145 1146 out_sigsegv: 1147 force_sig(SIGSEGV); 1148 goto out; 1149 } 1150 1151 asmlinkage void do_ri(struct pt_regs *regs) 1152 { 1153 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 1154 unsigned long old_epc = regs->cp0_epc; 1155 unsigned long old31 = regs->regs[31]; 1156 enum ctx_state prev_state; 1157 unsigned int opcode = 0; 1158 int status = -1; 1159 1160 /* 1161 * Avoid any kernel code. Just emulate the R2 instruction 1162 * as quickly as possible. 1163 */ 1164 if (mipsr2_emulation && cpu_has_mips_r6 && 1165 likely(user_mode(regs)) && 1166 likely(get_user(opcode, epc) >= 0)) { 1167 unsigned long fcr31 = 0; 1168 1169 status = mipsr2_decoder(regs, opcode, &fcr31); 1170 switch (status) { 1171 case 0: 1172 case SIGEMT: 1173 return; 1174 case SIGILL: 1175 goto no_r2_instr; 1176 default: 1177 process_fpemu_return(status, 1178 ¤t->thread.cp0_baduaddr, 1179 fcr31); 1180 return; 1181 } 1182 } 1183 1184 no_r2_instr: 1185 1186 prev_state = exception_enter(); 1187 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1188 1189 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, 1190 SIGILL) == NOTIFY_STOP) 1191 goto out; 1192 1193 die_if_kernel("Reserved instruction in kernel code", regs); 1194 1195 if (unlikely(compute_return_epc(regs) < 0)) 1196 goto out; 1197 1198 if (!get_isa16_mode(regs->cp0_epc)) { 1199 if (unlikely(get_user(opcode, epc) < 0)) 1200 status = SIGSEGV; 1201 1202 if (!cpu_has_llsc && status < 0) 1203 status = simulate_llsc(regs, opcode); 1204 1205 if (status < 0) 1206 status = simulate_rdhwr_normal(regs, opcode); 1207 1208 if (status < 0) 1209 status = simulate_sync(regs, opcode); 1210 1211 if (status < 0) 1212 status = simulate_fp(regs, opcode, old_epc, old31); 1213 1214 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION 1215 if (status < 0) 1216 status = simulate_loongson3_cpucfg(regs, opcode); 1217 #endif 1218 } else if (cpu_has_mmips) { 1219 unsigned short mmop[2] = { 0 }; 1220 1221 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0)) 1222 status = SIGSEGV; 1223 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0)) 1224 status = SIGSEGV; 1225 opcode = mmop[0]; 1226 opcode = (opcode << 16) | mmop[1]; 1227 1228 if (status < 0) 1229 status = simulate_rdhwr_mm(regs, opcode); 1230 } 1231 1232 if (status < 0) 1233 status = SIGILL; 1234 1235 if (unlikely(status > 0)) { 1236 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1237 regs->regs[31] = old31; 1238 force_sig(status); 1239 } 1240 1241 out: 1242 exception_exit(prev_state); 1243 } 1244 1245 /* 1246 * No lock; only written during early bootup by CPU 0. 1247 */ 1248 static RAW_NOTIFIER_HEAD(cu2_chain); 1249 1250 int __ref register_cu2_notifier(struct notifier_block *nb) 1251 { 1252 return raw_notifier_chain_register(&cu2_chain, nb); 1253 } 1254 1255 int cu2_notifier_call_chain(unsigned long val, void *v) 1256 { 1257 return raw_notifier_call_chain(&cu2_chain, val, v); 1258 } 1259 1260 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 1261 void *data) 1262 { 1263 struct pt_regs *regs = data; 1264 1265 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " 1266 "instruction", regs); 1267 force_sig(SIGILL); 1268 1269 return NOTIFY_OK; 1270 } 1271 1272 #ifdef CONFIG_MIPS_FP_SUPPORT 1273 1274 static int enable_restore_fp_context(int msa) 1275 { 1276 int err, was_fpu_owner, prior_msa; 1277 bool first_fp; 1278 1279 /* Initialize context if it hasn't been used already */ 1280 first_fp = init_fp_ctx(current); 1281 1282 if (first_fp) { 1283 preempt_disable(); 1284 err = own_fpu_inatomic(1); 1285 if (msa && !err) { 1286 enable_msa(); 1287 set_thread_flag(TIF_USEDMSA); 1288 set_thread_flag(TIF_MSA_CTX_LIVE); 1289 } 1290 preempt_enable(); 1291 return err; 1292 } 1293 1294 /* 1295 * This task has formerly used the FP context. 1296 * 1297 * If this thread has no live MSA vector context then we can simply 1298 * restore the scalar FP context. If it has live MSA vector context 1299 * (that is, it has or may have used MSA since last performing a 1300 * function call) then we'll need to restore the vector context. This 1301 * applies even if we're currently only executing a scalar FP 1302 * instruction. This is because if we were to later execute an MSA 1303 * instruction then we'd either have to: 1304 * 1305 * - Restore the vector context & clobber any registers modified by 1306 * scalar FP instructions between now & then. 1307 * 1308 * or 1309 * 1310 * - Not restore the vector context & lose the most significant bits 1311 * of all vector registers. 1312 * 1313 * Neither of those options is acceptable. We cannot restore the least 1314 * significant bits of the registers now & only restore the most 1315 * significant bits later because the most significant bits of any 1316 * vector registers whose aliased FP register is modified now will have 1317 * been zeroed. We'd have no way to know that when restoring the vector 1318 * context & thus may load an outdated value for the most significant 1319 * bits of a vector register. 1320 */ 1321 if (!msa && !thread_msa_context_live()) 1322 return own_fpu(1); 1323 1324 /* 1325 * This task is using or has previously used MSA. Thus we require 1326 * that Status.FR == 1. 1327 */ 1328 preempt_disable(); 1329 was_fpu_owner = is_fpu_owner(); 1330 err = own_fpu_inatomic(0); 1331 if (err) 1332 goto out; 1333 1334 enable_msa(); 1335 write_msa_csr(current->thread.fpu.msacsr); 1336 set_thread_flag(TIF_USEDMSA); 1337 1338 /* 1339 * If this is the first time that the task is using MSA and it has 1340 * previously used scalar FP in this time slice then we already nave 1341 * FP context which we shouldn't clobber. We do however need to clear 1342 * the upper 64b of each vector register so that this task has no 1343 * opportunity to see data left behind by another. 1344 */ 1345 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); 1346 if (!prior_msa && was_fpu_owner) { 1347 init_msa_upper(); 1348 1349 goto out; 1350 } 1351 1352 if (!prior_msa) { 1353 /* 1354 * Restore the least significant 64b of each vector register 1355 * from the existing scalar FP context. 1356 */ 1357 _restore_fp(current); 1358 1359 /* 1360 * The task has not formerly used MSA, so clear the upper 64b 1361 * of each vector register such that it cannot see data left 1362 * behind by another task. 1363 */ 1364 init_msa_upper(); 1365 } else { 1366 /* We need to restore the vector context. */ 1367 restore_msa(current); 1368 1369 /* Restore the scalar FP control & status register */ 1370 if (!was_fpu_owner) 1371 write_32bit_cp1_register(CP1_STATUS, 1372 current->thread.fpu.fcr31); 1373 } 1374 1375 out: 1376 preempt_enable(); 1377 1378 return 0; 1379 } 1380 1381 #else /* !CONFIG_MIPS_FP_SUPPORT */ 1382 1383 static int enable_restore_fp_context(int msa) 1384 { 1385 return SIGILL; 1386 } 1387 1388 #endif /* CONFIG_MIPS_FP_SUPPORT */ 1389 1390 asmlinkage void do_cpu(struct pt_regs *regs) 1391 { 1392 enum ctx_state prev_state; 1393 unsigned int __user *epc; 1394 unsigned long old_epc, old31; 1395 unsigned int opcode; 1396 unsigned int cpid; 1397 int status; 1398 1399 prev_state = exception_enter(); 1400 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1401 1402 if (cpid != 2) 1403 die_if_kernel("do_cpu invoked from kernel context!", regs); 1404 1405 switch (cpid) { 1406 case 0: 1407 epc = (unsigned int __user *)exception_epc(regs); 1408 old_epc = regs->cp0_epc; 1409 old31 = regs->regs[31]; 1410 opcode = 0; 1411 status = -1; 1412 1413 if (unlikely(compute_return_epc(regs) < 0)) 1414 break; 1415 1416 if (!get_isa16_mode(regs->cp0_epc)) { 1417 if (unlikely(get_user(opcode, epc) < 0)) 1418 status = SIGSEGV; 1419 1420 if (!cpu_has_llsc && status < 0) 1421 status = simulate_llsc(regs, opcode); 1422 } 1423 1424 if (status < 0) 1425 status = SIGILL; 1426 1427 if (unlikely(status > 0)) { 1428 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1429 regs->regs[31] = old31; 1430 force_sig(status); 1431 } 1432 1433 break; 1434 1435 #ifdef CONFIG_MIPS_FP_SUPPORT 1436 case 3: 1437 /* 1438 * The COP3 opcode space and consequently the CP0.Status.CU3 1439 * bit and the CP0.Cause.CE=3 encoding have been removed as 1440 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs 1441 * up the space has been reused for COP1X instructions, that 1442 * are enabled by the CP0.Status.CU1 bit and consequently 1443 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable 1444 * exceptions. Some FPU-less processors that implement one 1445 * of these ISAs however use this code erroneously for COP1X 1446 * instructions. Therefore we redirect this trap to the FP 1447 * emulator too. 1448 */ 1449 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) { 1450 force_sig(SIGILL); 1451 break; 1452 } 1453 fallthrough; 1454 case 1: { 1455 void __user *fault_addr; 1456 unsigned long fcr31; 1457 int err, sig; 1458 1459 err = enable_restore_fp_context(0); 1460 1461 if (raw_cpu_has_fpu && !err) 1462 break; 1463 1464 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, 1465 &fault_addr); 1466 1467 /* 1468 * We can't allow the emulated instruction to leave 1469 * any enabled Cause bits set in $fcr31. 1470 */ 1471 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 1472 current->thread.fpu.fcr31 &= ~fcr31; 1473 1474 /* Send a signal if required. */ 1475 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err) 1476 mt_ase_fp_affinity(); 1477 1478 break; 1479 } 1480 #else /* CONFIG_MIPS_FP_SUPPORT */ 1481 case 1: 1482 case 3: 1483 force_sig(SIGILL); 1484 break; 1485 #endif /* CONFIG_MIPS_FP_SUPPORT */ 1486 1487 case 2: 1488 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1489 break; 1490 } 1491 1492 exception_exit(prev_state); 1493 } 1494 1495 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr) 1496 { 1497 enum ctx_state prev_state; 1498 1499 prev_state = exception_enter(); 1500 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1501 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0, 1502 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP) 1503 goto out; 1504 1505 /* Clear MSACSR.Cause before enabling interrupts */ 1506 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF); 1507 local_irq_enable(); 1508 1509 die_if_kernel("do_msa_fpe invoked from kernel context!", regs); 1510 force_sig(SIGFPE); 1511 out: 1512 exception_exit(prev_state); 1513 } 1514 1515 asmlinkage void do_msa(struct pt_regs *regs) 1516 { 1517 enum ctx_state prev_state; 1518 int err; 1519 1520 prev_state = exception_enter(); 1521 1522 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { 1523 force_sig(SIGILL); 1524 goto out; 1525 } 1526 1527 die_if_kernel("do_msa invoked from kernel context!", regs); 1528 1529 err = enable_restore_fp_context(1); 1530 if (err) 1531 force_sig(SIGILL); 1532 out: 1533 exception_exit(prev_state); 1534 } 1535 1536 asmlinkage void do_mdmx(struct pt_regs *regs) 1537 { 1538 enum ctx_state prev_state; 1539 1540 prev_state = exception_enter(); 1541 force_sig(SIGILL); 1542 exception_exit(prev_state); 1543 } 1544 1545 /* 1546 * Called with interrupts disabled. 1547 */ 1548 asmlinkage void do_watch(struct pt_regs *regs) 1549 { 1550 enum ctx_state prev_state; 1551 1552 prev_state = exception_enter(); 1553 /* 1554 * Clear WP (bit 22) bit of cause register so we don't loop 1555 * forever. 1556 */ 1557 clear_c0_cause(CAUSEF_WP); 1558 1559 /* 1560 * If the current thread has the watch registers loaded, save 1561 * their values and send SIGTRAP. Otherwise another thread 1562 * left the registers set, clear them and continue. 1563 */ 1564 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1565 mips_read_watch_registers(); 1566 local_irq_enable(); 1567 force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL); 1568 } else { 1569 mips_clear_watch_registers(); 1570 local_irq_enable(); 1571 } 1572 exception_exit(prev_state); 1573 } 1574 1575 asmlinkage void do_mcheck(struct pt_regs *regs) 1576 { 1577 int multi_match = regs->cp0_status & ST0_TS; 1578 enum ctx_state prev_state; 1579 mm_segment_t old_fs = get_fs(); 1580 1581 prev_state = exception_enter(); 1582 show_regs(regs); 1583 1584 if (multi_match) { 1585 dump_tlb_regs(); 1586 pr_info("\n"); 1587 dump_tlb_all(); 1588 } 1589 1590 if (!user_mode(regs)) 1591 set_fs(KERNEL_DS); 1592 1593 show_code((unsigned int __user *) regs->cp0_epc); 1594 1595 set_fs(old_fs); 1596 1597 /* 1598 * Some chips may have other causes of machine check (e.g. SB1 1599 * graduation timer) 1600 */ 1601 panic("Caught Machine Check exception - %scaused by multiple " 1602 "matching entries in the TLB.", 1603 (multi_match) ? "" : "not "); 1604 } 1605 1606 asmlinkage void do_mt(struct pt_regs *regs) 1607 { 1608 int subcode; 1609 1610 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1611 >> VPECONTROL_EXCPT_SHIFT; 1612 switch (subcode) { 1613 case 0: 1614 printk(KERN_DEBUG "Thread Underflow\n"); 1615 break; 1616 case 1: 1617 printk(KERN_DEBUG "Thread Overflow\n"); 1618 break; 1619 case 2: 1620 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1621 break; 1622 case 3: 1623 printk(KERN_DEBUG "Gating Storage Exception\n"); 1624 break; 1625 case 4: 1626 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1627 break; 1628 case 5: 1629 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1630 break; 1631 default: 1632 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1633 subcode); 1634 break; 1635 } 1636 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1637 1638 force_sig(SIGILL); 1639 } 1640 1641 1642 asmlinkage void do_dsp(struct pt_regs *regs) 1643 { 1644 if (cpu_has_dsp) 1645 panic("Unexpected DSP exception"); 1646 1647 force_sig(SIGILL); 1648 } 1649 1650 asmlinkage void do_reserved(struct pt_regs *regs) 1651 { 1652 /* 1653 * Game over - no way to handle this if it ever occurs. Most probably 1654 * caused by a new unknown cpu type or after another deadly 1655 * hard/software error. 1656 */ 1657 show_regs(regs); 1658 panic("Caught reserved exception %ld - should not happen.", 1659 (regs->cp0_cause & 0x7f) >> 2); 1660 } 1661 1662 static int __initdata l1parity = 1; 1663 static int __init nol1parity(char *s) 1664 { 1665 l1parity = 0; 1666 return 1; 1667 } 1668 __setup("nol1par", nol1parity); 1669 static int __initdata l2parity = 1; 1670 static int __init nol2parity(char *s) 1671 { 1672 l2parity = 0; 1673 return 1; 1674 } 1675 __setup("nol2par", nol2parity); 1676 1677 /* 1678 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1679 * it different ways. 1680 */ 1681 static inline void parity_protection_init(void) 1682 { 1683 #define ERRCTL_PE 0x80000000 1684 #define ERRCTL_L2P 0x00800000 1685 1686 if (mips_cm_revision() >= CM_REV_CM3) { 1687 ulong gcr_ectl, cp0_ectl; 1688 1689 /* 1690 * With CM3 systems we need to ensure that the L1 & L2 1691 * parity enables are set to the same value, since this 1692 * is presumed by the hardware engineers. 1693 * 1694 * If the user disabled either of L1 or L2 ECC checking, 1695 * disable both. 1696 */ 1697 l1parity &= l2parity; 1698 l2parity &= l1parity; 1699 1700 /* Probe L1 ECC support */ 1701 cp0_ectl = read_c0_ecc(); 1702 write_c0_ecc(cp0_ectl | ERRCTL_PE); 1703 back_to_back_c0_hazard(); 1704 cp0_ectl = read_c0_ecc(); 1705 1706 /* Probe L2 ECC support */ 1707 gcr_ectl = read_gcr_err_control(); 1708 1709 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) || 1710 !(cp0_ectl & ERRCTL_PE)) { 1711 /* 1712 * One of L1 or L2 ECC checking isn't supported, 1713 * so we cannot enable either. 1714 */ 1715 l1parity = l2parity = 0; 1716 } 1717 1718 /* Configure L1 ECC checking */ 1719 if (l1parity) 1720 cp0_ectl |= ERRCTL_PE; 1721 else 1722 cp0_ectl &= ~ERRCTL_PE; 1723 write_c0_ecc(cp0_ectl); 1724 back_to_back_c0_hazard(); 1725 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity); 1726 1727 /* Configure L2 ECC checking */ 1728 if (l2parity) 1729 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN; 1730 else 1731 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN; 1732 write_gcr_err_control(gcr_ectl); 1733 gcr_ectl = read_gcr_err_control(); 1734 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN; 1735 WARN_ON(!!gcr_ectl != l2parity); 1736 1737 pr_info("Cache parity protection %sabled\n", 1738 l1parity ? "en" : "dis"); 1739 return; 1740 } 1741 1742 switch (current_cpu_type()) { 1743 case CPU_24K: 1744 case CPU_34K: 1745 case CPU_74K: 1746 case CPU_1004K: 1747 case CPU_1074K: 1748 case CPU_INTERAPTIV: 1749 case CPU_PROAPTIV: 1750 case CPU_P5600: 1751 case CPU_QEMU_GENERIC: 1752 case CPU_P6600: 1753 { 1754 unsigned long errctl; 1755 unsigned int l1parity_present, l2parity_present; 1756 1757 errctl = read_c0_ecc(); 1758 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1759 1760 /* probe L1 parity support */ 1761 write_c0_ecc(errctl | ERRCTL_PE); 1762 back_to_back_c0_hazard(); 1763 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1764 1765 /* probe L2 parity support */ 1766 write_c0_ecc(errctl|ERRCTL_L2P); 1767 back_to_back_c0_hazard(); 1768 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1769 1770 if (l1parity_present && l2parity_present) { 1771 if (l1parity) 1772 errctl |= ERRCTL_PE; 1773 if (l1parity ^ l2parity) 1774 errctl |= ERRCTL_L2P; 1775 } else if (l1parity_present) { 1776 if (l1parity) 1777 errctl |= ERRCTL_PE; 1778 } else if (l2parity_present) { 1779 if (l2parity) 1780 errctl |= ERRCTL_L2P; 1781 } else { 1782 /* No parity available */ 1783 } 1784 1785 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1786 1787 write_c0_ecc(errctl); 1788 back_to_back_c0_hazard(); 1789 errctl = read_c0_ecc(); 1790 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1791 1792 if (l1parity_present) 1793 printk(KERN_INFO "Cache parity protection %sabled\n", 1794 (errctl & ERRCTL_PE) ? "en" : "dis"); 1795 1796 if (l2parity_present) { 1797 if (l1parity_present && l1parity) 1798 errctl ^= ERRCTL_L2P; 1799 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1800 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1801 } 1802 } 1803 break; 1804 1805 case CPU_5KC: 1806 case CPU_5KE: 1807 case CPU_LOONGSON32: 1808 write_c0_ecc(0x80000000); 1809 back_to_back_c0_hazard(); 1810 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1811 printk(KERN_INFO "Cache parity protection %sabled\n", 1812 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1813 break; 1814 case CPU_20KC: 1815 case CPU_25KF: 1816 /* Clear the DE bit (bit 16) in the c0_status register. */ 1817 printk(KERN_INFO "Enable cache parity protection for " 1818 "MIPS 20KC/25KF CPUs.\n"); 1819 clear_c0_status(ST0_DE); 1820 break; 1821 default: 1822 break; 1823 } 1824 } 1825 1826 asmlinkage void cache_parity_error(void) 1827 { 1828 const int field = 2 * sizeof(unsigned long); 1829 unsigned int reg_val; 1830 1831 /* For the moment, report the problem and hang. */ 1832 printk("Cache error exception:\n"); 1833 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1834 reg_val = read_c0_cacheerr(); 1835 printk("c0_cacheerr == %08x\n", reg_val); 1836 1837 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1838 reg_val & (1<<30) ? "secondary" : "primary", 1839 reg_val & (1<<31) ? "data" : "insn"); 1840 if ((cpu_has_mips_r2_r6) && 1841 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1842 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1843 reg_val & (1<<29) ? "ED " : "", 1844 reg_val & (1<<28) ? "ET " : "", 1845 reg_val & (1<<27) ? "ES " : "", 1846 reg_val & (1<<26) ? "EE " : "", 1847 reg_val & (1<<25) ? "EB " : "", 1848 reg_val & (1<<24) ? "EI " : "", 1849 reg_val & (1<<23) ? "E1 " : "", 1850 reg_val & (1<<22) ? "E0 " : ""); 1851 } else { 1852 pr_err("Error bits: %s%s%s%s%s%s%s\n", 1853 reg_val & (1<<29) ? "ED " : "", 1854 reg_val & (1<<28) ? "ET " : "", 1855 reg_val & (1<<26) ? "EE " : "", 1856 reg_val & (1<<25) ? "EB " : "", 1857 reg_val & (1<<24) ? "EI " : "", 1858 reg_val & (1<<23) ? "E1 " : "", 1859 reg_val & (1<<22) ? "E0 " : ""); 1860 } 1861 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1862 1863 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1864 if (reg_val & (1<<22)) 1865 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1866 1867 if (reg_val & (1<<23)) 1868 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1869 #endif 1870 1871 panic("Can't handle the cache error!"); 1872 } 1873 1874 asmlinkage void do_ftlb(void) 1875 { 1876 const int field = 2 * sizeof(unsigned long); 1877 unsigned int reg_val; 1878 1879 /* For the moment, report the problem and hang. */ 1880 if ((cpu_has_mips_r2_r6) && 1881 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) || 1882 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) { 1883 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1884 read_c0_ecc()); 1885 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1886 reg_val = read_c0_cacheerr(); 1887 pr_err("c0_cacheerr == %08x\n", reg_val); 1888 1889 if ((reg_val & 0xc0000000) == 0xc0000000) { 1890 pr_err("Decoded c0_cacheerr: FTLB parity error\n"); 1891 } else { 1892 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1893 reg_val & (1<<30) ? "secondary" : "primary", 1894 reg_val & (1<<31) ? "data" : "insn"); 1895 } 1896 } else { 1897 pr_err("FTLB error exception\n"); 1898 } 1899 /* Just print the cacheerr bits for now */ 1900 cache_parity_error(); 1901 } 1902 1903 /* 1904 * SDBBP EJTAG debug exception handler. 1905 * We skip the instruction and return to the next instruction. 1906 */ 1907 void ejtag_exception_handler(struct pt_regs *regs) 1908 { 1909 const int field = 2 * sizeof(unsigned long); 1910 unsigned long depc, old_epc, old_ra; 1911 unsigned int debug; 1912 1913 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1914 depc = read_c0_depc(); 1915 debug = read_c0_debug(); 1916 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1917 if (debug & 0x80000000) { 1918 /* 1919 * In branch delay slot. 1920 * We cheat a little bit here and use EPC to calculate the 1921 * debug return address (DEPC). EPC is restored after the 1922 * calculation. 1923 */ 1924 old_epc = regs->cp0_epc; 1925 old_ra = regs->regs[31]; 1926 regs->cp0_epc = depc; 1927 compute_return_epc(regs); 1928 depc = regs->cp0_epc; 1929 regs->cp0_epc = old_epc; 1930 regs->regs[31] = old_ra; 1931 } else 1932 depc += 4; 1933 write_c0_depc(depc); 1934 1935 #if 0 1936 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1937 write_c0_debug(debug | 0x100); 1938 #endif 1939 } 1940 1941 /* 1942 * NMI exception handler. 1943 * No lock; only written during early bootup by CPU 0. 1944 */ 1945 static RAW_NOTIFIER_HEAD(nmi_chain); 1946 1947 int register_nmi_notifier(struct notifier_block *nb) 1948 { 1949 return raw_notifier_chain_register(&nmi_chain, nb); 1950 } 1951 1952 void __noreturn nmi_exception_handler(struct pt_regs *regs) 1953 { 1954 char str[100]; 1955 1956 nmi_enter(); 1957 raw_notifier_call_chain(&nmi_chain, 0, regs); 1958 bust_spinlocks(1); 1959 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", 1960 smp_processor_id(), regs->cp0_epc); 1961 regs->cp0_epc = read_c0_errorepc(); 1962 die(str, regs); 1963 nmi_exit(); 1964 } 1965 1966 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1967 1968 unsigned long ebase; 1969 EXPORT_SYMBOL_GPL(ebase); 1970 unsigned long exception_handlers[32]; 1971 unsigned long vi_handlers[64]; 1972 1973 void __init *set_except_vector(int n, void *addr) 1974 { 1975 unsigned long handler = (unsigned long) addr; 1976 unsigned long old_handler; 1977 1978 #ifdef CONFIG_CPU_MICROMIPS 1979 /* 1980 * Only the TLB handlers are cache aligned with an even 1981 * address. All other handlers are on an odd address and 1982 * require no modification. Otherwise, MIPS32 mode will 1983 * be entered when handling any TLB exceptions. That 1984 * would be bad...since we must stay in microMIPS mode. 1985 */ 1986 if (!(handler & 0x1)) 1987 handler |= 1; 1988 #endif 1989 old_handler = xchg(&exception_handlers[n], handler); 1990 1991 if (n == 0 && cpu_has_divec) { 1992 #ifdef CONFIG_CPU_MICROMIPS 1993 unsigned long jump_mask = ~((1 << 27) - 1); 1994 #else 1995 unsigned long jump_mask = ~((1 << 28) - 1); 1996 #endif 1997 u32 *buf = (u32 *)(ebase + 0x200); 1998 unsigned int k0 = 26; 1999 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 2000 uasm_i_j(&buf, handler & ~jump_mask); 2001 uasm_i_nop(&buf); 2002 } else { 2003 UASM_i_LA(&buf, k0, handler); 2004 uasm_i_jr(&buf, k0); 2005 uasm_i_nop(&buf); 2006 } 2007 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 2008 } 2009 return (void *)old_handler; 2010 } 2011 2012 static void do_default_vi(void) 2013 { 2014 show_regs(get_irq_regs()); 2015 panic("Caught unexpected vectored interrupt."); 2016 } 2017 2018 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 2019 { 2020 unsigned long handler; 2021 unsigned long old_handler = vi_handlers[n]; 2022 int srssets = current_cpu_data.srsets; 2023 u16 *h; 2024 unsigned char *b; 2025 2026 BUG_ON(!cpu_has_veic && !cpu_has_vint); 2027 2028 if (addr == NULL) { 2029 handler = (unsigned long) do_default_vi; 2030 srs = 0; 2031 } else 2032 handler = (unsigned long) addr; 2033 vi_handlers[n] = handler; 2034 2035 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 2036 2037 if (srs >= srssets) 2038 panic("Shadow register set %d not supported", srs); 2039 2040 if (cpu_has_veic) { 2041 if (board_bind_eic_interrupt) 2042 board_bind_eic_interrupt(n, srs); 2043 } else if (cpu_has_vint) { 2044 /* SRSMap is only defined if shadow sets are implemented */ 2045 if (srssets > 1) 2046 change_c0_srsmap(0xf << n*4, srs << n*4); 2047 } 2048 2049 if (srs == 0) { 2050 /* 2051 * If no shadow set is selected then use the default handler 2052 * that does normal register saving and standard interrupt exit 2053 */ 2054 extern char except_vec_vi, except_vec_vi_lui; 2055 extern char except_vec_vi_ori, except_vec_vi_end; 2056 extern char rollback_except_vec_vi; 2057 char *vec_start = using_rollback_handler() ? 2058 &rollback_except_vec_vi : &except_vec_vi; 2059 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) 2060 const int lui_offset = &except_vec_vi_lui - vec_start + 2; 2061 const int ori_offset = &except_vec_vi_ori - vec_start + 2; 2062 #else 2063 const int lui_offset = &except_vec_vi_lui - vec_start; 2064 const int ori_offset = &except_vec_vi_ori - vec_start; 2065 #endif 2066 const int handler_len = &except_vec_vi_end - vec_start; 2067 2068 if (handler_len > VECTORSPACING) { 2069 /* 2070 * Sigh... panicing won't help as the console 2071 * is probably not configured :( 2072 */ 2073 panic("VECTORSPACING too small"); 2074 } 2075 2076 set_handler(((unsigned long)b - ebase), vec_start, 2077 #ifdef CONFIG_CPU_MICROMIPS 2078 (handler_len - 1)); 2079 #else 2080 handler_len); 2081 #endif 2082 h = (u16 *)(b + lui_offset); 2083 *h = (handler >> 16) & 0xffff; 2084 h = (u16 *)(b + ori_offset); 2085 *h = (handler & 0xffff); 2086 local_flush_icache_range((unsigned long)b, 2087 (unsigned long)(b+handler_len)); 2088 } 2089 else { 2090 /* 2091 * In other cases jump directly to the interrupt handler. It 2092 * is the handler's responsibility to save registers if required 2093 * (eg hi/lo) and return from the exception using "eret". 2094 */ 2095 u32 insn; 2096 2097 h = (u16 *)b; 2098 /* j handler */ 2099 #ifdef CONFIG_CPU_MICROMIPS 2100 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); 2101 #else 2102 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); 2103 #endif 2104 h[0] = (insn >> 16) & 0xffff; 2105 h[1] = insn & 0xffff; 2106 h[2] = 0; 2107 h[3] = 0; 2108 local_flush_icache_range((unsigned long)b, 2109 (unsigned long)(b+8)); 2110 } 2111 2112 return (void *)old_handler; 2113 } 2114 2115 void *set_vi_handler(int n, vi_handler_t addr) 2116 { 2117 return set_vi_srs_handler(n, addr, 0); 2118 } 2119 2120 extern void tlb_init(void); 2121 2122 /* 2123 * Timer interrupt 2124 */ 2125 int cp0_compare_irq; 2126 EXPORT_SYMBOL_GPL(cp0_compare_irq); 2127 int cp0_compare_irq_shift; 2128 2129 /* 2130 * Performance counter IRQ or -1 if shared with timer 2131 */ 2132 int cp0_perfcount_irq; 2133 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 2134 2135 /* 2136 * Fast debug channel IRQ or -1 if not present 2137 */ 2138 int cp0_fdc_irq; 2139 EXPORT_SYMBOL_GPL(cp0_fdc_irq); 2140 2141 static int noulri; 2142 2143 static int __init ulri_disable(char *s) 2144 { 2145 pr_info("Disabling ulri\n"); 2146 noulri = 1; 2147 2148 return 1; 2149 } 2150 __setup("noulri", ulri_disable); 2151 2152 /* configure STATUS register */ 2153 static void configure_status(void) 2154 { 2155 /* 2156 * Disable coprocessors and select 32-bit or 64-bit addressing 2157 * and the 16/32 or 32/32 FPR register model. Reset the BEV 2158 * flag that some firmware may have left set and the TS bit (for 2159 * IP27). Set XX for ISA IV code to work. 2160 */ 2161 unsigned int status_set = ST0_CU0; 2162 #ifdef CONFIG_64BIT 2163 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 2164 #endif 2165 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) 2166 status_set |= ST0_XX; 2167 if (cpu_has_dsp) 2168 status_set |= ST0_MX; 2169 2170 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 2171 status_set); 2172 } 2173 2174 unsigned int hwrena; 2175 EXPORT_SYMBOL_GPL(hwrena); 2176 2177 /* configure HWRENA register */ 2178 static void configure_hwrena(void) 2179 { 2180 hwrena = cpu_hwrena_impl_bits; 2181 2182 if (cpu_has_mips_r2_r6) 2183 hwrena |= MIPS_HWRENA_CPUNUM | 2184 MIPS_HWRENA_SYNCISTEP | 2185 MIPS_HWRENA_CC | 2186 MIPS_HWRENA_CCRES; 2187 2188 if (!noulri && cpu_has_userlocal) 2189 hwrena |= MIPS_HWRENA_ULR; 2190 2191 if (hwrena) 2192 write_c0_hwrena(hwrena); 2193 } 2194 2195 static void configure_exception_vector(void) 2196 { 2197 if (cpu_has_mips_r2_r6) { 2198 unsigned long sr = set_c0_status(ST0_BEV); 2199 /* If available, use WG to set top bits of EBASE */ 2200 if (cpu_has_ebase_wg) { 2201 #ifdef CONFIG_64BIT 2202 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 2203 #else 2204 write_c0_ebase(ebase | MIPS_EBASE_WG); 2205 #endif 2206 } 2207 write_c0_ebase(ebase); 2208 write_c0_status(sr); 2209 } 2210 if (cpu_has_veic || cpu_has_vint) { 2211 /* Setting vector spacing enables EI/VI mode */ 2212 change_c0_intctl(0x3e0, VECTORSPACING); 2213 } 2214 if (cpu_has_divec) { 2215 if (cpu_has_mipsmt) { 2216 unsigned int vpflags = dvpe(); 2217 set_c0_cause(CAUSEF_IV); 2218 evpe(vpflags); 2219 } else 2220 set_c0_cause(CAUSEF_IV); 2221 } 2222 } 2223 2224 void per_cpu_trap_init(bool is_boot_cpu) 2225 { 2226 unsigned int cpu = smp_processor_id(); 2227 2228 configure_status(); 2229 configure_hwrena(); 2230 2231 configure_exception_vector(); 2232 2233 /* 2234 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 2235 * 2236 * o read IntCtl.IPTI to determine the timer interrupt 2237 * o read IntCtl.IPPCI to determine the performance counter interrupt 2238 * o read IntCtl.IPFDC to determine the fast debug channel interrupt 2239 */ 2240 if (cpu_has_mips_r2_r6) { 2241 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 2242 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 2243 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 2244 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7; 2245 if (!cp0_fdc_irq) 2246 cp0_fdc_irq = -1; 2247 2248 } else { 2249 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 2250 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 2251 cp0_perfcount_irq = -1; 2252 cp0_fdc_irq = -1; 2253 } 2254 2255 if (cpu_has_mmid) 2256 cpu_data[cpu].asid_cache = 0; 2257 else if (!cpu_data[cpu].asid_cache) 2258 cpu_data[cpu].asid_cache = asid_first_version(cpu); 2259 2260 mmgrab(&init_mm); 2261 current->active_mm = &init_mm; 2262 BUG_ON(current->mm); 2263 enter_lazy_tlb(&init_mm, current); 2264 2265 /* Boot CPU's cache setup in setup_arch(). */ 2266 if (!is_boot_cpu) 2267 cpu_cache_init(); 2268 tlb_init(); 2269 TLBMISS_HANDLER_SETUP(); 2270 } 2271 2272 /* Install CPU exception handler */ 2273 void set_handler(unsigned long offset, void *addr, unsigned long size) 2274 { 2275 #ifdef CONFIG_CPU_MICROMIPS 2276 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); 2277 #else 2278 memcpy((void *)(ebase + offset), addr, size); 2279 #endif 2280 local_flush_icache_range(ebase + offset, ebase + offset + size); 2281 } 2282 2283 static const char panic_null_cerr[] = 2284 "Trying to set NULL cache error exception handler\n"; 2285 2286 /* 2287 * Install uncached CPU exception handler. 2288 * This is suitable only for the cache error exception which is the only 2289 * exception handler that is being run uncached. 2290 */ 2291 void set_uncached_handler(unsigned long offset, void *addr, 2292 unsigned long size) 2293 { 2294 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 2295 2296 if (!addr) 2297 panic(panic_null_cerr); 2298 2299 memcpy((void *)(uncached_ebase + offset), addr, size); 2300 } 2301 2302 static int __initdata rdhwr_noopt; 2303 static int __init set_rdhwr_noopt(char *str) 2304 { 2305 rdhwr_noopt = 1; 2306 return 1; 2307 } 2308 2309 __setup("rdhwr_noopt", set_rdhwr_noopt); 2310 2311 void __init trap_init(void) 2312 { 2313 extern char except_vec3_generic; 2314 extern char except_vec4; 2315 extern char except_vec3_r4000; 2316 unsigned long i, vec_size; 2317 phys_addr_t ebase_pa; 2318 2319 check_wait(); 2320 2321 if (!cpu_has_mips_r2_r6) { 2322 ebase = CAC_BASE; 2323 ebase_pa = virt_to_phys((void *)ebase); 2324 vec_size = 0x400; 2325 2326 memblock_reserve(ebase_pa, vec_size); 2327 } else { 2328 if (cpu_has_veic || cpu_has_vint) 2329 vec_size = 0x200 + VECTORSPACING*64; 2330 else 2331 vec_size = PAGE_SIZE; 2332 2333 ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); 2334 if (!ebase_pa) 2335 panic("%s: Failed to allocate %lu bytes align=0x%x\n", 2336 __func__, vec_size, 1 << fls(vec_size)); 2337 2338 /* 2339 * Try to ensure ebase resides in KSeg0 if possible. 2340 * 2341 * It shouldn't generally be in XKPhys on MIPS64 to avoid 2342 * hitting a poorly defined exception base for Cache Errors. 2343 * The allocation is likely to be in the low 512MB of physical, 2344 * in which case we should be able to convert to KSeg0. 2345 * 2346 * EVA is special though as it allows segments to be rearranged 2347 * and to become uncached during cache error handling. 2348 */ 2349 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) 2350 ebase = CKSEG0ADDR(ebase_pa); 2351 else 2352 ebase = (unsigned long)phys_to_virt(ebase_pa); 2353 } 2354 2355 if (cpu_has_mmips) { 2356 unsigned int config3 = read_c0_config3(); 2357 2358 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) 2359 write_c0_config3(config3 | MIPS_CONF3_ISA_OE); 2360 else 2361 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); 2362 } 2363 2364 if (board_ebase_setup) 2365 board_ebase_setup(); 2366 per_cpu_trap_init(true); 2367 memblock_set_bottom_up(false); 2368 2369 /* 2370 * Copy the generic exception handlers to their final destination. 2371 * This will be overridden later as suitable for a particular 2372 * configuration. 2373 */ 2374 set_handler(0x180, &except_vec3_generic, 0x80); 2375 2376 /* 2377 * Setup default vectors 2378 */ 2379 for (i = 0; i <= 31; i++) 2380 set_except_vector(i, handle_reserved); 2381 2382 /* 2383 * Copy the EJTAG debug exception vector handler code to it's final 2384 * destination. 2385 */ 2386 if (cpu_has_ejtag && board_ejtag_handler_setup) 2387 board_ejtag_handler_setup(); 2388 2389 /* 2390 * Only some CPUs have the watch exceptions. 2391 */ 2392 if (cpu_has_watch) 2393 set_except_vector(EXCCODE_WATCH, handle_watch); 2394 2395 /* 2396 * Initialise interrupt handlers 2397 */ 2398 if (cpu_has_veic || cpu_has_vint) { 2399 int nvec = cpu_has_veic ? 64 : 8; 2400 for (i = 0; i < nvec; i++) 2401 set_vi_handler(i, NULL); 2402 } 2403 else if (cpu_has_divec) 2404 set_handler(0x200, &except_vec4, 0x8); 2405 2406 /* 2407 * Some CPUs can enable/disable for cache parity detection, but does 2408 * it different ways. 2409 */ 2410 parity_protection_init(); 2411 2412 /* 2413 * The Data Bus Errors / Instruction Bus Errors are signaled 2414 * by external hardware. Therefore these two exceptions 2415 * may have board specific handlers. 2416 */ 2417 if (board_be_init) 2418 board_be_init(); 2419 2420 set_except_vector(EXCCODE_INT, using_rollback_handler() ? 2421 rollback_handle_int : handle_int); 2422 set_except_vector(EXCCODE_MOD, handle_tlbm); 2423 set_except_vector(EXCCODE_TLBL, handle_tlbl); 2424 set_except_vector(EXCCODE_TLBS, handle_tlbs); 2425 2426 set_except_vector(EXCCODE_ADEL, handle_adel); 2427 set_except_vector(EXCCODE_ADES, handle_ades); 2428 2429 set_except_vector(EXCCODE_IBE, handle_ibe); 2430 set_except_vector(EXCCODE_DBE, handle_dbe); 2431 2432 set_except_vector(EXCCODE_SYS, handle_sys); 2433 set_except_vector(EXCCODE_BP, handle_bp); 2434 2435 if (rdhwr_noopt) 2436 set_except_vector(EXCCODE_RI, handle_ri); 2437 else { 2438 if (cpu_has_vtag_icache) 2439 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 2440 else if (current_cpu_type() == CPU_LOONGSON64) 2441 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 2442 else 2443 set_except_vector(EXCCODE_RI, handle_ri_rdhwr); 2444 } 2445 2446 set_except_vector(EXCCODE_CPU, handle_cpu); 2447 set_except_vector(EXCCODE_OV, handle_ov); 2448 set_except_vector(EXCCODE_TR, handle_tr); 2449 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe); 2450 2451 if (board_nmi_handler_setup) 2452 board_nmi_handler_setup(); 2453 2454 if (cpu_has_fpu && !cpu_has_nofpuex) 2455 set_except_vector(EXCCODE_FPE, handle_fpe); 2456 2457 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); 2458 2459 if (cpu_has_rixiex) { 2460 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0); 2461 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0); 2462 } 2463 2464 set_except_vector(EXCCODE_MSADIS, handle_msa); 2465 set_except_vector(EXCCODE_MDMX, handle_mdmx); 2466 2467 if (cpu_has_mcheck) 2468 set_except_vector(EXCCODE_MCHECK, handle_mcheck); 2469 2470 if (cpu_has_mipsmt) 2471 set_except_vector(EXCCODE_THREAD, handle_mt); 2472 2473 set_except_vector(EXCCODE_DSPDIS, handle_dsp); 2474 2475 if (board_cache_error_setup) 2476 board_cache_error_setup(); 2477 2478 if (cpu_has_vce) 2479 /* Special exception: R4[04]00 uses also the divec space. */ 2480 set_handler(0x180, &except_vec3_r4000, 0x100); 2481 else if (cpu_has_4kex) 2482 set_handler(0x180, &except_vec3_generic, 0x80); 2483 else 2484 set_handler(0x080, &except_vec3_generic, 0x80); 2485 2486 local_flush_icache_range(ebase, ebase + vec_size); 2487 2488 sort_extable(__start___dbe_table, __stop___dbe_table); 2489 2490 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 2491 } 2492 2493 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, 2494 void *v) 2495 { 2496 switch (cmd) { 2497 case CPU_PM_ENTER_FAILED: 2498 case CPU_PM_EXIT: 2499 configure_status(); 2500 configure_hwrena(); 2501 configure_exception_vector(); 2502 2503 /* Restore register with CPU number for TLB handlers */ 2504 TLBMISS_HANDLER_RESTORE(); 2505 2506 break; 2507 } 2508 2509 return NOTIFY_OK; 2510 } 2511 2512 static struct notifier_block trap_pm_notifier_block = { 2513 .notifier_call = trap_pm_notifier, 2514 }; 2515 2516 static int __init trap_pm_init(void) 2517 { 2518 return cpu_pm_register_notifier(&trap_pm_notifier_block); 2519 } 2520 arch_initcall(trap_pm_init); 2521