xref: /openbmc/linux/arch/mips/kernel/traps.c (revision 3d3337de)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7  * Copyright (C) 1995, 1996 Paul M. Antoine
8  * Copyright (C) 1998 Ulf Carlsson
9  * Copyright (C) 1999 Silicon Graphics, Inc.
10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11  * Copyright (C) 2002, 2003, 2004, 2005, 2007  Maciej W. Rozycki
12  * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc.  All rights reserved.
13  * Copyright (C) 2014, Imagination Technologies Ltd.
14  */
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mm.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/spinlock.h>
28 #include <linux/kallsyms.h>
29 #include <linux/bootmem.h>
30 #include <linux/interrupt.h>
31 #include <linux/ptrace.h>
32 #include <linux/kgdb.h>
33 #include <linux/kdebug.h>
34 #include <linux/kprobes.h>
35 #include <linux/notifier.h>
36 #include <linux/kdb.h>
37 #include <linux/irq.h>
38 #include <linux/perf_event.h>
39 
40 #include <asm/bootinfo.h>
41 #include <asm/branch.h>
42 #include <asm/break.h>
43 #include <asm/cop2.h>
44 #include <asm/cpu.h>
45 #include <asm/cpu-type.h>
46 #include <asm/dsp.h>
47 #include <asm/fpu.h>
48 #include <asm/fpu_emulator.h>
49 #include <asm/idle.h>
50 #include <asm/mips-r2-to-r6-emul.h>
51 #include <asm/mipsregs.h>
52 #include <asm/mipsmtregs.h>
53 #include <asm/module.h>
54 #include <asm/msa.h>
55 #include <asm/pgtable.h>
56 #include <asm/ptrace.h>
57 #include <asm/sections.h>
58 #include <asm/tlbdebug.h>
59 #include <asm/traps.h>
60 #include <asm/uaccess.h>
61 #include <asm/watch.h>
62 #include <asm/mmu_context.h>
63 #include <asm/types.h>
64 #include <asm/stacktrace.h>
65 #include <asm/uasm.h>
66 
67 extern void check_wait(void);
68 extern asmlinkage void rollback_handle_int(void);
69 extern asmlinkage void handle_int(void);
70 extern u32 handle_tlbl[];
71 extern u32 handle_tlbs[];
72 extern u32 handle_tlbm[];
73 extern asmlinkage void handle_adel(void);
74 extern asmlinkage void handle_ades(void);
75 extern asmlinkage void handle_ibe(void);
76 extern asmlinkage void handle_dbe(void);
77 extern asmlinkage void handle_sys(void);
78 extern asmlinkage void handle_bp(void);
79 extern asmlinkage void handle_ri(void);
80 extern asmlinkage void handle_ri_rdhwr_vivt(void);
81 extern asmlinkage void handle_ri_rdhwr(void);
82 extern asmlinkage void handle_cpu(void);
83 extern asmlinkage void handle_ov(void);
84 extern asmlinkage void handle_tr(void);
85 extern asmlinkage void handle_msa_fpe(void);
86 extern asmlinkage void handle_fpe(void);
87 extern asmlinkage void handle_ftlb(void);
88 extern asmlinkage void handle_msa(void);
89 extern asmlinkage void handle_mdmx(void);
90 extern asmlinkage void handle_watch(void);
91 extern asmlinkage void handle_mt(void);
92 extern asmlinkage void handle_dsp(void);
93 extern asmlinkage void handle_mcheck(void);
94 extern asmlinkage void handle_reserved(void);
95 extern void tlb_do_page_fault_0(void);
96 
97 void (*board_be_init)(void);
98 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
99 void (*board_nmi_handler_setup)(void);
100 void (*board_ejtag_handler_setup)(void);
101 void (*board_bind_eic_interrupt)(int irq, int regset);
102 void (*board_ebase_setup)(void);
103 void(*board_cache_error_setup)(void);
104 
105 static void show_raw_backtrace(unsigned long reg29)
106 {
107 	unsigned long *sp = (unsigned long *)(reg29 & ~3);
108 	unsigned long addr;
109 
110 	printk("Call Trace:");
111 #ifdef CONFIG_KALLSYMS
112 	printk("\n");
113 #endif
114 	while (!kstack_end(sp)) {
115 		unsigned long __user *p =
116 			(unsigned long __user *)(unsigned long)sp++;
117 		if (__get_user(addr, p)) {
118 			printk(" (Bad stack address)");
119 			break;
120 		}
121 		if (__kernel_text_address(addr))
122 			print_ip_sym(addr);
123 	}
124 	printk("\n");
125 }
126 
127 #ifdef CONFIG_KALLSYMS
128 int raw_show_trace;
129 static int __init set_raw_show_trace(char *str)
130 {
131 	raw_show_trace = 1;
132 	return 1;
133 }
134 __setup("raw_show_trace", set_raw_show_trace);
135 #endif
136 
137 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
138 {
139 	unsigned long sp = regs->regs[29];
140 	unsigned long ra = regs->regs[31];
141 	unsigned long pc = regs->cp0_epc;
142 
143 	if (!task)
144 		task = current;
145 
146 	if (raw_show_trace || !__kernel_text_address(pc)) {
147 		show_raw_backtrace(sp);
148 		return;
149 	}
150 	printk("Call Trace:\n");
151 	do {
152 		print_ip_sym(pc);
153 		pc = unwind_stack(task, &sp, pc, &ra);
154 	} while (pc);
155 	printk("\n");
156 }
157 
158 /*
159  * This routine abuses get_user()/put_user() to reference pointers
160  * with at least a bit of error checking ...
161  */
162 static void show_stacktrace(struct task_struct *task,
163 	const struct pt_regs *regs)
164 {
165 	const int field = 2 * sizeof(unsigned long);
166 	long stackdata;
167 	int i;
168 	unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
169 
170 	printk("Stack :");
171 	i = 0;
172 	while ((unsigned long) sp & (PAGE_SIZE - 1)) {
173 		if (i && ((i % (64 / field)) == 0))
174 			printk("\n	 ");
175 		if (i > 39) {
176 			printk(" ...");
177 			break;
178 		}
179 
180 		if (__get_user(stackdata, sp++)) {
181 			printk(" (Bad stack address)");
182 			break;
183 		}
184 
185 		printk(" %0*lx", field, stackdata);
186 		i++;
187 	}
188 	printk("\n");
189 	show_backtrace(task, regs);
190 }
191 
192 void show_stack(struct task_struct *task, unsigned long *sp)
193 {
194 	struct pt_regs regs;
195 	if (sp) {
196 		regs.regs[29] = (unsigned long)sp;
197 		regs.regs[31] = 0;
198 		regs.cp0_epc = 0;
199 	} else {
200 		if (task && task != current) {
201 			regs.regs[29] = task->thread.reg29;
202 			regs.regs[31] = 0;
203 			regs.cp0_epc = task->thread.reg31;
204 #ifdef CONFIG_KGDB_KDB
205 		} else if (atomic_read(&kgdb_active) != -1 &&
206 			   kdb_current_regs) {
207 			memcpy(&regs, kdb_current_regs, sizeof(regs));
208 #endif /* CONFIG_KGDB_KDB */
209 		} else {
210 			prepare_frametrace(&regs);
211 		}
212 	}
213 	show_stacktrace(task, &regs);
214 }
215 
216 static void show_code(unsigned int __user *pc)
217 {
218 	long i;
219 	unsigned short __user *pc16 = NULL;
220 
221 	printk("\nCode:");
222 
223 	if ((unsigned long)pc & 1)
224 		pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
225 	for(i = -3 ; i < 6 ; i++) {
226 		unsigned int insn;
227 		if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
228 			printk(" (Bad address in epc)\n");
229 			break;
230 		}
231 		printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
232 	}
233 }
234 
235 static void __show_regs(const struct pt_regs *regs)
236 {
237 	const int field = 2 * sizeof(unsigned long);
238 	unsigned int cause = regs->cp0_cause;
239 	int i;
240 
241 	show_regs_print_info(KERN_DEFAULT);
242 
243 	/*
244 	 * Saved main processor registers
245 	 */
246 	for (i = 0; i < 32; ) {
247 		if ((i % 4) == 0)
248 			printk("$%2d   :", i);
249 		if (i == 0)
250 			printk(" %0*lx", field, 0UL);
251 		else if (i == 26 || i == 27)
252 			printk(" %*s", field, "");
253 		else
254 			printk(" %0*lx", field, regs->regs[i]);
255 
256 		i++;
257 		if ((i % 4) == 0)
258 			printk("\n");
259 	}
260 
261 #ifdef CONFIG_CPU_HAS_SMARTMIPS
262 	printk("Acx    : %0*lx\n", field, regs->acx);
263 #endif
264 	printk("Hi    : %0*lx\n", field, regs->hi);
265 	printk("Lo    : %0*lx\n", field, regs->lo);
266 
267 	/*
268 	 * Saved cp0 registers
269 	 */
270 	printk("epc   : %0*lx %pS\n", field, regs->cp0_epc,
271 	       (void *) regs->cp0_epc);
272 	printk("    %s\n", print_tainted());
273 	printk("ra    : %0*lx %pS\n", field, regs->regs[31],
274 	       (void *) regs->regs[31]);
275 
276 	printk("Status: %08x	", (uint32_t) regs->cp0_status);
277 
278 	if (cpu_has_3kex) {
279 		if (regs->cp0_status & ST0_KUO)
280 			printk("KUo ");
281 		if (regs->cp0_status & ST0_IEO)
282 			printk("IEo ");
283 		if (regs->cp0_status & ST0_KUP)
284 			printk("KUp ");
285 		if (regs->cp0_status & ST0_IEP)
286 			printk("IEp ");
287 		if (regs->cp0_status & ST0_KUC)
288 			printk("KUc ");
289 		if (regs->cp0_status & ST0_IEC)
290 			printk("IEc ");
291 	} else if (cpu_has_4kex) {
292 		if (regs->cp0_status & ST0_KX)
293 			printk("KX ");
294 		if (regs->cp0_status & ST0_SX)
295 			printk("SX ");
296 		if (regs->cp0_status & ST0_UX)
297 			printk("UX ");
298 		switch (regs->cp0_status & ST0_KSU) {
299 		case KSU_USER:
300 			printk("USER ");
301 			break;
302 		case KSU_SUPERVISOR:
303 			printk("SUPERVISOR ");
304 			break;
305 		case KSU_KERNEL:
306 			printk("KERNEL ");
307 			break;
308 		default:
309 			printk("BAD_MODE ");
310 			break;
311 		}
312 		if (regs->cp0_status & ST0_ERL)
313 			printk("ERL ");
314 		if (regs->cp0_status & ST0_EXL)
315 			printk("EXL ");
316 		if (regs->cp0_status & ST0_IE)
317 			printk("IE ");
318 	}
319 	printk("\n");
320 
321 	printk("Cause : %08x\n", cause);
322 
323 	cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
324 	if (1 <= cause && cause <= 5)
325 		printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
326 
327 	printk("PrId  : %08x (%s)\n", read_c0_prid(),
328 	       cpu_name_string());
329 }
330 
331 /*
332  * FIXME: really the generic show_regs should take a const pointer argument.
333  */
334 void show_regs(struct pt_regs *regs)
335 {
336 	__show_regs((struct pt_regs *)regs);
337 }
338 
339 void show_registers(struct pt_regs *regs)
340 {
341 	const int field = 2 * sizeof(unsigned long);
342 	mm_segment_t old_fs = get_fs();
343 
344 	__show_regs(regs);
345 	print_modules();
346 	printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
347 	       current->comm, current->pid, current_thread_info(), current,
348 	      field, current_thread_info()->tp_value);
349 	if (cpu_has_userlocal) {
350 		unsigned long tls;
351 
352 		tls = read_c0_userlocal();
353 		if (tls != current_thread_info()->tp_value)
354 			printk("*HwTLS: %0*lx\n", field, tls);
355 	}
356 
357 	if (!user_mode(regs))
358 		/* Necessary for getting the correct stack content */
359 		set_fs(KERNEL_DS);
360 	show_stacktrace(current, regs);
361 	show_code((unsigned int __user *) regs->cp0_epc);
362 	printk("\n");
363 	set_fs(old_fs);
364 }
365 
366 static int regs_to_trapnr(struct pt_regs *regs)
367 {
368 	return (regs->cp0_cause >> 2) & 0x1f;
369 }
370 
371 static DEFINE_RAW_SPINLOCK(die_lock);
372 
373 void __noreturn die(const char *str, struct pt_regs *regs)
374 {
375 	static int die_counter;
376 	int sig = SIGSEGV;
377 
378 	oops_enter();
379 
380 	if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs),
381 		       SIGSEGV) == NOTIFY_STOP)
382 		sig = 0;
383 
384 	console_verbose();
385 	raw_spin_lock_irq(&die_lock);
386 	bust_spinlocks(1);
387 
388 	printk("%s[#%d]:\n", str, ++die_counter);
389 	show_registers(regs);
390 	add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
391 	raw_spin_unlock_irq(&die_lock);
392 
393 	oops_exit();
394 
395 	if (in_interrupt())
396 		panic("Fatal exception in interrupt");
397 
398 	if (panic_on_oops) {
399 		printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
400 		ssleep(5);
401 		panic("Fatal exception");
402 	}
403 
404 	if (regs && kexec_should_crash(current))
405 		crash_kexec(regs);
406 
407 	do_exit(sig);
408 }
409 
410 extern struct exception_table_entry __start___dbe_table[];
411 extern struct exception_table_entry __stop___dbe_table[];
412 
413 __asm__(
414 "	.section	__dbe_table, \"a\"\n"
415 "	.previous			\n");
416 
417 /* Given an address, look for it in the exception tables. */
418 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
419 {
420 	const struct exception_table_entry *e;
421 
422 	e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
423 	if (!e)
424 		e = search_module_dbetables(addr);
425 	return e;
426 }
427 
428 asmlinkage void do_be(struct pt_regs *regs)
429 {
430 	const int field = 2 * sizeof(unsigned long);
431 	const struct exception_table_entry *fixup = NULL;
432 	int data = regs->cp0_cause & 4;
433 	int action = MIPS_BE_FATAL;
434 	enum ctx_state prev_state;
435 
436 	prev_state = exception_enter();
437 	/* XXX For now.	 Fixme, this searches the wrong table ...  */
438 	if (data && !user_mode(regs))
439 		fixup = search_dbe_tables(exception_epc(regs));
440 
441 	if (fixup)
442 		action = MIPS_BE_FIXUP;
443 
444 	if (board_be_handler)
445 		action = board_be_handler(regs, fixup != NULL);
446 
447 	switch (action) {
448 	case MIPS_BE_DISCARD:
449 		goto out;
450 	case MIPS_BE_FIXUP:
451 		if (fixup) {
452 			regs->cp0_epc = fixup->nextinsn;
453 			goto out;
454 		}
455 		break;
456 	default:
457 		break;
458 	}
459 
460 	/*
461 	 * Assume it would be too dangerous to continue ...
462 	 */
463 	printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
464 	       data ? "Data" : "Instruction",
465 	       field, regs->cp0_epc, field, regs->regs[31]);
466 	if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs),
467 		       SIGBUS) == NOTIFY_STOP)
468 		goto out;
469 
470 	die_if_kernel("Oops", regs);
471 	force_sig(SIGBUS, current);
472 
473 out:
474 	exception_exit(prev_state);
475 }
476 
477 /*
478  * ll/sc, rdhwr, sync emulation
479  */
480 
481 #define OPCODE 0xfc000000
482 #define BASE   0x03e00000
483 #define RT     0x001f0000
484 #define OFFSET 0x0000ffff
485 #define LL     0xc0000000
486 #define SC     0xe0000000
487 #define SPEC0  0x00000000
488 #define SPEC3  0x7c000000
489 #define RD     0x0000f800
490 #define FUNC   0x0000003f
491 #define SYNC   0x0000000f
492 #define RDHWR  0x0000003b
493 
494 /*  microMIPS definitions   */
495 #define MM_POOL32A_FUNC 0xfc00ffff
496 #define MM_RDHWR        0x00006b3c
497 #define MM_RS           0x001f0000
498 #define MM_RT           0x03e00000
499 
500 /*
501  * The ll_bit is cleared by r*_switch.S
502  */
503 
504 unsigned int ll_bit;
505 struct task_struct *ll_task;
506 
507 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
508 {
509 	unsigned long value, __user *vaddr;
510 	long offset;
511 
512 	/*
513 	 * analyse the ll instruction that just caused a ri exception
514 	 * and put the referenced address to addr.
515 	 */
516 
517 	/* sign extend offset */
518 	offset = opcode & OFFSET;
519 	offset <<= 16;
520 	offset >>= 16;
521 
522 	vaddr = (unsigned long __user *)
523 		((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
524 
525 	if ((unsigned long)vaddr & 3)
526 		return SIGBUS;
527 	if (get_user(value, vaddr))
528 		return SIGSEGV;
529 
530 	preempt_disable();
531 
532 	if (ll_task == NULL || ll_task == current) {
533 		ll_bit = 1;
534 	} else {
535 		ll_bit = 0;
536 	}
537 	ll_task = current;
538 
539 	preempt_enable();
540 
541 	regs->regs[(opcode & RT) >> 16] = value;
542 
543 	return 0;
544 }
545 
546 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
547 {
548 	unsigned long __user *vaddr;
549 	unsigned long reg;
550 	long offset;
551 
552 	/*
553 	 * analyse the sc instruction that just caused a ri exception
554 	 * and put the referenced address to addr.
555 	 */
556 
557 	/* sign extend offset */
558 	offset = opcode & OFFSET;
559 	offset <<= 16;
560 	offset >>= 16;
561 
562 	vaddr = (unsigned long __user *)
563 		((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
564 	reg = (opcode & RT) >> 16;
565 
566 	if ((unsigned long)vaddr & 3)
567 		return SIGBUS;
568 
569 	preempt_disable();
570 
571 	if (ll_bit == 0 || ll_task != current) {
572 		regs->regs[reg] = 0;
573 		preempt_enable();
574 		return 0;
575 	}
576 
577 	preempt_enable();
578 
579 	if (put_user(regs->regs[reg], vaddr))
580 		return SIGSEGV;
581 
582 	regs->regs[reg] = 1;
583 
584 	return 0;
585 }
586 
587 /*
588  * ll uses the opcode of lwc0 and sc uses the opcode of swc0.  That is both
589  * opcodes are supposed to result in coprocessor unusable exceptions if
590  * executed on ll/sc-less processors.  That's the theory.  In practice a
591  * few processors such as NEC's VR4100 throw reserved instruction exceptions
592  * instead, so we're doing the emulation thing in both exception handlers.
593  */
594 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
595 {
596 	if ((opcode & OPCODE) == LL) {
597 		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
598 				1, regs, 0);
599 		return simulate_ll(regs, opcode);
600 	}
601 	if ((opcode & OPCODE) == SC) {
602 		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
603 				1, regs, 0);
604 		return simulate_sc(regs, opcode);
605 	}
606 
607 	return -1;			/* Must be something else ... */
608 }
609 
610 /*
611  * Simulate trapping 'rdhwr' instructions to provide user accessible
612  * registers not implemented in hardware.
613  */
614 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
615 {
616 	struct thread_info *ti = task_thread_info(current);
617 
618 	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
619 			1, regs, 0);
620 	switch (rd) {
621 	case 0:		/* CPU number */
622 		regs->regs[rt] = smp_processor_id();
623 		return 0;
624 	case 1:		/* SYNCI length */
625 		regs->regs[rt] = min(current_cpu_data.dcache.linesz,
626 				     current_cpu_data.icache.linesz);
627 		return 0;
628 	case 2:		/* Read count register */
629 		regs->regs[rt] = read_c0_count();
630 		return 0;
631 	case 3:		/* Count register resolution */
632 		switch (current_cpu_type()) {
633 		case CPU_20KC:
634 		case CPU_25KF:
635 			regs->regs[rt] = 1;
636 			break;
637 		default:
638 			regs->regs[rt] = 2;
639 		}
640 		return 0;
641 	case 29:
642 		regs->regs[rt] = ti->tp_value;
643 		return 0;
644 	default:
645 		return -1;
646 	}
647 }
648 
649 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
650 {
651 	if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
652 		int rd = (opcode & RD) >> 11;
653 		int rt = (opcode & RT) >> 16;
654 
655 		simulate_rdhwr(regs, rd, rt);
656 		return 0;
657 	}
658 
659 	/* Not ours.  */
660 	return -1;
661 }
662 
663 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
664 {
665 	if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
666 		int rd = (opcode & MM_RS) >> 16;
667 		int rt = (opcode & MM_RT) >> 21;
668 		simulate_rdhwr(regs, rd, rt);
669 		return 0;
670 	}
671 
672 	/* Not ours.  */
673 	return -1;
674 }
675 
676 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
677 {
678 	if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
679 		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
680 				1, regs, 0);
681 		return 0;
682 	}
683 
684 	return -1;			/* Must be something else ... */
685 }
686 
687 asmlinkage void do_ov(struct pt_regs *regs)
688 {
689 	enum ctx_state prev_state;
690 	siginfo_t info;
691 
692 	prev_state = exception_enter();
693 	die_if_kernel("Integer overflow", regs);
694 
695 	info.si_code = FPE_INTOVF;
696 	info.si_signo = SIGFPE;
697 	info.si_errno = 0;
698 	info.si_addr = (void __user *) regs->cp0_epc;
699 	force_sig_info(SIGFPE, &info, current);
700 	exception_exit(prev_state);
701 }
702 
703 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
704 {
705 	struct siginfo si = { 0 };
706 
707 	switch (sig) {
708 	case 0:
709 		return 0;
710 
711 	case SIGFPE:
712 		si.si_addr = fault_addr;
713 		si.si_signo = sig;
714 		/*
715 		 * Inexact can happen together with Overflow or Underflow.
716 		 * Respect the mask to deliver the correct exception.
717 		 */
718 		fcr31 &= (fcr31 & FPU_CSR_ALL_E) <<
719 			 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E));
720 		if (fcr31 & FPU_CSR_INV_X)
721 			si.si_code = FPE_FLTINV;
722 		else if (fcr31 & FPU_CSR_DIV_X)
723 			si.si_code = FPE_FLTDIV;
724 		else if (fcr31 & FPU_CSR_OVF_X)
725 			si.si_code = FPE_FLTOVF;
726 		else if (fcr31 & FPU_CSR_UDF_X)
727 			si.si_code = FPE_FLTUND;
728 		else if (fcr31 & FPU_CSR_INE_X)
729 			si.si_code = FPE_FLTRES;
730 		else
731 			si.si_code = __SI_FAULT;
732 		force_sig_info(sig, &si, current);
733 		return 1;
734 
735 	case SIGBUS:
736 		si.si_addr = fault_addr;
737 		si.si_signo = sig;
738 		si.si_code = BUS_ADRERR;
739 		force_sig_info(sig, &si, current);
740 		return 1;
741 
742 	case SIGSEGV:
743 		si.si_addr = fault_addr;
744 		si.si_signo = sig;
745 		down_read(&current->mm->mmap_sem);
746 		if (find_vma(current->mm, (unsigned long)fault_addr))
747 			si.si_code = SEGV_ACCERR;
748 		else
749 			si.si_code = SEGV_MAPERR;
750 		up_read(&current->mm->mmap_sem);
751 		force_sig_info(sig, &si, current);
752 		return 1;
753 
754 	default:
755 		force_sig(sig, current);
756 		return 1;
757 	}
758 }
759 
760 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
761 		       unsigned long old_epc, unsigned long old_ra)
762 {
763 	union mips_instruction inst = { .word = opcode };
764 	void __user *fault_addr;
765 	unsigned long fcr31;
766 	int sig;
767 
768 	/* If it's obviously not an FP instruction, skip it */
769 	switch (inst.i_format.opcode) {
770 	case cop1_op:
771 	case cop1x_op:
772 	case lwc1_op:
773 	case ldc1_op:
774 	case swc1_op:
775 	case sdc1_op:
776 		break;
777 
778 	default:
779 		return -1;
780 	}
781 
782 	/*
783 	 * do_ri skipped over the instruction via compute_return_epc, undo
784 	 * that for the FPU emulator.
785 	 */
786 	regs->cp0_epc = old_epc;
787 	regs->regs[31] = old_ra;
788 
789 	/* Save the FP context to struct thread_struct */
790 	lose_fpu(1);
791 
792 	/* Run the emulator */
793 	sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
794 				       &fault_addr);
795 	fcr31 = current->thread.fpu.fcr31;
796 
797 	/*
798 	 * We can't allow the emulated instruction to leave any of
799 	 * the cause bits set in $fcr31.
800 	 */
801 	current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
802 
803 	/* Restore the hardware register state */
804 	own_fpu(1);
805 
806 	/* Send a signal if required.  */
807 	process_fpemu_return(sig, fault_addr, fcr31);
808 
809 	return 0;
810 }
811 
812 /*
813  * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
814  */
815 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
816 {
817 	enum ctx_state prev_state;
818 	void __user *fault_addr;
819 	int sig;
820 
821 	prev_state = exception_enter();
822 	if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs),
823 		       SIGFPE) == NOTIFY_STOP)
824 		goto out;
825 
826 	/* Clear FCSR.Cause before enabling interrupts */
827 	write_32bit_cp1_register(CP1_STATUS, fcr31 & ~FPU_CSR_ALL_X);
828 	local_irq_enable();
829 
830 	die_if_kernel("FP exception in kernel code", regs);
831 
832 	if (fcr31 & FPU_CSR_UNI_X) {
833 		/*
834 		 * Unimplemented operation exception.  If we've got the full
835 		 * software emulator on-board, let's use it...
836 		 *
837 		 * Force FPU to dump state into task/thread context.  We're
838 		 * moving a lot of data here for what is probably a single
839 		 * instruction, but the alternative is to pre-decode the FP
840 		 * register operands before invoking the emulator, which seems
841 		 * a bit extreme for what should be an infrequent event.
842 		 */
843 		/* Ensure 'resume' not overwrite saved fp context again. */
844 		lose_fpu(1);
845 
846 		/* Run the emulator */
847 		sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
848 					       &fault_addr);
849 		fcr31 = current->thread.fpu.fcr31;
850 
851 		/*
852 		 * We can't allow the emulated instruction to leave any of
853 		 * the cause bits set in $fcr31.
854 		 */
855 		current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
856 
857 		/* Restore the hardware register state */
858 		own_fpu(1);	/* Using the FPU again.	 */
859 	} else {
860 		sig = SIGFPE;
861 		fault_addr = (void __user *) regs->cp0_epc;
862 	}
863 
864 	/* Send a signal if required.  */
865 	process_fpemu_return(sig, fault_addr, fcr31);
866 
867 out:
868 	exception_exit(prev_state);
869 }
870 
871 void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
872 	const char *str)
873 {
874 	siginfo_t info;
875 	char b[40];
876 
877 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
878 	if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
879 		return;
880 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
881 
882 	if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs),
883 		       SIGTRAP) == NOTIFY_STOP)
884 		return;
885 
886 	/*
887 	 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
888 	 * insns, even for trap and break codes that indicate arithmetic
889 	 * failures.  Weird ...
890 	 * But should we continue the brokenness???  --macro
891 	 */
892 	switch (code) {
893 	case BRK_OVERFLOW:
894 	case BRK_DIVZERO:
895 		scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
896 		die_if_kernel(b, regs);
897 		if (code == BRK_DIVZERO)
898 			info.si_code = FPE_INTDIV;
899 		else
900 			info.si_code = FPE_INTOVF;
901 		info.si_signo = SIGFPE;
902 		info.si_errno = 0;
903 		info.si_addr = (void __user *) regs->cp0_epc;
904 		force_sig_info(SIGFPE, &info, current);
905 		break;
906 	case BRK_BUG:
907 		die_if_kernel("Kernel bug detected", regs);
908 		force_sig(SIGTRAP, current);
909 		break;
910 	case BRK_MEMU:
911 		/*
912 		 * This breakpoint code is used by the FPU emulator to retake
913 		 * control of the CPU after executing the instruction from the
914 		 * delay slot of an emulated branch.
915 		 *
916 		 * Terminate if exception was recognized as a delay slot return
917 		 * otherwise handle as normal.
918 		 */
919 		if (do_dsemulret(regs))
920 			return;
921 
922 		die_if_kernel("Math emu break/trap", regs);
923 		force_sig(SIGTRAP, current);
924 		break;
925 	default:
926 		scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
927 		die_if_kernel(b, regs);
928 		force_sig(SIGTRAP, current);
929 	}
930 }
931 
932 asmlinkage void do_bp(struct pt_regs *regs)
933 {
934 	unsigned long epc = msk_isa16_mode(exception_epc(regs));
935 	unsigned int opcode, bcode;
936 	enum ctx_state prev_state;
937 	mm_segment_t seg;
938 
939 	seg = get_fs();
940 	if (!user_mode(regs))
941 		set_fs(KERNEL_DS);
942 
943 	prev_state = exception_enter();
944 	if (get_isa16_mode(regs->cp0_epc)) {
945 		u16 instr[2];
946 
947 		if (__get_user(instr[0], (u16 __user *)epc))
948 			goto out_sigsegv;
949 
950 		if (!cpu_has_mmips) {
951 			/* MIPS16e mode */
952 			bcode = (instr[0] >> 5) & 0x3f;
953 		} else if (mm_insn_16bit(instr[0])) {
954 			/* 16-bit microMIPS BREAK */
955 			bcode = instr[0] & 0xf;
956 		} else {
957 			/* 32-bit microMIPS BREAK */
958 			if (__get_user(instr[1], (u16 __user *)(epc + 2)))
959 				goto out_sigsegv;
960 			opcode = (instr[0] << 16) | instr[1];
961 			bcode = (opcode >> 6) & ((1 << 20) - 1);
962 		}
963 	} else {
964 		if (__get_user(opcode, (unsigned int __user *)epc))
965 			goto out_sigsegv;
966 		bcode = (opcode >> 6) & ((1 << 20) - 1);
967 	}
968 
969 	/*
970 	 * There is the ancient bug in the MIPS assemblers that the break
971 	 * code starts left to bit 16 instead to bit 6 in the opcode.
972 	 * Gas is bug-compatible, but not always, grrr...
973 	 * We handle both cases with a simple heuristics.  --macro
974 	 */
975 	if (bcode >= (1 << 10))
976 		bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
977 
978 	/*
979 	 * notify the kprobe handlers, if instruction is likely to
980 	 * pertain to them.
981 	 */
982 	switch (bcode) {
983 	case BRK_KPROBE_BP:
984 		if (notify_die(DIE_BREAK, "debug", regs, bcode,
985 			       regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
986 			goto out;
987 		else
988 			break;
989 	case BRK_KPROBE_SSTEPBP:
990 		if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
991 			       regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
992 			goto out;
993 		else
994 			break;
995 	default:
996 		break;
997 	}
998 
999 	do_trap_or_bp(regs, bcode, "Break");
1000 
1001 out:
1002 	set_fs(seg);
1003 	exception_exit(prev_state);
1004 	return;
1005 
1006 out_sigsegv:
1007 	force_sig(SIGSEGV, current);
1008 	goto out;
1009 }
1010 
1011 asmlinkage void do_tr(struct pt_regs *regs)
1012 {
1013 	u32 opcode, tcode = 0;
1014 	enum ctx_state prev_state;
1015 	u16 instr[2];
1016 	mm_segment_t seg;
1017 	unsigned long epc = msk_isa16_mode(exception_epc(regs));
1018 
1019 	seg = get_fs();
1020 	if (!user_mode(regs))
1021 		set_fs(get_ds());
1022 
1023 	prev_state = exception_enter();
1024 	if (get_isa16_mode(regs->cp0_epc)) {
1025 		if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1026 		    __get_user(instr[1], (u16 __user *)(epc + 2)))
1027 			goto out_sigsegv;
1028 		opcode = (instr[0] << 16) | instr[1];
1029 		/* Immediate versions don't provide a code.  */
1030 		if (!(opcode & OPCODE))
1031 			tcode = (opcode >> 12) & ((1 << 4) - 1);
1032 	} else {
1033 		if (__get_user(opcode, (u32 __user *)epc))
1034 			goto out_sigsegv;
1035 		/* Immediate versions don't provide a code.  */
1036 		if (!(opcode & OPCODE))
1037 			tcode = (opcode >> 6) & ((1 << 10) - 1);
1038 	}
1039 
1040 	do_trap_or_bp(regs, tcode, "Trap");
1041 
1042 out:
1043 	set_fs(seg);
1044 	exception_exit(prev_state);
1045 	return;
1046 
1047 out_sigsegv:
1048 	force_sig(SIGSEGV, current);
1049 	goto out;
1050 }
1051 
1052 asmlinkage void do_ri(struct pt_regs *regs)
1053 {
1054 	unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1055 	unsigned long old_epc = regs->cp0_epc;
1056 	unsigned long old31 = regs->regs[31];
1057 	enum ctx_state prev_state;
1058 	unsigned int opcode = 0;
1059 	int status = -1;
1060 
1061 	/*
1062 	 * Avoid any kernel code. Just emulate the R2 instruction
1063 	 * as quickly as possible.
1064 	 */
1065 	if (mipsr2_emulation && cpu_has_mips_r6 &&
1066 	    likely(user_mode(regs)) &&
1067 	    likely(get_user(opcode, epc) >= 0)) {
1068 		unsigned long fcr31 = 0;
1069 
1070 		status = mipsr2_decoder(regs, opcode, &fcr31);
1071 		switch (status) {
1072 		case 0:
1073 		case SIGEMT:
1074 			task_thread_info(current)->r2_emul_return = 1;
1075 			return;
1076 		case SIGILL:
1077 			goto no_r2_instr;
1078 		default:
1079 			process_fpemu_return(status,
1080 					     &current->thread.cp0_baduaddr,
1081 					     fcr31);
1082 			task_thread_info(current)->r2_emul_return = 1;
1083 			return;
1084 		}
1085 	}
1086 
1087 no_r2_instr:
1088 
1089 	prev_state = exception_enter();
1090 
1091 	if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs),
1092 		       SIGILL) == NOTIFY_STOP)
1093 		goto out;
1094 
1095 	die_if_kernel("Reserved instruction in kernel code", regs);
1096 
1097 	if (unlikely(compute_return_epc(regs) < 0))
1098 		goto out;
1099 
1100 	if (get_isa16_mode(regs->cp0_epc)) {
1101 		unsigned short mmop[2] = { 0 };
1102 
1103 		if (unlikely(get_user(mmop[0], epc) < 0))
1104 			status = SIGSEGV;
1105 		if (unlikely(get_user(mmop[1], epc) < 0))
1106 			status = SIGSEGV;
1107 		opcode = (mmop[0] << 16) | mmop[1];
1108 
1109 		if (status < 0)
1110 			status = simulate_rdhwr_mm(regs, opcode);
1111 	} else {
1112 		if (unlikely(get_user(opcode, epc) < 0))
1113 			status = SIGSEGV;
1114 
1115 		if (!cpu_has_llsc && status < 0)
1116 			status = simulate_llsc(regs, opcode);
1117 
1118 		if (status < 0)
1119 			status = simulate_rdhwr_normal(regs, opcode);
1120 
1121 		if (status < 0)
1122 			status = simulate_sync(regs, opcode);
1123 
1124 		if (status < 0)
1125 			status = simulate_fp(regs, opcode, old_epc, old31);
1126 	}
1127 
1128 	if (status < 0)
1129 		status = SIGILL;
1130 
1131 	if (unlikely(status > 0)) {
1132 		regs->cp0_epc = old_epc;		/* Undo skip-over.  */
1133 		regs->regs[31] = old31;
1134 		force_sig(status, current);
1135 	}
1136 
1137 out:
1138 	exception_exit(prev_state);
1139 }
1140 
1141 /*
1142  * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1143  * emulated more than some threshold number of instructions, force migration to
1144  * a "CPU" that has FP support.
1145  */
1146 static void mt_ase_fp_affinity(void)
1147 {
1148 #ifdef CONFIG_MIPS_MT_FPAFF
1149 	if (mt_fpemul_threshold > 0 &&
1150 	     ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1151 		/*
1152 		 * If there's no FPU present, or if the application has already
1153 		 * restricted the allowed set to exclude any CPUs with FPUs,
1154 		 * we'll skip the procedure.
1155 		 */
1156 		if (cpumask_intersects(&current->cpus_allowed, &mt_fpu_cpumask)) {
1157 			cpumask_t tmask;
1158 
1159 			current->thread.user_cpus_allowed
1160 				= current->cpus_allowed;
1161 			cpumask_and(&tmask, &current->cpus_allowed,
1162 				    &mt_fpu_cpumask);
1163 			set_cpus_allowed_ptr(current, &tmask);
1164 			set_thread_flag(TIF_FPUBOUND);
1165 		}
1166 	}
1167 #endif /* CONFIG_MIPS_MT_FPAFF */
1168 }
1169 
1170 /*
1171  * No lock; only written during early bootup by CPU 0.
1172  */
1173 static RAW_NOTIFIER_HEAD(cu2_chain);
1174 
1175 int __ref register_cu2_notifier(struct notifier_block *nb)
1176 {
1177 	return raw_notifier_chain_register(&cu2_chain, nb);
1178 }
1179 
1180 int cu2_notifier_call_chain(unsigned long val, void *v)
1181 {
1182 	return raw_notifier_call_chain(&cu2_chain, val, v);
1183 }
1184 
1185 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1186 	void *data)
1187 {
1188 	struct pt_regs *regs = data;
1189 
1190 	die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1191 			      "instruction", regs);
1192 	force_sig(SIGILL, current);
1193 
1194 	return NOTIFY_OK;
1195 }
1196 
1197 static int wait_on_fp_mode_switch(atomic_t *p)
1198 {
1199 	/*
1200 	 * The FP mode for this task is currently being switched. That may
1201 	 * involve modifications to the format of this tasks FP context which
1202 	 * make it unsafe to proceed with execution for the moment. Instead,
1203 	 * schedule some other task.
1204 	 */
1205 	schedule();
1206 	return 0;
1207 }
1208 
1209 static int enable_restore_fp_context(int msa)
1210 {
1211 	int err, was_fpu_owner, prior_msa;
1212 
1213 	/*
1214 	 * If an FP mode switch is currently underway, wait for it to
1215 	 * complete before proceeding.
1216 	 */
1217 	wait_on_atomic_t(&current->mm->context.fp_mode_switching,
1218 			 wait_on_fp_mode_switch, TASK_KILLABLE);
1219 
1220 	if (!used_math()) {
1221 		/* First time FP context user. */
1222 		preempt_disable();
1223 		err = init_fpu();
1224 		if (msa && !err) {
1225 			enable_msa();
1226 			_init_msa_upper();
1227 			set_thread_flag(TIF_USEDMSA);
1228 			set_thread_flag(TIF_MSA_CTX_LIVE);
1229 		}
1230 		preempt_enable();
1231 		if (!err)
1232 			set_used_math();
1233 		return err;
1234 	}
1235 
1236 	/*
1237 	 * This task has formerly used the FP context.
1238 	 *
1239 	 * If this thread has no live MSA vector context then we can simply
1240 	 * restore the scalar FP context. If it has live MSA vector context
1241 	 * (that is, it has or may have used MSA since last performing a
1242 	 * function call) then we'll need to restore the vector context. This
1243 	 * applies even if we're currently only executing a scalar FP
1244 	 * instruction. This is because if we were to later execute an MSA
1245 	 * instruction then we'd either have to:
1246 	 *
1247 	 *  - Restore the vector context & clobber any registers modified by
1248 	 *    scalar FP instructions between now & then.
1249 	 *
1250 	 * or
1251 	 *
1252 	 *  - Not restore the vector context & lose the most significant bits
1253 	 *    of all vector registers.
1254 	 *
1255 	 * Neither of those options is acceptable. We cannot restore the least
1256 	 * significant bits of the registers now & only restore the most
1257 	 * significant bits later because the most significant bits of any
1258 	 * vector registers whose aliased FP register is modified now will have
1259 	 * been zeroed. We'd have no way to know that when restoring the vector
1260 	 * context & thus may load an outdated value for the most significant
1261 	 * bits of a vector register.
1262 	 */
1263 	if (!msa && !thread_msa_context_live())
1264 		return own_fpu(1);
1265 
1266 	/*
1267 	 * This task is using or has previously used MSA. Thus we require
1268 	 * that Status.FR == 1.
1269 	 */
1270 	preempt_disable();
1271 	was_fpu_owner = is_fpu_owner();
1272 	err = own_fpu_inatomic(0);
1273 	if (err)
1274 		goto out;
1275 
1276 	enable_msa();
1277 	write_msa_csr(current->thread.fpu.msacsr);
1278 	set_thread_flag(TIF_USEDMSA);
1279 
1280 	/*
1281 	 * If this is the first time that the task is using MSA and it has
1282 	 * previously used scalar FP in this time slice then we already nave
1283 	 * FP context which we shouldn't clobber. We do however need to clear
1284 	 * the upper 64b of each vector register so that this task has no
1285 	 * opportunity to see data left behind by another.
1286 	 */
1287 	prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1288 	if (!prior_msa && was_fpu_owner) {
1289 		_init_msa_upper();
1290 
1291 		goto out;
1292 	}
1293 
1294 	if (!prior_msa) {
1295 		/*
1296 		 * Restore the least significant 64b of each vector register
1297 		 * from the existing scalar FP context.
1298 		 */
1299 		_restore_fp(current);
1300 
1301 		/*
1302 		 * The task has not formerly used MSA, so clear the upper 64b
1303 		 * of each vector register such that it cannot see data left
1304 		 * behind by another task.
1305 		 */
1306 		_init_msa_upper();
1307 	} else {
1308 		/* We need to restore the vector context. */
1309 		restore_msa(current);
1310 
1311 		/* Restore the scalar FP control & status register */
1312 		if (!was_fpu_owner)
1313 			write_32bit_cp1_register(CP1_STATUS,
1314 						 current->thread.fpu.fcr31);
1315 	}
1316 
1317 out:
1318 	preempt_enable();
1319 
1320 	return 0;
1321 }
1322 
1323 asmlinkage void do_cpu(struct pt_regs *regs)
1324 {
1325 	enum ctx_state prev_state;
1326 	unsigned int __user *epc;
1327 	unsigned long old_epc, old31;
1328 	void __user *fault_addr;
1329 	unsigned int opcode;
1330 	unsigned long fcr31;
1331 	unsigned int cpid;
1332 	int status, err;
1333 	unsigned long __maybe_unused flags;
1334 	int sig;
1335 
1336 	prev_state = exception_enter();
1337 	cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1338 
1339 	if (cpid != 2)
1340 		die_if_kernel("do_cpu invoked from kernel context!", regs);
1341 
1342 	switch (cpid) {
1343 	case 0:
1344 		epc = (unsigned int __user *)exception_epc(regs);
1345 		old_epc = regs->cp0_epc;
1346 		old31 = regs->regs[31];
1347 		opcode = 0;
1348 		status = -1;
1349 
1350 		if (unlikely(compute_return_epc(regs) < 0))
1351 			break;
1352 
1353 		if (get_isa16_mode(regs->cp0_epc)) {
1354 			unsigned short mmop[2] = { 0 };
1355 
1356 			if (unlikely(get_user(mmop[0], epc) < 0))
1357 				status = SIGSEGV;
1358 			if (unlikely(get_user(mmop[1], epc) < 0))
1359 				status = SIGSEGV;
1360 			opcode = (mmop[0] << 16) | mmop[1];
1361 
1362 			if (status < 0)
1363 				status = simulate_rdhwr_mm(regs, opcode);
1364 		} else {
1365 			if (unlikely(get_user(opcode, epc) < 0))
1366 				status = SIGSEGV;
1367 
1368 			if (!cpu_has_llsc && status < 0)
1369 				status = simulate_llsc(regs, opcode);
1370 
1371 			if (status < 0)
1372 				status = simulate_rdhwr_normal(regs, opcode);
1373 		}
1374 
1375 		if (status < 0)
1376 			status = SIGILL;
1377 
1378 		if (unlikely(status > 0)) {
1379 			regs->cp0_epc = old_epc;	/* Undo skip-over.  */
1380 			regs->regs[31] = old31;
1381 			force_sig(status, current);
1382 		}
1383 
1384 		break;
1385 
1386 	case 3:
1387 		/*
1388 		 * The COP3 opcode space and consequently the CP0.Status.CU3
1389 		 * bit and the CP0.Cause.CE=3 encoding have been removed as
1390 		 * of the MIPS III ISA.  From the MIPS IV and MIPS32r2 ISAs
1391 		 * up the space has been reused for COP1X instructions, that
1392 		 * are enabled by the CP0.Status.CU1 bit and consequently
1393 		 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1394 		 * exceptions.  Some FPU-less processors that implement one
1395 		 * of these ISAs however use this code erroneously for COP1X
1396 		 * instructions.  Therefore we redirect this trap to the FP
1397 		 * emulator too.
1398 		 */
1399 		if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1400 			force_sig(SIGILL, current);
1401 			break;
1402 		}
1403 		/* Fall through.  */
1404 
1405 	case 1:
1406 		err = enable_restore_fp_context(0);
1407 
1408 		if (raw_cpu_has_fpu && !err)
1409 			break;
1410 
1411 		sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1412 					       &fault_addr);
1413 		fcr31 = current->thread.fpu.fcr31;
1414 
1415 		/*
1416 		 * We can't allow the emulated instruction to leave
1417 		 * any of the cause bits set in $fcr31.
1418 		 */
1419 		current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
1420 
1421 		/* Send a signal if required.  */
1422 		if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1423 			mt_ase_fp_affinity();
1424 
1425 		break;
1426 
1427 	case 2:
1428 		raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1429 		break;
1430 	}
1431 
1432 	exception_exit(prev_state);
1433 }
1434 
1435 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1436 {
1437 	enum ctx_state prev_state;
1438 
1439 	prev_state = exception_enter();
1440 	if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1441 		       regs_to_trapnr(regs), SIGFPE) == NOTIFY_STOP)
1442 		goto out;
1443 
1444 	/* Clear MSACSR.Cause before enabling interrupts */
1445 	write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1446 	local_irq_enable();
1447 
1448 	die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1449 	force_sig(SIGFPE, current);
1450 out:
1451 	exception_exit(prev_state);
1452 }
1453 
1454 asmlinkage void do_msa(struct pt_regs *regs)
1455 {
1456 	enum ctx_state prev_state;
1457 	int err;
1458 
1459 	prev_state = exception_enter();
1460 
1461 	if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1462 		force_sig(SIGILL, current);
1463 		goto out;
1464 	}
1465 
1466 	die_if_kernel("do_msa invoked from kernel context!", regs);
1467 
1468 	err = enable_restore_fp_context(1);
1469 	if (err)
1470 		force_sig(SIGILL, current);
1471 out:
1472 	exception_exit(prev_state);
1473 }
1474 
1475 asmlinkage void do_mdmx(struct pt_regs *regs)
1476 {
1477 	enum ctx_state prev_state;
1478 
1479 	prev_state = exception_enter();
1480 	force_sig(SIGILL, current);
1481 	exception_exit(prev_state);
1482 }
1483 
1484 /*
1485  * Called with interrupts disabled.
1486  */
1487 asmlinkage void do_watch(struct pt_regs *regs)
1488 {
1489 	enum ctx_state prev_state;
1490 	u32 cause;
1491 
1492 	prev_state = exception_enter();
1493 	/*
1494 	 * Clear WP (bit 22) bit of cause register so we don't loop
1495 	 * forever.
1496 	 */
1497 	cause = read_c0_cause();
1498 	cause &= ~(1 << 22);
1499 	write_c0_cause(cause);
1500 
1501 	/*
1502 	 * If the current thread has the watch registers loaded, save
1503 	 * their values and send SIGTRAP.  Otherwise another thread
1504 	 * left the registers set, clear them and continue.
1505 	 */
1506 	if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1507 		mips_read_watch_registers();
1508 		local_irq_enable();
1509 		force_sig(SIGTRAP, current);
1510 	} else {
1511 		mips_clear_watch_registers();
1512 		local_irq_enable();
1513 	}
1514 	exception_exit(prev_state);
1515 }
1516 
1517 asmlinkage void do_mcheck(struct pt_regs *regs)
1518 {
1519 	const int field = 2 * sizeof(unsigned long);
1520 	int multi_match = regs->cp0_status & ST0_TS;
1521 	enum ctx_state prev_state;
1522 
1523 	prev_state = exception_enter();
1524 	show_regs(regs);
1525 
1526 	if (multi_match) {
1527 		pr_err("Index	: %0x\n", read_c0_index());
1528 		pr_err("Pagemask: %0x\n", read_c0_pagemask());
1529 		pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi());
1530 		pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1531 		pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1532 		pr_err("Wired   : %0x\n", read_c0_wired());
1533 		pr_err("Pagegrain: %0x\n", read_c0_pagegrain());
1534 		if (cpu_has_htw) {
1535 			pr_err("PWField : %0*lx\n", field, read_c0_pwfield());
1536 			pr_err("PWSize  : %0*lx\n", field, read_c0_pwsize());
1537 			pr_err("PWCtl   : %0x\n", read_c0_pwctl());
1538 		}
1539 		pr_err("\n");
1540 		dump_tlb_all();
1541 	}
1542 
1543 	show_code((unsigned int __user *) regs->cp0_epc);
1544 
1545 	/*
1546 	 * Some chips may have other causes of machine check (e.g. SB1
1547 	 * graduation timer)
1548 	 */
1549 	panic("Caught Machine Check exception - %scaused by multiple "
1550 	      "matching entries in the TLB.",
1551 	      (multi_match) ? "" : "not ");
1552 }
1553 
1554 asmlinkage void do_mt(struct pt_regs *regs)
1555 {
1556 	int subcode;
1557 
1558 	subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1559 			>> VPECONTROL_EXCPT_SHIFT;
1560 	switch (subcode) {
1561 	case 0:
1562 		printk(KERN_DEBUG "Thread Underflow\n");
1563 		break;
1564 	case 1:
1565 		printk(KERN_DEBUG "Thread Overflow\n");
1566 		break;
1567 	case 2:
1568 		printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1569 		break;
1570 	case 3:
1571 		printk(KERN_DEBUG "Gating Storage Exception\n");
1572 		break;
1573 	case 4:
1574 		printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1575 		break;
1576 	case 5:
1577 		printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1578 		break;
1579 	default:
1580 		printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1581 			subcode);
1582 		break;
1583 	}
1584 	die_if_kernel("MIPS MT Thread exception in kernel", regs);
1585 
1586 	force_sig(SIGILL, current);
1587 }
1588 
1589 
1590 asmlinkage void do_dsp(struct pt_regs *regs)
1591 {
1592 	if (cpu_has_dsp)
1593 		panic("Unexpected DSP exception");
1594 
1595 	force_sig(SIGILL, current);
1596 }
1597 
1598 asmlinkage void do_reserved(struct pt_regs *regs)
1599 {
1600 	/*
1601 	 * Game over - no way to handle this if it ever occurs.	 Most probably
1602 	 * caused by a new unknown cpu type or after another deadly
1603 	 * hard/software error.
1604 	 */
1605 	show_regs(regs);
1606 	panic("Caught reserved exception %ld - should not happen.",
1607 	      (regs->cp0_cause & 0x7f) >> 2);
1608 }
1609 
1610 static int __initdata l1parity = 1;
1611 static int __init nol1parity(char *s)
1612 {
1613 	l1parity = 0;
1614 	return 1;
1615 }
1616 __setup("nol1par", nol1parity);
1617 static int __initdata l2parity = 1;
1618 static int __init nol2parity(char *s)
1619 {
1620 	l2parity = 0;
1621 	return 1;
1622 }
1623 __setup("nol2par", nol2parity);
1624 
1625 /*
1626  * Some MIPS CPUs can enable/disable for cache parity detection, but do
1627  * it different ways.
1628  */
1629 static inline void parity_protection_init(void)
1630 {
1631 	switch (current_cpu_type()) {
1632 	case CPU_24K:
1633 	case CPU_34K:
1634 	case CPU_74K:
1635 	case CPU_1004K:
1636 	case CPU_1074K:
1637 	case CPU_INTERAPTIV:
1638 	case CPU_PROAPTIV:
1639 	case CPU_P5600:
1640 	case CPU_QEMU_GENERIC:
1641 		{
1642 #define ERRCTL_PE	0x80000000
1643 #define ERRCTL_L2P	0x00800000
1644 			unsigned long errctl;
1645 			unsigned int l1parity_present, l2parity_present;
1646 
1647 			errctl = read_c0_ecc();
1648 			errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1649 
1650 			/* probe L1 parity support */
1651 			write_c0_ecc(errctl | ERRCTL_PE);
1652 			back_to_back_c0_hazard();
1653 			l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1654 
1655 			/* probe L2 parity support */
1656 			write_c0_ecc(errctl|ERRCTL_L2P);
1657 			back_to_back_c0_hazard();
1658 			l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1659 
1660 			if (l1parity_present && l2parity_present) {
1661 				if (l1parity)
1662 					errctl |= ERRCTL_PE;
1663 				if (l1parity ^ l2parity)
1664 					errctl |= ERRCTL_L2P;
1665 			} else if (l1parity_present) {
1666 				if (l1parity)
1667 					errctl |= ERRCTL_PE;
1668 			} else if (l2parity_present) {
1669 				if (l2parity)
1670 					errctl |= ERRCTL_L2P;
1671 			} else {
1672 				/* No parity available */
1673 			}
1674 
1675 			printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1676 
1677 			write_c0_ecc(errctl);
1678 			back_to_back_c0_hazard();
1679 			errctl = read_c0_ecc();
1680 			printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1681 
1682 			if (l1parity_present)
1683 				printk(KERN_INFO "Cache parity protection %sabled\n",
1684 				       (errctl & ERRCTL_PE) ? "en" : "dis");
1685 
1686 			if (l2parity_present) {
1687 				if (l1parity_present && l1parity)
1688 					errctl ^= ERRCTL_L2P;
1689 				printk(KERN_INFO "L2 cache parity protection %sabled\n",
1690 				       (errctl & ERRCTL_L2P) ? "en" : "dis");
1691 			}
1692 		}
1693 		break;
1694 
1695 	case CPU_5KC:
1696 	case CPU_5KE:
1697 	case CPU_LOONGSON1:
1698 		write_c0_ecc(0x80000000);
1699 		back_to_back_c0_hazard();
1700 		/* Set the PE bit (bit 31) in the c0_errctl register. */
1701 		printk(KERN_INFO "Cache parity protection %sabled\n",
1702 		       (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1703 		break;
1704 	case CPU_20KC:
1705 	case CPU_25KF:
1706 		/* Clear the DE bit (bit 16) in the c0_status register. */
1707 		printk(KERN_INFO "Enable cache parity protection for "
1708 		       "MIPS 20KC/25KF CPUs.\n");
1709 		clear_c0_status(ST0_DE);
1710 		break;
1711 	default:
1712 		break;
1713 	}
1714 }
1715 
1716 asmlinkage void cache_parity_error(void)
1717 {
1718 	const int field = 2 * sizeof(unsigned long);
1719 	unsigned int reg_val;
1720 
1721 	/* For the moment, report the problem and hang. */
1722 	printk("Cache error exception:\n");
1723 	printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1724 	reg_val = read_c0_cacheerr();
1725 	printk("c0_cacheerr == %08x\n", reg_val);
1726 
1727 	printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1728 	       reg_val & (1<<30) ? "secondary" : "primary",
1729 	       reg_val & (1<<31) ? "data" : "insn");
1730 	if ((cpu_has_mips_r2_r6) &&
1731 	    ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1732 		pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1733 			reg_val & (1<<29) ? "ED " : "",
1734 			reg_val & (1<<28) ? "ET " : "",
1735 			reg_val & (1<<27) ? "ES " : "",
1736 			reg_val & (1<<26) ? "EE " : "",
1737 			reg_val & (1<<25) ? "EB " : "",
1738 			reg_val & (1<<24) ? "EI " : "",
1739 			reg_val & (1<<23) ? "E1 " : "",
1740 			reg_val & (1<<22) ? "E0 " : "");
1741 	} else {
1742 		pr_err("Error bits: %s%s%s%s%s%s%s\n",
1743 			reg_val & (1<<29) ? "ED " : "",
1744 			reg_val & (1<<28) ? "ET " : "",
1745 			reg_val & (1<<26) ? "EE " : "",
1746 			reg_val & (1<<25) ? "EB " : "",
1747 			reg_val & (1<<24) ? "EI " : "",
1748 			reg_val & (1<<23) ? "E1 " : "",
1749 			reg_val & (1<<22) ? "E0 " : "");
1750 	}
1751 	printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1752 
1753 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1754 	if (reg_val & (1<<22))
1755 		printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1756 
1757 	if (reg_val & (1<<23))
1758 		printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1759 #endif
1760 
1761 	panic("Can't handle the cache error!");
1762 }
1763 
1764 asmlinkage void do_ftlb(void)
1765 {
1766 	const int field = 2 * sizeof(unsigned long);
1767 	unsigned int reg_val;
1768 
1769 	/* For the moment, report the problem and hang. */
1770 	if ((cpu_has_mips_r2_r6) &&
1771 	    ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1772 		pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1773 		       read_c0_ecc());
1774 		pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1775 		reg_val = read_c0_cacheerr();
1776 		pr_err("c0_cacheerr == %08x\n", reg_val);
1777 
1778 		if ((reg_val & 0xc0000000) == 0xc0000000) {
1779 			pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1780 		} else {
1781 			pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1782 			       reg_val & (1<<30) ? "secondary" : "primary",
1783 			       reg_val & (1<<31) ? "data" : "insn");
1784 		}
1785 	} else {
1786 		pr_err("FTLB error exception\n");
1787 	}
1788 	/* Just print the cacheerr bits for now */
1789 	cache_parity_error();
1790 }
1791 
1792 /*
1793  * SDBBP EJTAG debug exception handler.
1794  * We skip the instruction and return to the next instruction.
1795  */
1796 void ejtag_exception_handler(struct pt_regs *regs)
1797 {
1798 	const int field = 2 * sizeof(unsigned long);
1799 	unsigned long depc, old_epc, old_ra;
1800 	unsigned int debug;
1801 
1802 	printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1803 	depc = read_c0_depc();
1804 	debug = read_c0_debug();
1805 	printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1806 	if (debug & 0x80000000) {
1807 		/*
1808 		 * In branch delay slot.
1809 		 * We cheat a little bit here and use EPC to calculate the
1810 		 * debug return address (DEPC). EPC is restored after the
1811 		 * calculation.
1812 		 */
1813 		old_epc = regs->cp0_epc;
1814 		old_ra = regs->regs[31];
1815 		regs->cp0_epc = depc;
1816 		compute_return_epc(regs);
1817 		depc = regs->cp0_epc;
1818 		regs->cp0_epc = old_epc;
1819 		regs->regs[31] = old_ra;
1820 	} else
1821 		depc += 4;
1822 	write_c0_depc(depc);
1823 
1824 #if 0
1825 	printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1826 	write_c0_debug(debug | 0x100);
1827 #endif
1828 }
1829 
1830 /*
1831  * NMI exception handler.
1832  * No lock; only written during early bootup by CPU 0.
1833  */
1834 static RAW_NOTIFIER_HEAD(nmi_chain);
1835 
1836 int register_nmi_notifier(struct notifier_block *nb)
1837 {
1838 	return raw_notifier_chain_register(&nmi_chain, nb);
1839 }
1840 
1841 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1842 {
1843 	char str[100];
1844 
1845 	raw_notifier_call_chain(&nmi_chain, 0, regs);
1846 	bust_spinlocks(1);
1847 	snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1848 		 smp_processor_id(), regs->cp0_epc);
1849 	regs->cp0_epc = read_c0_errorepc();
1850 	die(str, regs);
1851 }
1852 
1853 #define VECTORSPACING 0x100	/* for EI/VI mode */
1854 
1855 unsigned long ebase;
1856 unsigned long exception_handlers[32];
1857 unsigned long vi_handlers[64];
1858 
1859 void __init *set_except_vector(int n, void *addr)
1860 {
1861 	unsigned long handler = (unsigned long) addr;
1862 	unsigned long old_handler;
1863 
1864 #ifdef CONFIG_CPU_MICROMIPS
1865 	/*
1866 	 * Only the TLB handlers are cache aligned with an even
1867 	 * address. All other handlers are on an odd address and
1868 	 * require no modification. Otherwise, MIPS32 mode will
1869 	 * be entered when handling any TLB exceptions. That
1870 	 * would be bad...since we must stay in microMIPS mode.
1871 	 */
1872 	if (!(handler & 0x1))
1873 		handler |= 1;
1874 #endif
1875 	old_handler = xchg(&exception_handlers[n], handler);
1876 
1877 	if (n == 0 && cpu_has_divec) {
1878 #ifdef CONFIG_CPU_MICROMIPS
1879 		unsigned long jump_mask = ~((1 << 27) - 1);
1880 #else
1881 		unsigned long jump_mask = ~((1 << 28) - 1);
1882 #endif
1883 		u32 *buf = (u32 *)(ebase + 0x200);
1884 		unsigned int k0 = 26;
1885 		if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1886 			uasm_i_j(&buf, handler & ~jump_mask);
1887 			uasm_i_nop(&buf);
1888 		} else {
1889 			UASM_i_LA(&buf, k0, handler);
1890 			uasm_i_jr(&buf, k0);
1891 			uasm_i_nop(&buf);
1892 		}
1893 		local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1894 	}
1895 	return (void *)old_handler;
1896 }
1897 
1898 static void do_default_vi(void)
1899 {
1900 	show_regs(get_irq_regs());
1901 	panic("Caught unexpected vectored interrupt.");
1902 }
1903 
1904 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1905 {
1906 	unsigned long handler;
1907 	unsigned long old_handler = vi_handlers[n];
1908 	int srssets = current_cpu_data.srsets;
1909 	u16 *h;
1910 	unsigned char *b;
1911 
1912 	BUG_ON(!cpu_has_veic && !cpu_has_vint);
1913 
1914 	if (addr == NULL) {
1915 		handler = (unsigned long) do_default_vi;
1916 		srs = 0;
1917 	} else
1918 		handler = (unsigned long) addr;
1919 	vi_handlers[n] = handler;
1920 
1921 	b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1922 
1923 	if (srs >= srssets)
1924 		panic("Shadow register set %d not supported", srs);
1925 
1926 	if (cpu_has_veic) {
1927 		if (board_bind_eic_interrupt)
1928 			board_bind_eic_interrupt(n, srs);
1929 	} else if (cpu_has_vint) {
1930 		/* SRSMap is only defined if shadow sets are implemented */
1931 		if (srssets > 1)
1932 			change_c0_srsmap(0xf << n*4, srs << n*4);
1933 	}
1934 
1935 	if (srs == 0) {
1936 		/*
1937 		 * If no shadow set is selected then use the default handler
1938 		 * that does normal register saving and standard interrupt exit
1939 		 */
1940 		extern char except_vec_vi, except_vec_vi_lui;
1941 		extern char except_vec_vi_ori, except_vec_vi_end;
1942 		extern char rollback_except_vec_vi;
1943 		char *vec_start = using_rollback_handler() ?
1944 			&rollback_except_vec_vi : &except_vec_vi;
1945 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1946 		const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1947 		const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1948 #else
1949 		const int lui_offset = &except_vec_vi_lui - vec_start;
1950 		const int ori_offset = &except_vec_vi_ori - vec_start;
1951 #endif
1952 		const int handler_len = &except_vec_vi_end - vec_start;
1953 
1954 		if (handler_len > VECTORSPACING) {
1955 			/*
1956 			 * Sigh... panicing won't help as the console
1957 			 * is probably not configured :(
1958 			 */
1959 			panic("VECTORSPACING too small");
1960 		}
1961 
1962 		set_handler(((unsigned long)b - ebase), vec_start,
1963 #ifdef CONFIG_CPU_MICROMIPS
1964 				(handler_len - 1));
1965 #else
1966 				handler_len);
1967 #endif
1968 		h = (u16 *)(b + lui_offset);
1969 		*h = (handler >> 16) & 0xffff;
1970 		h = (u16 *)(b + ori_offset);
1971 		*h = (handler & 0xffff);
1972 		local_flush_icache_range((unsigned long)b,
1973 					 (unsigned long)(b+handler_len));
1974 	}
1975 	else {
1976 		/*
1977 		 * In other cases jump directly to the interrupt handler. It
1978 		 * is the handler's responsibility to save registers if required
1979 		 * (eg hi/lo) and return from the exception using "eret".
1980 		 */
1981 		u32 insn;
1982 
1983 		h = (u16 *)b;
1984 		/* j handler */
1985 #ifdef CONFIG_CPU_MICROMIPS
1986 		insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1987 #else
1988 		insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1989 #endif
1990 		h[0] = (insn >> 16) & 0xffff;
1991 		h[1] = insn & 0xffff;
1992 		h[2] = 0;
1993 		h[3] = 0;
1994 		local_flush_icache_range((unsigned long)b,
1995 					 (unsigned long)(b+8));
1996 	}
1997 
1998 	return (void *)old_handler;
1999 }
2000 
2001 void *set_vi_handler(int n, vi_handler_t addr)
2002 {
2003 	return set_vi_srs_handler(n, addr, 0);
2004 }
2005 
2006 extern void tlb_init(void);
2007 
2008 /*
2009  * Timer interrupt
2010  */
2011 int cp0_compare_irq;
2012 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2013 int cp0_compare_irq_shift;
2014 
2015 /*
2016  * Performance counter IRQ or -1 if shared with timer
2017  */
2018 int cp0_perfcount_irq;
2019 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2020 
2021 /*
2022  * Fast debug channel IRQ or -1 if not present
2023  */
2024 int cp0_fdc_irq;
2025 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2026 
2027 static int noulri;
2028 
2029 static int __init ulri_disable(char *s)
2030 {
2031 	pr_info("Disabling ulri\n");
2032 	noulri = 1;
2033 
2034 	return 1;
2035 }
2036 __setup("noulri", ulri_disable);
2037 
2038 /* configure STATUS register */
2039 static void configure_status(void)
2040 {
2041 	/*
2042 	 * Disable coprocessors and select 32-bit or 64-bit addressing
2043 	 * and the 16/32 or 32/32 FPR register model.  Reset the BEV
2044 	 * flag that some firmware may have left set and the TS bit (for
2045 	 * IP27).  Set XX for ISA IV code to work.
2046 	 */
2047 	unsigned int status_set = ST0_CU0;
2048 #ifdef CONFIG_64BIT
2049 	status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2050 #endif
2051 	if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2052 		status_set |= ST0_XX;
2053 	if (cpu_has_dsp)
2054 		status_set |= ST0_MX;
2055 
2056 	change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2057 			 status_set);
2058 }
2059 
2060 /* configure HWRENA register */
2061 static void configure_hwrena(void)
2062 {
2063 	unsigned int hwrena = cpu_hwrena_impl_bits;
2064 
2065 	if (cpu_has_mips_r2_r6)
2066 		hwrena |= 0x0000000f;
2067 
2068 	if (!noulri && cpu_has_userlocal)
2069 		hwrena |= (1 << 29);
2070 
2071 	if (hwrena)
2072 		write_c0_hwrena(hwrena);
2073 }
2074 
2075 static void configure_exception_vector(void)
2076 {
2077 	if (cpu_has_veic || cpu_has_vint) {
2078 		unsigned long sr = set_c0_status(ST0_BEV);
2079 		write_c0_ebase(ebase);
2080 		write_c0_status(sr);
2081 		/* Setting vector spacing enables EI/VI mode  */
2082 		change_c0_intctl(0x3e0, VECTORSPACING);
2083 	}
2084 	if (cpu_has_divec) {
2085 		if (cpu_has_mipsmt) {
2086 			unsigned int vpflags = dvpe();
2087 			set_c0_cause(CAUSEF_IV);
2088 			evpe(vpflags);
2089 		} else
2090 			set_c0_cause(CAUSEF_IV);
2091 	}
2092 }
2093 
2094 void per_cpu_trap_init(bool is_boot_cpu)
2095 {
2096 	unsigned int cpu = smp_processor_id();
2097 
2098 	configure_status();
2099 	configure_hwrena();
2100 
2101 	configure_exception_vector();
2102 
2103 	/*
2104 	 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2105 	 *
2106 	 *  o read IntCtl.IPTI to determine the timer interrupt
2107 	 *  o read IntCtl.IPPCI to determine the performance counter interrupt
2108 	 *  o read IntCtl.IPFDC to determine the fast debug channel interrupt
2109 	 */
2110 	if (cpu_has_mips_r2_r6) {
2111 		cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2112 		cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2113 		cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2114 		cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2115 		if (!cp0_fdc_irq)
2116 			cp0_fdc_irq = -1;
2117 
2118 	} else {
2119 		cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2120 		cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2121 		cp0_perfcount_irq = -1;
2122 		cp0_fdc_irq = -1;
2123 	}
2124 
2125 	if (!cpu_data[cpu].asid_cache)
2126 		cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
2127 
2128 	atomic_inc(&init_mm.mm_count);
2129 	current->active_mm = &init_mm;
2130 	BUG_ON(current->mm);
2131 	enter_lazy_tlb(&init_mm, current);
2132 
2133 		/* Boot CPU's cache setup in setup_arch(). */
2134 		if (!is_boot_cpu)
2135 			cpu_cache_init();
2136 		tlb_init();
2137 	TLBMISS_HANDLER_SETUP();
2138 }
2139 
2140 /* Install CPU exception handler */
2141 void set_handler(unsigned long offset, void *addr, unsigned long size)
2142 {
2143 #ifdef CONFIG_CPU_MICROMIPS
2144 	memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2145 #else
2146 	memcpy((void *)(ebase + offset), addr, size);
2147 #endif
2148 	local_flush_icache_range(ebase + offset, ebase + offset + size);
2149 }
2150 
2151 static char panic_null_cerr[] =
2152 	"Trying to set NULL cache error exception handler";
2153 
2154 /*
2155  * Install uncached CPU exception handler.
2156  * This is suitable only for the cache error exception which is the only
2157  * exception handler that is being run uncached.
2158  */
2159 void set_uncached_handler(unsigned long offset, void *addr,
2160 	unsigned long size)
2161 {
2162 	unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2163 
2164 	if (!addr)
2165 		panic(panic_null_cerr);
2166 
2167 	memcpy((void *)(uncached_ebase + offset), addr, size);
2168 }
2169 
2170 static int __initdata rdhwr_noopt;
2171 static int __init set_rdhwr_noopt(char *str)
2172 {
2173 	rdhwr_noopt = 1;
2174 	return 1;
2175 }
2176 
2177 __setup("rdhwr_noopt", set_rdhwr_noopt);
2178 
2179 void __init trap_init(void)
2180 {
2181 	extern char except_vec3_generic;
2182 	extern char except_vec4;
2183 	extern char except_vec3_r4000;
2184 	unsigned long i;
2185 
2186 	check_wait();
2187 
2188 #if defined(CONFIG_KGDB)
2189 	if (kgdb_early_setup)
2190 		return; /* Already done */
2191 #endif
2192 
2193 	if (cpu_has_veic || cpu_has_vint) {
2194 		unsigned long size = 0x200 + VECTORSPACING*64;
2195 		ebase = (unsigned long)
2196 			__alloc_bootmem(size, 1 << fls(size), 0);
2197 	} else {
2198 #ifdef CONFIG_KVM_GUEST
2199 #define KVM_GUEST_KSEG0     0x40000000
2200         ebase = KVM_GUEST_KSEG0;
2201 #else
2202         ebase = CKSEG0;
2203 #endif
2204 		if (cpu_has_mips_r2_r6)
2205 			ebase += (read_c0_ebase() & 0x3ffff000);
2206 	}
2207 
2208 	if (cpu_has_mmips) {
2209 		unsigned int config3 = read_c0_config3();
2210 
2211 		if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2212 			write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2213 		else
2214 			write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2215 	}
2216 
2217 	if (board_ebase_setup)
2218 		board_ebase_setup();
2219 	per_cpu_trap_init(true);
2220 
2221 	/*
2222 	 * Copy the generic exception handlers to their final destination.
2223 	 * This will be overriden later as suitable for a particular
2224 	 * configuration.
2225 	 */
2226 	set_handler(0x180, &except_vec3_generic, 0x80);
2227 
2228 	/*
2229 	 * Setup default vectors
2230 	 */
2231 	for (i = 0; i <= 31; i++)
2232 		set_except_vector(i, handle_reserved);
2233 
2234 	/*
2235 	 * Copy the EJTAG debug exception vector handler code to it's final
2236 	 * destination.
2237 	 */
2238 	if (cpu_has_ejtag && board_ejtag_handler_setup)
2239 		board_ejtag_handler_setup();
2240 
2241 	/*
2242 	 * Only some CPUs have the watch exceptions.
2243 	 */
2244 	if (cpu_has_watch)
2245 		set_except_vector(23, handle_watch);
2246 
2247 	/*
2248 	 * Initialise interrupt handlers
2249 	 */
2250 	if (cpu_has_veic || cpu_has_vint) {
2251 		int nvec = cpu_has_veic ? 64 : 8;
2252 		for (i = 0; i < nvec; i++)
2253 			set_vi_handler(i, NULL);
2254 	}
2255 	else if (cpu_has_divec)
2256 		set_handler(0x200, &except_vec4, 0x8);
2257 
2258 	/*
2259 	 * Some CPUs can enable/disable for cache parity detection, but does
2260 	 * it different ways.
2261 	 */
2262 	parity_protection_init();
2263 
2264 	/*
2265 	 * The Data Bus Errors / Instruction Bus Errors are signaled
2266 	 * by external hardware.  Therefore these two exceptions
2267 	 * may have board specific handlers.
2268 	 */
2269 	if (board_be_init)
2270 		board_be_init();
2271 
2272 	set_except_vector(0, using_rollback_handler() ? rollback_handle_int
2273 						      : handle_int);
2274 	set_except_vector(1, handle_tlbm);
2275 	set_except_vector(2, handle_tlbl);
2276 	set_except_vector(3, handle_tlbs);
2277 
2278 	set_except_vector(4, handle_adel);
2279 	set_except_vector(5, handle_ades);
2280 
2281 	set_except_vector(6, handle_ibe);
2282 	set_except_vector(7, handle_dbe);
2283 
2284 	set_except_vector(8, handle_sys);
2285 	set_except_vector(9, handle_bp);
2286 	set_except_vector(10, rdhwr_noopt ? handle_ri :
2287 			  (cpu_has_vtag_icache ?
2288 			   handle_ri_rdhwr_vivt : handle_ri_rdhwr));
2289 	set_except_vector(11, handle_cpu);
2290 	set_except_vector(12, handle_ov);
2291 	set_except_vector(13, handle_tr);
2292 	set_except_vector(14, handle_msa_fpe);
2293 
2294 	if (current_cpu_type() == CPU_R6000 ||
2295 	    current_cpu_type() == CPU_R6000A) {
2296 		/*
2297 		 * The R6000 is the only R-series CPU that features a machine
2298 		 * check exception (similar to the R4000 cache error) and
2299 		 * unaligned ldc1/sdc1 exception.  The handlers have not been
2300 		 * written yet.	 Well, anyway there is no R6000 machine on the
2301 		 * current list of targets for Linux/MIPS.
2302 		 * (Duh, crap, there is someone with a triple R6k machine)
2303 		 */
2304 		//set_except_vector(14, handle_mc);
2305 		//set_except_vector(15, handle_ndc);
2306 	}
2307 
2308 
2309 	if (board_nmi_handler_setup)
2310 		board_nmi_handler_setup();
2311 
2312 	if (cpu_has_fpu && !cpu_has_nofpuex)
2313 		set_except_vector(15, handle_fpe);
2314 
2315 	set_except_vector(16, handle_ftlb);
2316 
2317 	if (cpu_has_rixiex) {
2318 		set_except_vector(19, tlb_do_page_fault_0);
2319 		set_except_vector(20, tlb_do_page_fault_0);
2320 	}
2321 
2322 	set_except_vector(21, handle_msa);
2323 	set_except_vector(22, handle_mdmx);
2324 
2325 	if (cpu_has_mcheck)
2326 		set_except_vector(24, handle_mcheck);
2327 
2328 	if (cpu_has_mipsmt)
2329 		set_except_vector(25, handle_mt);
2330 
2331 	set_except_vector(26, handle_dsp);
2332 
2333 	if (board_cache_error_setup)
2334 		board_cache_error_setup();
2335 
2336 	if (cpu_has_vce)
2337 		/* Special exception: R4[04]00 uses also the divec space. */
2338 		set_handler(0x180, &except_vec3_r4000, 0x100);
2339 	else if (cpu_has_4kex)
2340 		set_handler(0x180, &except_vec3_generic, 0x80);
2341 	else
2342 		set_handler(0x080, &except_vec3_generic, 0x80);
2343 
2344 	local_flush_icache_range(ebase, ebase + 0x400);
2345 
2346 	sort_extable(__start___dbe_table, __stop___dbe_table);
2347 
2348 	cu2_notifier(default_cu2_call, 0x80000000);	/* Run last  */
2349 }
2350 
2351 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2352 			    void *v)
2353 {
2354 	switch (cmd) {
2355 	case CPU_PM_ENTER_FAILED:
2356 	case CPU_PM_EXIT:
2357 		configure_status();
2358 		configure_hwrena();
2359 		configure_exception_vector();
2360 
2361 		/* Restore register with CPU number for TLB handlers */
2362 		TLBMISS_HANDLER_RESTORE();
2363 
2364 		break;
2365 	}
2366 
2367 	return NOTIFY_OK;
2368 }
2369 
2370 static struct notifier_block trap_pm_notifier_block = {
2371 	.notifier_call = trap_pm_notifier,
2372 };
2373 
2374 static int __init trap_pm_init(void)
2375 {
2376 	return cpu_pm_register_notifier(&trap_pm_notifier_block);
2377 }
2378 arch_initcall(trap_pm_init);
2379