1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. 13 * Copyright (C) 2014, Imagination Technologies Ltd. 14 */ 15 #include <linux/bitops.h> 16 #include <linux/bug.h> 17 #include <linux/compiler.h> 18 #include <linux/context_tracking.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/kexec.h> 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/extable.h> 25 #include <linux/mm.h> 26 #include <linux/sched/mm.h> 27 #include <linux/sched/debug.h> 28 #include <linux/smp.h> 29 #include <linux/spinlock.h> 30 #include <linux/kallsyms.h> 31 #include <linux/memblock.h> 32 #include <linux/interrupt.h> 33 #include <linux/ptrace.h> 34 #include <linux/kgdb.h> 35 #include <linux/kdebug.h> 36 #include <linux/kprobes.h> 37 #include <linux/notifier.h> 38 #include <linux/kdb.h> 39 #include <linux/irq.h> 40 #include <linux/perf_event.h> 41 42 #include <asm/addrspace.h> 43 #include <asm/bootinfo.h> 44 #include <asm/branch.h> 45 #include <asm/break.h> 46 #include <asm/cop2.h> 47 #include <asm/cpu.h> 48 #include <asm/cpu-type.h> 49 #include <asm/dsp.h> 50 #include <asm/fpu.h> 51 #include <asm/fpu_emulator.h> 52 #include <asm/idle.h> 53 #include <asm/isa-rev.h> 54 #include <asm/mips-cps.h> 55 #include <asm/mips-r2-to-r6-emul.h> 56 #include <asm/mipsregs.h> 57 #include <asm/mipsmtregs.h> 58 #include <asm/module.h> 59 #include <asm/msa.h> 60 #include <asm/ptrace.h> 61 #include <asm/sections.h> 62 #include <asm/siginfo.h> 63 #include <asm/tlbdebug.h> 64 #include <asm/traps.h> 65 #include <linux/uaccess.h> 66 #include <asm/watch.h> 67 #include <asm/mmu_context.h> 68 #include <asm/types.h> 69 #include <asm/stacktrace.h> 70 #include <asm/tlbex.h> 71 #include <asm/uasm.h> 72 73 #include <asm/mach-loongson64/cpucfg-emul.h> 74 75 extern void check_wait(void); 76 extern asmlinkage void rollback_handle_int(void); 77 extern asmlinkage void handle_int(void); 78 extern asmlinkage void handle_adel(void); 79 extern asmlinkage void handle_ades(void); 80 extern asmlinkage void handle_ibe(void); 81 extern asmlinkage void handle_dbe(void); 82 extern asmlinkage void handle_sys(void); 83 extern asmlinkage void handle_bp(void); 84 extern asmlinkage void handle_ri(void); 85 extern asmlinkage void handle_ri_rdhwr_tlbp(void); 86 extern asmlinkage void handle_ri_rdhwr(void); 87 extern asmlinkage void handle_cpu(void); 88 extern asmlinkage void handle_ov(void); 89 extern asmlinkage void handle_tr(void); 90 extern asmlinkage void handle_msa_fpe(void); 91 extern asmlinkage void handle_fpe(void); 92 extern asmlinkage void handle_ftlb(void); 93 extern asmlinkage void handle_gsexc(void); 94 extern asmlinkage void handle_msa(void); 95 extern asmlinkage void handle_mdmx(void); 96 extern asmlinkage void handle_watch(void); 97 extern asmlinkage void handle_mt(void); 98 extern asmlinkage void handle_dsp(void); 99 extern asmlinkage void handle_mcheck(void); 100 extern asmlinkage void handle_reserved(void); 101 extern void tlb_do_page_fault_0(void); 102 103 void (*board_be_init)(void); 104 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 105 void (*board_nmi_handler_setup)(void); 106 void (*board_ejtag_handler_setup)(void); 107 void (*board_bind_eic_interrupt)(int irq, int regset); 108 void (*board_ebase_setup)(void); 109 void(*board_cache_error_setup)(void); 110 111 static void show_raw_backtrace(unsigned long reg29, const char *loglvl) 112 { 113 unsigned long *sp = (unsigned long *)(reg29 & ~3); 114 unsigned long addr; 115 116 printk("%sCall Trace:", loglvl); 117 #ifdef CONFIG_KALLSYMS 118 printk("%s\n", loglvl); 119 #endif 120 while (!kstack_end(sp)) { 121 unsigned long __user *p = 122 (unsigned long __user *)(unsigned long)sp++; 123 if (__get_user(addr, p)) { 124 printk("%s (Bad stack address)", loglvl); 125 break; 126 } 127 if (__kernel_text_address(addr)) 128 print_ip_sym(loglvl, addr); 129 } 130 printk("%s\n", loglvl); 131 } 132 133 #ifdef CONFIG_KALLSYMS 134 int raw_show_trace; 135 static int __init set_raw_show_trace(char *str) 136 { 137 raw_show_trace = 1; 138 return 1; 139 } 140 __setup("raw_show_trace", set_raw_show_trace); 141 #endif 142 143 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs, 144 const char *loglvl) 145 { 146 unsigned long sp = regs->regs[29]; 147 unsigned long ra = regs->regs[31]; 148 unsigned long pc = regs->cp0_epc; 149 150 if (!task) 151 task = current; 152 153 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) { 154 show_raw_backtrace(sp, loglvl); 155 return; 156 } 157 printk("%sCall Trace:\n", loglvl); 158 do { 159 print_ip_sym(loglvl, pc); 160 pc = unwind_stack(task, &sp, pc, &ra); 161 } while (pc); 162 pr_cont("\n"); 163 } 164 165 /* 166 * This routine abuses get_user()/put_user() to reference pointers 167 * with at least a bit of error checking ... 168 */ 169 static void show_stacktrace(struct task_struct *task, 170 const struct pt_regs *regs, const char *loglvl) 171 { 172 const int field = 2 * sizeof(unsigned long); 173 long stackdata; 174 int i; 175 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 176 177 printk("%sStack :", loglvl); 178 i = 0; 179 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 180 if (i && ((i % (64 / field)) == 0)) { 181 pr_cont("\n"); 182 printk("%s ", loglvl); 183 } 184 if (i > 39) { 185 pr_cont(" ..."); 186 break; 187 } 188 189 if (__get_user(stackdata, sp++)) { 190 pr_cont(" (Bad stack address)"); 191 break; 192 } 193 194 pr_cont(" %0*lx", field, stackdata); 195 i++; 196 } 197 pr_cont("\n"); 198 show_backtrace(task, regs, loglvl); 199 } 200 201 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl) 202 { 203 struct pt_regs regs; 204 mm_segment_t old_fs = get_fs(); 205 206 regs.cp0_status = KSU_KERNEL; 207 if (sp) { 208 regs.regs[29] = (unsigned long)sp; 209 regs.regs[31] = 0; 210 regs.cp0_epc = 0; 211 } else { 212 if (task && task != current) { 213 regs.regs[29] = task->thread.reg29; 214 regs.regs[31] = 0; 215 regs.cp0_epc = task->thread.reg31; 216 } else { 217 prepare_frametrace(®s); 218 } 219 } 220 /* 221 * show_stack() deals exclusively with kernel mode, so be sure to access 222 * the stack in the kernel (not user) address space. 223 */ 224 set_fs(KERNEL_DS); 225 show_stacktrace(task, ®s, loglvl); 226 set_fs(old_fs); 227 } 228 229 static void show_code(unsigned int __user *pc) 230 { 231 long i; 232 unsigned short __user *pc16 = NULL; 233 234 printk("Code:"); 235 236 if ((unsigned long)pc & 1) 237 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 238 for(i = -3 ; i < 6 ; i++) { 239 unsigned int insn; 240 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 241 pr_cont(" (Bad address in epc)\n"); 242 break; 243 } 244 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 245 } 246 pr_cont("\n"); 247 } 248 249 static void __show_regs(const struct pt_regs *regs) 250 { 251 const int field = 2 * sizeof(unsigned long); 252 unsigned int cause = regs->cp0_cause; 253 unsigned int exccode; 254 int i; 255 256 show_regs_print_info(KERN_DEFAULT); 257 258 /* 259 * Saved main processor registers 260 */ 261 for (i = 0; i < 32; ) { 262 if ((i % 4) == 0) 263 printk("$%2d :", i); 264 if (i == 0) 265 pr_cont(" %0*lx", field, 0UL); 266 else if (i == 26 || i == 27) 267 pr_cont(" %*s", field, ""); 268 else 269 pr_cont(" %0*lx", field, regs->regs[i]); 270 271 i++; 272 if ((i % 4) == 0) 273 pr_cont("\n"); 274 } 275 276 #ifdef CONFIG_CPU_HAS_SMARTMIPS 277 printk("Acx : %0*lx\n", field, regs->acx); 278 #endif 279 if (MIPS_ISA_REV < 6) { 280 printk("Hi : %0*lx\n", field, regs->hi); 281 printk("Lo : %0*lx\n", field, regs->lo); 282 } 283 284 /* 285 * Saved cp0 registers 286 */ 287 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 288 (void *) regs->cp0_epc); 289 printk("ra : %0*lx %pS\n", field, regs->regs[31], 290 (void *) regs->regs[31]); 291 292 printk("Status: %08x ", (uint32_t) regs->cp0_status); 293 294 if (cpu_has_3kex) { 295 if (regs->cp0_status & ST0_KUO) 296 pr_cont("KUo "); 297 if (regs->cp0_status & ST0_IEO) 298 pr_cont("IEo "); 299 if (regs->cp0_status & ST0_KUP) 300 pr_cont("KUp "); 301 if (regs->cp0_status & ST0_IEP) 302 pr_cont("IEp "); 303 if (regs->cp0_status & ST0_KUC) 304 pr_cont("KUc "); 305 if (regs->cp0_status & ST0_IEC) 306 pr_cont("IEc "); 307 } else if (cpu_has_4kex) { 308 if (regs->cp0_status & ST0_KX) 309 pr_cont("KX "); 310 if (regs->cp0_status & ST0_SX) 311 pr_cont("SX "); 312 if (regs->cp0_status & ST0_UX) 313 pr_cont("UX "); 314 switch (regs->cp0_status & ST0_KSU) { 315 case KSU_USER: 316 pr_cont("USER "); 317 break; 318 case KSU_SUPERVISOR: 319 pr_cont("SUPERVISOR "); 320 break; 321 case KSU_KERNEL: 322 pr_cont("KERNEL "); 323 break; 324 default: 325 pr_cont("BAD_MODE "); 326 break; 327 } 328 if (regs->cp0_status & ST0_ERL) 329 pr_cont("ERL "); 330 if (regs->cp0_status & ST0_EXL) 331 pr_cont("EXL "); 332 if (regs->cp0_status & ST0_IE) 333 pr_cont("IE "); 334 } 335 pr_cont("\n"); 336 337 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 338 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode); 339 340 if (1 <= exccode && exccode <= 5) 341 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 342 343 printk("PrId : %08x (%s)\n", read_c0_prid(), 344 cpu_name_string()); 345 } 346 347 /* 348 * FIXME: really the generic show_regs should take a const pointer argument. 349 */ 350 void show_regs(struct pt_regs *regs) 351 { 352 __show_regs(regs); 353 dump_stack(); 354 } 355 356 void show_registers(struct pt_regs *regs) 357 { 358 const int field = 2 * sizeof(unsigned long); 359 mm_segment_t old_fs = get_fs(); 360 361 __show_regs(regs); 362 print_modules(); 363 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 364 current->comm, current->pid, current_thread_info(), current, 365 field, current_thread_info()->tp_value); 366 if (cpu_has_userlocal) { 367 unsigned long tls; 368 369 tls = read_c0_userlocal(); 370 if (tls != current_thread_info()->tp_value) 371 printk("*HwTLS: %0*lx\n", field, tls); 372 } 373 374 if (!user_mode(regs)) 375 /* Necessary for getting the correct stack content */ 376 set_fs(KERNEL_DS); 377 show_stacktrace(current, regs, KERN_DEFAULT); 378 show_code((unsigned int __user *) regs->cp0_epc); 379 printk("\n"); 380 set_fs(old_fs); 381 } 382 383 static DEFINE_RAW_SPINLOCK(die_lock); 384 385 void __noreturn die(const char *str, struct pt_regs *regs) 386 { 387 static int die_counter; 388 int sig = SIGSEGV; 389 390 oops_enter(); 391 392 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, 393 SIGSEGV) == NOTIFY_STOP) 394 sig = 0; 395 396 console_verbose(); 397 raw_spin_lock_irq(&die_lock); 398 bust_spinlocks(1); 399 400 printk("%s[#%d]:\n", str, ++die_counter); 401 show_registers(regs); 402 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 403 raw_spin_unlock_irq(&die_lock); 404 405 oops_exit(); 406 407 if (in_interrupt()) 408 panic("Fatal exception in interrupt"); 409 410 if (panic_on_oops) 411 panic("Fatal exception"); 412 413 if (regs && kexec_should_crash(current)) 414 crash_kexec(regs); 415 416 do_exit(sig); 417 } 418 419 extern struct exception_table_entry __start___dbe_table[]; 420 extern struct exception_table_entry __stop___dbe_table[]; 421 422 __asm__( 423 " .section __dbe_table, \"a\"\n" 424 " .previous \n"); 425 426 /* Given an address, look for it in the exception tables. */ 427 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 428 { 429 const struct exception_table_entry *e; 430 431 e = search_extable(__start___dbe_table, 432 __stop___dbe_table - __start___dbe_table, addr); 433 if (!e) 434 e = search_module_dbetables(addr); 435 return e; 436 } 437 438 asmlinkage void do_be(struct pt_regs *regs) 439 { 440 const int field = 2 * sizeof(unsigned long); 441 const struct exception_table_entry *fixup = NULL; 442 int data = regs->cp0_cause & 4; 443 int action = MIPS_BE_FATAL; 444 enum ctx_state prev_state; 445 446 prev_state = exception_enter(); 447 /* XXX For now. Fixme, this searches the wrong table ... */ 448 if (data && !user_mode(regs)) 449 fixup = search_dbe_tables(exception_epc(regs)); 450 451 if (fixup) 452 action = MIPS_BE_FIXUP; 453 454 if (board_be_handler) 455 action = board_be_handler(regs, fixup != NULL); 456 else 457 mips_cm_error_report(); 458 459 switch (action) { 460 case MIPS_BE_DISCARD: 461 goto out; 462 case MIPS_BE_FIXUP: 463 if (fixup) { 464 regs->cp0_epc = fixup->nextinsn; 465 goto out; 466 } 467 break; 468 default: 469 break; 470 } 471 472 /* 473 * Assume it would be too dangerous to continue ... 474 */ 475 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 476 data ? "Data" : "Instruction", 477 field, regs->cp0_epc, field, regs->regs[31]); 478 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr, 479 SIGBUS) == NOTIFY_STOP) 480 goto out; 481 482 die_if_kernel("Oops", regs); 483 force_sig(SIGBUS); 484 485 out: 486 exception_exit(prev_state); 487 } 488 489 /* 490 * ll/sc, rdhwr, sync emulation 491 */ 492 493 #define OPCODE 0xfc000000 494 #define BASE 0x03e00000 495 #define RT 0x001f0000 496 #define OFFSET 0x0000ffff 497 #define LL 0xc0000000 498 #define SC 0xe0000000 499 #define SPEC0 0x00000000 500 #define SPEC3 0x7c000000 501 #define RD 0x0000f800 502 #define FUNC 0x0000003f 503 #define SYNC 0x0000000f 504 #define RDHWR 0x0000003b 505 506 /* microMIPS definitions */ 507 #define MM_POOL32A_FUNC 0xfc00ffff 508 #define MM_RDHWR 0x00006b3c 509 #define MM_RS 0x001f0000 510 #define MM_RT 0x03e00000 511 512 /* 513 * The ll_bit is cleared by r*_switch.S 514 */ 515 516 unsigned int ll_bit; 517 struct task_struct *ll_task; 518 519 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 520 { 521 unsigned long value, __user *vaddr; 522 long offset; 523 524 /* 525 * analyse the ll instruction that just caused a ri exception 526 * and put the referenced address to addr. 527 */ 528 529 /* sign extend offset */ 530 offset = opcode & OFFSET; 531 offset <<= 16; 532 offset >>= 16; 533 534 vaddr = (unsigned long __user *) 535 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 536 537 if ((unsigned long)vaddr & 3) 538 return SIGBUS; 539 if (get_user(value, vaddr)) 540 return SIGSEGV; 541 542 preempt_disable(); 543 544 if (ll_task == NULL || ll_task == current) { 545 ll_bit = 1; 546 } else { 547 ll_bit = 0; 548 } 549 ll_task = current; 550 551 preempt_enable(); 552 553 regs->regs[(opcode & RT) >> 16] = value; 554 555 return 0; 556 } 557 558 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 559 { 560 unsigned long __user *vaddr; 561 unsigned long reg; 562 long offset; 563 564 /* 565 * analyse the sc instruction that just caused a ri exception 566 * and put the referenced address to addr. 567 */ 568 569 /* sign extend offset */ 570 offset = opcode & OFFSET; 571 offset <<= 16; 572 offset >>= 16; 573 574 vaddr = (unsigned long __user *) 575 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 576 reg = (opcode & RT) >> 16; 577 578 if ((unsigned long)vaddr & 3) 579 return SIGBUS; 580 581 preempt_disable(); 582 583 if (ll_bit == 0 || ll_task != current) { 584 regs->regs[reg] = 0; 585 preempt_enable(); 586 return 0; 587 } 588 589 preempt_enable(); 590 591 if (put_user(regs->regs[reg], vaddr)) 592 return SIGSEGV; 593 594 regs->regs[reg] = 1; 595 596 return 0; 597 } 598 599 /* 600 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 601 * opcodes are supposed to result in coprocessor unusable exceptions if 602 * executed on ll/sc-less processors. That's the theory. In practice a 603 * few processors such as NEC's VR4100 throw reserved instruction exceptions 604 * instead, so we're doing the emulation thing in both exception handlers. 605 */ 606 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 607 { 608 if ((opcode & OPCODE) == LL) { 609 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 610 1, regs, 0); 611 return simulate_ll(regs, opcode); 612 } 613 if ((opcode & OPCODE) == SC) { 614 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 615 1, regs, 0); 616 return simulate_sc(regs, opcode); 617 } 618 619 return -1; /* Must be something else ... */ 620 } 621 622 /* 623 * Simulate trapping 'rdhwr' instructions to provide user accessible 624 * registers not implemented in hardware. 625 */ 626 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) 627 { 628 struct thread_info *ti = task_thread_info(current); 629 630 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 631 1, regs, 0); 632 switch (rd) { 633 case MIPS_HWR_CPUNUM: /* CPU number */ 634 regs->regs[rt] = smp_processor_id(); 635 return 0; 636 case MIPS_HWR_SYNCISTEP: /* SYNCI length */ 637 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 638 current_cpu_data.icache.linesz); 639 return 0; 640 case MIPS_HWR_CC: /* Read count register */ 641 regs->regs[rt] = read_c0_count(); 642 return 0; 643 case MIPS_HWR_CCRES: /* Count register resolution */ 644 switch (current_cpu_type()) { 645 case CPU_20KC: 646 case CPU_25KF: 647 regs->regs[rt] = 1; 648 break; 649 default: 650 regs->regs[rt] = 2; 651 } 652 return 0; 653 case MIPS_HWR_ULR: /* Read UserLocal register */ 654 regs->regs[rt] = ti->tp_value; 655 return 0; 656 default: 657 return -1; 658 } 659 } 660 661 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) 662 { 663 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 664 int rd = (opcode & RD) >> 11; 665 int rt = (opcode & RT) >> 16; 666 667 simulate_rdhwr(regs, rd, rt); 668 return 0; 669 } 670 671 /* Not ours. */ 672 return -1; 673 } 674 675 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode) 676 { 677 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { 678 int rd = (opcode & MM_RS) >> 16; 679 int rt = (opcode & MM_RT) >> 21; 680 simulate_rdhwr(regs, rd, rt); 681 return 0; 682 } 683 684 /* Not ours. */ 685 return -1; 686 } 687 688 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 689 { 690 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 691 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 692 1, regs, 0); 693 return 0; 694 } 695 696 return -1; /* Must be something else ... */ 697 } 698 699 /* 700 * Loongson-3 CSR instructions emulation 701 */ 702 703 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION 704 705 #define LWC2 0xc8000000 706 #define RS BASE 707 #define CSR_OPCODE2 0x00000118 708 #define CSR_OPCODE2_MASK 0x000007ff 709 #define CSR_FUNC_MASK RT 710 #define CSR_FUNC_CPUCFG 0x8 711 712 static int simulate_loongson3_cpucfg(struct pt_regs *regs, 713 unsigned int opcode) 714 { 715 int op = opcode & OPCODE; 716 int op2 = opcode & CSR_OPCODE2_MASK; 717 int csr_func = (opcode & CSR_FUNC_MASK) >> 16; 718 719 if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) { 720 int rd = (opcode & RD) >> 11; 721 int rs = (opcode & RS) >> 21; 722 __u64 sel = regs->regs[rs]; 723 724 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0); 725 726 /* Do not emulate on unsupported core models. */ 727 if (!loongson3_cpucfg_emulation_enabled(¤t_cpu_data)) 728 return -1; 729 730 regs->regs[rd] = loongson3_cpucfg_read_synthesized( 731 ¤t_cpu_data, sel); 732 733 return 0; 734 } 735 736 /* Not ours. */ 737 return -1; 738 } 739 #endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */ 740 741 asmlinkage void do_ov(struct pt_regs *regs) 742 { 743 enum ctx_state prev_state; 744 745 prev_state = exception_enter(); 746 die_if_kernel("Integer overflow", regs); 747 748 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc); 749 exception_exit(prev_state); 750 } 751 752 #ifdef CONFIG_MIPS_FP_SUPPORT 753 754 /* 755 * Send SIGFPE according to FCSR Cause bits, which must have already 756 * been masked against Enable bits. This is impotant as Inexact can 757 * happen together with Overflow or Underflow, and `ptrace' can set 758 * any bits. 759 */ 760 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr, 761 struct task_struct *tsk) 762 { 763 int si_code = FPE_FLTUNK; 764 765 if (fcr31 & FPU_CSR_INV_X) 766 si_code = FPE_FLTINV; 767 else if (fcr31 & FPU_CSR_DIV_X) 768 si_code = FPE_FLTDIV; 769 else if (fcr31 & FPU_CSR_OVF_X) 770 si_code = FPE_FLTOVF; 771 else if (fcr31 & FPU_CSR_UDF_X) 772 si_code = FPE_FLTUND; 773 else if (fcr31 & FPU_CSR_INE_X) 774 si_code = FPE_FLTRES; 775 776 force_sig_fault_to_task(SIGFPE, si_code, fault_addr, tsk); 777 } 778 779 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31) 780 { 781 int si_code; 782 struct vm_area_struct *vma; 783 784 switch (sig) { 785 case 0: 786 return 0; 787 788 case SIGFPE: 789 force_fcr31_sig(fcr31, fault_addr, current); 790 return 1; 791 792 case SIGBUS: 793 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr); 794 return 1; 795 796 case SIGSEGV: 797 mmap_read_lock(current->mm); 798 vma = find_vma(current->mm, (unsigned long)fault_addr); 799 if (vma && (vma->vm_start <= (unsigned long)fault_addr)) 800 si_code = SEGV_ACCERR; 801 else 802 si_code = SEGV_MAPERR; 803 mmap_read_unlock(current->mm); 804 force_sig_fault(SIGSEGV, si_code, fault_addr); 805 return 1; 806 807 default: 808 force_sig(sig); 809 return 1; 810 } 811 } 812 813 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 814 unsigned long old_epc, unsigned long old_ra) 815 { 816 union mips_instruction inst = { .word = opcode }; 817 void __user *fault_addr; 818 unsigned long fcr31; 819 int sig; 820 821 /* If it's obviously not an FP instruction, skip it */ 822 switch (inst.i_format.opcode) { 823 case cop1_op: 824 case cop1x_op: 825 case lwc1_op: 826 case ldc1_op: 827 case swc1_op: 828 case sdc1_op: 829 break; 830 831 default: 832 return -1; 833 } 834 835 /* 836 * do_ri skipped over the instruction via compute_return_epc, undo 837 * that for the FPU emulator. 838 */ 839 regs->cp0_epc = old_epc; 840 regs->regs[31] = old_ra; 841 842 /* Run the emulator */ 843 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 844 &fault_addr); 845 846 /* 847 * We can't allow the emulated instruction to leave any 848 * enabled Cause bits set in $fcr31. 849 */ 850 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 851 current->thread.fpu.fcr31 &= ~fcr31; 852 853 /* Restore the hardware register state */ 854 own_fpu(1); 855 856 /* Send a signal if required. */ 857 process_fpemu_return(sig, fault_addr, fcr31); 858 859 return 0; 860 } 861 862 /* 863 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 864 */ 865 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 866 { 867 enum ctx_state prev_state; 868 void __user *fault_addr; 869 int sig; 870 871 prev_state = exception_enter(); 872 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, 873 SIGFPE) == NOTIFY_STOP) 874 goto out; 875 876 /* Clear FCSR.Cause before enabling interrupts */ 877 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31)); 878 local_irq_enable(); 879 880 die_if_kernel("FP exception in kernel code", regs); 881 882 if (fcr31 & FPU_CSR_UNI_X) { 883 /* 884 * Unimplemented operation exception. If we've got the full 885 * software emulator on-board, let's use it... 886 * 887 * Force FPU to dump state into task/thread context. We're 888 * moving a lot of data here for what is probably a single 889 * instruction, but the alternative is to pre-decode the FP 890 * register operands before invoking the emulator, which seems 891 * a bit extreme for what should be an infrequent event. 892 */ 893 894 /* Run the emulator */ 895 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 896 &fault_addr); 897 898 /* 899 * We can't allow the emulated instruction to leave any 900 * enabled Cause bits set in $fcr31. 901 */ 902 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 903 current->thread.fpu.fcr31 &= ~fcr31; 904 905 /* Restore the hardware register state */ 906 own_fpu(1); /* Using the FPU again. */ 907 } else { 908 sig = SIGFPE; 909 fault_addr = (void __user *) regs->cp0_epc; 910 } 911 912 /* Send a signal if required. */ 913 process_fpemu_return(sig, fault_addr, fcr31); 914 915 out: 916 exception_exit(prev_state); 917 } 918 919 /* 920 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 921 * emulated more than some threshold number of instructions, force migration to 922 * a "CPU" that has FP support. 923 */ 924 static void mt_ase_fp_affinity(void) 925 { 926 #ifdef CONFIG_MIPS_MT_FPAFF 927 if (mt_fpemul_threshold > 0 && 928 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 929 /* 930 * If there's no FPU present, or if the application has already 931 * restricted the allowed set to exclude any CPUs with FPUs, 932 * we'll skip the procedure. 933 */ 934 if (cpumask_intersects(¤t->cpus_mask, &mt_fpu_cpumask)) { 935 cpumask_t tmask; 936 937 current->thread.user_cpus_allowed 938 = current->cpus_mask; 939 cpumask_and(&tmask, ¤t->cpus_mask, 940 &mt_fpu_cpumask); 941 set_cpus_allowed_ptr(current, &tmask); 942 set_thread_flag(TIF_FPUBOUND); 943 } 944 } 945 #endif /* CONFIG_MIPS_MT_FPAFF */ 946 } 947 948 #else /* !CONFIG_MIPS_FP_SUPPORT */ 949 950 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 951 unsigned long old_epc, unsigned long old_ra) 952 { 953 return -1; 954 } 955 956 #endif /* !CONFIG_MIPS_FP_SUPPORT */ 957 958 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code, 959 const char *str) 960 { 961 char b[40]; 962 963 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 964 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr, 965 SIGTRAP) == NOTIFY_STOP) 966 return; 967 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 968 969 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr, 970 SIGTRAP) == NOTIFY_STOP) 971 return; 972 973 /* 974 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 975 * insns, even for trap and break codes that indicate arithmetic 976 * failures. Weird ... 977 * But should we continue the brokenness??? --macro 978 */ 979 switch (code) { 980 case BRK_OVERFLOW: 981 case BRK_DIVZERO: 982 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 983 die_if_kernel(b, regs); 984 force_sig_fault(SIGFPE, 985 code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF, 986 (void __user *) regs->cp0_epc); 987 break; 988 case BRK_BUG: 989 die_if_kernel("Kernel bug detected", regs); 990 force_sig(SIGTRAP); 991 break; 992 case BRK_MEMU: 993 /* 994 * This breakpoint code is used by the FPU emulator to retake 995 * control of the CPU after executing the instruction from the 996 * delay slot of an emulated branch. 997 * 998 * Terminate if exception was recognized as a delay slot return 999 * otherwise handle as normal. 1000 */ 1001 if (do_dsemulret(regs)) 1002 return; 1003 1004 die_if_kernel("Math emu break/trap", regs); 1005 force_sig(SIGTRAP); 1006 break; 1007 default: 1008 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 1009 die_if_kernel(b, regs); 1010 if (si_code) { 1011 force_sig_fault(SIGTRAP, si_code, NULL); 1012 } else { 1013 force_sig(SIGTRAP); 1014 } 1015 } 1016 } 1017 1018 asmlinkage void do_bp(struct pt_regs *regs) 1019 { 1020 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 1021 unsigned int opcode, bcode; 1022 enum ctx_state prev_state; 1023 mm_segment_t seg; 1024 1025 seg = get_fs(); 1026 if (!user_mode(regs)) 1027 set_fs(KERNEL_DS); 1028 1029 prev_state = exception_enter(); 1030 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1031 if (get_isa16_mode(regs->cp0_epc)) { 1032 u16 instr[2]; 1033 1034 if (__get_user(instr[0], (u16 __user *)epc)) 1035 goto out_sigsegv; 1036 1037 if (!cpu_has_mmips) { 1038 /* MIPS16e mode */ 1039 bcode = (instr[0] >> 5) & 0x3f; 1040 } else if (mm_insn_16bit(instr[0])) { 1041 /* 16-bit microMIPS BREAK */ 1042 bcode = instr[0] & 0xf; 1043 } else { 1044 /* 32-bit microMIPS BREAK */ 1045 if (__get_user(instr[1], (u16 __user *)(epc + 2))) 1046 goto out_sigsegv; 1047 opcode = (instr[0] << 16) | instr[1]; 1048 bcode = (opcode >> 6) & ((1 << 20) - 1); 1049 } 1050 } else { 1051 if (__get_user(opcode, (unsigned int __user *)epc)) 1052 goto out_sigsegv; 1053 bcode = (opcode >> 6) & ((1 << 20) - 1); 1054 } 1055 1056 /* 1057 * There is the ancient bug in the MIPS assemblers that the break 1058 * code starts left to bit 16 instead to bit 6 in the opcode. 1059 * Gas is bug-compatible, but not always, grrr... 1060 * We handle both cases with a simple heuristics. --macro 1061 */ 1062 if (bcode >= (1 << 10)) 1063 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10); 1064 1065 /* 1066 * notify the kprobe handlers, if instruction is likely to 1067 * pertain to them. 1068 */ 1069 switch (bcode) { 1070 case BRK_UPROBE: 1071 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode, 1072 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1073 goto out; 1074 else 1075 break; 1076 case BRK_UPROBE_XOL: 1077 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode, 1078 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1079 goto out; 1080 else 1081 break; 1082 case BRK_KPROBE_BP: 1083 if (notify_die(DIE_BREAK, "debug", regs, bcode, 1084 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1085 goto out; 1086 else 1087 break; 1088 case BRK_KPROBE_SSTEPBP: 1089 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 1090 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1091 goto out; 1092 else 1093 break; 1094 default: 1095 break; 1096 } 1097 1098 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break"); 1099 1100 out: 1101 set_fs(seg); 1102 exception_exit(prev_state); 1103 return; 1104 1105 out_sigsegv: 1106 force_sig(SIGSEGV); 1107 goto out; 1108 } 1109 1110 asmlinkage void do_tr(struct pt_regs *regs) 1111 { 1112 u32 opcode, tcode = 0; 1113 enum ctx_state prev_state; 1114 u16 instr[2]; 1115 mm_segment_t seg; 1116 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 1117 1118 seg = get_fs(); 1119 if (!user_mode(regs)) 1120 set_fs(KERNEL_DS); 1121 1122 prev_state = exception_enter(); 1123 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1124 if (get_isa16_mode(regs->cp0_epc)) { 1125 if (__get_user(instr[0], (u16 __user *)(epc + 0)) || 1126 __get_user(instr[1], (u16 __user *)(epc + 2))) 1127 goto out_sigsegv; 1128 opcode = (instr[0] << 16) | instr[1]; 1129 /* Immediate versions don't provide a code. */ 1130 if (!(opcode & OPCODE)) 1131 tcode = (opcode >> 12) & ((1 << 4) - 1); 1132 } else { 1133 if (__get_user(opcode, (u32 __user *)epc)) 1134 goto out_sigsegv; 1135 /* Immediate versions don't provide a code. */ 1136 if (!(opcode & OPCODE)) 1137 tcode = (opcode >> 6) & ((1 << 10) - 1); 1138 } 1139 1140 do_trap_or_bp(regs, tcode, 0, "Trap"); 1141 1142 out: 1143 set_fs(seg); 1144 exception_exit(prev_state); 1145 return; 1146 1147 out_sigsegv: 1148 force_sig(SIGSEGV); 1149 goto out; 1150 } 1151 1152 asmlinkage void do_ri(struct pt_regs *regs) 1153 { 1154 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 1155 unsigned long old_epc = regs->cp0_epc; 1156 unsigned long old31 = regs->regs[31]; 1157 enum ctx_state prev_state; 1158 unsigned int opcode = 0; 1159 int status = -1; 1160 1161 /* 1162 * Avoid any kernel code. Just emulate the R2 instruction 1163 * as quickly as possible. 1164 */ 1165 if (mipsr2_emulation && cpu_has_mips_r6 && 1166 likely(user_mode(regs)) && 1167 likely(get_user(opcode, epc) >= 0)) { 1168 unsigned long fcr31 = 0; 1169 1170 status = mipsr2_decoder(regs, opcode, &fcr31); 1171 switch (status) { 1172 case 0: 1173 case SIGEMT: 1174 return; 1175 case SIGILL: 1176 goto no_r2_instr; 1177 default: 1178 process_fpemu_return(status, 1179 ¤t->thread.cp0_baduaddr, 1180 fcr31); 1181 return; 1182 } 1183 } 1184 1185 no_r2_instr: 1186 1187 prev_state = exception_enter(); 1188 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1189 1190 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, 1191 SIGILL) == NOTIFY_STOP) 1192 goto out; 1193 1194 die_if_kernel("Reserved instruction in kernel code", regs); 1195 1196 if (unlikely(compute_return_epc(regs) < 0)) 1197 goto out; 1198 1199 if (!get_isa16_mode(regs->cp0_epc)) { 1200 if (unlikely(get_user(opcode, epc) < 0)) 1201 status = SIGSEGV; 1202 1203 if (!cpu_has_llsc && status < 0) 1204 status = simulate_llsc(regs, opcode); 1205 1206 if (status < 0) 1207 status = simulate_rdhwr_normal(regs, opcode); 1208 1209 if (status < 0) 1210 status = simulate_sync(regs, opcode); 1211 1212 if (status < 0) 1213 status = simulate_fp(regs, opcode, old_epc, old31); 1214 1215 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION 1216 if (status < 0) 1217 status = simulate_loongson3_cpucfg(regs, opcode); 1218 #endif 1219 } else if (cpu_has_mmips) { 1220 unsigned short mmop[2] = { 0 }; 1221 1222 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0)) 1223 status = SIGSEGV; 1224 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0)) 1225 status = SIGSEGV; 1226 opcode = mmop[0]; 1227 opcode = (opcode << 16) | mmop[1]; 1228 1229 if (status < 0) 1230 status = simulate_rdhwr_mm(regs, opcode); 1231 } 1232 1233 if (status < 0) 1234 status = SIGILL; 1235 1236 if (unlikely(status > 0)) { 1237 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1238 regs->regs[31] = old31; 1239 force_sig(status); 1240 } 1241 1242 out: 1243 exception_exit(prev_state); 1244 } 1245 1246 /* 1247 * No lock; only written during early bootup by CPU 0. 1248 */ 1249 static RAW_NOTIFIER_HEAD(cu2_chain); 1250 1251 int __ref register_cu2_notifier(struct notifier_block *nb) 1252 { 1253 return raw_notifier_chain_register(&cu2_chain, nb); 1254 } 1255 1256 int cu2_notifier_call_chain(unsigned long val, void *v) 1257 { 1258 return raw_notifier_call_chain(&cu2_chain, val, v); 1259 } 1260 1261 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 1262 void *data) 1263 { 1264 struct pt_regs *regs = data; 1265 1266 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " 1267 "instruction", regs); 1268 force_sig(SIGILL); 1269 1270 return NOTIFY_OK; 1271 } 1272 1273 #ifdef CONFIG_MIPS_FP_SUPPORT 1274 1275 static int enable_restore_fp_context(int msa) 1276 { 1277 int err, was_fpu_owner, prior_msa; 1278 bool first_fp; 1279 1280 /* Initialize context if it hasn't been used already */ 1281 first_fp = init_fp_ctx(current); 1282 1283 if (first_fp) { 1284 preempt_disable(); 1285 err = own_fpu_inatomic(1); 1286 if (msa && !err) { 1287 enable_msa(); 1288 set_thread_flag(TIF_USEDMSA); 1289 set_thread_flag(TIF_MSA_CTX_LIVE); 1290 } 1291 preempt_enable(); 1292 return err; 1293 } 1294 1295 /* 1296 * This task has formerly used the FP context. 1297 * 1298 * If this thread has no live MSA vector context then we can simply 1299 * restore the scalar FP context. If it has live MSA vector context 1300 * (that is, it has or may have used MSA since last performing a 1301 * function call) then we'll need to restore the vector context. This 1302 * applies even if we're currently only executing a scalar FP 1303 * instruction. This is because if we were to later execute an MSA 1304 * instruction then we'd either have to: 1305 * 1306 * - Restore the vector context & clobber any registers modified by 1307 * scalar FP instructions between now & then. 1308 * 1309 * or 1310 * 1311 * - Not restore the vector context & lose the most significant bits 1312 * of all vector registers. 1313 * 1314 * Neither of those options is acceptable. We cannot restore the least 1315 * significant bits of the registers now & only restore the most 1316 * significant bits later because the most significant bits of any 1317 * vector registers whose aliased FP register is modified now will have 1318 * been zeroed. We'd have no way to know that when restoring the vector 1319 * context & thus may load an outdated value for the most significant 1320 * bits of a vector register. 1321 */ 1322 if (!msa && !thread_msa_context_live()) 1323 return own_fpu(1); 1324 1325 /* 1326 * This task is using or has previously used MSA. Thus we require 1327 * that Status.FR == 1. 1328 */ 1329 preempt_disable(); 1330 was_fpu_owner = is_fpu_owner(); 1331 err = own_fpu_inatomic(0); 1332 if (err) 1333 goto out; 1334 1335 enable_msa(); 1336 write_msa_csr(current->thread.fpu.msacsr); 1337 set_thread_flag(TIF_USEDMSA); 1338 1339 /* 1340 * If this is the first time that the task is using MSA and it has 1341 * previously used scalar FP in this time slice then we already nave 1342 * FP context which we shouldn't clobber. We do however need to clear 1343 * the upper 64b of each vector register so that this task has no 1344 * opportunity to see data left behind by another. 1345 */ 1346 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); 1347 if (!prior_msa && was_fpu_owner) { 1348 init_msa_upper(); 1349 1350 goto out; 1351 } 1352 1353 if (!prior_msa) { 1354 /* 1355 * Restore the least significant 64b of each vector register 1356 * from the existing scalar FP context. 1357 */ 1358 _restore_fp(current); 1359 1360 /* 1361 * The task has not formerly used MSA, so clear the upper 64b 1362 * of each vector register such that it cannot see data left 1363 * behind by another task. 1364 */ 1365 init_msa_upper(); 1366 } else { 1367 /* We need to restore the vector context. */ 1368 restore_msa(current); 1369 1370 /* Restore the scalar FP control & status register */ 1371 if (!was_fpu_owner) 1372 write_32bit_cp1_register(CP1_STATUS, 1373 current->thread.fpu.fcr31); 1374 } 1375 1376 out: 1377 preempt_enable(); 1378 1379 return 0; 1380 } 1381 1382 #else /* !CONFIG_MIPS_FP_SUPPORT */ 1383 1384 static int enable_restore_fp_context(int msa) 1385 { 1386 return SIGILL; 1387 } 1388 1389 #endif /* CONFIG_MIPS_FP_SUPPORT */ 1390 1391 asmlinkage void do_cpu(struct pt_regs *regs) 1392 { 1393 enum ctx_state prev_state; 1394 unsigned int __user *epc; 1395 unsigned long old_epc, old31; 1396 unsigned int opcode; 1397 unsigned int cpid; 1398 int status; 1399 1400 prev_state = exception_enter(); 1401 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1402 1403 if (cpid != 2) 1404 die_if_kernel("do_cpu invoked from kernel context!", regs); 1405 1406 switch (cpid) { 1407 case 0: 1408 epc = (unsigned int __user *)exception_epc(regs); 1409 old_epc = regs->cp0_epc; 1410 old31 = regs->regs[31]; 1411 opcode = 0; 1412 status = -1; 1413 1414 if (unlikely(compute_return_epc(regs) < 0)) 1415 break; 1416 1417 if (!get_isa16_mode(regs->cp0_epc)) { 1418 if (unlikely(get_user(opcode, epc) < 0)) 1419 status = SIGSEGV; 1420 1421 if (!cpu_has_llsc && status < 0) 1422 status = simulate_llsc(regs, opcode); 1423 } 1424 1425 if (status < 0) 1426 status = SIGILL; 1427 1428 if (unlikely(status > 0)) { 1429 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1430 regs->regs[31] = old31; 1431 force_sig(status); 1432 } 1433 1434 break; 1435 1436 #ifdef CONFIG_MIPS_FP_SUPPORT 1437 case 3: 1438 /* 1439 * The COP3 opcode space and consequently the CP0.Status.CU3 1440 * bit and the CP0.Cause.CE=3 encoding have been removed as 1441 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs 1442 * up the space has been reused for COP1X instructions, that 1443 * are enabled by the CP0.Status.CU1 bit and consequently 1444 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable 1445 * exceptions. Some FPU-less processors that implement one 1446 * of these ISAs however use this code erroneously for COP1X 1447 * instructions. Therefore we redirect this trap to the FP 1448 * emulator too. 1449 */ 1450 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) { 1451 force_sig(SIGILL); 1452 break; 1453 } 1454 fallthrough; 1455 case 1: { 1456 void __user *fault_addr; 1457 unsigned long fcr31; 1458 int err, sig; 1459 1460 err = enable_restore_fp_context(0); 1461 1462 if (raw_cpu_has_fpu && !err) 1463 break; 1464 1465 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, 1466 &fault_addr); 1467 1468 /* 1469 * We can't allow the emulated instruction to leave 1470 * any enabled Cause bits set in $fcr31. 1471 */ 1472 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 1473 current->thread.fpu.fcr31 &= ~fcr31; 1474 1475 /* Send a signal if required. */ 1476 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err) 1477 mt_ase_fp_affinity(); 1478 1479 break; 1480 } 1481 #else /* CONFIG_MIPS_FP_SUPPORT */ 1482 case 1: 1483 case 3: 1484 force_sig(SIGILL); 1485 break; 1486 #endif /* CONFIG_MIPS_FP_SUPPORT */ 1487 1488 case 2: 1489 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1490 break; 1491 } 1492 1493 exception_exit(prev_state); 1494 } 1495 1496 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr) 1497 { 1498 enum ctx_state prev_state; 1499 1500 prev_state = exception_enter(); 1501 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1502 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0, 1503 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP) 1504 goto out; 1505 1506 /* Clear MSACSR.Cause before enabling interrupts */ 1507 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF); 1508 local_irq_enable(); 1509 1510 die_if_kernel("do_msa_fpe invoked from kernel context!", regs); 1511 force_sig(SIGFPE); 1512 out: 1513 exception_exit(prev_state); 1514 } 1515 1516 asmlinkage void do_msa(struct pt_regs *regs) 1517 { 1518 enum ctx_state prev_state; 1519 int err; 1520 1521 prev_state = exception_enter(); 1522 1523 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { 1524 force_sig(SIGILL); 1525 goto out; 1526 } 1527 1528 die_if_kernel("do_msa invoked from kernel context!", regs); 1529 1530 err = enable_restore_fp_context(1); 1531 if (err) 1532 force_sig(SIGILL); 1533 out: 1534 exception_exit(prev_state); 1535 } 1536 1537 asmlinkage void do_mdmx(struct pt_regs *regs) 1538 { 1539 enum ctx_state prev_state; 1540 1541 prev_state = exception_enter(); 1542 force_sig(SIGILL); 1543 exception_exit(prev_state); 1544 } 1545 1546 /* 1547 * Called with interrupts disabled. 1548 */ 1549 asmlinkage void do_watch(struct pt_regs *regs) 1550 { 1551 enum ctx_state prev_state; 1552 1553 prev_state = exception_enter(); 1554 /* 1555 * Clear WP (bit 22) bit of cause register so we don't loop 1556 * forever. 1557 */ 1558 clear_c0_cause(CAUSEF_WP); 1559 1560 /* 1561 * If the current thread has the watch registers loaded, save 1562 * their values and send SIGTRAP. Otherwise another thread 1563 * left the registers set, clear them and continue. 1564 */ 1565 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1566 mips_read_watch_registers(); 1567 local_irq_enable(); 1568 force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL); 1569 } else { 1570 mips_clear_watch_registers(); 1571 local_irq_enable(); 1572 } 1573 exception_exit(prev_state); 1574 } 1575 1576 asmlinkage void do_mcheck(struct pt_regs *regs) 1577 { 1578 int multi_match = regs->cp0_status & ST0_TS; 1579 enum ctx_state prev_state; 1580 mm_segment_t old_fs = get_fs(); 1581 1582 prev_state = exception_enter(); 1583 show_regs(regs); 1584 1585 if (multi_match) { 1586 dump_tlb_regs(); 1587 pr_info("\n"); 1588 dump_tlb_all(); 1589 } 1590 1591 if (!user_mode(regs)) 1592 set_fs(KERNEL_DS); 1593 1594 show_code((unsigned int __user *) regs->cp0_epc); 1595 1596 set_fs(old_fs); 1597 1598 /* 1599 * Some chips may have other causes of machine check (e.g. SB1 1600 * graduation timer) 1601 */ 1602 panic("Caught Machine Check exception - %scaused by multiple " 1603 "matching entries in the TLB.", 1604 (multi_match) ? "" : "not "); 1605 } 1606 1607 asmlinkage void do_mt(struct pt_regs *regs) 1608 { 1609 int subcode; 1610 1611 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1612 >> VPECONTROL_EXCPT_SHIFT; 1613 switch (subcode) { 1614 case 0: 1615 printk(KERN_DEBUG "Thread Underflow\n"); 1616 break; 1617 case 1: 1618 printk(KERN_DEBUG "Thread Overflow\n"); 1619 break; 1620 case 2: 1621 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1622 break; 1623 case 3: 1624 printk(KERN_DEBUG "Gating Storage Exception\n"); 1625 break; 1626 case 4: 1627 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1628 break; 1629 case 5: 1630 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1631 break; 1632 default: 1633 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1634 subcode); 1635 break; 1636 } 1637 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1638 1639 force_sig(SIGILL); 1640 } 1641 1642 1643 asmlinkage void do_dsp(struct pt_regs *regs) 1644 { 1645 if (cpu_has_dsp) 1646 panic("Unexpected DSP exception"); 1647 1648 force_sig(SIGILL); 1649 } 1650 1651 asmlinkage void do_reserved(struct pt_regs *regs) 1652 { 1653 /* 1654 * Game over - no way to handle this if it ever occurs. Most probably 1655 * caused by a new unknown cpu type or after another deadly 1656 * hard/software error. 1657 */ 1658 show_regs(regs); 1659 panic("Caught reserved exception %ld - should not happen.", 1660 (regs->cp0_cause & 0x7f) >> 2); 1661 } 1662 1663 static int __initdata l1parity = 1; 1664 static int __init nol1parity(char *s) 1665 { 1666 l1parity = 0; 1667 return 1; 1668 } 1669 __setup("nol1par", nol1parity); 1670 static int __initdata l2parity = 1; 1671 static int __init nol2parity(char *s) 1672 { 1673 l2parity = 0; 1674 return 1; 1675 } 1676 __setup("nol2par", nol2parity); 1677 1678 /* 1679 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1680 * it different ways. 1681 */ 1682 static inline __init void parity_protection_init(void) 1683 { 1684 #define ERRCTL_PE 0x80000000 1685 #define ERRCTL_L2P 0x00800000 1686 1687 if (mips_cm_revision() >= CM_REV_CM3) { 1688 ulong gcr_ectl, cp0_ectl; 1689 1690 /* 1691 * With CM3 systems we need to ensure that the L1 & L2 1692 * parity enables are set to the same value, since this 1693 * is presumed by the hardware engineers. 1694 * 1695 * If the user disabled either of L1 or L2 ECC checking, 1696 * disable both. 1697 */ 1698 l1parity &= l2parity; 1699 l2parity &= l1parity; 1700 1701 /* Probe L1 ECC support */ 1702 cp0_ectl = read_c0_ecc(); 1703 write_c0_ecc(cp0_ectl | ERRCTL_PE); 1704 back_to_back_c0_hazard(); 1705 cp0_ectl = read_c0_ecc(); 1706 1707 /* Probe L2 ECC support */ 1708 gcr_ectl = read_gcr_err_control(); 1709 1710 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) || 1711 !(cp0_ectl & ERRCTL_PE)) { 1712 /* 1713 * One of L1 or L2 ECC checking isn't supported, 1714 * so we cannot enable either. 1715 */ 1716 l1parity = l2parity = 0; 1717 } 1718 1719 /* Configure L1 ECC checking */ 1720 if (l1parity) 1721 cp0_ectl |= ERRCTL_PE; 1722 else 1723 cp0_ectl &= ~ERRCTL_PE; 1724 write_c0_ecc(cp0_ectl); 1725 back_to_back_c0_hazard(); 1726 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity); 1727 1728 /* Configure L2 ECC checking */ 1729 if (l2parity) 1730 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN; 1731 else 1732 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN; 1733 write_gcr_err_control(gcr_ectl); 1734 gcr_ectl = read_gcr_err_control(); 1735 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN; 1736 WARN_ON(!!gcr_ectl != l2parity); 1737 1738 pr_info("Cache parity protection %sabled\n", 1739 l1parity ? "en" : "dis"); 1740 return; 1741 } 1742 1743 switch (current_cpu_type()) { 1744 case CPU_24K: 1745 case CPU_34K: 1746 case CPU_74K: 1747 case CPU_1004K: 1748 case CPU_1074K: 1749 case CPU_INTERAPTIV: 1750 case CPU_PROAPTIV: 1751 case CPU_P5600: 1752 case CPU_QEMU_GENERIC: 1753 case CPU_P6600: 1754 { 1755 unsigned long errctl; 1756 unsigned int l1parity_present, l2parity_present; 1757 1758 errctl = read_c0_ecc(); 1759 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1760 1761 /* probe L1 parity support */ 1762 write_c0_ecc(errctl | ERRCTL_PE); 1763 back_to_back_c0_hazard(); 1764 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1765 1766 /* probe L2 parity support */ 1767 write_c0_ecc(errctl|ERRCTL_L2P); 1768 back_to_back_c0_hazard(); 1769 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1770 1771 if (l1parity_present && l2parity_present) { 1772 if (l1parity) 1773 errctl |= ERRCTL_PE; 1774 if (l1parity ^ l2parity) 1775 errctl |= ERRCTL_L2P; 1776 } else if (l1parity_present) { 1777 if (l1parity) 1778 errctl |= ERRCTL_PE; 1779 } else if (l2parity_present) { 1780 if (l2parity) 1781 errctl |= ERRCTL_L2P; 1782 } else { 1783 /* No parity available */ 1784 } 1785 1786 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1787 1788 write_c0_ecc(errctl); 1789 back_to_back_c0_hazard(); 1790 errctl = read_c0_ecc(); 1791 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1792 1793 if (l1parity_present) 1794 printk(KERN_INFO "Cache parity protection %sabled\n", 1795 (errctl & ERRCTL_PE) ? "en" : "dis"); 1796 1797 if (l2parity_present) { 1798 if (l1parity_present && l1parity) 1799 errctl ^= ERRCTL_L2P; 1800 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1801 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1802 } 1803 } 1804 break; 1805 1806 case CPU_5KC: 1807 case CPU_5KE: 1808 case CPU_LOONGSON32: 1809 write_c0_ecc(0x80000000); 1810 back_to_back_c0_hazard(); 1811 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1812 printk(KERN_INFO "Cache parity protection %sabled\n", 1813 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1814 break; 1815 case CPU_20KC: 1816 case CPU_25KF: 1817 /* Clear the DE bit (bit 16) in the c0_status register. */ 1818 printk(KERN_INFO "Enable cache parity protection for " 1819 "MIPS 20KC/25KF CPUs.\n"); 1820 clear_c0_status(ST0_DE); 1821 break; 1822 default: 1823 break; 1824 } 1825 } 1826 1827 asmlinkage void cache_parity_error(void) 1828 { 1829 const int field = 2 * sizeof(unsigned long); 1830 unsigned int reg_val; 1831 1832 /* For the moment, report the problem and hang. */ 1833 printk("Cache error exception:\n"); 1834 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1835 reg_val = read_c0_cacheerr(); 1836 printk("c0_cacheerr == %08x\n", reg_val); 1837 1838 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1839 reg_val & (1<<30) ? "secondary" : "primary", 1840 reg_val & (1<<31) ? "data" : "insn"); 1841 if ((cpu_has_mips_r2_r6) && 1842 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1843 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1844 reg_val & (1<<29) ? "ED " : "", 1845 reg_val & (1<<28) ? "ET " : "", 1846 reg_val & (1<<27) ? "ES " : "", 1847 reg_val & (1<<26) ? "EE " : "", 1848 reg_val & (1<<25) ? "EB " : "", 1849 reg_val & (1<<24) ? "EI " : "", 1850 reg_val & (1<<23) ? "E1 " : "", 1851 reg_val & (1<<22) ? "E0 " : ""); 1852 } else { 1853 pr_err("Error bits: %s%s%s%s%s%s%s\n", 1854 reg_val & (1<<29) ? "ED " : "", 1855 reg_val & (1<<28) ? "ET " : "", 1856 reg_val & (1<<26) ? "EE " : "", 1857 reg_val & (1<<25) ? "EB " : "", 1858 reg_val & (1<<24) ? "EI " : "", 1859 reg_val & (1<<23) ? "E1 " : "", 1860 reg_val & (1<<22) ? "E0 " : ""); 1861 } 1862 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1863 1864 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1865 if (reg_val & (1<<22)) 1866 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1867 1868 if (reg_val & (1<<23)) 1869 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1870 #endif 1871 1872 panic("Can't handle the cache error!"); 1873 } 1874 1875 asmlinkage void do_ftlb(void) 1876 { 1877 const int field = 2 * sizeof(unsigned long); 1878 unsigned int reg_val; 1879 1880 /* For the moment, report the problem and hang. */ 1881 if ((cpu_has_mips_r2_r6) && 1882 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) || 1883 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) { 1884 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1885 read_c0_ecc()); 1886 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1887 reg_val = read_c0_cacheerr(); 1888 pr_err("c0_cacheerr == %08x\n", reg_val); 1889 1890 if ((reg_val & 0xc0000000) == 0xc0000000) { 1891 pr_err("Decoded c0_cacheerr: FTLB parity error\n"); 1892 } else { 1893 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1894 reg_val & (1<<30) ? "secondary" : "primary", 1895 reg_val & (1<<31) ? "data" : "insn"); 1896 } 1897 } else { 1898 pr_err("FTLB error exception\n"); 1899 } 1900 /* Just print the cacheerr bits for now */ 1901 cache_parity_error(); 1902 } 1903 1904 asmlinkage void do_gsexc(struct pt_regs *regs, u32 diag1) 1905 { 1906 u32 exccode = (diag1 & LOONGSON_DIAG1_EXCCODE) >> 1907 LOONGSON_DIAG1_EXCCODE_SHIFT; 1908 enum ctx_state prev_state; 1909 1910 prev_state = exception_enter(); 1911 1912 switch (exccode) { 1913 case 0x08: 1914 /* Undocumented exception, will trigger on certain 1915 * also-undocumented instructions accessible from userspace. 1916 * Processor state is not otherwise corrupted, but currently 1917 * we don't know how to proceed. Maybe there is some 1918 * undocumented control flag to enable the instructions? 1919 */ 1920 force_sig(SIGILL); 1921 break; 1922 1923 default: 1924 /* None of the other exceptions, documented or not, have 1925 * further details given; none are encountered in the wild 1926 * either. Panic in case some of them turn out to be fatal. 1927 */ 1928 show_regs(regs); 1929 panic("Unhandled Loongson exception - GSCause = %08x", diag1); 1930 } 1931 1932 exception_exit(prev_state); 1933 } 1934 1935 /* 1936 * SDBBP EJTAG debug exception handler. 1937 * We skip the instruction and return to the next instruction. 1938 */ 1939 void ejtag_exception_handler(struct pt_regs *regs) 1940 { 1941 const int field = 2 * sizeof(unsigned long); 1942 unsigned long depc, old_epc, old_ra; 1943 unsigned int debug; 1944 1945 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1946 depc = read_c0_depc(); 1947 debug = read_c0_debug(); 1948 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1949 if (debug & 0x80000000) { 1950 /* 1951 * In branch delay slot. 1952 * We cheat a little bit here and use EPC to calculate the 1953 * debug return address (DEPC). EPC is restored after the 1954 * calculation. 1955 */ 1956 old_epc = regs->cp0_epc; 1957 old_ra = regs->regs[31]; 1958 regs->cp0_epc = depc; 1959 compute_return_epc(regs); 1960 depc = regs->cp0_epc; 1961 regs->cp0_epc = old_epc; 1962 regs->regs[31] = old_ra; 1963 } else 1964 depc += 4; 1965 write_c0_depc(depc); 1966 1967 #if 0 1968 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1969 write_c0_debug(debug | 0x100); 1970 #endif 1971 } 1972 1973 /* 1974 * NMI exception handler. 1975 * No lock; only written during early bootup by CPU 0. 1976 */ 1977 static RAW_NOTIFIER_HEAD(nmi_chain); 1978 1979 int register_nmi_notifier(struct notifier_block *nb) 1980 { 1981 return raw_notifier_chain_register(&nmi_chain, nb); 1982 } 1983 1984 void __noreturn nmi_exception_handler(struct pt_regs *regs) 1985 { 1986 char str[100]; 1987 1988 nmi_enter(); 1989 raw_notifier_call_chain(&nmi_chain, 0, regs); 1990 bust_spinlocks(1); 1991 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", 1992 smp_processor_id(), regs->cp0_epc); 1993 regs->cp0_epc = read_c0_errorepc(); 1994 die(str, regs); 1995 nmi_exit(); 1996 } 1997 1998 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1999 2000 unsigned long ebase; 2001 EXPORT_SYMBOL_GPL(ebase); 2002 unsigned long exception_handlers[32]; 2003 unsigned long vi_handlers[64]; 2004 2005 void __init *set_except_vector(int n, void *addr) 2006 { 2007 unsigned long handler = (unsigned long) addr; 2008 unsigned long old_handler; 2009 2010 #ifdef CONFIG_CPU_MICROMIPS 2011 /* 2012 * Only the TLB handlers are cache aligned with an even 2013 * address. All other handlers are on an odd address and 2014 * require no modification. Otherwise, MIPS32 mode will 2015 * be entered when handling any TLB exceptions. That 2016 * would be bad...since we must stay in microMIPS mode. 2017 */ 2018 if (!(handler & 0x1)) 2019 handler |= 1; 2020 #endif 2021 old_handler = xchg(&exception_handlers[n], handler); 2022 2023 if (n == 0 && cpu_has_divec) { 2024 #ifdef CONFIG_CPU_MICROMIPS 2025 unsigned long jump_mask = ~((1 << 27) - 1); 2026 #else 2027 unsigned long jump_mask = ~((1 << 28) - 1); 2028 #endif 2029 u32 *buf = (u32 *)(ebase + 0x200); 2030 unsigned int k0 = 26; 2031 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 2032 uasm_i_j(&buf, handler & ~jump_mask); 2033 uasm_i_nop(&buf); 2034 } else { 2035 UASM_i_LA(&buf, k0, handler); 2036 uasm_i_jr(&buf, k0); 2037 uasm_i_nop(&buf); 2038 } 2039 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 2040 } 2041 return (void *)old_handler; 2042 } 2043 2044 static void do_default_vi(void) 2045 { 2046 show_regs(get_irq_regs()); 2047 panic("Caught unexpected vectored interrupt."); 2048 } 2049 2050 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 2051 { 2052 unsigned long handler; 2053 unsigned long old_handler = vi_handlers[n]; 2054 int srssets = current_cpu_data.srsets; 2055 u16 *h; 2056 unsigned char *b; 2057 2058 BUG_ON(!cpu_has_veic && !cpu_has_vint); 2059 2060 if (addr == NULL) { 2061 handler = (unsigned long) do_default_vi; 2062 srs = 0; 2063 } else 2064 handler = (unsigned long) addr; 2065 vi_handlers[n] = handler; 2066 2067 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 2068 2069 if (srs >= srssets) 2070 panic("Shadow register set %d not supported", srs); 2071 2072 if (cpu_has_veic) { 2073 if (board_bind_eic_interrupt) 2074 board_bind_eic_interrupt(n, srs); 2075 } else if (cpu_has_vint) { 2076 /* SRSMap is only defined if shadow sets are implemented */ 2077 if (srssets > 1) 2078 change_c0_srsmap(0xf << n*4, srs << n*4); 2079 } 2080 2081 if (srs == 0) { 2082 /* 2083 * If no shadow set is selected then use the default handler 2084 * that does normal register saving and standard interrupt exit 2085 */ 2086 extern char except_vec_vi, except_vec_vi_lui; 2087 extern char except_vec_vi_ori, except_vec_vi_end; 2088 extern char rollback_except_vec_vi; 2089 char *vec_start = using_rollback_handler() ? 2090 &rollback_except_vec_vi : &except_vec_vi; 2091 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) 2092 const int lui_offset = &except_vec_vi_lui - vec_start + 2; 2093 const int ori_offset = &except_vec_vi_ori - vec_start + 2; 2094 #else 2095 const int lui_offset = &except_vec_vi_lui - vec_start; 2096 const int ori_offset = &except_vec_vi_ori - vec_start; 2097 #endif 2098 const int handler_len = &except_vec_vi_end - vec_start; 2099 2100 if (handler_len > VECTORSPACING) { 2101 /* 2102 * Sigh... panicing won't help as the console 2103 * is probably not configured :( 2104 */ 2105 panic("VECTORSPACING too small"); 2106 } 2107 2108 set_handler(((unsigned long)b - ebase), vec_start, 2109 #ifdef CONFIG_CPU_MICROMIPS 2110 (handler_len - 1)); 2111 #else 2112 handler_len); 2113 #endif 2114 h = (u16 *)(b + lui_offset); 2115 *h = (handler >> 16) & 0xffff; 2116 h = (u16 *)(b + ori_offset); 2117 *h = (handler & 0xffff); 2118 local_flush_icache_range((unsigned long)b, 2119 (unsigned long)(b+handler_len)); 2120 } 2121 else { 2122 /* 2123 * In other cases jump directly to the interrupt handler. It 2124 * is the handler's responsibility to save registers if required 2125 * (eg hi/lo) and return from the exception using "eret". 2126 */ 2127 u32 insn; 2128 2129 h = (u16 *)b; 2130 /* j handler */ 2131 #ifdef CONFIG_CPU_MICROMIPS 2132 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); 2133 #else 2134 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); 2135 #endif 2136 h[0] = (insn >> 16) & 0xffff; 2137 h[1] = insn & 0xffff; 2138 h[2] = 0; 2139 h[3] = 0; 2140 local_flush_icache_range((unsigned long)b, 2141 (unsigned long)(b+8)); 2142 } 2143 2144 return (void *)old_handler; 2145 } 2146 2147 void *set_vi_handler(int n, vi_handler_t addr) 2148 { 2149 return set_vi_srs_handler(n, addr, 0); 2150 } 2151 2152 extern void tlb_init(void); 2153 2154 /* 2155 * Timer interrupt 2156 */ 2157 int cp0_compare_irq; 2158 EXPORT_SYMBOL_GPL(cp0_compare_irq); 2159 int cp0_compare_irq_shift; 2160 2161 /* 2162 * Performance counter IRQ or -1 if shared with timer 2163 */ 2164 int cp0_perfcount_irq; 2165 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 2166 2167 /* 2168 * Fast debug channel IRQ or -1 if not present 2169 */ 2170 int cp0_fdc_irq; 2171 EXPORT_SYMBOL_GPL(cp0_fdc_irq); 2172 2173 static int noulri; 2174 2175 static int __init ulri_disable(char *s) 2176 { 2177 pr_info("Disabling ulri\n"); 2178 noulri = 1; 2179 2180 return 1; 2181 } 2182 __setup("noulri", ulri_disable); 2183 2184 /* configure STATUS register */ 2185 static void configure_status(void) 2186 { 2187 /* 2188 * Disable coprocessors and select 32-bit or 64-bit addressing 2189 * and the 16/32 or 32/32 FPR register model. Reset the BEV 2190 * flag that some firmware may have left set and the TS bit (for 2191 * IP27). Set XX for ISA IV code to work. 2192 */ 2193 unsigned int status_set = ST0_CU0; 2194 #ifdef CONFIG_64BIT 2195 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 2196 #endif 2197 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) 2198 status_set |= ST0_XX; 2199 if (cpu_has_dsp) 2200 status_set |= ST0_MX; 2201 2202 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 2203 status_set); 2204 } 2205 2206 unsigned int hwrena; 2207 EXPORT_SYMBOL_GPL(hwrena); 2208 2209 /* configure HWRENA register */ 2210 static void configure_hwrena(void) 2211 { 2212 hwrena = cpu_hwrena_impl_bits; 2213 2214 if (cpu_has_mips_r2_r6) 2215 hwrena |= MIPS_HWRENA_CPUNUM | 2216 MIPS_HWRENA_SYNCISTEP | 2217 MIPS_HWRENA_CC | 2218 MIPS_HWRENA_CCRES; 2219 2220 if (!noulri && cpu_has_userlocal) 2221 hwrena |= MIPS_HWRENA_ULR; 2222 2223 if (hwrena) 2224 write_c0_hwrena(hwrena); 2225 } 2226 2227 static void configure_exception_vector(void) 2228 { 2229 if (cpu_has_mips_r2_r6) { 2230 unsigned long sr = set_c0_status(ST0_BEV); 2231 /* If available, use WG to set top bits of EBASE */ 2232 if (cpu_has_ebase_wg) { 2233 #ifdef CONFIG_64BIT 2234 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 2235 #else 2236 write_c0_ebase(ebase | MIPS_EBASE_WG); 2237 #endif 2238 } 2239 write_c0_ebase(ebase); 2240 write_c0_status(sr); 2241 } 2242 if (cpu_has_veic || cpu_has_vint) { 2243 /* Setting vector spacing enables EI/VI mode */ 2244 change_c0_intctl(0x3e0, VECTORSPACING); 2245 } 2246 if (cpu_has_divec) { 2247 if (cpu_has_mipsmt) { 2248 unsigned int vpflags = dvpe(); 2249 set_c0_cause(CAUSEF_IV); 2250 evpe(vpflags); 2251 } else 2252 set_c0_cause(CAUSEF_IV); 2253 } 2254 } 2255 2256 void per_cpu_trap_init(bool is_boot_cpu) 2257 { 2258 unsigned int cpu = smp_processor_id(); 2259 2260 configure_status(); 2261 configure_hwrena(); 2262 2263 configure_exception_vector(); 2264 2265 /* 2266 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 2267 * 2268 * o read IntCtl.IPTI to determine the timer interrupt 2269 * o read IntCtl.IPPCI to determine the performance counter interrupt 2270 * o read IntCtl.IPFDC to determine the fast debug channel interrupt 2271 */ 2272 if (cpu_has_mips_r2_r6) { 2273 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 2274 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 2275 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 2276 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7; 2277 if (!cp0_fdc_irq) 2278 cp0_fdc_irq = -1; 2279 2280 } else { 2281 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 2282 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 2283 cp0_perfcount_irq = -1; 2284 cp0_fdc_irq = -1; 2285 } 2286 2287 if (cpu_has_mmid) 2288 cpu_data[cpu].asid_cache = 0; 2289 else if (!cpu_data[cpu].asid_cache) 2290 cpu_data[cpu].asid_cache = asid_first_version(cpu); 2291 2292 mmgrab(&init_mm); 2293 current->active_mm = &init_mm; 2294 BUG_ON(current->mm); 2295 enter_lazy_tlb(&init_mm, current); 2296 2297 /* Boot CPU's cache setup in setup_arch(). */ 2298 if (!is_boot_cpu) 2299 cpu_cache_init(); 2300 tlb_init(); 2301 TLBMISS_HANDLER_SETUP(); 2302 } 2303 2304 /* Install CPU exception handler */ 2305 void set_handler(unsigned long offset, void *addr, unsigned long size) 2306 { 2307 #ifdef CONFIG_CPU_MICROMIPS 2308 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); 2309 #else 2310 memcpy((void *)(ebase + offset), addr, size); 2311 #endif 2312 local_flush_icache_range(ebase + offset, ebase + offset + size); 2313 } 2314 2315 static const char panic_null_cerr[] = 2316 "Trying to set NULL cache error exception handler\n"; 2317 2318 /* 2319 * Install uncached CPU exception handler. 2320 * This is suitable only for the cache error exception which is the only 2321 * exception handler that is being run uncached. 2322 */ 2323 void set_uncached_handler(unsigned long offset, void *addr, 2324 unsigned long size) 2325 { 2326 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 2327 2328 if (!addr) 2329 panic(panic_null_cerr); 2330 2331 memcpy((void *)(uncached_ebase + offset), addr, size); 2332 } 2333 2334 static int __initdata rdhwr_noopt; 2335 static int __init set_rdhwr_noopt(char *str) 2336 { 2337 rdhwr_noopt = 1; 2338 return 1; 2339 } 2340 2341 __setup("rdhwr_noopt", set_rdhwr_noopt); 2342 2343 void __init trap_init(void) 2344 { 2345 extern char except_vec3_generic; 2346 extern char except_vec4; 2347 extern char except_vec3_r4000; 2348 unsigned long i, vec_size; 2349 phys_addr_t ebase_pa; 2350 2351 check_wait(); 2352 2353 if (!cpu_has_mips_r2_r6) { 2354 ebase = CAC_BASE; 2355 ebase_pa = virt_to_phys((void *)ebase); 2356 vec_size = 0x400; 2357 2358 memblock_reserve(ebase_pa, vec_size); 2359 } else { 2360 if (cpu_has_veic || cpu_has_vint) 2361 vec_size = 0x200 + VECTORSPACING*64; 2362 else 2363 vec_size = PAGE_SIZE; 2364 2365 ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); 2366 if (!ebase_pa) 2367 panic("%s: Failed to allocate %lu bytes align=0x%x\n", 2368 __func__, vec_size, 1 << fls(vec_size)); 2369 2370 /* 2371 * Try to ensure ebase resides in KSeg0 if possible. 2372 * 2373 * It shouldn't generally be in XKPhys on MIPS64 to avoid 2374 * hitting a poorly defined exception base for Cache Errors. 2375 * The allocation is likely to be in the low 512MB of physical, 2376 * in which case we should be able to convert to KSeg0. 2377 * 2378 * EVA is special though as it allows segments to be rearranged 2379 * and to become uncached during cache error handling. 2380 */ 2381 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) 2382 ebase = CKSEG0ADDR(ebase_pa); 2383 else 2384 ebase = (unsigned long)phys_to_virt(ebase_pa); 2385 } 2386 2387 if (cpu_has_mmips) { 2388 unsigned int config3 = read_c0_config3(); 2389 2390 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) 2391 write_c0_config3(config3 | MIPS_CONF3_ISA_OE); 2392 else 2393 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); 2394 } 2395 2396 if (board_ebase_setup) 2397 board_ebase_setup(); 2398 per_cpu_trap_init(true); 2399 memblock_set_bottom_up(false); 2400 2401 /* 2402 * Copy the generic exception handlers to their final destination. 2403 * This will be overridden later as suitable for a particular 2404 * configuration. 2405 */ 2406 set_handler(0x180, &except_vec3_generic, 0x80); 2407 2408 /* 2409 * Setup default vectors 2410 */ 2411 for (i = 0; i <= 31; i++) 2412 set_except_vector(i, handle_reserved); 2413 2414 /* 2415 * Copy the EJTAG debug exception vector handler code to it's final 2416 * destination. 2417 */ 2418 if (cpu_has_ejtag && board_ejtag_handler_setup) 2419 board_ejtag_handler_setup(); 2420 2421 /* 2422 * Only some CPUs have the watch exceptions. 2423 */ 2424 if (cpu_has_watch) 2425 set_except_vector(EXCCODE_WATCH, handle_watch); 2426 2427 /* 2428 * Initialise interrupt handlers 2429 */ 2430 if (cpu_has_veic || cpu_has_vint) { 2431 int nvec = cpu_has_veic ? 64 : 8; 2432 for (i = 0; i < nvec; i++) 2433 set_vi_handler(i, NULL); 2434 } 2435 else if (cpu_has_divec) 2436 set_handler(0x200, &except_vec4, 0x8); 2437 2438 /* 2439 * Some CPUs can enable/disable for cache parity detection, but does 2440 * it different ways. 2441 */ 2442 parity_protection_init(); 2443 2444 /* 2445 * The Data Bus Errors / Instruction Bus Errors are signaled 2446 * by external hardware. Therefore these two exceptions 2447 * may have board specific handlers. 2448 */ 2449 if (board_be_init) 2450 board_be_init(); 2451 2452 set_except_vector(EXCCODE_INT, using_rollback_handler() ? 2453 rollback_handle_int : handle_int); 2454 set_except_vector(EXCCODE_MOD, handle_tlbm); 2455 set_except_vector(EXCCODE_TLBL, handle_tlbl); 2456 set_except_vector(EXCCODE_TLBS, handle_tlbs); 2457 2458 set_except_vector(EXCCODE_ADEL, handle_adel); 2459 set_except_vector(EXCCODE_ADES, handle_ades); 2460 2461 set_except_vector(EXCCODE_IBE, handle_ibe); 2462 set_except_vector(EXCCODE_DBE, handle_dbe); 2463 2464 set_except_vector(EXCCODE_SYS, handle_sys); 2465 set_except_vector(EXCCODE_BP, handle_bp); 2466 2467 if (rdhwr_noopt) 2468 set_except_vector(EXCCODE_RI, handle_ri); 2469 else { 2470 if (cpu_has_vtag_icache) 2471 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 2472 else if (current_cpu_type() == CPU_LOONGSON64) 2473 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 2474 else 2475 set_except_vector(EXCCODE_RI, handle_ri_rdhwr); 2476 } 2477 2478 set_except_vector(EXCCODE_CPU, handle_cpu); 2479 set_except_vector(EXCCODE_OV, handle_ov); 2480 set_except_vector(EXCCODE_TR, handle_tr); 2481 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe); 2482 2483 if (board_nmi_handler_setup) 2484 board_nmi_handler_setup(); 2485 2486 if (cpu_has_fpu && !cpu_has_nofpuex) 2487 set_except_vector(EXCCODE_FPE, handle_fpe); 2488 2489 if (cpu_has_ftlbparex) 2490 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); 2491 2492 if (cpu_has_gsexcex) 2493 set_except_vector(LOONGSON_EXCCODE_GSEXC, handle_gsexc); 2494 2495 if (cpu_has_rixiex) { 2496 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0); 2497 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0); 2498 } 2499 2500 set_except_vector(EXCCODE_MSADIS, handle_msa); 2501 set_except_vector(EXCCODE_MDMX, handle_mdmx); 2502 2503 if (cpu_has_mcheck) 2504 set_except_vector(EXCCODE_MCHECK, handle_mcheck); 2505 2506 if (cpu_has_mipsmt) 2507 set_except_vector(EXCCODE_THREAD, handle_mt); 2508 2509 set_except_vector(EXCCODE_DSPDIS, handle_dsp); 2510 2511 if (board_cache_error_setup) 2512 board_cache_error_setup(); 2513 2514 if (cpu_has_vce) 2515 /* Special exception: R4[04]00 uses also the divec space. */ 2516 set_handler(0x180, &except_vec3_r4000, 0x100); 2517 else if (cpu_has_4kex) 2518 set_handler(0x180, &except_vec3_generic, 0x80); 2519 else 2520 set_handler(0x080, &except_vec3_generic, 0x80); 2521 2522 local_flush_icache_range(ebase, ebase + vec_size); 2523 2524 sort_extable(__start___dbe_table, __stop___dbe_table); 2525 2526 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 2527 } 2528 2529 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, 2530 void *v) 2531 { 2532 switch (cmd) { 2533 case CPU_PM_ENTER_FAILED: 2534 case CPU_PM_EXIT: 2535 configure_status(); 2536 configure_hwrena(); 2537 configure_exception_vector(); 2538 2539 /* Restore register with CPU number for TLB handlers */ 2540 TLBMISS_HANDLER_RESTORE(); 2541 2542 break; 2543 } 2544 2545 return NOTIFY_OK; 2546 } 2547 2548 static struct notifier_block trap_pm_notifier_block = { 2549 .notifier_call = trap_pm_notifier, 2550 }; 2551 2552 static int __init trap_pm_init(void) 2553 { 2554 return cpu_pm_register_notifier(&trap_pm_notifier_block); 2555 } 2556 arch_initcall(trap_pm_init); 2557