1 /* 2 * This program is free software; you can distribute it and/or modify it 3 * under the terms of the GNU General Public License (Version 2) as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope it will be useful, but WITHOUT 7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 8 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 9 * for more details. 10 * 11 * You should have received a copy of the GNU General Public License along 12 * with this program; if not, write to the Free Software Foundation, Inc., 13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 14 * 15 * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc. 16 * Elizabeth Clarke (beth@mips.com) 17 * Ralf Baechle (ralf@linux-mips.org) 18 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 19 */ 20 #include <linux/kernel.h> 21 #include <linux/sched.h> 22 #include <linux/cpumask.h> 23 #include <linux/interrupt.h> 24 #include <linux/compiler.h> 25 #include <linux/smp.h> 26 27 #include <linux/atomic.h> 28 #include <asm/cacheflush.h> 29 #include <asm/cpu.h> 30 #include <asm/processor.h> 31 #include <asm/hardirq.h> 32 #include <asm/mmu_context.h> 33 #include <asm/time.h> 34 #include <asm/mipsregs.h> 35 #include <asm/mipsmtregs.h> 36 #include <asm/mips_mt.h> 37 38 static void __init smvp_copy_vpe_config(void) 39 { 40 write_vpe_c0_status( 41 (read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0); 42 43 /* set config to be the same as vpe0, particularly kseg0 coherency alg */ 44 write_vpe_c0_config( read_c0_config()); 45 46 /* make sure there are no software interrupts pending */ 47 write_vpe_c0_cause(0); 48 49 /* Propagate Config7 */ 50 write_vpe_c0_config7(read_c0_config7()); 51 52 write_vpe_c0_count(read_c0_count()); 53 } 54 55 static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0, 56 unsigned int ncpu) 57 { 58 if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) 59 return ncpu; 60 61 /* Deactivate all but VPE 0 */ 62 if (tc != 0) { 63 unsigned long tmp = read_vpe_c0_vpeconf0(); 64 65 tmp &= ~VPECONF0_VPA; 66 67 /* master VPE */ 68 tmp |= VPECONF0_MVP; 69 write_vpe_c0_vpeconf0(tmp); 70 71 /* Record this as available CPU */ 72 set_cpu_possible(tc, true); 73 __cpu_number_map[tc] = ++ncpu; 74 __cpu_logical_map[ncpu] = tc; 75 } 76 77 /* Disable multi-threading with TC's */ 78 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); 79 80 if (tc != 0) 81 smvp_copy_vpe_config(); 82 83 return ncpu; 84 } 85 86 static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0) 87 { 88 unsigned long tmp; 89 90 if (!tc) 91 return; 92 93 /* bind a TC to each VPE, May as well put all excess TC's 94 on the last VPE */ 95 if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1)) 96 write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)); 97 else { 98 write_tc_c0_tcbind(read_tc_c0_tcbind() | tc); 99 100 /* and set XTC */ 101 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT)); 102 } 103 104 tmp = read_tc_c0_tcstatus(); 105 106 /* mark not allocated and not dynamically allocatable */ 107 tmp &= ~(TCSTATUS_A | TCSTATUS_DA); 108 tmp |= TCSTATUS_IXMT; /* interrupt exempt */ 109 write_tc_c0_tcstatus(tmp); 110 111 write_tc_c0_tchalt(TCHALT_H); 112 } 113 114 static void vsmp_send_ipi_single(int cpu, unsigned int action) 115 { 116 int i; 117 unsigned long flags; 118 int vpflags; 119 120 local_irq_save(flags); 121 122 vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ 123 124 switch (action) { 125 case SMP_CALL_FUNCTION: 126 i = C_SW1; 127 break; 128 129 case SMP_RESCHEDULE_YOURSELF: 130 default: 131 i = C_SW0; 132 break; 133 } 134 135 /* 1:1 mapping of vpe and tc... */ 136 settc(cpu); 137 write_vpe_c0_cause(read_vpe_c0_cause() | i); 138 evpe(vpflags); 139 140 local_irq_restore(flags); 141 } 142 143 static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) 144 { 145 unsigned int i; 146 147 for_each_cpu(i, mask) 148 vsmp_send_ipi_single(i, action); 149 } 150 151 static void __cpuinit vsmp_init_secondary(void) 152 { 153 extern int gic_present; 154 155 /* This is Malta specific: IPI,performance and timer interrupts */ 156 if (gic_present) 157 change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | 158 STATUSF_IP6 | STATUSF_IP7); 159 else 160 change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 | 161 STATUSF_IP6 | STATUSF_IP7); 162 } 163 164 static void __cpuinit vsmp_smp_finish(void) 165 { 166 /* CDFIXME: remove this? */ 167 write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); 168 169 #ifdef CONFIG_MIPS_MT_FPAFF 170 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 171 if (cpu_has_fpu) 172 cpu_set(smp_processor_id(), mt_fpu_cpumask); 173 #endif /* CONFIG_MIPS_MT_FPAFF */ 174 175 local_irq_enable(); 176 } 177 178 static void vsmp_cpus_done(void) 179 { 180 } 181 182 /* 183 * Setup the PC, SP, and GP of a secondary processor and start it 184 * running! 185 * smp_bootstrap is the place to resume from 186 * __KSTK_TOS(idle) is apparently the stack pointer 187 * (unsigned long)idle->thread_info the gp 188 * assumes a 1:1 mapping of TC => VPE 189 */ 190 static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) 191 { 192 struct thread_info *gp = task_thread_info(idle); 193 dvpe(); 194 set_c0_mvpcontrol(MVPCONTROL_VPC); 195 196 settc(cpu); 197 198 /* restart */ 199 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); 200 201 /* enable the tc this vpe/cpu will be running */ 202 write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A); 203 204 write_tc_c0_tchalt(0); 205 206 /* enable the VPE */ 207 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); 208 209 /* stack pointer */ 210 write_tc_gpr_sp( __KSTK_TOS(idle)); 211 212 /* global pointer */ 213 write_tc_gpr_gp((unsigned long)gp); 214 215 flush_icache_range((unsigned long)gp, 216 (unsigned long)(gp + sizeof(struct thread_info))); 217 218 /* finally out of configuration and into chaos */ 219 clear_c0_mvpcontrol(MVPCONTROL_VPC); 220 221 evpe(EVPE_ENABLE); 222 } 223 224 /* 225 * Common setup before any secondaries are started 226 * Make sure all CPU's are in a sensible state before we boot any of the 227 * secondaries 228 */ 229 static void __init vsmp_smp_setup(void) 230 { 231 unsigned int mvpconf0, ntc, tc, ncpu = 0; 232 unsigned int nvpe; 233 234 #ifdef CONFIG_MIPS_MT_FPAFF 235 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 236 if (cpu_has_fpu) 237 cpu_set(0, mt_fpu_cpumask); 238 #endif /* CONFIG_MIPS_MT_FPAFF */ 239 if (!cpu_has_mipsmt) 240 return; 241 242 /* disable MT so we can configure */ 243 dvpe(); 244 dmt(); 245 246 /* Put MVPE's into 'configuration state' */ 247 set_c0_mvpcontrol(MVPCONTROL_VPC); 248 249 mvpconf0 = read_c0_mvpconf0(); 250 ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT; 251 252 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 253 smp_num_siblings = nvpe; 254 255 /* we'll always have more TC's than VPE's, so loop setting everything 256 to a sensible state */ 257 for (tc = 0; tc <= ntc; tc++) { 258 settc(tc); 259 260 smvp_tc_init(tc, mvpconf0); 261 ncpu = smvp_vpe_init(tc, mvpconf0, ncpu); 262 } 263 264 /* Release config state */ 265 clear_c0_mvpcontrol(MVPCONTROL_VPC); 266 267 /* We'll wait until starting the secondaries before starting MVPE */ 268 269 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu); 270 } 271 272 static void __init vsmp_prepare_cpus(unsigned int max_cpus) 273 { 274 mips_mt_set_cpuoptions(); 275 } 276 277 struct plat_smp_ops vsmp_smp_ops = { 278 .send_ipi_single = vsmp_send_ipi_single, 279 .send_ipi_mask = vsmp_send_ipi_mask, 280 .init_secondary = vsmp_init_secondary, 281 .smp_finish = vsmp_smp_finish, 282 .cpus_done = vsmp_cpus_done, 283 .boot_secondary = vsmp_boot_secondary, 284 .smp_setup = vsmp_smp_setup, 285 .prepare_cpus = vsmp_prepare_cpus, 286 }; 287