xref: /openbmc/linux/arch/mips/kernel/smp-cps.c (revision d2999e1b)
1 /*
2  * Copyright (C) 2013 Imagination Technologies
3  * Author: Paul Burton <paul.burton@imgtec.com>
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation;  either version 2 of the  License, or (at your
8  * option) any later version.
9  */
10 
11 #include <linux/io.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
14 #include <linux/smp.h>
15 #include <linux/types.h>
16 
17 #include <asm/cacheflush.h>
18 #include <asm/gic.h>
19 #include <asm/mips-cm.h>
20 #include <asm/mips-cpc.h>
21 #include <asm/mips_mt.h>
22 #include <asm/mipsregs.h>
23 #include <asm/pm-cps.h>
24 #include <asm/smp-cps.h>
25 #include <asm/time.h>
26 #include <asm/uasm.h>
27 
28 static DECLARE_BITMAP(core_power, NR_CPUS);
29 
30 struct core_boot_config *mips_cps_core_bootcfg;
31 
32 static unsigned core_vpe_count(unsigned core)
33 {
34 	unsigned cfg;
35 
36 	if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
37 		return 1;
38 
39 	write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
40 	cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
41 	return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
42 }
43 
44 static void __init cps_smp_setup(void)
45 {
46 	unsigned int ncores, nvpes, core_vpes;
47 	int c, v;
48 
49 	/* Detect & record VPE topology */
50 	ncores = mips_cm_numcores();
51 	pr_info("VPE topology ");
52 	for (c = nvpes = 0; c < ncores; c++) {
53 		core_vpes = core_vpe_count(c);
54 		pr_cont("%c%u", c ? ',' : '{', core_vpes);
55 
56 		/* Use the number of VPEs in core 0 for smp_num_siblings */
57 		if (!c)
58 			smp_num_siblings = core_vpes;
59 
60 		for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
61 			cpu_data[nvpes + v].core = c;
62 #ifdef CONFIG_MIPS_MT_SMP
63 			cpu_data[nvpes + v].vpe_id = v;
64 #endif
65 		}
66 
67 		nvpes += core_vpes;
68 	}
69 	pr_cont("} total %u\n", nvpes);
70 
71 	/* Indicate present CPUs (CPU being synonymous with VPE) */
72 	for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
73 		set_cpu_possible(v, true);
74 		set_cpu_present(v, true);
75 		__cpu_number_map[v] = v;
76 		__cpu_logical_map[v] = v;
77 	}
78 
79 	/* Set a coherent default CCA (CWB) */
80 	change_c0_config(CONF_CM_CMASK, 0x5);
81 
82 	/* Core 0 is powered up (we're running on it) */
83 	bitmap_set(core_power, 0, 1);
84 
85 	/* Initialise core 0 */
86 	mips_cps_core_init();
87 
88 	/* Make core 0 coherent with everything */
89 	write_gcr_cl_coherence(0xff);
90 }
91 
92 static void __init cps_prepare_cpus(unsigned int max_cpus)
93 {
94 	unsigned ncores, core_vpes, c, cca;
95 	bool cca_unsuitable;
96 	u32 *entry_code;
97 
98 	mips_mt_set_cpuoptions();
99 
100 	/* Detect whether the CCA is unsuited to multi-core SMP */
101 	cca = read_c0_config() & CONF_CM_CMASK;
102 	switch (cca) {
103 	case 0x4: /* CWBE */
104 	case 0x5: /* CWB */
105 		/* The CCA is coherent, multi-core is fine */
106 		cca_unsuitable = false;
107 		break;
108 
109 	default:
110 		/* CCA is not coherent, multi-core is not usable */
111 		cca_unsuitable = true;
112 	}
113 
114 	/* Warn the user if the CCA prevents multi-core */
115 	ncores = mips_cm_numcores();
116 	if (cca_unsuitable && ncores > 1) {
117 		pr_warn("Using only one core due to unsuitable CCA 0x%x\n",
118 			cca);
119 
120 		for_each_present_cpu(c) {
121 			if (cpu_data[c].core)
122 				set_cpu_present(c, false);
123 		}
124 	}
125 
126 	/*
127 	 * Patch the start of mips_cps_core_entry to provide:
128 	 *
129 	 * v0 = CM base address
130 	 * s0 = kseg0 CCA
131 	 */
132 	entry_code = (u32 *)&mips_cps_core_entry;
133 	UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
134 	uasm_i_addiu(&entry_code, 16, 0, cca);
135 	dma_cache_wback_inv((unsigned long)&mips_cps_core_entry,
136 			    (void *)entry_code - (void *)&mips_cps_core_entry);
137 
138 	/* Allocate core boot configuration structs */
139 	mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
140 					GFP_KERNEL);
141 	if (!mips_cps_core_bootcfg) {
142 		pr_err("Failed to allocate boot config for %u cores\n", ncores);
143 		goto err_out;
144 	}
145 
146 	/* Allocate VPE boot configuration structs */
147 	for (c = 0; c < ncores; c++) {
148 		core_vpes = core_vpe_count(c);
149 		mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
150 				sizeof(*mips_cps_core_bootcfg[c].vpe_config),
151 				GFP_KERNEL);
152 		if (!mips_cps_core_bootcfg[c].vpe_config) {
153 			pr_err("Failed to allocate %u VPE boot configs\n",
154 			       core_vpes);
155 			goto err_out;
156 		}
157 	}
158 
159 	/* Mark this CPU as booted */
160 	atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
161 		   1 << cpu_vpe_id(&current_cpu_data));
162 
163 	return;
164 err_out:
165 	/* Clean up allocations */
166 	if (mips_cps_core_bootcfg) {
167 		for (c = 0; c < ncores; c++)
168 			kfree(mips_cps_core_bootcfg[c].vpe_config);
169 		kfree(mips_cps_core_bootcfg);
170 		mips_cps_core_bootcfg = NULL;
171 	}
172 
173 	/* Effectively disable SMP by declaring CPUs not present */
174 	for_each_possible_cpu(c) {
175 		if (c == 0)
176 			continue;
177 		set_cpu_present(c, false);
178 	}
179 }
180 
181 static void boot_core(unsigned core)
182 {
183 	u32 access;
184 
185 	/* Select the appropriate core */
186 	write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
187 
188 	/* Set its reset vector */
189 	write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
190 
191 	/* Ensure its coherency is disabled */
192 	write_gcr_co_coherence(0);
193 
194 	/* Ensure the core can access the GCRs */
195 	access = read_gcr_access();
196 	access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
197 	write_gcr_access(access);
198 
199 	if (mips_cpc_present()) {
200 		/* Reset the core */
201 		mips_cpc_lock_other(core);
202 		write_cpc_co_cmd(CPC_Cx_CMD_RESET);
203 		mips_cpc_unlock_other();
204 	} else {
205 		/* Take the core out of reset */
206 		write_gcr_co_reset_release(0);
207 	}
208 
209 	/* The core is now powered up */
210 	bitmap_set(core_power, core, 1);
211 }
212 
213 static void remote_vpe_boot(void *dummy)
214 {
215 	mips_cps_boot_vpes();
216 }
217 
218 static void cps_boot_secondary(int cpu, struct task_struct *idle)
219 {
220 	unsigned core = cpu_data[cpu].core;
221 	unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
222 	struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
223 	struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
224 	unsigned int remote;
225 	int err;
226 
227 	vpe_cfg->pc = (unsigned long)&smp_bootstrap;
228 	vpe_cfg->sp = __KSTK_TOS(idle);
229 	vpe_cfg->gp = (unsigned long)task_thread_info(idle);
230 
231 	atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
232 
233 	preempt_disable();
234 
235 	if (!test_bit(core, core_power)) {
236 		/* Boot a VPE on a powered down core */
237 		boot_core(core);
238 		goto out;
239 	}
240 
241 	if (core != current_cpu_data.core) {
242 		/* Boot a VPE on another powered up core */
243 		for (remote = 0; remote < NR_CPUS; remote++) {
244 			if (cpu_data[remote].core != core)
245 				continue;
246 			if (cpu_online(remote))
247 				break;
248 		}
249 		BUG_ON(remote >= NR_CPUS);
250 
251 		err = smp_call_function_single(remote, remote_vpe_boot,
252 					       NULL, 1);
253 		if (err)
254 			panic("Failed to call remote CPU\n");
255 		goto out;
256 	}
257 
258 	BUG_ON(!cpu_has_mipsmt);
259 
260 	/* Boot a VPE on this core */
261 	mips_cps_boot_vpes();
262 out:
263 	preempt_enable();
264 }
265 
266 static void cps_init_secondary(void)
267 {
268 	/* Disable MT - we only want to run 1 TC per VPE */
269 	if (cpu_has_mipsmt)
270 		dmt();
271 
272 	change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
273 				 STATUSF_IP6 | STATUSF_IP7);
274 }
275 
276 static void cps_smp_finish(void)
277 {
278 	write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
279 
280 #ifdef CONFIG_MIPS_MT_FPAFF
281 	/* If we have an FPU, enroll ourselves in the FPU-full mask */
282 	if (cpu_has_fpu)
283 		cpu_set(smp_processor_id(), mt_fpu_cpumask);
284 #endif /* CONFIG_MIPS_MT_FPAFF */
285 
286 	local_irq_enable();
287 }
288 
289 #ifdef CONFIG_HOTPLUG_CPU
290 
291 static int cps_cpu_disable(void)
292 {
293 	unsigned cpu = smp_processor_id();
294 	struct core_boot_config *core_cfg;
295 
296 	if (!cpu)
297 		return -EBUSY;
298 
299 	if (!cps_pm_support_state(CPS_PM_POWER_GATED))
300 		return -EINVAL;
301 
302 	core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
303 	atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
304 	smp_mb__after_atomic();
305 	set_cpu_online(cpu, false);
306 	cpu_clear(cpu, cpu_callin_map);
307 
308 	return 0;
309 }
310 
311 static DECLARE_COMPLETION(cpu_death_chosen);
312 static unsigned cpu_death_sibling;
313 static enum {
314 	CPU_DEATH_HALT,
315 	CPU_DEATH_POWER,
316 } cpu_death;
317 
318 void play_dead(void)
319 {
320 	unsigned cpu, core;
321 
322 	local_irq_disable();
323 	idle_task_exit();
324 	cpu = smp_processor_id();
325 	cpu_death = CPU_DEATH_POWER;
326 
327 	if (cpu_has_mipsmt) {
328 		core = cpu_data[cpu].core;
329 
330 		/* Look for another online VPE within the core */
331 		for_each_online_cpu(cpu_death_sibling) {
332 			if (cpu_data[cpu_death_sibling].core != core)
333 				continue;
334 
335 			/*
336 			 * There is an online VPE within the core. Just halt
337 			 * this TC and leave the core alone.
338 			 */
339 			cpu_death = CPU_DEATH_HALT;
340 			break;
341 		}
342 	}
343 
344 	/* This CPU has chosen its way out */
345 	complete(&cpu_death_chosen);
346 
347 	if (cpu_death == CPU_DEATH_HALT) {
348 		/* Halt this TC */
349 		write_c0_tchalt(TCHALT_H);
350 		instruction_hazard();
351 	} else {
352 		/* Power down the core */
353 		cps_pm_enter_state(CPS_PM_POWER_GATED);
354 	}
355 
356 	/* This should never be reached */
357 	panic("Failed to offline CPU %u", cpu);
358 }
359 
360 static void wait_for_sibling_halt(void *ptr_cpu)
361 {
362 	unsigned cpu = (unsigned)ptr_cpu;
363 	unsigned vpe_id = cpu_data[cpu].vpe_id;
364 	unsigned halted;
365 	unsigned long flags;
366 
367 	do {
368 		local_irq_save(flags);
369 		settc(vpe_id);
370 		halted = read_tc_c0_tchalt();
371 		local_irq_restore(flags);
372 	} while (!(halted & TCHALT_H));
373 }
374 
375 static void cps_cpu_die(unsigned int cpu)
376 {
377 	unsigned core = cpu_data[cpu].core;
378 	unsigned stat;
379 	int err;
380 
381 	/* Wait for the cpu to choose its way out */
382 	if (!wait_for_completion_timeout(&cpu_death_chosen,
383 					 msecs_to_jiffies(5000))) {
384 		pr_err("CPU%u: didn't offline\n", cpu);
385 		return;
386 	}
387 
388 	/*
389 	 * Now wait for the CPU to actually offline. Without doing this that
390 	 * offlining may race with one or more of:
391 	 *
392 	 *   - Onlining the CPU again.
393 	 *   - Powering down the core if another VPE within it is offlined.
394 	 *   - A sibling VPE entering a non-coherent state.
395 	 *
396 	 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
397 	 * with which we could race, so do nothing.
398 	 */
399 	if (cpu_death == CPU_DEATH_POWER) {
400 		/*
401 		 * Wait for the core to enter a powered down or clock gated
402 		 * state, the latter happening when a JTAG probe is connected
403 		 * in which case the CPC will refuse to power down the core.
404 		 */
405 		do {
406 			mips_cpc_lock_other(core);
407 			stat = read_cpc_co_stat_conf();
408 			stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
409 			mips_cpc_unlock_other();
410 		} while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 &&
411 			 stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 &&
412 			 stat != CPC_Cx_STAT_CONF_SEQSTATE_U2);
413 
414 		/* Indicate the core is powered off */
415 		bitmap_clear(core_power, core, 1);
416 	} else if (cpu_has_mipsmt) {
417 		/*
418 		 * Have a CPU with access to the offlined CPUs registers wait
419 		 * for its TC to halt.
420 		 */
421 		err = smp_call_function_single(cpu_death_sibling,
422 					       wait_for_sibling_halt,
423 					       (void *)cpu, 1);
424 		if (err)
425 			panic("Failed to call remote sibling CPU\n");
426 	}
427 }
428 
429 #endif /* CONFIG_HOTPLUG_CPU */
430 
431 static struct plat_smp_ops cps_smp_ops = {
432 	.smp_setup		= cps_smp_setup,
433 	.prepare_cpus		= cps_prepare_cpus,
434 	.boot_secondary		= cps_boot_secondary,
435 	.init_secondary		= cps_init_secondary,
436 	.smp_finish		= cps_smp_finish,
437 	.send_ipi_single	= gic_send_ipi_single,
438 	.send_ipi_mask		= gic_send_ipi_mask,
439 #ifdef CONFIG_HOTPLUG_CPU
440 	.cpu_disable		= cps_cpu_disable,
441 	.cpu_die		= cps_cpu_die,
442 #endif
443 };
444 
445 bool mips_cps_smp_in_use(void)
446 {
447 	extern struct plat_smp_ops *mp_ops;
448 	return mp_ops == &cps_smp_ops;
449 }
450 
451 int register_cps_smp_ops(void)
452 {
453 	if (!mips_cm_present()) {
454 		pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
455 		return -ENODEV;
456 	}
457 
458 	/* check we have a GIC - we need one for IPIs */
459 	if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
460 		pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
461 		return -ENODEV;
462 	}
463 
464 	register_smp_ops(&cps_smp_ops);
465 	return 0;
466 }
467