1 /* 2 * Copyright (C) 2013 Imagination Technologies 3 * Author: Paul Burton <paul.burton@imgtec.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/io.h> 13 #include <linux/irqchip/mips-gic.h> 14 #include <linux/sched.h> 15 #include <linux/slab.h> 16 #include <linux/smp.h> 17 #include <linux/types.h> 18 19 #include <asm/bcache.h> 20 #include <asm/mips-cm.h> 21 #include <asm/mips-cpc.h> 22 #include <asm/mips_mt.h> 23 #include <asm/mipsregs.h> 24 #include <asm/pm-cps.h> 25 #include <asm/r4kcache.h> 26 #include <asm/smp-cps.h> 27 #include <asm/time.h> 28 #include <asm/uasm.h> 29 30 static DECLARE_BITMAP(core_power, NR_CPUS); 31 32 struct core_boot_config *mips_cps_core_bootcfg; 33 34 static unsigned core_vpe_count(unsigned core) 35 { 36 unsigned cfg; 37 38 if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt) 39 return 1; 40 41 mips_cm_lock_other(core, 0); 42 cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK; 43 mips_cm_unlock_other(); 44 return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1; 45 } 46 47 static void __init cps_smp_setup(void) 48 { 49 unsigned int ncores, nvpes, core_vpes; 50 int c, v; 51 52 /* Detect & record VPE topology */ 53 ncores = mips_cm_numcores(); 54 pr_info("VPE topology "); 55 for (c = nvpes = 0; c < ncores; c++) { 56 core_vpes = core_vpe_count(c); 57 pr_cont("%c%u", c ? ',' : '{', core_vpes); 58 59 /* Use the number of VPEs in core 0 for smp_num_siblings */ 60 if (!c) 61 smp_num_siblings = core_vpes; 62 63 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { 64 cpu_data[nvpes + v].core = c; 65 #ifdef CONFIG_MIPS_MT_SMP 66 cpu_data[nvpes + v].vpe_id = v; 67 #endif 68 } 69 70 nvpes += core_vpes; 71 } 72 pr_cont("} total %u\n", nvpes); 73 74 /* Indicate present CPUs (CPU being synonymous with VPE) */ 75 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { 76 set_cpu_possible(v, true); 77 set_cpu_present(v, true); 78 __cpu_number_map[v] = v; 79 __cpu_logical_map[v] = v; 80 } 81 82 /* Set a coherent default CCA (CWB) */ 83 change_c0_config(CONF_CM_CMASK, 0x5); 84 85 /* Core 0 is powered up (we're running on it) */ 86 bitmap_set(core_power, 0, 1); 87 88 /* Initialise core 0 */ 89 mips_cps_core_init(); 90 91 /* Make core 0 coherent with everything */ 92 write_gcr_cl_coherence(0xff); 93 94 #ifdef CONFIG_MIPS_MT_FPAFF 95 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 96 if (cpu_has_fpu) 97 cpumask_set_cpu(0, &mt_fpu_cpumask); 98 #endif /* CONFIG_MIPS_MT_FPAFF */ 99 } 100 101 static void __init cps_prepare_cpus(unsigned int max_cpus) 102 { 103 unsigned ncores, core_vpes, c, cca; 104 bool cca_unsuitable; 105 u32 *entry_code; 106 107 mips_mt_set_cpuoptions(); 108 109 /* Detect whether the CCA is unsuited to multi-core SMP */ 110 cca = read_c0_config() & CONF_CM_CMASK; 111 switch (cca) { 112 case 0x4: /* CWBE */ 113 case 0x5: /* CWB */ 114 /* The CCA is coherent, multi-core is fine */ 115 cca_unsuitable = false; 116 break; 117 118 default: 119 /* CCA is not coherent, multi-core is not usable */ 120 cca_unsuitable = true; 121 } 122 123 /* Warn the user if the CCA prevents multi-core */ 124 ncores = mips_cm_numcores(); 125 if (cca_unsuitable && ncores > 1) { 126 pr_warn("Using only one core due to unsuitable CCA 0x%x\n", 127 cca); 128 129 for_each_present_cpu(c) { 130 if (cpu_data[c].core) 131 set_cpu_present(c, false); 132 } 133 } 134 135 /* 136 * Patch the start of mips_cps_core_entry to provide: 137 * 138 * s0 = kseg0 CCA 139 */ 140 entry_code = (u32 *)&mips_cps_core_entry; 141 uasm_i_addiu(&entry_code, 16, 0, cca); 142 blast_dcache_range((unsigned long)&mips_cps_core_entry, 143 (unsigned long)entry_code); 144 bc_wback_inv((unsigned long)&mips_cps_core_entry, 145 (void *)entry_code - (void *)&mips_cps_core_entry); 146 __sync(); 147 148 /* Allocate core boot configuration structs */ 149 mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), 150 GFP_KERNEL); 151 if (!mips_cps_core_bootcfg) { 152 pr_err("Failed to allocate boot config for %u cores\n", ncores); 153 goto err_out; 154 } 155 156 /* Allocate VPE boot configuration structs */ 157 for (c = 0; c < ncores; c++) { 158 core_vpes = core_vpe_count(c); 159 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes, 160 sizeof(*mips_cps_core_bootcfg[c].vpe_config), 161 GFP_KERNEL); 162 if (!mips_cps_core_bootcfg[c].vpe_config) { 163 pr_err("Failed to allocate %u VPE boot configs\n", 164 core_vpes); 165 goto err_out; 166 } 167 } 168 169 /* Mark this CPU as booted */ 170 atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask, 171 1 << cpu_vpe_id(¤t_cpu_data)); 172 173 return; 174 err_out: 175 /* Clean up allocations */ 176 if (mips_cps_core_bootcfg) { 177 for (c = 0; c < ncores; c++) 178 kfree(mips_cps_core_bootcfg[c].vpe_config); 179 kfree(mips_cps_core_bootcfg); 180 mips_cps_core_bootcfg = NULL; 181 } 182 183 /* Effectively disable SMP by declaring CPUs not present */ 184 for_each_possible_cpu(c) { 185 if (c == 0) 186 continue; 187 set_cpu_present(c, false); 188 } 189 } 190 191 static void boot_core(unsigned core) 192 { 193 u32 access, stat, seq_state; 194 unsigned timeout; 195 196 /* Select the appropriate core */ 197 mips_cm_lock_other(core, 0); 198 199 /* Set its reset vector */ 200 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); 201 202 /* Ensure its coherency is disabled */ 203 write_gcr_co_coherence(0); 204 205 /* Ensure the core can access the GCRs */ 206 access = read_gcr_access(); 207 access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core); 208 write_gcr_access(access); 209 210 if (mips_cpc_present()) { 211 /* Reset the core */ 212 mips_cpc_lock_other(core); 213 write_cpc_co_cmd(CPC_Cx_CMD_RESET); 214 215 timeout = 100; 216 while (true) { 217 stat = read_cpc_co_stat_conf(); 218 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK; 219 220 /* U6 == coherent execution, ie. the core is up */ 221 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6) 222 break; 223 224 /* Delay a little while before we start warning */ 225 if (timeout) { 226 timeout--; 227 mdelay(10); 228 continue; 229 } 230 231 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n", 232 core, stat); 233 mdelay(1000); 234 } 235 236 mips_cpc_unlock_other(); 237 } else { 238 /* Take the core out of reset */ 239 write_gcr_co_reset_release(0); 240 } 241 242 mips_cm_unlock_other(); 243 244 /* The core is now powered up */ 245 bitmap_set(core_power, core, 1); 246 } 247 248 static void remote_vpe_boot(void *dummy) 249 { 250 mips_cps_boot_vpes(); 251 } 252 253 static void cps_boot_secondary(int cpu, struct task_struct *idle) 254 { 255 unsigned core = cpu_data[cpu].core; 256 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); 257 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; 258 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; 259 unsigned int remote; 260 int err; 261 262 vpe_cfg->pc = (unsigned long)&smp_bootstrap; 263 vpe_cfg->sp = __KSTK_TOS(idle); 264 vpe_cfg->gp = (unsigned long)task_thread_info(idle); 265 266 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask); 267 268 preempt_disable(); 269 270 if (!test_bit(core, core_power)) { 271 /* Boot a VPE on a powered down core */ 272 boot_core(core); 273 goto out; 274 } 275 276 if (core != current_cpu_data.core) { 277 /* Boot a VPE on another powered up core */ 278 for (remote = 0; remote < NR_CPUS; remote++) { 279 if (cpu_data[remote].core != core) 280 continue; 281 if (cpu_online(remote)) 282 break; 283 } 284 BUG_ON(remote >= NR_CPUS); 285 286 err = smp_call_function_single(remote, remote_vpe_boot, 287 NULL, 1); 288 if (err) 289 panic("Failed to call remote CPU\n"); 290 goto out; 291 } 292 293 BUG_ON(!cpu_has_mipsmt); 294 295 /* Boot a VPE on this core */ 296 mips_cps_boot_vpes(); 297 out: 298 preempt_enable(); 299 } 300 301 static void cps_init_secondary(void) 302 { 303 /* Disable MT - we only want to run 1 TC per VPE */ 304 if (cpu_has_mipsmt) 305 dmt(); 306 307 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | 308 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); 309 } 310 311 static void cps_smp_finish(void) 312 { 313 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); 314 315 #ifdef CONFIG_MIPS_MT_FPAFF 316 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 317 if (cpu_has_fpu) 318 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask); 319 #endif /* CONFIG_MIPS_MT_FPAFF */ 320 321 local_irq_enable(); 322 } 323 324 #ifdef CONFIG_HOTPLUG_CPU 325 326 static int cps_cpu_disable(void) 327 { 328 unsigned cpu = smp_processor_id(); 329 struct core_boot_config *core_cfg; 330 331 if (!cpu) 332 return -EBUSY; 333 334 if (!cps_pm_support_state(CPS_PM_POWER_GATED)) 335 return -EINVAL; 336 337 core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core]; 338 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask); 339 smp_mb__after_atomic(); 340 set_cpu_online(cpu, false); 341 cpumask_clear_cpu(cpu, &cpu_callin_map); 342 343 return 0; 344 } 345 346 static DECLARE_COMPLETION(cpu_death_chosen); 347 static unsigned cpu_death_sibling; 348 static enum { 349 CPU_DEATH_HALT, 350 CPU_DEATH_POWER, 351 } cpu_death; 352 353 void play_dead(void) 354 { 355 unsigned cpu, core; 356 357 local_irq_disable(); 358 idle_task_exit(); 359 cpu = smp_processor_id(); 360 cpu_death = CPU_DEATH_POWER; 361 362 if (cpu_has_mipsmt) { 363 core = cpu_data[cpu].core; 364 365 /* Look for another online VPE within the core */ 366 for_each_online_cpu(cpu_death_sibling) { 367 if (cpu_data[cpu_death_sibling].core != core) 368 continue; 369 370 /* 371 * There is an online VPE within the core. Just halt 372 * this TC and leave the core alone. 373 */ 374 cpu_death = CPU_DEATH_HALT; 375 break; 376 } 377 } 378 379 /* This CPU has chosen its way out */ 380 complete(&cpu_death_chosen); 381 382 if (cpu_death == CPU_DEATH_HALT) { 383 /* Halt this TC */ 384 write_c0_tchalt(TCHALT_H); 385 instruction_hazard(); 386 } else { 387 /* Power down the core */ 388 cps_pm_enter_state(CPS_PM_POWER_GATED); 389 } 390 391 /* This should never be reached */ 392 panic("Failed to offline CPU %u", cpu); 393 } 394 395 static void wait_for_sibling_halt(void *ptr_cpu) 396 { 397 unsigned cpu = (unsigned long)ptr_cpu; 398 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); 399 unsigned halted; 400 unsigned long flags; 401 402 do { 403 local_irq_save(flags); 404 settc(vpe_id); 405 halted = read_tc_c0_tchalt(); 406 local_irq_restore(flags); 407 } while (!(halted & TCHALT_H)); 408 } 409 410 static void cps_cpu_die(unsigned int cpu) 411 { 412 unsigned core = cpu_data[cpu].core; 413 unsigned stat; 414 int err; 415 416 /* Wait for the cpu to choose its way out */ 417 if (!wait_for_completion_timeout(&cpu_death_chosen, 418 msecs_to_jiffies(5000))) { 419 pr_err("CPU%u: didn't offline\n", cpu); 420 return; 421 } 422 423 /* 424 * Now wait for the CPU to actually offline. Without doing this that 425 * offlining may race with one or more of: 426 * 427 * - Onlining the CPU again. 428 * - Powering down the core if another VPE within it is offlined. 429 * - A sibling VPE entering a non-coherent state. 430 * 431 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing 432 * with which we could race, so do nothing. 433 */ 434 if (cpu_death == CPU_DEATH_POWER) { 435 /* 436 * Wait for the core to enter a powered down or clock gated 437 * state, the latter happening when a JTAG probe is connected 438 * in which case the CPC will refuse to power down the core. 439 */ 440 do { 441 mips_cpc_lock_other(core); 442 stat = read_cpc_co_stat_conf(); 443 stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK; 444 mips_cpc_unlock_other(); 445 } while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 && 446 stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 && 447 stat != CPC_Cx_STAT_CONF_SEQSTATE_U2); 448 449 /* Indicate the core is powered off */ 450 bitmap_clear(core_power, core, 1); 451 } else if (cpu_has_mipsmt) { 452 /* 453 * Have a CPU with access to the offlined CPUs registers wait 454 * for its TC to halt. 455 */ 456 err = smp_call_function_single(cpu_death_sibling, 457 wait_for_sibling_halt, 458 (void *)(unsigned long)cpu, 1); 459 if (err) 460 panic("Failed to call remote sibling CPU\n"); 461 } 462 } 463 464 #endif /* CONFIG_HOTPLUG_CPU */ 465 466 static struct plat_smp_ops cps_smp_ops = { 467 .smp_setup = cps_smp_setup, 468 .prepare_cpus = cps_prepare_cpus, 469 .boot_secondary = cps_boot_secondary, 470 .init_secondary = cps_init_secondary, 471 .smp_finish = cps_smp_finish, 472 .send_ipi_single = gic_send_ipi_single, 473 .send_ipi_mask = gic_send_ipi_mask, 474 #ifdef CONFIG_HOTPLUG_CPU 475 .cpu_disable = cps_cpu_disable, 476 .cpu_die = cps_cpu_die, 477 #endif 478 }; 479 480 bool mips_cps_smp_in_use(void) 481 { 482 extern struct plat_smp_ops *mp_ops; 483 return mp_ops == &cps_smp_ops; 484 } 485 486 int register_cps_smp_ops(void) 487 { 488 if (!mips_cm_present()) { 489 pr_warn("MIPS CPS SMP unable to proceed without a CM\n"); 490 return -ENODEV; 491 } 492 493 /* check we have a GIC - we need one for IPIs */ 494 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) { 495 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n"); 496 return -ENODEV; 497 } 498 499 register_smp_ops(&cps_smp_ops); 500 return 0; 501 } 502