1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2013 Imagination Technologies 4 * Author: Paul Burton <paul.burton@mips.com> 5 */ 6 7 #include <linux/cpu.h> 8 #include <linux/delay.h> 9 #include <linux/io.h> 10 #include <linux/sched/task_stack.h> 11 #include <linux/sched/hotplug.h> 12 #include <linux/slab.h> 13 #include <linux/smp.h> 14 #include <linux/types.h> 15 #include <linux/irq.h> 16 17 #include <asm/bcache.h> 18 #include <asm/mips-cps.h> 19 #include <asm/mips_mt.h> 20 #include <asm/mipsregs.h> 21 #include <asm/pm-cps.h> 22 #include <asm/r4kcache.h> 23 #include <asm/smp-cps.h> 24 #include <asm/time.h> 25 #include <asm/uasm.h> 26 27 static bool threads_disabled; 28 static DECLARE_BITMAP(core_power, NR_CPUS); 29 30 struct core_boot_config *mips_cps_core_bootcfg; 31 32 static int __init setup_nothreads(char *s) 33 { 34 threads_disabled = true; 35 return 0; 36 } 37 early_param("nothreads", setup_nothreads); 38 39 static unsigned core_vpe_count(unsigned int cluster, unsigned core) 40 { 41 if (threads_disabled) 42 return 1; 43 44 return mips_cps_numvps(cluster, core); 45 } 46 47 static void __init cps_smp_setup(void) 48 { 49 unsigned int nclusters, ncores, nvpes, core_vpes; 50 unsigned long core_entry; 51 int cl, c, v; 52 53 /* Detect & record VPE topology */ 54 nvpes = 0; 55 nclusters = mips_cps_numclusters(); 56 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE"); 57 for (cl = 0; cl < nclusters; cl++) { 58 if (cl > 0) 59 pr_cont(","); 60 pr_cont("{"); 61 62 ncores = mips_cps_numcores(cl); 63 for (c = 0; c < ncores; c++) { 64 core_vpes = core_vpe_count(cl, c); 65 66 if (c > 0) 67 pr_cont(","); 68 pr_cont("%u", core_vpes); 69 70 /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */ 71 if (!cl && !c) 72 smp_num_siblings = core_vpes; 73 74 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { 75 cpu_set_cluster(&cpu_data[nvpes + v], cl); 76 cpu_set_core(&cpu_data[nvpes + v], c); 77 cpu_set_vpe_id(&cpu_data[nvpes + v], v); 78 } 79 80 nvpes += core_vpes; 81 } 82 83 pr_cont("}"); 84 } 85 pr_cont(" total %u\n", nvpes); 86 87 /* Indicate present CPUs (CPU being synonymous with VPE) */ 88 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { 89 set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0); 90 set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0); 91 __cpu_number_map[v] = v; 92 __cpu_logical_map[v] = v; 93 } 94 95 /* Set a coherent default CCA (CWB) */ 96 change_c0_config(CONF_CM_CMASK, 0x5); 97 98 /* Core 0 is powered up (we're running on it) */ 99 bitmap_set(core_power, 0, 1); 100 101 /* Initialise core 0 */ 102 mips_cps_core_init(); 103 104 /* Make core 0 coherent with everything */ 105 write_gcr_cl_coherence(0xff); 106 107 if (mips_cm_revision() >= CM_REV_CM3) { 108 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); 109 write_gcr_bev_base(core_entry); 110 } 111 112 #ifdef CONFIG_MIPS_MT_FPAFF 113 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 114 if (cpu_has_fpu) 115 cpumask_set_cpu(0, &mt_fpu_cpumask); 116 #endif /* CONFIG_MIPS_MT_FPAFF */ 117 } 118 119 static void __init cps_prepare_cpus(unsigned int max_cpus) 120 { 121 unsigned ncores, core_vpes, c, cca; 122 bool cca_unsuitable, cores_limited; 123 u32 *entry_code; 124 125 mips_mt_set_cpuoptions(); 126 127 /* Detect whether the CCA is unsuited to multi-core SMP */ 128 cca = read_c0_config() & CONF_CM_CMASK; 129 switch (cca) { 130 case 0x4: /* CWBE */ 131 case 0x5: /* CWB */ 132 /* The CCA is coherent, multi-core is fine */ 133 cca_unsuitable = false; 134 break; 135 136 default: 137 /* CCA is not coherent, multi-core is not usable */ 138 cca_unsuitable = true; 139 } 140 141 /* Warn the user if the CCA prevents multi-core */ 142 cores_limited = false; 143 if (cca_unsuitable || cpu_has_dc_aliases) { 144 for_each_present_cpu(c) { 145 if (cpus_are_siblings(smp_processor_id(), c)) 146 continue; 147 148 set_cpu_present(c, false); 149 cores_limited = true; 150 } 151 } 152 if (cores_limited) 153 pr_warn("Using only one core due to %s%s%s\n", 154 cca_unsuitable ? "unsuitable CCA" : "", 155 (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", 156 cpu_has_dc_aliases ? "dcache aliasing" : ""); 157 158 /* 159 * Patch the start of mips_cps_core_entry to provide: 160 * 161 * s0 = kseg0 CCA 162 */ 163 entry_code = (u32 *)&mips_cps_core_entry; 164 uasm_i_addiu(&entry_code, 16, 0, cca); 165 UASM_i_LA(&entry_code, 17, (long)mips_gcr_base); 166 BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end); 167 blast_dcache_range((unsigned long)&mips_cps_core_entry, 168 (unsigned long)entry_code); 169 bc_wback_inv((unsigned long)&mips_cps_core_entry, 170 (void *)entry_code - (void *)&mips_cps_core_entry); 171 __sync(); 172 173 /* Allocate core boot configuration structs */ 174 ncores = mips_cps_numcores(0); 175 mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), 176 GFP_KERNEL); 177 if (!mips_cps_core_bootcfg) { 178 pr_err("Failed to allocate boot config for %u cores\n", ncores); 179 goto err_out; 180 } 181 182 /* Allocate VPE boot configuration structs */ 183 for (c = 0; c < ncores; c++) { 184 core_vpes = core_vpe_count(0, c); 185 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes, 186 sizeof(*mips_cps_core_bootcfg[c].vpe_config), 187 GFP_KERNEL); 188 if (!mips_cps_core_bootcfg[c].vpe_config) { 189 pr_err("Failed to allocate %u VPE boot configs\n", 190 core_vpes); 191 goto err_out; 192 } 193 } 194 195 /* Mark this CPU as booted */ 196 atomic_set(&mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)].vpe_mask, 197 1 << cpu_vpe_id(¤t_cpu_data)); 198 199 return; 200 err_out: 201 /* Clean up allocations */ 202 if (mips_cps_core_bootcfg) { 203 for (c = 0; c < ncores; c++) 204 kfree(mips_cps_core_bootcfg[c].vpe_config); 205 kfree(mips_cps_core_bootcfg); 206 mips_cps_core_bootcfg = NULL; 207 } 208 209 /* Effectively disable SMP by declaring CPUs not present */ 210 for_each_possible_cpu(c) { 211 if (c == 0) 212 continue; 213 set_cpu_present(c, false); 214 } 215 } 216 217 static void boot_core(unsigned int core, unsigned int vpe_id) 218 { 219 u32 stat, seq_state; 220 unsigned timeout; 221 222 /* Select the appropriate core */ 223 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 224 225 /* Set its reset vector */ 226 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); 227 228 /* Ensure its coherency is disabled */ 229 write_gcr_co_coherence(0); 230 231 /* Start it with the legacy memory map and exception base */ 232 write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB); 233 234 /* Ensure the core can access the GCRs */ 235 set_gcr_access(1 << core); 236 237 if (mips_cpc_present()) { 238 /* Reset the core */ 239 mips_cpc_lock_other(core); 240 241 if (mips_cm_revision() >= CM_REV_CM3) { 242 /* Run only the requested VP following the reset */ 243 write_cpc_co_vp_stop(0xf); 244 write_cpc_co_vp_run(1 << vpe_id); 245 246 /* 247 * Ensure that the VP_RUN register is written before the 248 * core leaves reset. 249 */ 250 wmb(); 251 } 252 253 write_cpc_co_cmd(CPC_Cx_CMD_RESET); 254 255 timeout = 100; 256 while (true) { 257 stat = read_cpc_co_stat_conf(); 258 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 259 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 260 261 /* U6 == coherent execution, ie. the core is up */ 262 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6) 263 break; 264 265 /* Delay a little while before we start warning */ 266 if (timeout) { 267 timeout--; 268 mdelay(10); 269 continue; 270 } 271 272 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n", 273 core, stat); 274 mdelay(1000); 275 } 276 277 mips_cpc_unlock_other(); 278 } else { 279 /* Take the core out of reset */ 280 write_gcr_co_reset_release(0); 281 } 282 283 mips_cm_unlock_other(); 284 285 /* The core is now powered up */ 286 bitmap_set(core_power, core, 1); 287 } 288 289 static void remote_vpe_boot(void *dummy) 290 { 291 unsigned core = cpu_core(¤t_cpu_data); 292 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; 293 294 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data)); 295 } 296 297 static int cps_boot_secondary(int cpu, struct task_struct *idle) 298 { 299 unsigned core = cpu_core(&cpu_data[cpu]); 300 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); 301 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; 302 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; 303 unsigned long core_entry; 304 unsigned int remote; 305 int err; 306 307 /* We don't yet support booting CPUs in other clusters */ 308 if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data)) 309 return -ENOSYS; 310 311 vpe_cfg->pc = (unsigned long)&smp_bootstrap; 312 vpe_cfg->sp = __KSTK_TOS(idle); 313 vpe_cfg->gp = (unsigned long)task_thread_info(idle); 314 315 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask); 316 317 preempt_disable(); 318 319 if (!test_bit(core, core_power)) { 320 /* Boot a VPE on a powered down core */ 321 boot_core(core, vpe_id); 322 goto out; 323 } 324 325 if (cpu_has_vp) { 326 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 327 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); 328 write_gcr_co_reset_base(core_entry); 329 mips_cm_unlock_other(); 330 } 331 332 if (!cpus_are_siblings(cpu, smp_processor_id())) { 333 /* Boot a VPE on another powered up core */ 334 for (remote = 0; remote < NR_CPUS; remote++) { 335 if (!cpus_are_siblings(cpu, remote)) 336 continue; 337 if (cpu_online(remote)) 338 break; 339 } 340 if (remote >= NR_CPUS) { 341 pr_crit("No online CPU in core %u to start CPU%d\n", 342 core, cpu); 343 goto out; 344 } 345 346 err = smp_call_function_single(remote, remote_vpe_boot, 347 NULL, 1); 348 if (err) 349 panic("Failed to call remote CPU\n"); 350 goto out; 351 } 352 353 BUG_ON(!cpu_has_mipsmt && !cpu_has_vp); 354 355 /* Boot a VPE on this core */ 356 mips_cps_boot_vpes(core_cfg, vpe_id); 357 out: 358 preempt_enable(); 359 return 0; 360 } 361 362 static void cps_init_secondary(void) 363 { 364 /* Disable MT - we only want to run 1 TC per VPE */ 365 if (cpu_has_mipsmt) 366 dmt(); 367 368 if (mips_cm_revision() >= CM_REV_CM3) { 369 unsigned int ident = read_gic_vl_ident(); 370 371 /* 372 * Ensure that our calculation of the VP ID matches up with 373 * what the GIC reports, otherwise we'll have configured 374 * interrupts incorrectly. 375 */ 376 BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); 377 } 378 379 if (cpu_has_veic) 380 clear_c0_status(ST0_IM); 381 else 382 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | 383 STATUSF_IP4 | STATUSF_IP5 | 384 STATUSF_IP6 | STATUSF_IP7); 385 } 386 387 static void cps_smp_finish(void) 388 { 389 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); 390 391 #ifdef CONFIG_MIPS_MT_FPAFF 392 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 393 if (cpu_has_fpu) 394 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask); 395 #endif /* CONFIG_MIPS_MT_FPAFF */ 396 397 local_irq_enable(); 398 } 399 400 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC) 401 402 enum cpu_death { 403 CPU_DEATH_HALT, 404 CPU_DEATH_POWER, 405 }; 406 407 static void cps_shutdown_this_cpu(enum cpu_death death) 408 { 409 unsigned int cpu, core, vpe_id; 410 411 cpu = smp_processor_id(); 412 core = cpu_core(&cpu_data[cpu]); 413 414 if (death == CPU_DEATH_HALT) { 415 vpe_id = cpu_vpe_id(&cpu_data[cpu]); 416 417 pr_debug("Halting core %d VP%d\n", core, vpe_id); 418 if (cpu_has_mipsmt) { 419 /* Halt this TC */ 420 write_c0_tchalt(TCHALT_H); 421 instruction_hazard(); 422 } else if (cpu_has_vp) { 423 write_cpc_cl_vp_stop(1 << vpe_id); 424 425 /* Ensure that the VP_STOP register is written */ 426 wmb(); 427 } 428 } else { 429 if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) { 430 pr_debug("Gating power to core %d\n", core); 431 /* Power down the core */ 432 cps_pm_enter_state(CPS_PM_POWER_GATED); 433 } 434 } 435 } 436 437 #ifdef CONFIG_KEXEC 438 439 static void cps_kexec_nonboot_cpu(void) 440 { 441 if (cpu_has_mipsmt || cpu_has_vp) 442 cps_shutdown_this_cpu(CPU_DEATH_HALT); 443 else 444 cps_shutdown_this_cpu(CPU_DEATH_POWER); 445 } 446 447 #endif /* CONFIG_KEXEC */ 448 449 #endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC */ 450 451 #ifdef CONFIG_HOTPLUG_CPU 452 453 static int cps_cpu_disable(void) 454 { 455 unsigned cpu = smp_processor_id(); 456 struct core_boot_config *core_cfg; 457 458 if (!cps_pm_support_state(CPS_PM_POWER_GATED)) 459 return -EINVAL; 460 461 core_cfg = &mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)]; 462 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask); 463 smp_mb__after_atomic(); 464 set_cpu_online(cpu, false); 465 calculate_cpu_foreign_map(); 466 irq_migrate_all_off_this_cpu(); 467 468 return 0; 469 } 470 471 static unsigned cpu_death_sibling; 472 static enum cpu_death cpu_death; 473 474 void play_dead(void) 475 { 476 unsigned int cpu; 477 478 local_irq_disable(); 479 idle_task_exit(); 480 cpu = smp_processor_id(); 481 cpu_death = CPU_DEATH_POWER; 482 483 pr_debug("CPU%d going offline\n", cpu); 484 485 if (cpu_has_mipsmt || cpu_has_vp) { 486 /* Look for another online VPE within the core */ 487 for_each_online_cpu(cpu_death_sibling) { 488 if (!cpus_are_siblings(cpu, cpu_death_sibling)) 489 continue; 490 491 /* 492 * There is an online VPE within the core. Just halt 493 * this TC and leave the core alone. 494 */ 495 cpu_death = CPU_DEATH_HALT; 496 break; 497 } 498 } 499 500 /* This CPU has chosen its way out */ 501 (void)cpu_report_death(); 502 503 cps_shutdown_this_cpu(cpu_death); 504 505 /* This should never be reached */ 506 panic("Failed to offline CPU %u", cpu); 507 } 508 509 static void wait_for_sibling_halt(void *ptr_cpu) 510 { 511 unsigned cpu = (unsigned long)ptr_cpu; 512 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); 513 unsigned halted; 514 unsigned long flags; 515 516 do { 517 local_irq_save(flags); 518 settc(vpe_id); 519 halted = read_tc_c0_tchalt(); 520 local_irq_restore(flags); 521 } while (!(halted & TCHALT_H)); 522 } 523 524 static void cps_cpu_die(unsigned int cpu) 525 { 526 unsigned core = cpu_core(&cpu_data[cpu]); 527 unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]); 528 ktime_t fail_time; 529 unsigned stat; 530 int err; 531 532 /* Wait for the cpu to choose its way out */ 533 if (!cpu_wait_death(cpu, 5)) { 534 pr_err("CPU%u: didn't offline\n", cpu); 535 return; 536 } 537 538 /* 539 * Now wait for the CPU to actually offline. Without doing this that 540 * offlining may race with one or more of: 541 * 542 * - Onlining the CPU again. 543 * - Powering down the core if another VPE within it is offlined. 544 * - A sibling VPE entering a non-coherent state. 545 * 546 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing 547 * with which we could race, so do nothing. 548 */ 549 if (cpu_death == CPU_DEATH_POWER) { 550 /* 551 * Wait for the core to enter a powered down or clock gated 552 * state, the latter happening when a JTAG probe is connected 553 * in which case the CPC will refuse to power down the core. 554 */ 555 fail_time = ktime_add_ms(ktime_get(), 2000); 556 do { 557 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 558 mips_cpc_lock_other(core); 559 stat = read_cpc_co_stat_conf(); 560 stat &= CPC_Cx_STAT_CONF_SEQSTATE; 561 stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 562 mips_cpc_unlock_other(); 563 mips_cm_unlock_other(); 564 565 if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 || 566 stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 || 567 stat == CPC_Cx_STAT_CONF_SEQSTATE_U2) 568 break; 569 570 /* 571 * The core ought to have powered down, but didn't & 572 * now we don't really know what state it's in. It's 573 * likely that its _pwr_up pin has been wired to logic 574 * 1 & it powered back up as soon as we powered it 575 * down... 576 * 577 * The best we can do is warn the user & continue in 578 * the hope that the core is doing nothing harmful & 579 * might behave properly if we online it later. 580 */ 581 if (WARN(ktime_after(ktime_get(), fail_time), 582 "CPU%u hasn't powered down, seq. state %u\n", 583 cpu, stat)) 584 break; 585 } while (1); 586 587 /* Indicate the core is powered off */ 588 bitmap_clear(core_power, core, 1); 589 } else if (cpu_has_mipsmt) { 590 /* 591 * Have a CPU with access to the offlined CPUs registers wait 592 * for its TC to halt. 593 */ 594 err = smp_call_function_single(cpu_death_sibling, 595 wait_for_sibling_halt, 596 (void *)(unsigned long)cpu, 1); 597 if (err) 598 panic("Failed to call remote sibling CPU\n"); 599 } else if (cpu_has_vp) { 600 do { 601 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 602 stat = read_cpc_co_vp_running(); 603 mips_cm_unlock_other(); 604 } while (stat & (1 << vpe_id)); 605 } 606 } 607 608 #endif /* CONFIG_HOTPLUG_CPU */ 609 610 static const struct plat_smp_ops cps_smp_ops = { 611 .smp_setup = cps_smp_setup, 612 .prepare_cpus = cps_prepare_cpus, 613 .boot_secondary = cps_boot_secondary, 614 .init_secondary = cps_init_secondary, 615 .smp_finish = cps_smp_finish, 616 .send_ipi_single = mips_smp_send_ipi_single, 617 .send_ipi_mask = mips_smp_send_ipi_mask, 618 #ifdef CONFIG_HOTPLUG_CPU 619 .cpu_disable = cps_cpu_disable, 620 .cpu_die = cps_cpu_die, 621 #endif 622 #ifdef CONFIG_KEXEC 623 .kexec_nonboot_cpu = cps_kexec_nonboot_cpu, 624 #endif 625 }; 626 627 bool mips_cps_smp_in_use(void) 628 { 629 extern const struct plat_smp_ops *mp_ops; 630 return mp_ops == &cps_smp_ops; 631 } 632 633 int register_cps_smp_ops(void) 634 { 635 if (!mips_cm_present()) { 636 pr_warn("MIPS CPS SMP unable to proceed without a CM\n"); 637 return -ENODEV; 638 } 639 640 /* check we have a GIC - we need one for IPIs */ 641 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) { 642 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n"); 643 return -ENODEV; 644 } 645 646 register_smp_ops(&cps_smp_ops); 647 return 0; 648 } 649