1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) 7 * 8 * SMP support for BMIPS 9 */ 10 11 #include <linux/init.h> 12 #include <linux/sched.h> 13 #include <linux/sched/hotplug.h> 14 #include <linux/sched/task_stack.h> 15 #include <linux/mm.h> 16 #include <linux/delay.h> 17 #include <linux/smp.h> 18 #include <linux/interrupt.h> 19 #include <linux/spinlock.h> 20 #include <linux/cpu.h> 21 #include <linux/cpumask.h> 22 #include <linux/reboot.h> 23 #include <linux/io.h> 24 #include <linux/compiler.h> 25 #include <linux/linkage.h> 26 #include <linux/bug.h> 27 #include <linux/kernel.h> 28 #include <linux/kexec.h> 29 30 #include <asm/time.h> 31 #include <asm/processor.h> 32 #include <asm/bootinfo.h> 33 #include <asm/cacheflush.h> 34 #include <asm/tlbflush.h> 35 #include <asm/mipsregs.h> 36 #include <asm/bmips.h> 37 #include <asm/traps.h> 38 #include <asm/barrier.h> 39 #include <asm/cpu-features.h> 40 41 static int __maybe_unused max_cpus = 1; 42 43 /* these may be configured by the platform code */ 44 int bmips_smp_enabled = 1; 45 int bmips_cpu_offset; 46 cpumask_t bmips_booted_mask; 47 unsigned long bmips_tp1_irqs = IE_IRQ1; 48 49 #define RESET_FROM_KSEG0 0x80080800 50 #define RESET_FROM_KSEG1 0xa0080800 51 52 static void bmips_set_reset_vec(int cpu, u32 val); 53 54 #ifdef CONFIG_SMP 55 56 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */ 57 unsigned long bmips_smp_boot_sp; 58 unsigned long bmips_smp_boot_gp; 59 60 static void bmips43xx_send_ipi_single(int cpu, unsigned int action); 61 static void bmips5000_send_ipi_single(int cpu, unsigned int action); 62 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id); 63 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id); 64 65 /* SW interrupts 0,1 are used for interprocessor signaling */ 66 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) 67 #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1) 68 69 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) 70 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 71 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 72 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) 73 74 static void __init bmips_smp_setup(void) 75 { 76 int i, cpu = 1, boot_cpu = 0; 77 int cpu_hw_intr; 78 79 switch (current_cpu_type()) { 80 case CPU_BMIPS4350: 81 case CPU_BMIPS4380: 82 /* arbitration priority */ 83 clear_c0_brcm_cmt_ctrl(0x30); 84 85 /* NBK and weak order flags */ 86 set_c0_brcm_config_0(0x30000); 87 88 /* Find out if we are running on TP0 or TP1 */ 89 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 90 91 /* 92 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other 93 * thread 94 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 95 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 96 */ 97 if (boot_cpu == 0) 98 cpu_hw_intr = 0x02; 99 else 100 cpu_hw_intr = 0x1d; 101 102 change_c0_brcm_cmt_intr(0xf8018000, 103 (cpu_hw_intr << 27) | (0x03 << 15)); 104 105 /* single core, 2 threads (2 pipelines) */ 106 max_cpus = 2; 107 108 break; 109 case CPU_BMIPS5000: 110 /* enable raceless SW interrupts */ 111 set_c0_brcm_config(0x03 << 22); 112 113 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ 114 change_c0_brcm_mode(0x1f << 27, 0x02 << 27); 115 116 /* N cores, 2 threads per core */ 117 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; 118 119 /* clear any pending SW interrupts */ 120 for (i = 0; i < max_cpus; i++) { 121 write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); 122 write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); 123 } 124 125 break; 126 default: 127 max_cpus = 1; 128 } 129 130 if (!bmips_smp_enabled) 131 max_cpus = 1; 132 133 /* this can be overridden by the BSP */ 134 if (!board_ebase_setup) 135 board_ebase_setup = &bmips_ebase_setup; 136 137 __cpu_number_map[boot_cpu] = 0; 138 __cpu_logical_map[0] = boot_cpu; 139 140 for (i = 0; i < max_cpus; i++) { 141 if (i != boot_cpu) { 142 __cpu_number_map[i] = cpu; 143 __cpu_logical_map[cpu] = i; 144 cpu++; 145 } 146 set_cpu_possible(i, 1); 147 set_cpu_present(i, 1); 148 } 149 } 150 151 /* 152 * IPI IRQ setup - runs on CPU0 153 */ 154 static void bmips_prepare_cpus(unsigned int max_cpus) 155 { 156 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id); 157 158 switch (current_cpu_type()) { 159 case CPU_BMIPS4350: 160 case CPU_BMIPS4380: 161 bmips_ipi_interrupt = bmips43xx_ipi_interrupt; 162 break; 163 case CPU_BMIPS5000: 164 bmips_ipi_interrupt = bmips5000_ipi_interrupt; 165 break; 166 default: 167 return; 168 } 169 170 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, 171 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi0", NULL)) 172 panic("Can't request IPI0 interrupt"); 173 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, 174 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi1", NULL)) 175 panic("Can't request IPI1 interrupt"); 176 } 177 178 /* 179 * Tell the hardware to boot CPUx - runs on CPU0 180 */ 181 static int bmips_boot_secondary(int cpu, struct task_struct *idle) 182 { 183 bmips_smp_boot_sp = __KSTK_TOS(idle); 184 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle); 185 mb(); 186 187 /* 188 * Initial boot sequence for secondary CPU: 189 * bmips_reset_nmi_vec @ a000_0000 -> 190 * bmips_smp_entry -> 191 * plat_wired_tlb_setup (cached function call; optional) -> 192 * start_secondary (cached jump) 193 * 194 * Warm restart sequence: 195 * play_dead WAIT loop -> 196 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC -> 197 * eret to play_dead -> 198 * bmips_secondary_reentry -> 199 * start_secondary 200 */ 201 202 pr_info("SMP: Booting CPU%d...\n", cpu); 203 204 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { 205 /* kseg1 might not exist if this CPU enabled XKS01 */ 206 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0); 207 208 switch (current_cpu_type()) { 209 case CPU_BMIPS4350: 210 case CPU_BMIPS4380: 211 bmips43xx_send_ipi_single(cpu, 0); 212 break; 213 case CPU_BMIPS5000: 214 bmips5000_send_ipi_single(cpu, 0); 215 break; 216 } 217 } else { 218 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1); 219 220 switch (current_cpu_type()) { 221 case CPU_BMIPS4350: 222 case CPU_BMIPS4380: 223 /* Reset slave TP1 if booting from TP0 */ 224 if (cpu_logical_map(cpu) == 1) 225 set_c0_brcm_cmt_ctrl(0x01); 226 break; 227 case CPU_BMIPS5000: 228 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); 229 break; 230 } 231 cpumask_set_cpu(cpu, &bmips_booted_mask); 232 } 233 234 return 0; 235 } 236 237 /* 238 * Early setup - runs on secondary CPU after cache probe 239 */ 240 static void bmips_init_secondary(void) 241 { 242 bmips_cpu_setup(); 243 244 switch (current_cpu_type()) { 245 case CPU_BMIPS4350: 246 case CPU_BMIPS4380: 247 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); 248 break; 249 case CPU_BMIPS5000: 250 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); 251 cpu_set_core(¤t_cpu_data, (read_c0_brcm_config() >> 25) & 3); 252 break; 253 } 254 } 255 256 /* 257 * Late setup - runs on secondary CPU before entering the idle loop 258 */ 259 static void bmips_smp_finish(void) 260 { 261 pr_info("SMP: CPU%d is running\n", smp_processor_id()); 262 263 /* make sure there won't be a timer interrupt for a little while */ 264 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 265 266 irq_enable_hazard(); 267 set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE); 268 irq_enable_hazard(); 269 } 270 271 /* 272 * BMIPS5000 raceless IPIs 273 * 274 * Each CPU has two inbound SW IRQs which are independent of all other CPUs. 275 * IPI0 is used for SMP_RESCHEDULE_YOURSELF 276 * IPI1 is used for SMP_CALL_FUNCTION 277 */ 278 279 static void bmips5000_send_ipi_single(int cpu, unsigned int action) 280 { 281 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); 282 } 283 284 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) 285 { 286 int action = irq - IPI0_IRQ; 287 288 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action)); 289 290 if (action == 0) 291 scheduler_ipi(); 292 else 293 generic_smp_call_function_interrupt(); 294 295 return IRQ_HANDLED; 296 } 297 298 static void bmips5000_send_ipi_mask(const struct cpumask *mask, 299 unsigned int action) 300 { 301 unsigned int i; 302 303 for_each_cpu(i, mask) 304 bmips5000_send_ipi_single(i, action); 305 } 306 307 /* 308 * BMIPS43xx racey IPIs 309 * 310 * We use one inbound SW IRQ for each CPU. 311 * 312 * A spinlock must be held in order to keep CPUx from accidentally clearing 313 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The 314 * same spinlock is used to protect the action masks. 315 */ 316 317 static DEFINE_SPINLOCK(ipi_lock); 318 static DEFINE_PER_CPU(int, ipi_action_mask); 319 320 static void bmips43xx_send_ipi_single(int cpu, unsigned int action) 321 { 322 unsigned long flags; 323 324 spin_lock_irqsave(&ipi_lock, flags); 325 set_c0_cause(cpu ? C_SW1 : C_SW0); 326 per_cpu(ipi_action_mask, cpu) |= action; 327 irq_enable_hazard(); 328 spin_unlock_irqrestore(&ipi_lock, flags); 329 } 330 331 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) 332 { 333 unsigned long flags; 334 int action, cpu = irq - IPI0_IRQ; 335 336 spin_lock_irqsave(&ipi_lock, flags); 337 action = __this_cpu_read(ipi_action_mask); 338 per_cpu(ipi_action_mask, cpu) = 0; 339 clear_c0_cause(cpu ? C_SW1 : C_SW0); 340 spin_unlock_irqrestore(&ipi_lock, flags); 341 342 if (action & SMP_RESCHEDULE_YOURSELF) 343 scheduler_ipi(); 344 if (action & SMP_CALL_FUNCTION) 345 generic_smp_call_function_interrupt(); 346 347 return IRQ_HANDLED; 348 } 349 350 static void bmips43xx_send_ipi_mask(const struct cpumask *mask, 351 unsigned int action) 352 { 353 unsigned int i; 354 355 for_each_cpu(i, mask) 356 bmips43xx_send_ipi_single(i, action); 357 } 358 359 #ifdef CONFIG_HOTPLUG_CPU 360 361 static int bmips_cpu_disable(void) 362 { 363 unsigned int cpu = smp_processor_id(); 364 365 if (cpu == 0) 366 return -EBUSY; 367 368 pr_info("SMP: CPU%d is offline\n", cpu); 369 370 set_cpu_online(cpu, false); 371 calculate_cpu_foreign_map(); 372 irq_cpu_offline(); 373 clear_c0_status(IE_IRQ5); 374 375 local_flush_tlb_all(); 376 local_flush_icache_range(0, ~0); 377 378 return 0; 379 } 380 381 static void bmips_cpu_die(unsigned int cpu) 382 { 383 } 384 385 void __ref play_dead(void) 386 { 387 idle_task_exit(); 388 389 /* flush data cache */ 390 _dma_cache_wback_inv(0, ~0); 391 392 /* 393 * Wakeup is on SW0 or SW1; disable everything else 394 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux 395 * IRQ handlers; this clears ST0_IE and returns immediately. 396 */ 397 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1); 398 change_c0_status( 399 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV, 400 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV); 401 irq_disable_hazard(); 402 403 /* 404 * wait for SW interrupt from bmips_boot_secondary(), then jump 405 * back to start_secondary() 406 */ 407 __asm__ __volatile__( 408 " wait\n" 409 " j bmips_secondary_reentry\n" 410 : : : "memory"); 411 } 412 413 #endif /* CONFIG_HOTPLUG_CPU */ 414 415 const struct plat_smp_ops bmips43xx_smp_ops = { 416 .smp_setup = bmips_smp_setup, 417 .prepare_cpus = bmips_prepare_cpus, 418 .boot_secondary = bmips_boot_secondary, 419 .smp_finish = bmips_smp_finish, 420 .init_secondary = bmips_init_secondary, 421 .send_ipi_single = bmips43xx_send_ipi_single, 422 .send_ipi_mask = bmips43xx_send_ipi_mask, 423 #ifdef CONFIG_HOTPLUG_CPU 424 .cpu_disable = bmips_cpu_disable, 425 .cpu_die = bmips_cpu_die, 426 #endif 427 #ifdef CONFIG_KEXEC 428 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 429 #endif 430 }; 431 432 const struct plat_smp_ops bmips5000_smp_ops = { 433 .smp_setup = bmips_smp_setup, 434 .prepare_cpus = bmips_prepare_cpus, 435 .boot_secondary = bmips_boot_secondary, 436 .smp_finish = bmips_smp_finish, 437 .init_secondary = bmips_init_secondary, 438 .send_ipi_single = bmips5000_send_ipi_single, 439 .send_ipi_mask = bmips5000_send_ipi_mask, 440 #ifdef CONFIG_HOTPLUG_CPU 441 .cpu_disable = bmips_cpu_disable, 442 .cpu_die = bmips_cpu_die, 443 #endif 444 #ifdef CONFIG_KEXEC 445 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 446 #endif 447 }; 448 449 #endif /* CONFIG_SMP */ 450 451 /*********************************************************************** 452 * BMIPS vector relocation 453 * This is primarily used for SMP boot, but it is applicable to some 454 * UP BMIPS systems as well. 455 ***********************************************************************/ 456 457 static void bmips_wr_vec(unsigned long dst, char *start, char *end) 458 { 459 memcpy((void *)dst, start, end - start); 460 dma_cache_wback(dst, end - start); 461 local_flush_icache_range(dst, dst + (end - start)); 462 instruction_hazard(); 463 } 464 465 static inline void bmips_nmi_handler_setup(void) 466 { 467 bmips_wr_vec(BMIPS_NMI_RESET_VEC, bmips_reset_nmi_vec, 468 bmips_reset_nmi_vec_end); 469 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, bmips_smp_int_vec, 470 bmips_smp_int_vec_end); 471 } 472 473 struct reset_vec_info { 474 int cpu; 475 u32 val; 476 }; 477 478 static void bmips_set_reset_vec_remote(void *vinfo) 479 { 480 struct reset_vec_info *info = vinfo; 481 int shift = info->cpu & 0x01 ? 16 : 0; 482 u32 mask = ~(0xffff << shift), val = info->val >> 16; 483 484 preempt_disable(); 485 if (smp_processor_id() > 0) { 486 smp_call_function_single(0, &bmips_set_reset_vec_remote, 487 info, 1); 488 } else { 489 if (info->cpu & 0x02) { 490 /* BMIPS5200 "should" use mask/shift, but it's buggy */ 491 bmips_write_zscm_reg(0xa0, (val << 16) | val); 492 bmips_read_zscm_reg(0xa0); 493 } else { 494 write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) | 495 (val << shift)); 496 } 497 } 498 preempt_enable(); 499 } 500 501 static void bmips_set_reset_vec(int cpu, u32 val) 502 { 503 struct reset_vec_info info; 504 505 if (current_cpu_type() == CPU_BMIPS5000) { 506 /* this needs to run from CPU0 (which is always online) */ 507 info.cpu = cpu; 508 info.val = val; 509 bmips_set_reset_vec_remote(&info); 510 } else { 511 void __iomem *cbr = BMIPS_GET_CBR(); 512 513 if (cpu == 0) 514 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); 515 else { 516 if (current_cpu_type() != CPU_BMIPS4380) 517 return; 518 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); 519 } 520 } 521 __sync(); 522 back_to_back_c0_hazard(); 523 } 524 525 void bmips_ebase_setup(void) 526 { 527 unsigned long new_ebase = ebase; 528 529 BUG_ON(ebase != CKSEG0); 530 531 switch (current_cpu_type()) { 532 case CPU_BMIPS4350: 533 /* 534 * BMIPS4350 cannot relocate the normal vectors, but it 535 * can relocate the BEV=1 vectors. So CPU1 starts up at 536 * the relocated BEV=1, IV=0 general exception vector @ 537 * 0xa000_0380. 538 * 539 * set_uncached_handler() is used here because: 540 * - CPU1 will run this from uncached space 541 * - None of the cacheflush functions are set up yet 542 */ 543 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, 544 &bmips_smp_int_vec, 0x80); 545 __sync(); 546 return; 547 case CPU_BMIPS3300: 548 case CPU_BMIPS4380: 549 /* 550 * 0x8000_0000: reset/NMI (initially in kseg1) 551 * 0x8000_0400: normal vectors 552 */ 553 new_ebase = 0x80000400; 554 bmips_set_reset_vec(0, RESET_FROM_KSEG0); 555 break; 556 case CPU_BMIPS5000: 557 /* 558 * 0x8000_0000: reset/NMI (initially in kseg1) 559 * 0x8000_1000: normal vectors 560 */ 561 new_ebase = 0x80001000; 562 bmips_set_reset_vec(0, RESET_FROM_KSEG0); 563 write_c0_ebase(new_ebase); 564 break; 565 default: 566 return; 567 } 568 569 board_nmi_handler_setup = &bmips_nmi_handler_setup; 570 ebase = new_ebase; 571 } 572 573 asmlinkage void __weak plat_wired_tlb_setup(void) 574 { 575 /* 576 * Called when starting/restarting a secondary CPU. 577 * Kernel stacks and other important data might only be accessible 578 * once the wired entries are present. 579 */ 580 } 581 582 void bmips_cpu_setup(void) 583 { 584 void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); 585 u32 __maybe_unused cfg; 586 587 switch (current_cpu_type()) { 588 case CPU_BMIPS3300: 589 /* Set BIU to async mode */ 590 set_c0_brcm_bus_pll(BIT(22)); 591 __sync(); 592 593 /* put the BIU back in sync mode */ 594 clear_c0_brcm_bus_pll(BIT(22)); 595 596 /* clear BHTD to enable branch history table */ 597 clear_c0_brcm_reset(BIT(16)); 598 599 /* Flush and enable RAC */ 600 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); 601 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); 602 __raw_readl(cbr + BMIPS_RAC_CONFIG); 603 604 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); 605 __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG); 606 __raw_readl(cbr + BMIPS_RAC_CONFIG); 607 608 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); 609 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE); 610 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); 611 break; 612 613 case CPU_BMIPS4380: 614 /* CBG workaround for early BMIPS4380 CPUs */ 615 switch (read_c0_prid()) { 616 case 0x2a040: 617 case 0x2a042: 618 case 0x2a044: 619 case 0x2a060: 620 cfg = __raw_readl(cbr + BMIPS_L2_CONFIG); 621 __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG); 622 __raw_readl(cbr + BMIPS_L2_CONFIG); 623 } 624 625 /* clear BHTD to enable branch history table */ 626 clear_c0_brcm_config_0(BIT(21)); 627 628 /* XI/ROTR enable */ 629 set_c0_brcm_config_0(BIT(23)); 630 set_c0_brcm_cmt_ctrl(BIT(15)); 631 break; 632 633 case CPU_BMIPS5000: 634 /* enable RDHWR, BRDHWR */ 635 set_c0_brcm_config(BIT(17) | BIT(21)); 636 637 /* Disable JTB */ 638 __asm__ __volatile__( 639 " .set noreorder\n" 640 " li $8, 0x5a455048\n" 641 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */ 642 " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */ 643 " li $9, 0x00008000\n" 644 " or $8, $8, $9\n" 645 " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */ 646 " sync\n" 647 " li $8, 0x0\n" 648 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */ 649 " .set reorder\n" 650 : : : "$8", "$9"); 651 652 /* XI enable */ 653 set_c0_brcm_config(BIT(27)); 654 655 /* enable MIPS32R2 ROR instruction for XI TLB handlers */ 656 __asm__ __volatile__( 657 " li $8, 0x5a455048\n" 658 " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */ 659 " nop; nop; nop\n" 660 " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */ 661 " lui $9, 0x0100\n" 662 " or $8, $9\n" 663 " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */ 664 : : : "$8", "$9"); 665 break; 666 } 667 } 668