1df0ac8a4SKevin Cernekee /* 2df0ac8a4SKevin Cernekee * This file is subject to the terms and conditions of the GNU General Public 3df0ac8a4SKevin Cernekee * License. See the file "COPYING" in the main directory of this archive 4df0ac8a4SKevin Cernekee * for more details. 5df0ac8a4SKevin Cernekee * 6df0ac8a4SKevin Cernekee * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) 7df0ac8a4SKevin Cernekee * 8df0ac8a4SKevin Cernekee * SMP support for BMIPS 9df0ac8a4SKevin Cernekee */ 10df0ac8a4SKevin Cernekee 11df0ac8a4SKevin Cernekee #include <linux/init.h> 12df0ac8a4SKevin Cernekee #include <linux/sched.h> 13ef8bd77fSIngo Molnar #include <linux/sched/hotplug.h> 14df0ac8a4SKevin Cernekee #include <linux/mm.h> 15df0ac8a4SKevin Cernekee #include <linux/delay.h> 16df0ac8a4SKevin Cernekee #include <linux/smp.h> 17df0ac8a4SKevin Cernekee #include <linux/interrupt.h> 18df0ac8a4SKevin Cernekee #include <linux/spinlock.h> 19df0ac8a4SKevin Cernekee #include <linux/cpu.h> 20df0ac8a4SKevin Cernekee #include <linux/cpumask.h> 21df0ac8a4SKevin Cernekee #include <linux/reboot.h> 22df0ac8a4SKevin Cernekee #include <linux/io.h> 23df0ac8a4SKevin Cernekee #include <linux/compiler.h> 24df0ac8a4SKevin Cernekee #include <linux/linkage.h> 25df0ac8a4SKevin Cernekee #include <linux/bug.h> 26df0ac8a4SKevin Cernekee #include <linux/kernel.h> 27df0ac8a4SKevin Cernekee 28df0ac8a4SKevin Cernekee #include <asm/time.h> 29df0ac8a4SKevin Cernekee #include <asm/pgtable.h> 30df0ac8a4SKevin Cernekee #include <asm/processor.h> 31df0ac8a4SKevin Cernekee #include <asm/bootinfo.h> 32df0ac8a4SKevin Cernekee #include <asm/pmon.h> 33df0ac8a4SKevin Cernekee #include <asm/cacheflush.h> 34df0ac8a4SKevin Cernekee #include <asm/tlbflush.h> 35df0ac8a4SKevin Cernekee #include <asm/mipsregs.h> 36df0ac8a4SKevin Cernekee #include <asm/bmips.h> 37df0ac8a4SKevin Cernekee #include <asm/traps.h> 38df0ac8a4SKevin Cernekee #include <asm/barrier.h> 39fc455787SKevin Cernekee #include <asm/cpu-features.h> 40df0ac8a4SKevin Cernekee 41df0ac8a4SKevin Cernekee static int __maybe_unused max_cpus = 1; 42df0ac8a4SKevin Cernekee 43df0ac8a4SKevin Cernekee /* these may be configured by the platform code */ 44df0ac8a4SKevin Cernekee int bmips_smp_enabled = 1; 45df0ac8a4SKevin Cernekee int bmips_cpu_offset; 46df0ac8a4SKevin Cernekee cpumask_t bmips_booted_mask; 47d8010cebSKevin Cernekee unsigned long bmips_tp1_irqs = IE_IRQ1; 48df0ac8a4SKevin Cernekee 49fc455787SKevin Cernekee #define RESET_FROM_KSEG0 0x80080800 50fc455787SKevin Cernekee #define RESET_FROM_KSEG1 0xa0080800 51fc455787SKevin Cernekee 523677a283SKevin Cernekee static void bmips_set_reset_vec(int cpu, u32 val); 533677a283SKevin Cernekee 54df0ac8a4SKevin Cernekee #ifdef CONFIG_SMP 55df0ac8a4SKevin Cernekee 56df0ac8a4SKevin Cernekee /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */ 57df0ac8a4SKevin Cernekee unsigned long bmips_smp_boot_sp; 58df0ac8a4SKevin Cernekee unsigned long bmips_smp_boot_gp; 59df0ac8a4SKevin Cernekee 606465460cSJonas Gorski static void bmips43xx_send_ipi_single(int cpu, unsigned int action); 616465460cSJonas Gorski static void bmips5000_send_ipi_single(int cpu, unsigned int action); 626465460cSJonas Gorski static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id); 636465460cSJonas Gorski static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id); 64df0ac8a4SKevin Cernekee 65df0ac8a4SKevin Cernekee /* SW interrupts 0,1 are used for interprocessor signaling */ 66df0ac8a4SKevin Cernekee #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) 67df0ac8a4SKevin Cernekee #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1) 68df0ac8a4SKevin Cernekee 69df0ac8a4SKevin Cernekee #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) 70df0ac8a4SKevin Cernekee #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 71df0ac8a4SKevin Cernekee #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 72df0ac8a4SKevin Cernekee #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) 73df0ac8a4SKevin Cernekee 74df0ac8a4SKevin Cernekee static void __init bmips_smp_setup(void) 75df0ac8a4SKevin Cernekee { 764df715aaSFlorian Fainelli int i, cpu = 1, boot_cpu = 0; 77fcfa66deSFlorian Fainelli int cpu_hw_intr; 78fcfa66deSFlorian Fainelli 796465460cSJonas Gorski switch (current_cpu_type()) { 806465460cSJonas Gorski case CPU_BMIPS4350: 816465460cSJonas Gorski case CPU_BMIPS4380: 82df0ac8a4SKevin Cernekee /* arbitration priority */ 83df0ac8a4SKevin Cernekee clear_c0_brcm_cmt_ctrl(0x30); 84df0ac8a4SKevin Cernekee 85df0ac8a4SKevin Cernekee /* NBK and weak order flags */ 86df0ac8a4SKevin Cernekee set_c0_brcm_config_0(0x30000); 87df0ac8a4SKevin Cernekee 884df715aaSFlorian Fainelli /* Find out if we are running on TP0 or TP1 */ 894df715aaSFlorian Fainelli boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 904df715aaSFlorian Fainelli 91df0ac8a4SKevin Cernekee /* 926465460cSJonas Gorski * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other 936465460cSJonas Gorski * thread 94df0ac8a4SKevin Cernekee * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 95df0ac8a4SKevin Cernekee * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 96df0ac8a4SKevin Cernekee */ 97fcfa66deSFlorian Fainelli if (boot_cpu == 0) 98fcfa66deSFlorian Fainelli cpu_hw_intr = 0x02; 99fcfa66deSFlorian Fainelli else 100fcfa66deSFlorian Fainelli cpu_hw_intr = 0x1d; 101fcfa66deSFlorian Fainelli 1026465460cSJonas Gorski change_c0_brcm_cmt_intr(0xf8018000, 1036465460cSJonas Gorski (cpu_hw_intr << 27) | (0x03 << 15)); 104df0ac8a4SKevin Cernekee 105df0ac8a4SKevin Cernekee /* single core, 2 threads (2 pipelines) */ 106df0ac8a4SKevin Cernekee max_cpus = 2; 1076465460cSJonas Gorski 1086465460cSJonas Gorski break; 1096465460cSJonas Gorski case CPU_BMIPS5000: 110df0ac8a4SKevin Cernekee /* enable raceless SW interrupts */ 111df0ac8a4SKevin Cernekee set_c0_brcm_config(0x03 << 22); 112df0ac8a4SKevin Cernekee 113df0ac8a4SKevin Cernekee /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ 114df0ac8a4SKevin Cernekee change_c0_brcm_mode(0x1f << 27, 0x02 << 27); 115df0ac8a4SKevin Cernekee 116df0ac8a4SKevin Cernekee /* N cores, 2 threads per core */ 117df0ac8a4SKevin Cernekee max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; 118df0ac8a4SKevin Cernekee 119df0ac8a4SKevin Cernekee /* clear any pending SW interrupts */ 120df0ac8a4SKevin Cernekee for (i = 0; i < max_cpus; i++) { 121df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); 122df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); 123df0ac8a4SKevin Cernekee } 1246465460cSJonas Gorski 1256465460cSJonas Gorski break; 1266465460cSJonas Gorski default: 1276465460cSJonas Gorski max_cpus = 1; 1286465460cSJonas Gorski } 129df0ac8a4SKevin Cernekee 130df0ac8a4SKevin Cernekee if (!bmips_smp_enabled) 131df0ac8a4SKevin Cernekee max_cpus = 1; 132df0ac8a4SKevin Cernekee 133df0ac8a4SKevin Cernekee /* this can be overridden by the BSP */ 134df0ac8a4SKevin Cernekee if (!board_ebase_setup) 135df0ac8a4SKevin Cernekee board_ebase_setup = &bmips_ebase_setup; 136df0ac8a4SKevin Cernekee 1374df715aaSFlorian Fainelli __cpu_number_map[boot_cpu] = 0; 1384df715aaSFlorian Fainelli __cpu_logical_map[0] = boot_cpu; 1394df715aaSFlorian Fainelli 140df0ac8a4SKevin Cernekee for (i = 0; i < max_cpus; i++) { 1414df715aaSFlorian Fainelli if (i != boot_cpu) { 1424df715aaSFlorian Fainelli __cpu_number_map[i] = cpu; 1434df715aaSFlorian Fainelli __cpu_logical_map[cpu] = i; 1444df715aaSFlorian Fainelli cpu++; 1454df715aaSFlorian Fainelli } 146df0ac8a4SKevin Cernekee set_cpu_possible(i, 1); 147df0ac8a4SKevin Cernekee set_cpu_present(i, 1); 148df0ac8a4SKevin Cernekee } 149df0ac8a4SKevin Cernekee } 150df0ac8a4SKevin Cernekee 151df0ac8a4SKevin Cernekee /* 152df0ac8a4SKevin Cernekee * IPI IRQ setup - runs on CPU0 153df0ac8a4SKevin Cernekee */ 154df0ac8a4SKevin Cernekee static void bmips_prepare_cpus(unsigned int max_cpus) 155df0ac8a4SKevin Cernekee { 1566465460cSJonas Gorski irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id); 1576465460cSJonas Gorski 1586465460cSJonas Gorski switch (current_cpu_type()) { 1596465460cSJonas Gorski case CPU_BMIPS4350: 1606465460cSJonas Gorski case CPU_BMIPS4380: 1616465460cSJonas Gorski bmips_ipi_interrupt = bmips43xx_ipi_interrupt; 1626465460cSJonas Gorski break; 1636465460cSJonas Gorski case CPU_BMIPS5000: 1646465460cSJonas Gorski bmips_ipi_interrupt = bmips5000_ipi_interrupt; 1656465460cSJonas Gorski break; 1666465460cSJonas Gorski default: 1676465460cSJonas Gorski return; 1686465460cSJonas Gorski } 1696465460cSJonas Gorski 170df0ac8a4SKevin Cernekee if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 171df0ac8a4SKevin Cernekee "smp_ipi0", NULL)) 172f7777dccSRalf Baechle panic("Can't request IPI0 interrupt"); 173df0ac8a4SKevin Cernekee if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 174df0ac8a4SKevin Cernekee "smp_ipi1", NULL)) 175f7777dccSRalf Baechle panic("Can't request IPI1 interrupt"); 176df0ac8a4SKevin Cernekee } 177df0ac8a4SKevin Cernekee 178df0ac8a4SKevin Cernekee /* 179df0ac8a4SKevin Cernekee * Tell the hardware to boot CPUx - runs on CPU0 180df0ac8a4SKevin Cernekee */ 181df0ac8a4SKevin Cernekee static void bmips_boot_secondary(int cpu, struct task_struct *idle) 182df0ac8a4SKevin Cernekee { 183df0ac8a4SKevin Cernekee bmips_smp_boot_sp = __KSTK_TOS(idle); 184df0ac8a4SKevin Cernekee bmips_smp_boot_gp = (unsigned long)task_thread_info(idle); 185df0ac8a4SKevin Cernekee mb(); 186df0ac8a4SKevin Cernekee 187df0ac8a4SKevin Cernekee /* 188df0ac8a4SKevin Cernekee * Initial boot sequence for secondary CPU: 189df0ac8a4SKevin Cernekee * bmips_reset_nmi_vec @ a000_0000 -> 190df0ac8a4SKevin Cernekee * bmips_smp_entry -> 191df0ac8a4SKevin Cernekee * plat_wired_tlb_setup (cached function call; optional) -> 192df0ac8a4SKevin Cernekee * start_secondary (cached jump) 193df0ac8a4SKevin Cernekee * 194df0ac8a4SKevin Cernekee * Warm restart sequence: 195df0ac8a4SKevin Cernekee * play_dead WAIT loop -> 196df0ac8a4SKevin Cernekee * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC -> 197df0ac8a4SKevin Cernekee * eret to play_dead -> 198df0ac8a4SKevin Cernekee * bmips_secondary_reentry -> 199df0ac8a4SKevin Cernekee * start_secondary 200df0ac8a4SKevin Cernekee */ 201df0ac8a4SKevin Cernekee 202df0ac8a4SKevin Cernekee pr_info("SMP: Booting CPU%d...\n", cpu); 203df0ac8a4SKevin Cernekee 2046465460cSJonas Gorski if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { 2053677a283SKevin Cernekee /* kseg1 might not exist if this CPU enabled XKS01 */ 2063677a283SKevin Cernekee bmips_set_reset_vec(cpu, RESET_FROM_KSEG0); 2073677a283SKevin Cernekee 2086465460cSJonas Gorski switch (current_cpu_type()) { 2096465460cSJonas Gorski case CPU_BMIPS4350: 2106465460cSJonas Gorski case CPU_BMIPS4380: 2116465460cSJonas Gorski bmips43xx_send_ipi_single(cpu, 0); 2126465460cSJonas Gorski break; 2136465460cSJonas Gorski case CPU_BMIPS5000: 2146465460cSJonas Gorski bmips5000_send_ipi_single(cpu, 0); 2156465460cSJonas Gorski break; 2166465460cSJonas Gorski } 2173677a283SKevin Cernekee } else { 2183677a283SKevin Cernekee bmips_set_reset_vec(cpu, RESET_FROM_KSEG1); 2193677a283SKevin Cernekee 2206465460cSJonas Gorski switch (current_cpu_type()) { 2216465460cSJonas Gorski case CPU_BMIPS4350: 2226465460cSJonas Gorski case CPU_BMIPS4380: 2234df715aaSFlorian Fainelli /* Reset slave TP1 if booting from TP0 */ 224976f39b1SFlorian Fainelli if (cpu_logical_map(cpu) == 1) 225df0ac8a4SKevin Cernekee set_c0_brcm_cmt_ctrl(0x01); 2266465460cSJonas Gorski break; 2276465460cSJonas Gorski case CPU_BMIPS5000: 228df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); 2296465460cSJonas Gorski break; 2306465460cSJonas Gorski } 231df0ac8a4SKevin Cernekee cpumask_set_cpu(cpu, &bmips_booted_mask); 232df0ac8a4SKevin Cernekee } 233df0ac8a4SKevin Cernekee } 234df0ac8a4SKevin Cernekee 235df0ac8a4SKevin Cernekee /* 236df0ac8a4SKevin Cernekee * Early setup - runs on secondary CPU after cache probe 237df0ac8a4SKevin Cernekee */ 238df0ac8a4SKevin Cernekee static void bmips_init_secondary(void) 239df0ac8a4SKevin Cernekee { 2406465460cSJonas Gorski switch (current_cpu_type()) { 2416465460cSJonas Gorski case CPU_BMIPS4350: 2426465460cSJonas Gorski case CPU_BMIPS4380: 243df0ac8a4SKevin Cernekee clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); 2446465460cSJonas Gorski break; 2456465460cSJonas Gorski case CPU_BMIPS5000: 246df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); 247f6cc0ee9SFlorian Fainelli current_cpu_data.core = (read_c0_brcm_config() >> 25) & 3; 2486465460cSJonas Gorski break; 2496465460cSJonas Gorski } 250df0ac8a4SKevin Cernekee } 251df0ac8a4SKevin Cernekee 252df0ac8a4SKevin Cernekee /* 253df0ac8a4SKevin Cernekee * Late setup - runs on secondary CPU before entering the idle loop 254df0ac8a4SKevin Cernekee */ 255df0ac8a4SKevin Cernekee static void bmips_smp_finish(void) 256df0ac8a4SKevin Cernekee { 257df0ac8a4SKevin Cernekee pr_info("SMP: CPU%d is running\n", smp_processor_id()); 258856ac3c6SYong Zhang 259856ac3c6SYong Zhang /* make sure there won't be a timer interrupt for a little while */ 260856ac3c6SYong Zhang write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 261856ac3c6SYong Zhang 262856ac3c6SYong Zhang irq_enable_hazard(); 263d8010cebSKevin Cernekee set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE); 264856ac3c6SYong Zhang irq_enable_hazard(); 265df0ac8a4SKevin Cernekee } 266df0ac8a4SKevin Cernekee 267df0ac8a4SKevin Cernekee /* 268df0ac8a4SKevin Cernekee * BMIPS5000 raceless IPIs 269df0ac8a4SKevin Cernekee * 270df0ac8a4SKevin Cernekee * Each CPU has two inbound SW IRQs which are independent of all other CPUs. 271df0ac8a4SKevin Cernekee * IPI0 is used for SMP_RESCHEDULE_YOURSELF 272df0ac8a4SKevin Cernekee * IPI1 is used for SMP_CALL_FUNCTION 273df0ac8a4SKevin Cernekee */ 274df0ac8a4SKevin Cernekee 2756465460cSJonas Gorski static void bmips5000_send_ipi_single(int cpu, unsigned int action) 276df0ac8a4SKevin Cernekee { 277df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); 278df0ac8a4SKevin Cernekee } 279df0ac8a4SKevin Cernekee 2806465460cSJonas Gorski static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) 281df0ac8a4SKevin Cernekee { 282df0ac8a4SKevin Cernekee int action = irq - IPI0_IRQ; 283df0ac8a4SKevin Cernekee 284df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action)); 285df0ac8a4SKevin Cernekee 286df0ac8a4SKevin Cernekee if (action == 0) 287df0ac8a4SKevin Cernekee scheduler_ipi(); 288df0ac8a4SKevin Cernekee else 2894ace6139SAlex Smith generic_smp_call_function_interrupt(); 290df0ac8a4SKevin Cernekee 291df0ac8a4SKevin Cernekee return IRQ_HANDLED; 292df0ac8a4SKevin Cernekee } 293df0ac8a4SKevin Cernekee 2946465460cSJonas Gorski static void bmips5000_send_ipi_mask(const struct cpumask *mask, 2956465460cSJonas Gorski unsigned int action) 2966465460cSJonas Gorski { 2976465460cSJonas Gorski unsigned int i; 2986465460cSJonas Gorski 2996465460cSJonas Gorski for_each_cpu(i, mask) 3006465460cSJonas Gorski bmips5000_send_ipi_single(i, action); 3016465460cSJonas Gorski } 302df0ac8a4SKevin Cernekee 303df0ac8a4SKevin Cernekee /* 304df0ac8a4SKevin Cernekee * BMIPS43xx racey IPIs 305df0ac8a4SKevin Cernekee * 306df0ac8a4SKevin Cernekee * We use one inbound SW IRQ for each CPU. 307df0ac8a4SKevin Cernekee * 308df0ac8a4SKevin Cernekee * A spinlock must be held in order to keep CPUx from accidentally clearing 309df0ac8a4SKevin Cernekee * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The 310df0ac8a4SKevin Cernekee * same spinlock is used to protect the action masks. 311df0ac8a4SKevin Cernekee */ 312df0ac8a4SKevin Cernekee 313df0ac8a4SKevin Cernekee static DEFINE_SPINLOCK(ipi_lock); 314df0ac8a4SKevin Cernekee static DEFINE_PER_CPU(int, ipi_action_mask); 315df0ac8a4SKevin Cernekee 3166465460cSJonas Gorski static void bmips43xx_send_ipi_single(int cpu, unsigned int action) 317df0ac8a4SKevin Cernekee { 318df0ac8a4SKevin Cernekee unsigned long flags; 319df0ac8a4SKevin Cernekee 320df0ac8a4SKevin Cernekee spin_lock_irqsave(&ipi_lock, flags); 321df0ac8a4SKevin Cernekee set_c0_cause(cpu ? C_SW1 : C_SW0); 322df0ac8a4SKevin Cernekee per_cpu(ipi_action_mask, cpu) |= action; 323df0ac8a4SKevin Cernekee irq_enable_hazard(); 324df0ac8a4SKevin Cernekee spin_unlock_irqrestore(&ipi_lock, flags); 325df0ac8a4SKevin Cernekee } 326df0ac8a4SKevin Cernekee 3276465460cSJonas Gorski static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) 328df0ac8a4SKevin Cernekee { 329df0ac8a4SKevin Cernekee unsigned long flags; 330df0ac8a4SKevin Cernekee int action, cpu = irq - IPI0_IRQ; 331df0ac8a4SKevin Cernekee 332df0ac8a4SKevin Cernekee spin_lock_irqsave(&ipi_lock, flags); 33335898716SChristoph Lameter action = __this_cpu_read(ipi_action_mask); 334df0ac8a4SKevin Cernekee per_cpu(ipi_action_mask, cpu) = 0; 335df0ac8a4SKevin Cernekee clear_c0_cause(cpu ? C_SW1 : C_SW0); 336df0ac8a4SKevin Cernekee spin_unlock_irqrestore(&ipi_lock, flags); 337df0ac8a4SKevin Cernekee 338df0ac8a4SKevin Cernekee if (action & SMP_RESCHEDULE_YOURSELF) 339df0ac8a4SKevin Cernekee scheduler_ipi(); 340df0ac8a4SKevin Cernekee if (action & SMP_CALL_FUNCTION) 3414ace6139SAlex Smith generic_smp_call_function_interrupt(); 342df0ac8a4SKevin Cernekee 343df0ac8a4SKevin Cernekee return IRQ_HANDLED; 344df0ac8a4SKevin Cernekee } 345df0ac8a4SKevin Cernekee 3466465460cSJonas Gorski static void bmips43xx_send_ipi_mask(const struct cpumask *mask, 347df0ac8a4SKevin Cernekee unsigned int action) 348df0ac8a4SKevin Cernekee { 349df0ac8a4SKevin Cernekee unsigned int i; 350df0ac8a4SKevin Cernekee 351df0ac8a4SKevin Cernekee for_each_cpu(i, mask) 3526465460cSJonas Gorski bmips43xx_send_ipi_single(i, action); 353df0ac8a4SKevin Cernekee } 354df0ac8a4SKevin Cernekee 355df0ac8a4SKevin Cernekee #ifdef CONFIG_HOTPLUG_CPU 356df0ac8a4SKevin Cernekee 357df0ac8a4SKevin Cernekee static int bmips_cpu_disable(void) 358df0ac8a4SKevin Cernekee { 359df0ac8a4SKevin Cernekee unsigned int cpu = smp_processor_id(); 360df0ac8a4SKevin Cernekee 361df0ac8a4SKevin Cernekee if (cpu == 0) 362df0ac8a4SKevin Cernekee return -EBUSY; 363df0ac8a4SKevin Cernekee 364df0ac8a4SKevin Cernekee pr_info("SMP: CPU%d is offline\n", cpu); 365df0ac8a4SKevin Cernekee 3660b5f9c00SRusty Russell set_cpu_online(cpu, false); 367826e99beSJames Hogan calculate_cpu_foreign_map(); 36851ad4aceSFlorian Fainelli irq_cpu_offline(); 369230b6ff5SJon Fraser clear_c0_status(IE_IRQ5); 370df0ac8a4SKevin Cernekee 371df0ac8a4SKevin Cernekee local_flush_tlb_all(); 372df0ac8a4SKevin Cernekee local_flush_icache_range(0, ~0); 373df0ac8a4SKevin Cernekee 374df0ac8a4SKevin Cernekee return 0; 375df0ac8a4SKevin Cernekee } 376df0ac8a4SKevin Cernekee 377df0ac8a4SKevin Cernekee static void bmips_cpu_die(unsigned int cpu) 378df0ac8a4SKevin Cernekee { 379df0ac8a4SKevin Cernekee } 380df0ac8a4SKevin Cernekee 381df0ac8a4SKevin Cernekee void __ref play_dead(void) 382df0ac8a4SKevin Cernekee { 383df0ac8a4SKevin Cernekee idle_task_exit(); 384df0ac8a4SKevin Cernekee 385df0ac8a4SKevin Cernekee /* flush data cache */ 386df0ac8a4SKevin Cernekee _dma_cache_wback_inv(0, ~0); 387df0ac8a4SKevin Cernekee 388df0ac8a4SKevin Cernekee /* 389df0ac8a4SKevin Cernekee * Wakeup is on SW0 or SW1; disable everything else 390df0ac8a4SKevin Cernekee * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux 391df0ac8a4SKevin Cernekee * IRQ handlers; this clears ST0_IE and returns immediately. 392df0ac8a4SKevin Cernekee */ 393df0ac8a4SKevin Cernekee clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1); 394d8010cebSKevin Cernekee change_c0_status( 395d8010cebSKevin Cernekee IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV, 396df0ac8a4SKevin Cernekee IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV); 397df0ac8a4SKevin Cernekee irq_disable_hazard(); 398df0ac8a4SKevin Cernekee 399df0ac8a4SKevin Cernekee /* 400df0ac8a4SKevin Cernekee * wait for SW interrupt from bmips_boot_secondary(), then jump 401df0ac8a4SKevin Cernekee * back to start_secondary() 402df0ac8a4SKevin Cernekee */ 403df0ac8a4SKevin Cernekee __asm__ __volatile__( 404df0ac8a4SKevin Cernekee " wait\n" 405df0ac8a4SKevin Cernekee " j bmips_secondary_reentry\n" 406df0ac8a4SKevin Cernekee : : : "memory"); 407df0ac8a4SKevin Cernekee } 408df0ac8a4SKevin Cernekee 409df0ac8a4SKevin Cernekee #endif /* CONFIG_HOTPLUG_CPU */ 410df0ac8a4SKevin Cernekee 4116465460cSJonas Gorski struct plat_smp_ops bmips43xx_smp_ops = { 412df0ac8a4SKevin Cernekee .smp_setup = bmips_smp_setup, 413df0ac8a4SKevin Cernekee .prepare_cpus = bmips_prepare_cpus, 414df0ac8a4SKevin Cernekee .boot_secondary = bmips_boot_secondary, 415df0ac8a4SKevin Cernekee .smp_finish = bmips_smp_finish, 416df0ac8a4SKevin Cernekee .init_secondary = bmips_init_secondary, 4176465460cSJonas Gorski .send_ipi_single = bmips43xx_send_ipi_single, 4186465460cSJonas Gorski .send_ipi_mask = bmips43xx_send_ipi_mask, 4196465460cSJonas Gorski #ifdef CONFIG_HOTPLUG_CPU 4206465460cSJonas Gorski .cpu_disable = bmips_cpu_disable, 4216465460cSJonas Gorski .cpu_die = bmips_cpu_die, 4226465460cSJonas Gorski #endif 4236465460cSJonas Gorski }; 4246465460cSJonas Gorski 4256465460cSJonas Gorski struct plat_smp_ops bmips5000_smp_ops = { 4266465460cSJonas Gorski .smp_setup = bmips_smp_setup, 4276465460cSJonas Gorski .prepare_cpus = bmips_prepare_cpus, 4286465460cSJonas Gorski .boot_secondary = bmips_boot_secondary, 4296465460cSJonas Gorski .smp_finish = bmips_smp_finish, 4306465460cSJonas Gorski .init_secondary = bmips_init_secondary, 4316465460cSJonas Gorski .send_ipi_single = bmips5000_send_ipi_single, 4326465460cSJonas Gorski .send_ipi_mask = bmips5000_send_ipi_mask, 433df0ac8a4SKevin Cernekee #ifdef CONFIG_HOTPLUG_CPU 434df0ac8a4SKevin Cernekee .cpu_disable = bmips_cpu_disable, 435df0ac8a4SKevin Cernekee .cpu_die = bmips_cpu_die, 436df0ac8a4SKevin Cernekee #endif 437df0ac8a4SKevin Cernekee }; 438df0ac8a4SKevin Cernekee 439df0ac8a4SKevin Cernekee #endif /* CONFIG_SMP */ 440df0ac8a4SKevin Cernekee 441df0ac8a4SKevin Cernekee /*********************************************************************** 442df0ac8a4SKevin Cernekee * BMIPS vector relocation 443df0ac8a4SKevin Cernekee * This is primarily used for SMP boot, but it is applicable to some 444df0ac8a4SKevin Cernekee * UP BMIPS systems as well. 445df0ac8a4SKevin Cernekee ***********************************************************************/ 446df0ac8a4SKevin Cernekee 447078a55fcSPaul Gortmaker static void bmips_wr_vec(unsigned long dst, char *start, char *end) 448df0ac8a4SKevin Cernekee { 449df0ac8a4SKevin Cernekee memcpy((void *)dst, start, end - start); 45057b41758SPetri Gynther dma_cache_wback(dst, end - start); 451df0ac8a4SKevin Cernekee local_flush_icache_range(dst, dst + (end - start)); 452df0ac8a4SKevin Cernekee instruction_hazard(); 453df0ac8a4SKevin Cernekee } 454df0ac8a4SKevin Cernekee 455078a55fcSPaul Gortmaker static inline void bmips_nmi_handler_setup(void) 456df0ac8a4SKevin Cernekee { 457df0ac8a4SKevin Cernekee bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec, 458df0ac8a4SKevin Cernekee &bmips_reset_nmi_vec_end); 459df0ac8a4SKevin Cernekee bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec, 460df0ac8a4SKevin Cernekee &bmips_smp_int_vec_end); 461df0ac8a4SKevin Cernekee } 462df0ac8a4SKevin Cernekee 463fc455787SKevin Cernekee struct reset_vec_info { 464fc455787SKevin Cernekee int cpu; 465fc455787SKevin Cernekee u32 val; 466fc455787SKevin Cernekee }; 467fc455787SKevin Cernekee 468fc455787SKevin Cernekee static void bmips_set_reset_vec_remote(void *vinfo) 469fc455787SKevin Cernekee { 470fc455787SKevin Cernekee struct reset_vec_info *info = vinfo; 471fc455787SKevin Cernekee int shift = info->cpu & 0x01 ? 16 : 0; 472fc455787SKevin Cernekee u32 mask = ~(0xffff << shift), val = info->val >> 16; 473fc455787SKevin Cernekee 474fc455787SKevin Cernekee preempt_disable(); 475fc455787SKevin Cernekee if (smp_processor_id() > 0) { 476fc455787SKevin Cernekee smp_call_function_single(0, &bmips_set_reset_vec_remote, 477fc455787SKevin Cernekee info, 1); 478fc455787SKevin Cernekee } else { 479fc455787SKevin Cernekee if (info->cpu & 0x02) { 480fc455787SKevin Cernekee /* BMIPS5200 "should" use mask/shift, but it's buggy */ 481fc455787SKevin Cernekee bmips_write_zscm_reg(0xa0, (val << 16) | val); 482fc455787SKevin Cernekee bmips_read_zscm_reg(0xa0); 483fc455787SKevin Cernekee } else { 484fc455787SKevin Cernekee write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) | 485fc455787SKevin Cernekee (val << shift)); 486fc455787SKevin Cernekee } 487fc455787SKevin Cernekee } 488fc455787SKevin Cernekee preempt_enable(); 489fc455787SKevin Cernekee } 490fc455787SKevin Cernekee 491fc455787SKevin Cernekee static void bmips_set_reset_vec(int cpu, u32 val) 492fc455787SKevin Cernekee { 493fc455787SKevin Cernekee struct reset_vec_info info; 494fc455787SKevin Cernekee 495fc455787SKevin Cernekee if (current_cpu_type() == CPU_BMIPS5000) { 496fc455787SKevin Cernekee /* this needs to run from CPU0 (which is always online) */ 497fc455787SKevin Cernekee info.cpu = cpu; 498fc455787SKevin Cernekee info.val = val; 499fc455787SKevin Cernekee bmips_set_reset_vec_remote(&info); 500fc455787SKevin Cernekee } else { 501fc455787SKevin Cernekee void __iomem *cbr = BMIPS_GET_CBR(); 502fc455787SKevin Cernekee 503fc455787SKevin Cernekee if (cpu == 0) 504fc455787SKevin Cernekee __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); 505fc455787SKevin Cernekee else { 506fc455787SKevin Cernekee if (current_cpu_type() != CPU_BMIPS4380) 507fc455787SKevin Cernekee return; 508fc455787SKevin Cernekee __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); 509fc455787SKevin Cernekee } 510fc455787SKevin Cernekee } 511fc455787SKevin Cernekee __sync(); 512fc455787SKevin Cernekee back_to_back_c0_hazard(); 513fc455787SKevin Cernekee } 514fc455787SKevin Cernekee 515078a55fcSPaul Gortmaker void bmips_ebase_setup(void) 516df0ac8a4SKevin Cernekee { 517df0ac8a4SKevin Cernekee unsigned long new_ebase = ebase; 518df0ac8a4SKevin Cernekee 519df0ac8a4SKevin Cernekee BUG_ON(ebase != CKSEG0); 520df0ac8a4SKevin Cernekee 5216465460cSJonas Gorski switch (current_cpu_type()) { 5226465460cSJonas Gorski case CPU_BMIPS4350: 523df0ac8a4SKevin Cernekee /* 524df0ac8a4SKevin Cernekee * BMIPS4350 cannot relocate the normal vectors, but it 525df0ac8a4SKevin Cernekee * can relocate the BEV=1 vectors. So CPU1 starts up at 526df0ac8a4SKevin Cernekee * the relocated BEV=1, IV=0 general exception vector @ 527df0ac8a4SKevin Cernekee * 0xa000_0380. 528df0ac8a4SKevin Cernekee * 529df0ac8a4SKevin Cernekee * set_uncached_handler() is used here because: 530df0ac8a4SKevin Cernekee * - CPU1 will run this from uncached space 531df0ac8a4SKevin Cernekee * - None of the cacheflush functions are set up yet 532df0ac8a4SKevin Cernekee */ 533df0ac8a4SKevin Cernekee set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, 534df0ac8a4SKevin Cernekee &bmips_smp_int_vec, 0x80); 535df0ac8a4SKevin Cernekee __sync(); 536df0ac8a4SKevin Cernekee return; 537fa010672SJon Fraser case CPU_BMIPS3300: 5386465460cSJonas Gorski case CPU_BMIPS4380: 539df0ac8a4SKevin Cernekee /* 540df0ac8a4SKevin Cernekee * 0x8000_0000: reset/NMI (initially in kseg1) 541df0ac8a4SKevin Cernekee * 0x8000_0400: normal vectors 542df0ac8a4SKevin Cernekee */ 543df0ac8a4SKevin Cernekee new_ebase = 0x80000400; 544fc455787SKevin Cernekee bmips_set_reset_vec(0, RESET_FROM_KSEG0); 5456465460cSJonas Gorski break; 5466465460cSJonas Gorski case CPU_BMIPS5000: 547df0ac8a4SKevin Cernekee /* 548df0ac8a4SKevin Cernekee * 0x8000_0000: reset/NMI (initially in kseg1) 549df0ac8a4SKevin Cernekee * 0x8000_1000: normal vectors 550df0ac8a4SKevin Cernekee */ 551df0ac8a4SKevin Cernekee new_ebase = 0x80001000; 552fc455787SKevin Cernekee bmips_set_reset_vec(0, RESET_FROM_KSEG0); 553df0ac8a4SKevin Cernekee write_c0_ebase(new_ebase); 5546465460cSJonas Gorski break; 5556465460cSJonas Gorski default: 556df0ac8a4SKevin Cernekee return; 5576465460cSJonas Gorski } 5586465460cSJonas Gorski 559df0ac8a4SKevin Cernekee board_nmi_handler_setup = &bmips_nmi_handler_setup; 560df0ac8a4SKevin Cernekee ebase = new_ebase; 561df0ac8a4SKevin Cernekee } 562df0ac8a4SKevin Cernekee 563df0ac8a4SKevin Cernekee asmlinkage void __weak plat_wired_tlb_setup(void) 564df0ac8a4SKevin Cernekee { 565df0ac8a4SKevin Cernekee /* 566df0ac8a4SKevin Cernekee * Called when starting/restarting a secondary CPU. 567df0ac8a4SKevin Cernekee * Kernel stacks and other important data might only be accessible 568df0ac8a4SKevin Cernekee * once the wired entries are present. 569df0ac8a4SKevin Cernekee */ 570df0ac8a4SKevin Cernekee } 571738a3f79SFlorian Fainelli 572738a3f79SFlorian Fainelli void __init bmips_cpu_setup(void) 573738a3f79SFlorian Fainelli { 574738a3f79SFlorian Fainelli void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); 575738a3f79SFlorian Fainelli u32 __maybe_unused cfg; 576738a3f79SFlorian Fainelli 577738a3f79SFlorian Fainelli switch (current_cpu_type()) { 578738a3f79SFlorian Fainelli case CPU_BMIPS3300: 579738a3f79SFlorian Fainelli /* Set BIU to async mode */ 580738a3f79SFlorian Fainelli set_c0_brcm_bus_pll(BIT(22)); 581738a3f79SFlorian Fainelli __sync(); 582738a3f79SFlorian Fainelli 583738a3f79SFlorian Fainelli /* put the BIU back in sync mode */ 584738a3f79SFlorian Fainelli clear_c0_brcm_bus_pll(BIT(22)); 585738a3f79SFlorian Fainelli 586738a3f79SFlorian Fainelli /* clear BHTD to enable branch history table */ 587738a3f79SFlorian Fainelli clear_c0_brcm_reset(BIT(16)); 588738a3f79SFlorian Fainelli 589738a3f79SFlorian Fainelli /* Flush and enable RAC */ 590738a3f79SFlorian Fainelli cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); 591738a3f79SFlorian Fainelli __raw_writel(cfg | 0x100, BMIPS_RAC_CONFIG); 592738a3f79SFlorian Fainelli __raw_readl(cbr + BMIPS_RAC_CONFIG); 593738a3f79SFlorian Fainelli 594738a3f79SFlorian Fainelli cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); 595738a3f79SFlorian Fainelli __raw_writel(cfg | 0xf, BMIPS_RAC_CONFIG); 596738a3f79SFlorian Fainelli __raw_readl(cbr + BMIPS_RAC_CONFIG); 597738a3f79SFlorian Fainelli 598738a3f79SFlorian Fainelli cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); 599738a3f79SFlorian Fainelli __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE); 600738a3f79SFlorian Fainelli __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); 601738a3f79SFlorian Fainelli break; 602738a3f79SFlorian Fainelli 603738a3f79SFlorian Fainelli case CPU_BMIPS4380: 604738a3f79SFlorian Fainelli /* CBG workaround for early BMIPS4380 CPUs */ 605738a3f79SFlorian Fainelli switch (read_c0_prid()) { 606738a3f79SFlorian Fainelli case 0x2a040: 607738a3f79SFlorian Fainelli case 0x2a042: 608738a3f79SFlorian Fainelli case 0x2a044: 609738a3f79SFlorian Fainelli case 0x2a060: 610738a3f79SFlorian Fainelli cfg = __raw_readl(cbr + BMIPS_L2_CONFIG); 611738a3f79SFlorian Fainelli __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG); 612738a3f79SFlorian Fainelli __raw_readl(cbr + BMIPS_L2_CONFIG); 613738a3f79SFlorian Fainelli } 614738a3f79SFlorian Fainelli 615738a3f79SFlorian Fainelli /* clear BHTD to enable branch history table */ 616738a3f79SFlorian Fainelli clear_c0_brcm_config_0(BIT(21)); 617738a3f79SFlorian Fainelli 618738a3f79SFlorian Fainelli /* XI/ROTR enable */ 619738a3f79SFlorian Fainelli set_c0_brcm_config_0(BIT(23)); 620738a3f79SFlorian Fainelli set_c0_brcm_cmt_ctrl(BIT(15)); 621738a3f79SFlorian Fainelli break; 622738a3f79SFlorian Fainelli 623738a3f79SFlorian Fainelli case CPU_BMIPS5000: 624738a3f79SFlorian Fainelli /* enable RDHWR, BRDHWR */ 625738a3f79SFlorian Fainelli set_c0_brcm_config(BIT(17) | BIT(21)); 626738a3f79SFlorian Fainelli 627738a3f79SFlorian Fainelli /* Disable JTB */ 628738a3f79SFlorian Fainelli __asm__ __volatile__( 629738a3f79SFlorian Fainelli " .set noreorder\n" 630738a3f79SFlorian Fainelli " li $8, 0x5a455048\n" 631738a3f79SFlorian Fainelli " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */ 632738a3f79SFlorian Fainelli " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */ 633738a3f79SFlorian Fainelli " li $9, 0x00008000\n" 634738a3f79SFlorian Fainelli " or $8, $8, $9\n" 635738a3f79SFlorian Fainelli " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */ 636738a3f79SFlorian Fainelli " sync\n" 637738a3f79SFlorian Fainelli " li $8, 0x0\n" 638738a3f79SFlorian Fainelli " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */ 639738a3f79SFlorian Fainelli " .set reorder\n" 640738a3f79SFlorian Fainelli : : : "$8", "$9"); 641738a3f79SFlorian Fainelli 642738a3f79SFlorian Fainelli /* XI enable */ 643738a3f79SFlorian Fainelli set_c0_brcm_config(BIT(27)); 644738a3f79SFlorian Fainelli 645738a3f79SFlorian Fainelli /* enable MIPS32R2 ROR instruction for XI TLB handlers */ 646738a3f79SFlorian Fainelli __asm__ __volatile__( 647738a3f79SFlorian Fainelli " li $8, 0x5a455048\n" 648738a3f79SFlorian Fainelli " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */ 649738a3f79SFlorian Fainelli " nop; nop; nop\n" 650738a3f79SFlorian Fainelli " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */ 651738a3f79SFlorian Fainelli " lui $9, 0x0100\n" 652738a3f79SFlorian Fainelli " or $8, $9\n" 653738a3f79SFlorian Fainelli " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */ 654738a3f79SFlorian Fainelli : : : "$8", "$9"); 655738a3f79SFlorian Fainelli break; 656738a3f79SFlorian Fainelli } 657738a3f79SFlorian Fainelli } 658