1df0ac8a4SKevin Cernekee /* 2df0ac8a4SKevin Cernekee * This file is subject to the terms and conditions of the GNU General Public 3df0ac8a4SKevin Cernekee * License. See the file "COPYING" in the main directory of this archive 4df0ac8a4SKevin Cernekee * for more details. 5df0ac8a4SKevin Cernekee * 6df0ac8a4SKevin Cernekee * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) 7df0ac8a4SKevin Cernekee * 8df0ac8a4SKevin Cernekee * SMP support for BMIPS 9df0ac8a4SKevin Cernekee */ 10df0ac8a4SKevin Cernekee 11df0ac8a4SKevin Cernekee #include <linux/init.h> 12df0ac8a4SKevin Cernekee #include <linux/sched.h> 13df0ac8a4SKevin Cernekee #include <linux/mm.h> 14df0ac8a4SKevin Cernekee #include <linux/delay.h> 15df0ac8a4SKevin Cernekee #include <linux/smp.h> 16df0ac8a4SKevin Cernekee #include <linux/interrupt.h> 17df0ac8a4SKevin Cernekee #include <linux/spinlock.h> 18df0ac8a4SKevin Cernekee #include <linux/cpu.h> 19df0ac8a4SKevin Cernekee #include <linux/cpumask.h> 20df0ac8a4SKevin Cernekee #include <linux/reboot.h> 21df0ac8a4SKevin Cernekee #include <linux/io.h> 22df0ac8a4SKevin Cernekee #include <linux/compiler.h> 23df0ac8a4SKevin Cernekee #include <linux/linkage.h> 24df0ac8a4SKevin Cernekee #include <linux/bug.h> 25df0ac8a4SKevin Cernekee #include <linux/kernel.h> 26df0ac8a4SKevin Cernekee 27df0ac8a4SKevin Cernekee #include <asm/time.h> 28df0ac8a4SKevin Cernekee #include <asm/pgtable.h> 29df0ac8a4SKevin Cernekee #include <asm/processor.h> 30df0ac8a4SKevin Cernekee #include <asm/bootinfo.h> 31df0ac8a4SKevin Cernekee #include <asm/pmon.h> 32df0ac8a4SKevin Cernekee #include <asm/cacheflush.h> 33df0ac8a4SKevin Cernekee #include <asm/tlbflush.h> 34df0ac8a4SKevin Cernekee #include <asm/mipsregs.h> 35df0ac8a4SKevin Cernekee #include <asm/bmips.h> 36df0ac8a4SKevin Cernekee #include <asm/traps.h> 37df0ac8a4SKevin Cernekee #include <asm/barrier.h> 38fc455787SKevin Cernekee #include <asm/cpu-features.h> 39df0ac8a4SKevin Cernekee 40df0ac8a4SKevin Cernekee static int __maybe_unused max_cpus = 1; 41df0ac8a4SKevin Cernekee 42df0ac8a4SKevin Cernekee /* these may be configured by the platform code */ 43df0ac8a4SKevin Cernekee int bmips_smp_enabled = 1; 44df0ac8a4SKevin Cernekee int bmips_cpu_offset; 45df0ac8a4SKevin Cernekee cpumask_t bmips_booted_mask; 46d8010cebSKevin Cernekee unsigned long bmips_tp1_irqs = IE_IRQ1; 47df0ac8a4SKevin Cernekee 48fc455787SKevin Cernekee #define RESET_FROM_KSEG0 0x80080800 49fc455787SKevin Cernekee #define RESET_FROM_KSEG1 0xa0080800 50fc455787SKevin Cernekee 513677a283SKevin Cernekee static void bmips_set_reset_vec(int cpu, u32 val); 523677a283SKevin Cernekee 53df0ac8a4SKevin Cernekee #ifdef CONFIG_SMP 54df0ac8a4SKevin Cernekee 55df0ac8a4SKevin Cernekee /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */ 56df0ac8a4SKevin Cernekee unsigned long bmips_smp_boot_sp; 57df0ac8a4SKevin Cernekee unsigned long bmips_smp_boot_gp; 58df0ac8a4SKevin Cernekee 596465460cSJonas Gorski static void bmips43xx_send_ipi_single(int cpu, unsigned int action); 606465460cSJonas Gorski static void bmips5000_send_ipi_single(int cpu, unsigned int action); 616465460cSJonas Gorski static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id); 626465460cSJonas Gorski static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id); 63df0ac8a4SKevin Cernekee 64df0ac8a4SKevin Cernekee /* SW interrupts 0,1 are used for interprocessor signaling */ 65df0ac8a4SKevin Cernekee #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) 66df0ac8a4SKevin Cernekee #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1) 67df0ac8a4SKevin Cernekee 68df0ac8a4SKevin Cernekee #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) 69df0ac8a4SKevin Cernekee #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 70df0ac8a4SKevin Cernekee #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 71df0ac8a4SKevin Cernekee #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) 72df0ac8a4SKevin Cernekee 73df0ac8a4SKevin Cernekee static void __init bmips_smp_setup(void) 74df0ac8a4SKevin Cernekee { 754df715aaSFlorian Fainelli int i, cpu = 1, boot_cpu = 0; 76fcfa66deSFlorian Fainelli int cpu_hw_intr; 77fcfa66deSFlorian Fainelli 786465460cSJonas Gorski switch (current_cpu_type()) { 796465460cSJonas Gorski case CPU_BMIPS4350: 806465460cSJonas Gorski case CPU_BMIPS4380: 81df0ac8a4SKevin Cernekee /* arbitration priority */ 82df0ac8a4SKevin Cernekee clear_c0_brcm_cmt_ctrl(0x30); 83df0ac8a4SKevin Cernekee 84df0ac8a4SKevin Cernekee /* NBK and weak order flags */ 85df0ac8a4SKevin Cernekee set_c0_brcm_config_0(0x30000); 86df0ac8a4SKevin Cernekee 874df715aaSFlorian Fainelli /* Find out if we are running on TP0 or TP1 */ 884df715aaSFlorian Fainelli boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 894df715aaSFlorian Fainelli 90df0ac8a4SKevin Cernekee /* 916465460cSJonas Gorski * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other 926465460cSJonas Gorski * thread 93df0ac8a4SKevin Cernekee * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 94df0ac8a4SKevin Cernekee * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 95df0ac8a4SKevin Cernekee */ 96fcfa66deSFlorian Fainelli if (boot_cpu == 0) 97fcfa66deSFlorian Fainelli cpu_hw_intr = 0x02; 98fcfa66deSFlorian Fainelli else 99fcfa66deSFlorian Fainelli cpu_hw_intr = 0x1d; 100fcfa66deSFlorian Fainelli 1016465460cSJonas Gorski change_c0_brcm_cmt_intr(0xf8018000, 1026465460cSJonas Gorski (cpu_hw_intr << 27) | (0x03 << 15)); 103df0ac8a4SKevin Cernekee 104df0ac8a4SKevin Cernekee /* single core, 2 threads (2 pipelines) */ 105df0ac8a4SKevin Cernekee max_cpus = 2; 1066465460cSJonas Gorski 1076465460cSJonas Gorski break; 1086465460cSJonas Gorski case CPU_BMIPS5000: 109df0ac8a4SKevin Cernekee /* enable raceless SW interrupts */ 110df0ac8a4SKevin Cernekee set_c0_brcm_config(0x03 << 22); 111df0ac8a4SKevin Cernekee 112df0ac8a4SKevin Cernekee /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ 113df0ac8a4SKevin Cernekee change_c0_brcm_mode(0x1f << 27, 0x02 << 27); 114df0ac8a4SKevin Cernekee 115df0ac8a4SKevin Cernekee /* N cores, 2 threads per core */ 116df0ac8a4SKevin Cernekee max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; 117df0ac8a4SKevin Cernekee 118df0ac8a4SKevin Cernekee /* clear any pending SW interrupts */ 119df0ac8a4SKevin Cernekee for (i = 0; i < max_cpus; i++) { 120df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); 121df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); 122df0ac8a4SKevin Cernekee } 1236465460cSJonas Gorski 1246465460cSJonas Gorski break; 1256465460cSJonas Gorski default: 1266465460cSJonas Gorski max_cpus = 1; 1276465460cSJonas Gorski } 128df0ac8a4SKevin Cernekee 129df0ac8a4SKevin Cernekee if (!bmips_smp_enabled) 130df0ac8a4SKevin Cernekee max_cpus = 1; 131df0ac8a4SKevin Cernekee 132df0ac8a4SKevin Cernekee /* this can be overridden by the BSP */ 133df0ac8a4SKevin Cernekee if (!board_ebase_setup) 134df0ac8a4SKevin Cernekee board_ebase_setup = &bmips_ebase_setup; 135df0ac8a4SKevin Cernekee 1364df715aaSFlorian Fainelli __cpu_number_map[boot_cpu] = 0; 1374df715aaSFlorian Fainelli __cpu_logical_map[0] = boot_cpu; 1384df715aaSFlorian Fainelli 139df0ac8a4SKevin Cernekee for (i = 0; i < max_cpus; i++) { 1404df715aaSFlorian Fainelli if (i != boot_cpu) { 1414df715aaSFlorian Fainelli __cpu_number_map[i] = cpu; 1424df715aaSFlorian Fainelli __cpu_logical_map[cpu] = i; 1434df715aaSFlorian Fainelli cpu++; 1444df715aaSFlorian Fainelli } 145df0ac8a4SKevin Cernekee set_cpu_possible(i, 1); 146df0ac8a4SKevin Cernekee set_cpu_present(i, 1); 147df0ac8a4SKevin Cernekee } 148df0ac8a4SKevin Cernekee } 149df0ac8a4SKevin Cernekee 150df0ac8a4SKevin Cernekee /* 151df0ac8a4SKevin Cernekee * IPI IRQ setup - runs on CPU0 152df0ac8a4SKevin Cernekee */ 153df0ac8a4SKevin Cernekee static void bmips_prepare_cpus(unsigned int max_cpus) 154df0ac8a4SKevin Cernekee { 1556465460cSJonas Gorski irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id); 1566465460cSJonas Gorski 1576465460cSJonas Gorski switch (current_cpu_type()) { 1586465460cSJonas Gorski case CPU_BMIPS4350: 1596465460cSJonas Gorski case CPU_BMIPS4380: 1606465460cSJonas Gorski bmips_ipi_interrupt = bmips43xx_ipi_interrupt; 1616465460cSJonas Gorski break; 1626465460cSJonas Gorski case CPU_BMIPS5000: 1636465460cSJonas Gorski bmips_ipi_interrupt = bmips5000_ipi_interrupt; 1646465460cSJonas Gorski break; 1656465460cSJonas Gorski default: 1666465460cSJonas Gorski return; 1676465460cSJonas Gorski } 1686465460cSJonas Gorski 169df0ac8a4SKevin Cernekee if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 170df0ac8a4SKevin Cernekee "smp_ipi0", NULL)) 171f7777dccSRalf Baechle panic("Can't request IPI0 interrupt"); 172df0ac8a4SKevin Cernekee if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 173df0ac8a4SKevin Cernekee "smp_ipi1", NULL)) 174f7777dccSRalf Baechle panic("Can't request IPI1 interrupt"); 175df0ac8a4SKevin Cernekee } 176df0ac8a4SKevin Cernekee 177df0ac8a4SKevin Cernekee /* 178df0ac8a4SKevin Cernekee * Tell the hardware to boot CPUx - runs on CPU0 179df0ac8a4SKevin Cernekee */ 180df0ac8a4SKevin Cernekee static void bmips_boot_secondary(int cpu, struct task_struct *idle) 181df0ac8a4SKevin Cernekee { 182df0ac8a4SKevin Cernekee bmips_smp_boot_sp = __KSTK_TOS(idle); 183df0ac8a4SKevin Cernekee bmips_smp_boot_gp = (unsigned long)task_thread_info(idle); 184df0ac8a4SKevin Cernekee mb(); 185df0ac8a4SKevin Cernekee 186df0ac8a4SKevin Cernekee /* 187df0ac8a4SKevin Cernekee * Initial boot sequence for secondary CPU: 188df0ac8a4SKevin Cernekee * bmips_reset_nmi_vec @ a000_0000 -> 189df0ac8a4SKevin Cernekee * bmips_smp_entry -> 190df0ac8a4SKevin Cernekee * plat_wired_tlb_setup (cached function call; optional) -> 191df0ac8a4SKevin Cernekee * start_secondary (cached jump) 192df0ac8a4SKevin Cernekee * 193df0ac8a4SKevin Cernekee * Warm restart sequence: 194df0ac8a4SKevin Cernekee * play_dead WAIT loop -> 195df0ac8a4SKevin Cernekee * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC -> 196df0ac8a4SKevin Cernekee * eret to play_dead -> 197df0ac8a4SKevin Cernekee * bmips_secondary_reentry -> 198df0ac8a4SKevin Cernekee * start_secondary 199df0ac8a4SKevin Cernekee */ 200df0ac8a4SKevin Cernekee 201df0ac8a4SKevin Cernekee pr_info("SMP: Booting CPU%d...\n", cpu); 202df0ac8a4SKevin Cernekee 2036465460cSJonas Gorski if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { 2043677a283SKevin Cernekee /* kseg1 might not exist if this CPU enabled XKS01 */ 2053677a283SKevin Cernekee bmips_set_reset_vec(cpu, RESET_FROM_KSEG0); 2063677a283SKevin Cernekee 2076465460cSJonas Gorski switch (current_cpu_type()) { 2086465460cSJonas Gorski case CPU_BMIPS4350: 2096465460cSJonas Gorski case CPU_BMIPS4380: 2106465460cSJonas Gorski bmips43xx_send_ipi_single(cpu, 0); 2116465460cSJonas Gorski break; 2126465460cSJonas Gorski case CPU_BMIPS5000: 2136465460cSJonas Gorski bmips5000_send_ipi_single(cpu, 0); 2146465460cSJonas Gorski break; 2156465460cSJonas Gorski } 2163677a283SKevin Cernekee } else { 2173677a283SKevin Cernekee bmips_set_reset_vec(cpu, RESET_FROM_KSEG1); 2183677a283SKevin Cernekee 2196465460cSJonas Gorski switch (current_cpu_type()) { 2206465460cSJonas Gorski case CPU_BMIPS4350: 2216465460cSJonas Gorski case CPU_BMIPS4380: 2224df715aaSFlorian Fainelli /* Reset slave TP1 if booting from TP0 */ 223976f39b1SFlorian Fainelli if (cpu_logical_map(cpu) == 1) 224df0ac8a4SKevin Cernekee set_c0_brcm_cmt_ctrl(0x01); 2256465460cSJonas Gorski break; 2266465460cSJonas Gorski case CPU_BMIPS5000: 227df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); 2286465460cSJonas Gorski break; 2296465460cSJonas Gorski } 230df0ac8a4SKevin Cernekee cpumask_set_cpu(cpu, &bmips_booted_mask); 231df0ac8a4SKevin Cernekee } 232df0ac8a4SKevin Cernekee } 233df0ac8a4SKevin Cernekee 234df0ac8a4SKevin Cernekee /* 235df0ac8a4SKevin Cernekee * Early setup - runs on secondary CPU after cache probe 236df0ac8a4SKevin Cernekee */ 237df0ac8a4SKevin Cernekee static void bmips_init_secondary(void) 238df0ac8a4SKevin Cernekee { 2396465460cSJonas Gorski switch (current_cpu_type()) { 2406465460cSJonas Gorski case CPU_BMIPS4350: 2416465460cSJonas Gorski case CPU_BMIPS4380: 242df0ac8a4SKevin Cernekee clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); 2436465460cSJonas Gorski break; 2446465460cSJonas Gorski case CPU_BMIPS5000: 245df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); 2466465460cSJonas Gorski break; 2476465460cSJonas Gorski } 248df0ac8a4SKevin Cernekee } 249df0ac8a4SKevin Cernekee 250df0ac8a4SKevin Cernekee /* 251df0ac8a4SKevin Cernekee * Late setup - runs on secondary CPU before entering the idle loop 252df0ac8a4SKevin Cernekee */ 253df0ac8a4SKevin Cernekee static void bmips_smp_finish(void) 254df0ac8a4SKevin Cernekee { 255df0ac8a4SKevin Cernekee pr_info("SMP: CPU%d is running\n", smp_processor_id()); 256856ac3c6SYong Zhang 257856ac3c6SYong Zhang /* make sure there won't be a timer interrupt for a little while */ 258856ac3c6SYong Zhang write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 259856ac3c6SYong Zhang 260856ac3c6SYong Zhang irq_enable_hazard(); 261d8010cebSKevin Cernekee set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE); 262856ac3c6SYong Zhang irq_enable_hazard(); 263df0ac8a4SKevin Cernekee } 264df0ac8a4SKevin Cernekee 265df0ac8a4SKevin Cernekee /* 266df0ac8a4SKevin Cernekee * BMIPS5000 raceless IPIs 267df0ac8a4SKevin Cernekee * 268df0ac8a4SKevin Cernekee * Each CPU has two inbound SW IRQs which are independent of all other CPUs. 269df0ac8a4SKevin Cernekee * IPI0 is used for SMP_RESCHEDULE_YOURSELF 270df0ac8a4SKevin Cernekee * IPI1 is used for SMP_CALL_FUNCTION 271df0ac8a4SKevin Cernekee */ 272df0ac8a4SKevin Cernekee 2736465460cSJonas Gorski static void bmips5000_send_ipi_single(int cpu, unsigned int action) 274df0ac8a4SKevin Cernekee { 275df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); 276df0ac8a4SKevin Cernekee } 277df0ac8a4SKevin Cernekee 2786465460cSJonas Gorski static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) 279df0ac8a4SKevin Cernekee { 280df0ac8a4SKevin Cernekee int action = irq - IPI0_IRQ; 281df0ac8a4SKevin Cernekee 282df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action)); 283df0ac8a4SKevin Cernekee 284df0ac8a4SKevin Cernekee if (action == 0) 285df0ac8a4SKevin Cernekee scheduler_ipi(); 286df0ac8a4SKevin Cernekee else 287df0ac8a4SKevin Cernekee smp_call_function_interrupt(); 288df0ac8a4SKevin Cernekee 289df0ac8a4SKevin Cernekee return IRQ_HANDLED; 290df0ac8a4SKevin Cernekee } 291df0ac8a4SKevin Cernekee 2926465460cSJonas Gorski static void bmips5000_send_ipi_mask(const struct cpumask *mask, 2936465460cSJonas Gorski unsigned int action) 2946465460cSJonas Gorski { 2956465460cSJonas Gorski unsigned int i; 2966465460cSJonas Gorski 2976465460cSJonas Gorski for_each_cpu(i, mask) 2986465460cSJonas Gorski bmips5000_send_ipi_single(i, action); 2996465460cSJonas Gorski } 300df0ac8a4SKevin Cernekee 301df0ac8a4SKevin Cernekee /* 302df0ac8a4SKevin Cernekee * BMIPS43xx racey IPIs 303df0ac8a4SKevin Cernekee * 304df0ac8a4SKevin Cernekee * We use one inbound SW IRQ for each CPU. 305df0ac8a4SKevin Cernekee * 306df0ac8a4SKevin Cernekee * A spinlock must be held in order to keep CPUx from accidentally clearing 307df0ac8a4SKevin Cernekee * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The 308df0ac8a4SKevin Cernekee * same spinlock is used to protect the action masks. 309df0ac8a4SKevin Cernekee */ 310df0ac8a4SKevin Cernekee 311df0ac8a4SKevin Cernekee static DEFINE_SPINLOCK(ipi_lock); 312df0ac8a4SKevin Cernekee static DEFINE_PER_CPU(int, ipi_action_mask); 313df0ac8a4SKevin Cernekee 3146465460cSJonas Gorski static void bmips43xx_send_ipi_single(int cpu, unsigned int action) 315df0ac8a4SKevin Cernekee { 316df0ac8a4SKevin Cernekee unsigned long flags; 317df0ac8a4SKevin Cernekee 318df0ac8a4SKevin Cernekee spin_lock_irqsave(&ipi_lock, flags); 319df0ac8a4SKevin Cernekee set_c0_cause(cpu ? C_SW1 : C_SW0); 320df0ac8a4SKevin Cernekee per_cpu(ipi_action_mask, cpu) |= action; 321df0ac8a4SKevin Cernekee irq_enable_hazard(); 322df0ac8a4SKevin Cernekee spin_unlock_irqrestore(&ipi_lock, flags); 323df0ac8a4SKevin Cernekee } 324df0ac8a4SKevin Cernekee 3256465460cSJonas Gorski static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) 326df0ac8a4SKevin Cernekee { 327df0ac8a4SKevin Cernekee unsigned long flags; 328df0ac8a4SKevin Cernekee int action, cpu = irq - IPI0_IRQ; 329df0ac8a4SKevin Cernekee 330df0ac8a4SKevin Cernekee spin_lock_irqsave(&ipi_lock, flags); 33135898716SChristoph Lameter action = __this_cpu_read(ipi_action_mask); 332df0ac8a4SKevin Cernekee per_cpu(ipi_action_mask, cpu) = 0; 333df0ac8a4SKevin Cernekee clear_c0_cause(cpu ? C_SW1 : C_SW0); 334df0ac8a4SKevin Cernekee spin_unlock_irqrestore(&ipi_lock, flags); 335df0ac8a4SKevin Cernekee 336df0ac8a4SKevin Cernekee if (action & SMP_RESCHEDULE_YOURSELF) 337df0ac8a4SKevin Cernekee scheduler_ipi(); 338df0ac8a4SKevin Cernekee if (action & SMP_CALL_FUNCTION) 339df0ac8a4SKevin Cernekee smp_call_function_interrupt(); 340df0ac8a4SKevin Cernekee 341df0ac8a4SKevin Cernekee return IRQ_HANDLED; 342df0ac8a4SKevin Cernekee } 343df0ac8a4SKevin Cernekee 3446465460cSJonas Gorski static void bmips43xx_send_ipi_mask(const struct cpumask *mask, 345df0ac8a4SKevin Cernekee unsigned int action) 346df0ac8a4SKevin Cernekee { 347df0ac8a4SKevin Cernekee unsigned int i; 348df0ac8a4SKevin Cernekee 349df0ac8a4SKevin Cernekee for_each_cpu(i, mask) 3506465460cSJonas Gorski bmips43xx_send_ipi_single(i, action); 351df0ac8a4SKevin Cernekee } 352df0ac8a4SKevin Cernekee 353df0ac8a4SKevin Cernekee #ifdef CONFIG_HOTPLUG_CPU 354df0ac8a4SKevin Cernekee 355df0ac8a4SKevin Cernekee static int bmips_cpu_disable(void) 356df0ac8a4SKevin Cernekee { 357df0ac8a4SKevin Cernekee unsigned int cpu = smp_processor_id(); 358df0ac8a4SKevin Cernekee 359df0ac8a4SKevin Cernekee if (cpu == 0) 360df0ac8a4SKevin Cernekee return -EBUSY; 361df0ac8a4SKevin Cernekee 362df0ac8a4SKevin Cernekee pr_info("SMP: CPU%d is offline\n", cpu); 363df0ac8a4SKevin Cernekee 3640b5f9c00SRusty Russell set_cpu_online(cpu, false); 365df0ac8a4SKevin Cernekee cpu_clear(cpu, cpu_callin_map); 366230b6ff5SJon Fraser clear_c0_status(IE_IRQ5); 367df0ac8a4SKevin Cernekee 368df0ac8a4SKevin Cernekee local_flush_tlb_all(); 369df0ac8a4SKevin Cernekee local_flush_icache_range(0, ~0); 370df0ac8a4SKevin Cernekee 371df0ac8a4SKevin Cernekee return 0; 372df0ac8a4SKevin Cernekee } 373df0ac8a4SKevin Cernekee 374df0ac8a4SKevin Cernekee static void bmips_cpu_die(unsigned int cpu) 375df0ac8a4SKevin Cernekee { 376df0ac8a4SKevin Cernekee } 377df0ac8a4SKevin Cernekee 378df0ac8a4SKevin Cernekee void __ref play_dead(void) 379df0ac8a4SKevin Cernekee { 380df0ac8a4SKevin Cernekee idle_task_exit(); 381df0ac8a4SKevin Cernekee 382df0ac8a4SKevin Cernekee /* flush data cache */ 383df0ac8a4SKevin Cernekee _dma_cache_wback_inv(0, ~0); 384df0ac8a4SKevin Cernekee 385df0ac8a4SKevin Cernekee /* 386df0ac8a4SKevin Cernekee * Wakeup is on SW0 or SW1; disable everything else 387df0ac8a4SKevin Cernekee * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux 388df0ac8a4SKevin Cernekee * IRQ handlers; this clears ST0_IE and returns immediately. 389df0ac8a4SKevin Cernekee */ 390df0ac8a4SKevin Cernekee clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1); 391d8010cebSKevin Cernekee change_c0_status( 392d8010cebSKevin Cernekee IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV, 393df0ac8a4SKevin Cernekee IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV); 394df0ac8a4SKevin Cernekee irq_disable_hazard(); 395df0ac8a4SKevin Cernekee 396df0ac8a4SKevin Cernekee /* 397df0ac8a4SKevin Cernekee * wait for SW interrupt from bmips_boot_secondary(), then jump 398df0ac8a4SKevin Cernekee * back to start_secondary() 399df0ac8a4SKevin Cernekee */ 400df0ac8a4SKevin Cernekee __asm__ __volatile__( 401df0ac8a4SKevin Cernekee " wait\n" 402df0ac8a4SKevin Cernekee " j bmips_secondary_reentry\n" 403df0ac8a4SKevin Cernekee : : : "memory"); 404df0ac8a4SKevin Cernekee } 405df0ac8a4SKevin Cernekee 406df0ac8a4SKevin Cernekee #endif /* CONFIG_HOTPLUG_CPU */ 407df0ac8a4SKevin Cernekee 4086465460cSJonas Gorski struct plat_smp_ops bmips43xx_smp_ops = { 409df0ac8a4SKevin Cernekee .smp_setup = bmips_smp_setup, 410df0ac8a4SKevin Cernekee .prepare_cpus = bmips_prepare_cpus, 411df0ac8a4SKevin Cernekee .boot_secondary = bmips_boot_secondary, 412df0ac8a4SKevin Cernekee .smp_finish = bmips_smp_finish, 413df0ac8a4SKevin Cernekee .init_secondary = bmips_init_secondary, 4146465460cSJonas Gorski .send_ipi_single = bmips43xx_send_ipi_single, 4156465460cSJonas Gorski .send_ipi_mask = bmips43xx_send_ipi_mask, 4166465460cSJonas Gorski #ifdef CONFIG_HOTPLUG_CPU 4176465460cSJonas Gorski .cpu_disable = bmips_cpu_disable, 4186465460cSJonas Gorski .cpu_die = bmips_cpu_die, 4196465460cSJonas Gorski #endif 4206465460cSJonas Gorski }; 4216465460cSJonas Gorski 4226465460cSJonas Gorski struct plat_smp_ops bmips5000_smp_ops = { 4236465460cSJonas Gorski .smp_setup = bmips_smp_setup, 4246465460cSJonas Gorski .prepare_cpus = bmips_prepare_cpus, 4256465460cSJonas Gorski .boot_secondary = bmips_boot_secondary, 4266465460cSJonas Gorski .smp_finish = bmips_smp_finish, 4276465460cSJonas Gorski .init_secondary = bmips_init_secondary, 4286465460cSJonas Gorski .send_ipi_single = bmips5000_send_ipi_single, 4296465460cSJonas Gorski .send_ipi_mask = bmips5000_send_ipi_mask, 430df0ac8a4SKevin Cernekee #ifdef CONFIG_HOTPLUG_CPU 431df0ac8a4SKevin Cernekee .cpu_disable = bmips_cpu_disable, 432df0ac8a4SKevin Cernekee .cpu_die = bmips_cpu_die, 433df0ac8a4SKevin Cernekee #endif 434df0ac8a4SKevin Cernekee }; 435df0ac8a4SKevin Cernekee 436df0ac8a4SKevin Cernekee #endif /* CONFIG_SMP */ 437df0ac8a4SKevin Cernekee 438df0ac8a4SKevin Cernekee /*********************************************************************** 439df0ac8a4SKevin Cernekee * BMIPS vector relocation 440df0ac8a4SKevin Cernekee * This is primarily used for SMP boot, but it is applicable to some 441df0ac8a4SKevin Cernekee * UP BMIPS systems as well. 442df0ac8a4SKevin Cernekee ***********************************************************************/ 443df0ac8a4SKevin Cernekee 444078a55fcSPaul Gortmaker static void bmips_wr_vec(unsigned long dst, char *start, char *end) 445df0ac8a4SKevin Cernekee { 446df0ac8a4SKevin Cernekee memcpy((void *)dst, start, end - start); 447df0ac8a4SKevin Cernekee dma_cache_wback((unsigned long)start, end - start); 448df0ac8a4SKevin Cernekee local_flush_icache_range(dst, dst + (end - start)); 449df0ac8a4SKevin Cernekee instruction_hazard(); 450df0ac8a4SKevin Cernekee } 451df0ac8a4SKevin Cernekee 452078a55fcSPaul Gortmaker static inline void bmips_nmi_handler_setup(void) 453df0ac8a4SKevin Cernekee { 454df0ac8a4SKevin Cernekee bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec, 455df0ac8a4SKevin Cernekee &bmips_reset_nmi_vec_end); 456df0ac8a4SKevin Cernekee bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec, 457df0ac8a4SKevin Cernekee &bmips_smp_int_vec_end); 458df0ac8a4SKevin Cernekee } 459df0ac8a4SKevin Cernekee 460fc455787SKevin Cernekee struct reset_vec_info { 461fc455787SKevin Cernekee int cpu; 462fc455787SKevin Cernekee u32 val; 463fc455787SKevin Cernekee }; 464fc455787SKevin Cernekee 465fc455787SKevin Cernekee static void bmips_set_reset_vec_remote(void *vinfo) 466fc455787SKevin Cernekee { 467fc455787SKevin Cernekee struct reset_vec_info *info = vinfo; 468fc455787SKevin Cernekee int shift = info->cpu & 0x01 ? 16 : 0; 469fc455787SKevin Cernekee u32 mask = ~(0xffff << shift), val = info->val >> 16; 470fc455787SKevin Cernekee 471fc455787SKevin Cernekee preempt_disable(); 472fc455787SKevin Cernekee if (smp_processor_id() > 0) { 473fc455787SKevin Cernekee smp_call_function_single(0, &bmips_set_reset_vec_remote, 474fc455787SKevin Cernekee info, 1); 475fc455787SKevin Cernekee } else { 476fc455787SKevin Cernekee if (info->cpu & 0x02) { 477fc455787SKevin Cernekee /* BMIPS5200 "should" use mask/shift, but it's buggy */ 478fc455787SKevin Cernekee bmips_write_zscm_reg(0xa0, (val << 16) | val); 479fc455787SKevin Cernekee bmips_read_zscm_reg(0xa0); 480fc455787SKevin Cernekee } else { 481fc455787SKevin Cernekee write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) | 482fc455787SKevin Cernekee (val << shift)); 483fc455787SKevin Cernekee } 484fc455787SKevin Cernekee } 485fc455787SKevin Cernekee preempt_enable(); 486fc455787SKevin Cernekee } 487fc455787SKevin Cernekee 488fc455787SKevin Cernekee static void bmips_set_reset_vec(int cpu, u32 val) 489fc455787SKevin Cernekee { 490fc455787SKevin Cernekee struct reset_vec_info info; 491fc455787SKevin Cernekee 492fc455787SKevin Cernekee if (current_cpu_type() == CPU_BMIPS5000) { 493fc455787SKevin Cernekee /* this needs to run from CPU0 (which is always online) */ 494fc455787SKevin Cernekee info.cpu = cpu; 495fc455787SKevin Cernekee info.val = val; 496fc455787SKevin Cernekee bmips_set_reset_vec_remote(&info); 497fc455787SKevin Cernekee } else { 498fc455787SKevin Cernekee void __iomem *cbr = BMIPS_GET_CBR(); 499fc455787SKevin Cernekee 500fc455787SKevin Cernekee if (cpu == 0) 501fc455787SKevin Cernekee __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); 502fc455787SKevin Cernekee else { 503fc455787SKevin Cernekee if (current_cpu_type() != CPU_BMIPS4380) 504fc455787SKevin Cernekee return; 505fc455787SKevin Cernekee __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); 506fc455787SKevin Cernekee } 507fc455787SKevin Cernekee } 508fc455787SKevin Cernekee __sync(); 509fc455787SKevin Cernekee back_to_back_c0_hazard(); 510fc455787SKevin Cernekee } 511fc455787SKevin Cernekee 512078a55fcSPaul Gortmaker void bmips_ebase_setup(void) 513df0ac8a4SKevin Cernekee { 514df0ac8a4SKevin Cernekee unsigned long new_ebase = ebase; 515df0ac8a4SKevin Cernekee 516df0ac8a4SKevin Cernekee BUG_ON(ebase != CKSEG0); 517df0ac8a4SKevin Cernekee 5186465460cSJonas Gorski switch (current_cpu_type()) { 5196465460cSJonas Gorski case CPU_BMIPS4350: 520df0ac8a4SKevin Cernekee /* 521df0ac8a4SKevin Cernekee * BMIPS4350 cannot relocate the normal vectors, but it 522df0ac8a4SKevin Cernekee * can relocate the BEV=1 vectors. So CPU1 starts up at 523df0ac8a4SKevin Cernekee * the relocated BEV=1, IV=0 general exception vector @ 524df0ac8a4SKevin Cernekee * 0xa000_0380. 525df0ac8a4SKevin Cernekee * 526df0ac8a4SKevin Cernekee * set_uncached_handler() is used here because: 527df0ac8a4SKevin Cernekee * - CPU1 will run this from uncached space 528df0ac8a4SKevin Cernekee * - None of the cacheflush functions are set up yet 529df0ac8a4SKevin Cernekee */ 530df0ac8a4SKevin Cernekee set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, 531df0ac8a4SKevin Cernekee &bmips_smp_int_vec, 0x80); 532df0ac8a4SKevin Cernekee __sync(); 533df0ac8a4SKevin Cernekee return; 534fa010672SJon Fraser case CPU_BMIPS3300: 5356465460cSJonas Gorski case CPU_BMIPS4380: 536df0ac8a4SKevin Cernekee /* 537df0ac8a4SKevin Cernekee * 0x8000_0000: reset/NMI (initially in kseg1) 538df0ac8a4SKevin Cernekee * 0x8000_0400: normal vectors 539df0ac8a4SKevin Cernekee */ 540df0ac8a4SKevin Cernekee new_ebase = 0x80000400; 541fc455787SKevin Cernekee bmips_set_reset_vec(0, RESET_FROM_KSEG0); 5426465460cSJonas Gorski break; 5436465460cSJonas Gorski case CPU_BMIPS5000: 544df0ac8a4SKevin Cernekee /* 545df0ac8a4SKevin Cernekee * 0x8000_0000: reset/NMI (initially in kseg1) 546df0ac8a4SKevin Cernekee * 0x8000_1000: normal vectors 547df0ac8a4SKevin Cernekee */ 548df0ac8a4SKevin Cernekee new_ebase = 0x80001000; 549fc455787SKevin Cernekee bmips_set_reset_vec(0, RESET_FROM_KSEG0); 550df0ac8a4SKevin Cernekee write_c0_ebase(new_ebase); 5516465460cSJonas Gorski break; 5526465460cSJonas Gorski default: 553df0ac8a4SKevin Cernekee return; 5546465460cSJonas Gorski } 5556465460cSJonas Gorski 556df0ac8a4SKevin Cernekee board_nmi_handler_setup = &bmips_nmi_handler_setup; 557df0ac8a4SKevin Cernekee ebase = new_ebase; 558df0ac8a4SKevin Cernekee } 559df0ac8a4SKevin Cernekee 560df0ac8a4SKevin Cernekee asmlinkage void __weak plat_wired_tlb_setup(void) 561df0ac8a4SKevin Cernekee { 562df0ac8a4SKevin Cernekee /* 563df0ac8a4SKevin Cernekee * Called when starting/restarting a secondary CPU. 564df0ac8a4SKevin Cernekee * Kernel stacks and other important data might only be accessible 565df0ac8a4SKevin Cernekee * once the wired entries are present. 566df0ac8a4SKevin Cernekee */ 567df0ac8a4SKevin Cernekee } 568