1df0ac8a4SKevin Cernekee /* 2df0ac8a4SKevin Cernekee * This file is subject to the terms and conditions of the GNU General Public 3df0ac8a4SKevin Cernekee * License. See the file "COPYING" in the main directory of this archive 4df0ac8a4SKevin Cernekee * for more details. 5df0ac8a4SKevin Cernekee * 6df0ac8a4SKevin Cernekee * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) 7df0ac8a4SKevin Cernekee * 8df0ac8a4SKevin Cernekee * SMP support for BMIPS 9df0ac8a4SKevin Cernekee */ 10df0ac8a4SKevin Cernekee 11df0ac8a4SKevin Cernekee #include <linux/init.h> 12df0ac8a4SKevin Cernekee #include <linux/sched.h> 13ef8bd77fSIngo Molnar #include <linux/sched/hotplug.h> 14fc69910fSArnd Bergmann #include <linux/sched/task_stack.h> 15df0ac8a4SKevin Cernekee #include <linux/mm.h> 16df0ac8a4SKevin Cernekee #include <linux/delay.h> 17df0ac8a4SKevin Cernekee #include <linux/smp.h> 18df0ac8a4SKevin Cernekee #include <linux/interrupt.h> 19df0ac8a4SKevin Cernekee #include <linux/spinlock.h> 20df0ac8a4SKevin Cernekee #include <linux/cpu.h> 21df0ac8a4SKevin Cernekee #include <linux/cpumask.h> 22df0ac8a4SKevin Cernekee #include <linux/reboot.h> 23df0ac8a4SKevin Cernekee #include <linux/io.h> 24df0ac8a4SKevin Cernekee #include <linux/compiler.h> 25df0ac8a4SKevin Cernekee #include <linux/linkage.h> 26df0ac8a4SKevin Cernekee #include <linux/bug.h> 27df0ac8a4SKevin Cernekee #include <linux/kernel.h> 2862cac480SDengcheng Zhu #include <linux/kexec.h> 29bf8bde41SFlorian Fainelli #include <linux/irq.h> 30df0ac8a4SKevin Cernekee 31df0ac8a4SKevin Cernekee #include <asm/time.h> 32df0ac8a4SKevin Cernekee #include <asm/processor.h> 33df0ac8a4SKevin Cernekee #include <asm/bootinfo.h> 34df0ac8a4SKevin Cernekee #include <asm/cacheflush.h> 35df0ac8a4SKevin Cernekee #include <asm/tlbflush.h> 36df0ac8a4SKevin Cernekee #include <asm/mipsregs.h> 37df0ac8a4SKevin Cernekee #include <asm/bmips.h> 38df0ac8a4SKevin Cernekee #include <asm/traps.h> 39df0ac8a4SKevin Cernekee #include <asm/barrier.h> 40fc455787SKevin Cernekee #include <asm/cpu-features.h> 41df0ac8a4SKevin Cernekee 42df0ac8a4SKevin Cernekee static int __maybe_unused max_cpus = 1; 43df0ac8a4SKevin Cernekee 44df0ac8a4SKevin Cernekee /* these may be configured by the platform code */ 45df0ac8a4SKevin Cernekee int bmips_smp_enabled = 1; 46df0ac8a4SKevin Cernekee int bmips_cpu_offset; 47df0ac8a4SKevin Cernekee cpumask_t bmips_booted_mask; 48d8010cebSKevin Cernekee unsigned long bmips_tp1_irqs = IE_IRQ1; 49df0ac8a4SKevin Cernekee 50fc455787SKevin Cernekee #define RESET_FROM_KSEG0 0x80080800 51fc455787SKevin Cernekee #define RESET_FROM_KSEG1 0xa0080800 52fc455787SKevin Cernekee 533677a283SKevin Cernekee static void bmips_set_reset_vec(int cpu, u32 val); 543677a283SKevin Cernekee 55df0ac8a4SKevin Cernekee #ifdef CONFIG_SMP 56df0ac8a4SKevin Cernekee 57142dbcf3SJosh Poimboeuf #include <asm/smp.h> 58142dbcf3SJosh Poimboeuf 59df0ac8a4SKevin Cernekee /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */ 60df0ac8a4SKevin Cernekee unsigned long bmips_smp_boot_sp; 61df0ac8a4SKevin Cernekee unsigned long bmips_smp_boot_gp; 62df0ac8a4SKevin Cernekee 636465460cSJonas Gorski static void bmips43xx_send_ipi_single(int cpu, unsigned int action); 646465460cSJonas Gorski static void bmips5000_send_ipi_single(int cpu, unsigned int action); 656465460cSJonas Gorski static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id); 666465460cSJonas Gorski static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id); 67df0ac8a4SKevin Cernekee 68df0ac8a4SKevin Cernekee /* SW interrupts 0,1 are used for interprocessor signaling */ 69df0ac8a4SKevin Cernekee #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) 70df0ac8a4SKevin Cernekee #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1) 71df0ac8a4SKevin Cernekee 72df0ac8a4SKevin Cernekee #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) 73df0ac8a4SKevin Cernekee #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 74df0ac8a4SKevin Cernekee #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 75df0ac8a4SKevin Cernekee #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) 76df0ac8a4SKevin Cernekee 77df0ac8a4SKevin Cernekee static void __init bmips_smp_setup(void) 78df0ac8a4SKevin Cernekee { 794df715aaSFlorian Fainelli int i, cpu = 1, boot_cpu = 0; 80fcfa66deSFlorian Fainelli int cpu_hw_intr; 81fcfa66deSFlorian Fainelli 826465460cSJonas Gorski switch (current_cpu_type()) { 836465460cSJonas Gorski case CPU_BMIPS4350: 846465460cSJonas Gorski case CPU_BMIPS4380: 85df0ac8a4SKevin Cernekee /* arbitration priority */ 86df0ac8a4SKevin Cernekee clear_c0_brcm_cmt_ctrl(0x30); 87df0ac8a4SKevin Cernekee 88df0ac8a4SKevin Cernekee /* NBK and weak order flags */ 89df0ac8a4SKevin Cernekee set_c0_brcm_config_0(0x30000); 90df0ac8a4SKevin Cernekee 914df715aaSFlorian Fainelli /* Find out if we are running on TP0 or TP1 */ 924df715aaSFlorian Fainelli boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 934df715aaSFlorian Fainelli 94df0ac8a4SKevin Cernekee /* 956465460cSJonas Gorski * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other 966465460cSJonas Gorski * thread 97df0ac8a4SKevin Cernekee * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 98df0ac8a4SKevin Cernekee * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 99df0ac8a4SKevin Cernekee */ 100fcfa66deSFlorian Fainelli if (boot_cpu == 0) 101fcfa66deSFlorian Fainelli cpu_hw_intr = 0x02; 102fcfa66deSFlorian Fainelli else 103fcfa66deSFlorian Fainelli cpu_hw_intr = 0x1d; 104fcfa66deSFlorian Fainelli 1056465460cSJonas Gorski change_c0_brcm_cmt_intr(0xf8018000, 1066465460cSJonas Gorski (cpu_hw_intr << 27) | (0x03 << 15)); 107df0ac8a4SKevin Cernekee 108df0ac8a4SKevin Cernekee /* single core, 2 threads (2 pipelines) */ 109df0ac8a4SKevin Cernekee max_cpus = 2; 1106465460cSJonas Gorski 1116465460cSJonas Gorski break; 1126465460cSJonas Gorski case CPU_BMIPS5000: 113df0ac8a4SKevin Cernekee /* enable raceless SW interrupts */ 114df0ac8a4SKevin Cernekee set_c0_brcm_config(0x03 << 22); 115df0ac8a4SKevin Cernekee 116df0ac8a4SKevin Cernekee /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ 117df0ac8a4SKevin Cernekee change_c0_brcm_mode(0x1f << 27, 0x02 << 27); 118df0ac8a4SKevin Cernekee 119df0ac8a4SKevin Cernekee /* N cores, 2 threads per core */ 120df0ac8a4SKevin Cernekee max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; 121df0ac8a4SKevin Cernekee 122df0ac8a4SKevin Cernekee /* clear any pending SW interrupts */ 123df0ac8a4SKevin Cernekee for (i = 0; i < max_cpus; i++) { 124df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); 125df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); 126df0ac8a4SKevin Cernekee } 1276465460cSJonas Gorski 1286465460cSJonas Gorski break; 1296465460cSJonas Gorski default: 1306465460cSJonas Gorski max_cpus = 1; 1316465460cSJonas Gorski } 132df0ac8a4SKevin Cernekee 133df0ac8a4SKevin Cernekee if (!bmips_smp_enabled) 134df0ac8a4SKevin Cernekee max_cpus = 1; 135df0ac8a4SKevin Cernekee 136df0ac8a4SKevin Cernekee /* this can be overridden by the BSP */ 137df0ac8a4SKevin Cernekee if (!board_ebase_setup) 138df0ac8a4SKevin Cernekee board_ebase_setup = &bmips_ebase_setup; 139df0ac8a4SKevin Cernekee 1404f62d0a2SÁlvaro Fernández Rojas if (max_cpus > 1) { 1414df715aaSFlorian Fainelli __cpu_number_map[boot_cpu] = 0; 1424df715aaSFlorian Fainelli __cpu_logical_map[0] = boot_cpu; 1434df715aaSFlorian Fainelli 144df0ac8a4SKevin Cernekee for (i = 0; i < max_cpus; i++) { 1454df715aaSFlorian Fainelli if (i != boot_cpu) { 1464df715aaSFlorian Fainelli __cpu_number_map[i] = cpu; 1474df715aaSFlorian Fainelli __cpu_logical_map[cpu] = i; 1484df715aaSFlorian Fainelli cpu++; 1494df715aaSFlorian Fainelli } 150df0ac8a4SKevin Cernekee set_cpu_possible(i, 1); 151df0ac8a4SKevin Cernekee set_cpu_present(i, 1); 152df0ac8a4SKevin Cernekee } 1534f62d0a2SÁlvaro Fernández Rojas } else { 1544f62d0a2SÁlvaro Fernández Rojas __cpu_number_map[0] = boot_cpu; 1554f62d0a2SÁlvaro Fernández Rojas __cpu_logical_map[0] = 0; 1564f62d0a2SÁlvaro Fernández Rojas set_cpu_possible(0, 1); 1574f62d0a2SÁlvaro Fernández Rojas set_cpu_present(0, 1); 1584f62d0a2SÁlvaro Fernández Rojas } 159df0ac8a4SKevin Cernekee } 160df0ac8a4SKevin Cernekee 161df0ac8a4SKevin Cernekee /* 162df0ac8a4SKevin Cernekee * IPI IRQ setup - runs on CPU0 163df0ac8a4SKevin Cernekee */ 164df0ac8a4SKevin Cernekee static void bmips_prepare_cpus(unsigned int max_cpus) 165df0ac8a4SKevin Cernekee { 1666465460cSJonas Gorski irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id); 1676465460cSJonas Gorski 1686465460cSJonas Gorski switch (current_cpu_type()) { 1696465460cSJonas Gorski case CPU_BMIPS4350: 1706465460cSJonas Gorski case CPU_BMIPS4380: 1716465460cSJonas Gorski bmips_ipi_interrupt = bmips43xx_ipi_interrupt; 1726465460cSJonas Gorski break; 1736465460cSJonas Gorski case CPU_BMIPS5000: 1746465460cSJonas Gorski bmips_ipi_interrupt = bmips5000_ipi_interrupt; 1756465460cSJonas Gorski break; 1766465460cSJonas Gorski default: 1776465460cSJonas Gorski return; 1786465460cSJonas Gorski } 1796465460cSJonas Gorski 18006a3f0c9SJustin Chen if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, 18106a3f0c9SJustin Chen IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi0", NULL)) 182f7777dccSRalf Baechle panic("Can't request IPI0 interrupt"); 18306a3f0c9SJustin Chen if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, 18406a3f0c9SJustin Chen IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi1", NULL)) 185f7777dccSRalf Baechle panic("Can't request IPI1 interrupt"); 186df0ac8a4SKevin Cernekee } 187df0ac8a4SKevin Cernekee 188df0ac8a4SKevin Cernekee /* 189df0ac8a4SKevin Cernekee * Tell the hardware to boot CPUx - runs on CPU0 190df0ac8a4SKevin Cernekee */ 191d595d423SPaul Burton static int bmips_boot_secondary(int cpu, struct task_struct *idle) 192df0ac8a4SKevin Cernekee { 193df0ac8a4SKevin Cernekee bmips_smp_boot_sp = __KSTK_TOS(idle); 194df0ac8a4SKevin Cernekee bmips_smp_boot_gp = (unsigned long)task_thread_info(idle); 195df0ac8a4SKevin Cernekee mb(); 196df0ac8a4SKevin Cernekee 197df0ac8a4SKevin Cernekee /* 198df0ac8a4SKevin Cernekee * Initial boot sequence for secondary CPU: 199df0ac8a4SKevin Cernekee * bmips_reset_nmi_vec @ a000_0000 -> 200df0ac8a4SKevin Cernekee * bmips_smp_entry -> 201df0ac8a4SKevin Cernekee * plat_wired_tlb_setup (cached function call; optional) -> 202df0ac8a4SKevin Cernekee * start_secondary (cached jump) 203df0ac8a4SKevin Cernekee * 204df0ac8a4SKevin Cernekee * Warm restart sequence: 205df0ac8a4SKevin Cernekee * play_dead WAIT loop -> 206df0ac8a4SKevin Cernekee * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC -> 207df0ac8a4SKevin Cernekee * eret to play_dead -> 208df0ac8a4SKevin Cernekee * bmips_secondary_reentry -> 209df0ac8a4SKevin Cernekee * start_secondary 210df0ac8a4SKevin Cernekee */ 211df0ac8a4SKevin Cernekee 212df0ac8a4SKevin Cernekee pr_info("SMP: Booting CPU%d...\n", cpu); 213df0ac8a4SKevin Cernekee 2146465460cSJonas Gorski if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { 2153677a283SKevin Cernekee /* kseg1 might not exist if this CPU enabled XKS01 */ 2163677a283SKevin Cernekee bmips_set_reset_vec(cpu, RESET_FROM_KSEG0); 2173677a283SKevin Cernekee 2186465460cSJonas Gorski switch (current_cpu_type()) { 2196465460cSJonas Gorski case CPU_BMIPS4350: 2206465460cSJonas Gorski case CPU_BMIPS4380: 2216465460cSJonas Gorski bmips43xx_send_ipi_single(cpu, 0); 2226465460cSJonas Gorski break; 2236465460cSJonas Gorski case CPU_BMIPS5000: 2246465460cSJonas Gorski bmips5000_send_ipi_single(cpu, 0); 2256465460cSJonas Gorski break; 2266465460cSJonas Gorski } 2273677a283SKevin Cernekee } else { 2283677a283SKevin Cernekee bmips_set_reset_vec(cpu, RESET_FROM_KSEG1); 2293677a283SKevin Cernekee 2306465460cSJonas Gorski switch (current_cpu_type()) { 2316465460cSJonas Gorski case CPU_BMIPS4350: 2326465460cSJonas Gorski case CPU_BMIPS4380: 2334df715aaSFlorian Fainelli /* Reset slave TP1 if booting from TP0 */ 234976f39b1SFlorian Fainelli if (cpu_logical_map(cpu) == 1) 235df0ac8a4SKevin Cernekee set_c0_brcm_cmt_ctrl(0x01); 2366465460cSJonas Gorski break; 2376465460cSJonas Gorski case CPU_BMIPS5000: 238df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); 2396465460cSJonas Gorski break; 2406465460cSJonas Gorski } 241df0ac8a4SKevin Cernekee cpumask_set_cpu(cpu, &bmips_booted_mask); 242df0ac8a4SKevin Cernekee } 243d595d423SPaul Burton 244d595d423SPaul Burton return 0; 245df0ac8a4SKevin Cernekee } 246df0ac8a4SKevin Cernekee 247df0ac8a4SKevin Cernekee /* 248df0ac8a4SKevin Cernekee * Early setup - runs on secondary CPU after cache probe 249df0ac8a4SKevin Cernekee */ 250df0ac8a4SKevin Cernekee static void bmips_init_secondary(void) 251df0ac8a4SKevin Cernekee { 252e14f633bSFlorian Fainelli bmips_cpu_setup(); 253e14f633bSFlorian Fainelli 2546465460cSJonas Gorski switch (current_cpu_type()) { 2556465460cSJonas Gorski case CPU_BMIPS4350: 2566465460cSJonas Gorski case CPU_BMIPS4380: 257df0ac8a4SKevin Cernekee clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); 2586465460cSJonas Gorski break; 2596465460cSJonas Gorski case CPU_BMIPS5000: 260df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); 261f875a832SPaul Burton cpu_set_core(¤t_cpu_data, (read_c0_brcm_config() >> 25) & 3); 2626465460cSJonas Gorski break; 2636465460cSJonas Gorski } 264df0ac8a4SKevin Cernekee } 265df0ac8a4SKevin Cernekee 266df0ac8a4SKevin Cernekee /* 267df0ac8a4SKevin Cernekee * Late setup - runs on secondary CPU before entering the idle loop 268df0ac8a4SKevin Cernekee */ 269df0ac8a4SKevin Cernekee static void bmips_smp_finish(void) 270df0ac8a4SKevin Cernekee { 271df0ac8a4SKevin Cernekee pr_info("SMP: CPU%d is running\n", smp_processor_id()); 272856ac3c6SYong Zhang 273856ac3c6SYong Zhang /* make sure there won't be a timer interrupt for a little while */ 274856ac3c6SYong Zhang write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 275856ac3c6SYong Zhang 276856ac3c6SYong Zhang irq_enable_hazard(); 277d8010cebSKevin Cernekee set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE); 278856ac3c6SYong Zhang irq_enable_hazard(); 279df0ac8a4SKevin Cernekee } 280df0ac8a4SKevin Cernekee 281df0ac8a4SKevin Cernekee /* 282df0ac8a4SKevin Cernekee * BMIPS5000 raceless IPIs 283df0ac8a4SKevin Cernekee * 284df0ac8a4SKevin Cernekee * Each CPU has two inbound SW IRQs which are independent of all other CPUs. 285df0ac8a4SKevin Cernekee * IPI0 is used for SMP_RESCHEDULE_YOURSELF 286df0ac8a4SKevin Cernekee * IPI1 is used for SMP_CALL_FUNCTION 287df0ac8a4SKevin Cernekee */ 288df0ac8a4SKevin Cernekee 2896465460cSJonas Gorski static void bmips5000_send_ipi_single(int cpu, unsigned int action) 290df0ac8a4SKevin Cernekee { 291df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); 292df0ac8a4SKevin Cernekee } 293df0ac8a4SKevin Cernekee 2946465460cSJonas Gorski static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) 295df0ac8a4SKevin Cernekee { 296df0ac8a4SKevin Cernekee int action = irq - IPI0_IRQ; 297df0ac8a4SKevin Cernekee 298df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action)); 299df0ac8a4SKevin Cernekee 300df0ac8a4SKevin Cernekee if (action == 0) 301df0ac8a4SKevin Cernekee scheduler_ipi(); 302df0ac8a4SKevin Cernekee else 3034ace6139SAlex Smith generic_smp_call_function_interrupt(); 304df0ac8a4SKevin Cernekee 305df0ac8a4SKevin Cernekee return IRQ_HANDLED; 306df0ac8a4SKevin Cernekee } 307df0ac8a4SKevin Cernekee 3086465460cSJonas Gorski static void bmips5000_send_ipi_mask(const struct cpumask *mask, 3096465460cSJonas Gorski unsigned int action) 3106465460cSJonas Gorski { 3116465460cSJonas Gorski unsigned int i; 3126465460cSJonas Gorski 3136465460cSJonas Gorski for_each_cpu(i, mask) 3146465460cSJonas Gorski bmips5000_send_ipi_single(i, action); 3156465460cSJonas Gorski } 316df0ac8a4SKevin Cernekee 317df0ac8a4SKevin Cernekee /* 318df0ac8a4SKevin Cernekee * BMIPS43xx racey IPIs 319df0ac8a4SKevin Cernekee * 320df0ac8a4SKevin Cernekee * We use one inbound SW IRQ for each CPU. 321df0ac8a4SKevin Cernekee * 322df0ac8a4SKevin Cernekee * A spinlock must be held in order to keep CPUx from accidentally clearing 323df0ac8a4SKevin Cernekee * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The 324df0ac8a4SKevin Cernekee * same spinlock is used to protect the action masks. 325df0ac8a4SKevin Cernekee */ 326df0ac8a4SKevin Cernekee 327df0ac8a4SKevin Cernekee static DEFINE_SPINLOCK(ipi_lock); 328df0ac8a4SKevin Cernekee static DEFINE_PER_CPU(int, ipi_action_mask); 329df0ac8a4SKevin Cernekee 3306465460cSJonas Gorski static void bmips43xx_send_ipi_single(int cpu, unsigned int action) 331df0ac8a4SKevin Cernekee { 332df0ac8a4SKevin Cernekee unsigned long flags; 333df0ac8a4SKevin Cernekee 334df0ac8a4SKevin Cernekee spin_lock_irqsave(&ipi_lock, flags); 335df0ac8a4SKevin Cernekee set_c0_cause(cpu ? C_SW1 : C_SW0); 336df0ac8a4SKevin Cernekee per_cpu(ipi_action_mask, cpu) |= action; 337df0ac8a4SKevin Cernekee irq_enable_hazard(); 338df0ac8a4SKevin Cernekee spin_unlock_irqrestore(&ipi_lock, flags); 339df0ac8a4SKevin Cernekee } 340df0ac8a4SKevin Cernekee 3416465460cSJonas Gorski static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) 342df0ac8a4SKevin Cernekee { 343df0ac8a4SKevin Cernekee unsigned long flags; 344df0ac8a4SKevin Cernekee int action, cpu = irq - IPI0_IRQ; 345df0ac8a4SKevin Cernekee 346df0ac8a4SKevin Cernekee spin_lock_irqsave(&ipi_lock, flags); 34735898716SChristoph Lameter action = __this_cpu_read(ipi_action_mask); 348df0ac8a4SKevin Cernekee per_cpu(ipi_action_mask, cpu) = 0; 349df0ac8a4SKevin Cernekee clear_c0_cause(cpu ? C_SW1 : C_SW0); 350df0ac8a4SKevin Cernekee spin_unlock_irqrestore(&ipi_lock, flags); 351df0ac8a4SKevin Cernekee 352df0ac8a4SKevin Cernekee if (action & SMP_RESCHEDULE_YOURSELF) 353df0ac8a4SKevin Cernekee scheduler_ipi(); 354df0ac8a4SKevin Cernekee if (action & SMP_CALL_FUNCTION) 3554ace6139SAlex Smith generic_smp_call_function_interrupt(); 356df0ac8a4SKevin Cernekee 357df0ac8a4SKevin Cernekee return IRQ_HANDLED; 358df0ac8a4SKevin Cernekee } 359df0ac8a4SKevin Cernekee 3606465460cSJonas Gorski static void bmips43xx_send_ipi_mask(const struct cpumask *mask, 361df0ac8a4SKevin Cernekee unsigned int action) 362df0ac8a4SKevin Cernekee { 363df0ac8a4SKevin Cernekee unsigned int i; 364df0ac8a4SKevin Cernekee 365df0ac8a4SKevin Cernekee for_each_cpu(i, mask) 3666465460cSJonas Gorski bmips43xx_send_ipi_single(i, action); 367df0ac8a4SKevin Cernekee } 368df0ac8a4SKevin Cernekee 369df0ac8a4SKevin Cernekee #ifdef CONFIG_HOTPLUG_CPU 370df0ac8a4SKevin Cernekee 371df0ac8a4SKevin Cernekee static int bmips_cpu_disable(void) 372df0ac8a4SKevin Cernekee { 373df0ac8a4SKevin Cernekee unsigned int cpu = smp_processor_id(); 374df0ac8a4SKevin Cernekee 375df0ac8a4SKevin Cernekee pr_info("SMP: CPU%d is offline\n", cpu); 376df0ac8a4SKevin Cernekee 3770b5f9c00SRusty Russell set_cpu_online(cpu, false); 378826e99beSJames Hogan calculate_cpu_foreign_map(); 379bf8bde41SFlorian Fainelli irq_migrate_all_off_this_cpu(); 380230b6ff5SJon Fraser clear_c0_status(IE_IRQ5); 381df0ac8a4SKevin Cernekee 382df0ac8a4SKevin Cernekee local_flush_tlb_all(); 383df0ac8a4SKevin Cernekee local_flush_icache_range(0, ~0); 384df0ac8a4SKevin Cernekee 385df0ac8a4SKevin Cernekee return 0; 386df0ac8a4SKevin Cernekee } 387df0ac8a4SKevin Cernekee 388df0ac8a4SKevin Cernekee static void bmips_cpu_die(unsigned int cpu) 389df0ac8a4SKevin Cernekee { 390df0ac8a4SKevin Cernekee } 391df0ac8a4SKevin Cernekee 392df0ac8a4SKevin Cernekee void __ref play_dead(void) 393df0ac8a4SKevin Cernekee { 394df0ac8a4SKevin Cernekee idle_task_exit(); 395df0ac8a4SKevin Cernekee 396df0ac8a4SKevin Cernekee /* flush data cache */ 397df0ac8a4SKevin Cernekee _dma_cache_wback_inv(0, ~0); 398df0ac8a4SKevin Cernekee 399df0ac8a4SKevin Cernekee /* 400df0ac8a4SKevin Cernekee * Wakeup is on SW0 or SW1; disable everything else 401df0ac8a4SKevin Cernekee * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux 402df0ac8a4SKevin Cernekee * IRQ handlers; this clears ST0_IE and returns immediately. 403df0ac8a4SKevin Cernekee */ 404df0ac8a4SKevin Cernekee clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1); 405d8010cebSKevin Cernekee change_c0_status( 406d8010cebSKevin Cernekee IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV, 407df0ac8a4SKevin Cernekee IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV); 408df0ac8a4SKevin Cernekee irq_disable_hazard(); 409df0ac8a4SKevin Cernekee 410df0ac8a4SKevin Cernekee /* 411df0ac8a4SKevin Cernekee * wait for SW interrupt from bmips_boot_secondary(), then jump 412df0ac8a4SKevin Cernekee * back to start_secondary() 413df0ac8a4SKevin Cernekee */ 414df0ac8a4SKevin Cernekee __asm__ __volatile__( 415df0ac8a4SKevin Cernekee " wait\n" 416df0ac8a4SKevin Cernekee " j bmips_secondary_reentry\n" 417df0ac8a4SKevin Cernekee : : : "memory"); 418*a80ceed6SJosh Poimboeuf 419*a80ceed6SJosh Poimboeuf BUG(); 420df0ac8a4SKevin Cernekee } 421df0ac8a4SKevin Cernekee 422df0ac8a4SKevin Cernekee #endif /* CONFIG_HOTPLUG_CPU */ 423df0ac8a4SKevin Cernekee 424ff2c8252SMatt Redfearn const struct plat_smp_ops bmips43xx_smp_ops = { 425df0ac8a4SKevin Cernekee .smp_setup = bmips_smp_setup, 426df0ac8a4SKevin Cernekee .prepare_cpus = bmips_prepare_cpus, 427df0ac8a4SKevin Cernekee .boot_secondary = bmips_boot_secondary, 428df0ac8a4SKevin Cernekee .smp_finish = bmips_smp_finish, 429df0ac8a4SKevin Cernekee .init_secondary = bmips_init_secondary, 4306465460cSJonas Gorski .send_ipi_single = bmips43xx_send_ipi_single, 4316465460cSJonas Gorski .send_ipi_mask = bmips43xx_send_ipi_mask, 4326465460cSJonas Gorski #ifdef CONFIG_HOTPLUG_CPU 4336465460cSJonas Gorski .cpu_disable = bmips_cpu_disable, 4346465460cSJonas Gorski .cpu_die = bmips_cpu_die, 4356465460cSJonas Gorski #endif 43662cac480SDengcheng Zhu #ifdef CONFIG_KEXEC 43762cac480SDengcheng Zhu .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 43862cac480SDengcheng Zhu #endif 4396465460cSJonas Gorski }; 4406465460cSJonas Gorski 441ff2c8252SMatt Redfearn const struct plat_smp_ops bmips5000_smp_ops = { 4426465460cSJonas Gorski .smp_setup = bmips_smp_setup, 4436465460cSJonas Gorski .prepare_cpus = bmips_prepare_cpus, 4446465460cSJonas Gorski .boot_secondary = bmips_boot_secondary, 4456465460cSJonas Gorski .smp_finish = bmips_smp_finish, 4466465460cSJonas Gorski .init_secondary = bmips_init_secondary, 4476465460cSJonas Gorski .send_ipi_single = bmips5000_send_ipi_single, 4486465460cSJonas Gorski .send_ipi_mask = bmips5000_send_ipi_mask, 449df0ac8a4SKevin Cernekee #ifdef CONFIG_HOTPLUG_CPU 450df0ac8a4SKevin Cernekee .cpu_disable = bmips_cpu_disable, 451df0ac8a4SKevin Cernekee .cpu_die = bmips_cpu_die, 452df0ac8a4SKevin Cernekee #endif 45362cac480SDengcheng Zhu #ifdef CONFIG_KEXEC 45462cac480SDengcheng Zhu .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 45562cac480SDengcheng Zhu #endif 456df0ac8a4SKevin Cernekee }; 457df0ac8a4SKevin Cernekee 458df0ac8a4SKevin Cernekee #endif /* CONFIG_SMP */ 459df0ac8a4SKevin Cernekee 460df0ac8a4SKevin Cernekee /*********************************************************************** 461df0ac8a4SKevin Cernekee * BMIPS vector relocation 462df0ac8a4SKevin Cernekee * This is primarily used for SMP boot, but it is applicable to some 463df0ac8a4SKevin Cernekee * UP BMIPS systems as well. 464df0ac8a4SKevin Cernekee ***********************************************************************/ 465df0ac8a4SKevin Cernekee 466078a55fcSPaul Gortmaker static void bmips_wr_vec(unsigned long dst, char *start, char *end) 467df0ac8a4SKevin Cernekee { 468df0ac8a4SKevin Cernekee memcpy((void *)dst, start, end - start); 46957b41758SPetri Gynther dma_cache_wback(dst, end - start); 470df0ac8a4SKevin Cernekee local_flush_icache_range(dst, dst + (end - start)); 471df0ac8a4SKevin Cernekee instruction_hazard(); 472df0ac8a4SKevin Cernekee } 473df0ac8a4SKevin Cernekee 474078a55fcSPaul Gortmaker static inline void bmips_nmi_handler_setup(void) 475df0ac8a4SKevin Cernekee { 476e4f5cb1aSJonas Gorski bmips_wr_vec(BMIPS_NMI_RESET_VEC, bmips_reset_nmi_vec, 477e4f5cb1aSJonas Gorski bmips_reset_nmi_vec_end); 478e4f5cb1aSJonas Gorski bmips_wr_vec(BMIPS_WARM_RESTART_VEC, bmips_smp_int_vec, 479e4f5cb1aSJonas Gorski bmips_smp_int_vec_end); 480df0ac8a4SKevin Cernekee } 481df0ac8a4SKevin Cernekee 482fc455787SKevin Cernekee struct reset_vec_info { 483fc455787SKevin Cernekee int cpu; 484fc455787SKevin Cernekee u32 val; 485fc455787SKevin Cernekee }; 486fc455787SKevin Cernekee 487fc455787SKevin Cernekee static void bmips_set_reset_vec_remote(void *vinfo) 488fc455787SKevin Cernekee { 489fc455787SKevin Cernekee struct reset_vec_info *info = vinfo; 490fc455787SKevin Cernekee int shift = info->cpu & 0x01 ? 16 : 0; 491fc455787SKevin Cernekee u32 mask = ~(0xffff << shift), val = info->val >> 16; 492fc455787SKevin Cernekee 493fc455787SKevin Cernekee preempt_disable(); 494fc455787SKevin Cernekee if (smp_processor_id() > 0) { 495fc455787SKevin Cernekee smp_call_function_single(0, &bmips_set_reset_vec_remote, 496fc455787SKevin Cernekee info, 1); 497fc455787SKevin Cernekee } else { 498fc455787SKevin Cernekee if (info->cpu & 0x02) { 499fc455787SKevin Cernekee /* BMIPS5200 "should" use mask/shift, but it's buggy */ 500fc455787SKevin Cernekee bmips_write_zscm_reg(0xa0, (val << 16) | val); 501fc455787SKevin Cernekee bmips_read_zscm_reg(0xa0); 502fc455787SKevin Cernekee } else { 503fc455787SKevin Cernekee write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) | 504fc455787SKevin Cernekee (val << shift)); 505fc455787SKevin Cernekee } 506fc455787SKevin Cernekee } 507fc455787SKevin Cernekee preempt_enable(); 508fc455787SKevin Cernekee } 509fc455787SKevin Cernekee 510fc455787SKevin Cernekee static void bmips_set_reset_vec(int cpu, u32 val) 511fc455787SKevin Cernekee { 512fc455787SKevin Cernekee struct reset_vec_info info; 513fc455787SKevin Cernekee 514fc455787SKevin Cernekee if (current_cpu_type() == CPU_BMIPS5000) { 515fc455787SKevin Cernekee /* this needs to run from CPU0 (which is always online) */ 516fc455787SKevin Cernekee info.cpu = cpu; 517fc455787SKevin Cernekee info.val = val; 518fc455787SKevin Cernekee bmips_set_reset_vec_remote(&info); 519fc455787SKevin Cernekee } else { 520fc455787SKevin Cernekee void __iomem *cbr = BMIPS_GET_CBR(); 521fc455787SKevin Cernekee 522fc455787SKevin Cernekee if (cpu == 0) 523fc455787SKevin Cernekee __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); 524fc455787SKevin Cernekee else { 525fc455787SKevin Cernekee if (current_cpu_type() != CPU_BMIPS4380) 526fc455787SKevin Cernekee return; 527fc455787SKevin Cernekee __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); 528fc455787SKevin Cernekee } 529fc455787SKevin Cernekee } 530fc455787SKevin Cernekee __sync(); 531fc455787SKevin Cernekee back_to_back_c0_hazard(); 532fc455787SKevin Cernekee } 533fc455787SKevin Cernekee 534078a55fcSPaul Gortmaker void bmips_ebase_setup(void) 535df0ac8a4SKevin Cernekee { 536df0ac8a4SKevin Cernekee unsigned long new_ebase = ebase; 537df0ac8a4SKevin Cernekee 538df0ac8a4SKevin Cernekee BUG_ON(ebase != CKSEG0); 539df0ac8a4SKevin Cernekee 5406465460cSJonas Gorski switch (current_cpu_type()) { 5416465460cSJonas Gorski case CPU_BMIPS4350: 542df0ac8a4SKevin Cernekee /* 543df0ac8a4SKevin Cernekee * BMIPS4350 cannot relocate the normal vectors, but it 544df0ac8a4SKevin Cernekee * can relocate the BEV=1 vectors. So CPU1 starts up at 545df0ac8a4SKevin Cernekee * the relocated BEV=1, IV=0 general exception vector @ 546df0ac8a4SKevin Cernekee * 0xa000_0380. 547df0ac8a4SKevin Cernekee * 548df0ac8a4SKevin Cernekee * set_uncached_handler() is used here because: 549df0ac8a4SKevin Cernekee * - CPU1 will run this from uncached space 550df0ac8a4SKevin Cernekee * - None of the cacheflush functions are set up yet 551df0ac8a4SKevin Cernekee */ 552df0ac8a4SKevin Cernekee set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, 553df0ac8a4SKevin Cernekee &bmips_smp_int_vec, 0x80); 554df0ac8a4SKevin Cernekee __sync(); 555df0ac8a4SKevin Cernekee return; 556fa010672SJon Fraser case CPU_BMIPS3300: 5576465460cSJonas Gorski case CPU_BMIPS4380: 558df0ac8a4SKevin Cernekee /* 559df0ac8a4SKevin Cernekee * 0x8000_0000: reset/NMI (initially in kseg1) 560df0ac8a4SKevin Cernekee * 0x8000_0400: normal vectors 561df0ac8a4SKevin Cernekee */ 562df0ac8a4SKevin Cernekee new_ebase = 0x80000400; 563fc455787SKevin Cernekee bmips_set_reset_vec(0, RESET_FROM_KSEG0); 5646465460cSJonas Gorski break; 5656465460cSJonas Gorski case CPU_BMIPS5000: 566df0ac8a4SKevin Cernekee /* 567df0ac8a4SKevin Cernekee * 0x8000_0000: reset/NMI (initially in kseg1) 568df0ac8a4SKevin Cernekee * 0x8000_1000: normal vectors 569df0ac8a4SKevin Cernekee */ 570df0ac8a4SKevin Cernekee new_ebase = 0x80001000; 571fc455787SKevin Cernekee bmips_set_reset_vec(0, RESET_FROM_KSEG0); 572df0ac8a4SKevin Cernekee write_c0_ebase(new_ebase); 5736465460cSJonas Gorski break; 5746465460cSJonas Gorski default: 575df0ac8a4SKevin Cernekee return; 5766465460cSJonas Gorski } 5776465460cSJonas Gorski 578df0ac8a4SKevin Cernekee board_nmi_handler_setup = &bmips_nmi_handler_setup; 579df0ac8a4SKevin Cernekee ebase = new_ebase; 580df0ac8a4SKevin Cernekee } 581df0ac8a4SKevin Cernekee 582df0ac8a4SKevin Cernekee asmlinkage void __weak plat_wired_tlb_setup(void) 583df0ac8a4SKevin Cernekee { 584df0ac8a4SKevin Cernekee /* 585df0ac8a4SKevin Cernekee * Called when starting/restarting a secondary CPU. 586df0ac8a4SKevin Cernekee * Kernel stacks and other important data might only be accessible 587df0ac8a4SKevin Cernekee * once the wired entries are present. 588df0ac8a4SKevin Cernekee */ 589df0ac8a4SKevin Cernekee } 590738a3f79SFlorian Fainelli 591627f4a2bSJaedon Shin void bmips_cpu_setup(void) 592738a3f79SFlorian Fainelli { 593738a3f79SFlorian Fainelli void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); 594738a3f79SFlorian Fainelli u32 __maybe_unused cfg; 595738a3f79SFlorian Fainelli 596738a3f79SFlorian Fainelli switch (current_cpu_type()) { 597738a3f79SFlorian Fainelli case CPU_BMIPS3300: 598738a3f79SFlorian Fainelli /* Set BIU to async mode */ 599738a3f79SFlorian Fainelli set_c0_brcm_bus_pll(BIT(22)); 600738a3f79SFlorian Fainelli __sync(); 601738a3f79SFlorian Fainelli 602738a3f79SFlorian Fainelli /* put the BIU back in sync mode */ 603738a3f79SFlorian Fainelli clear_c0_brcm_bus_pll(BIT(22)); 604738a3f79SFlorian Fainelli 605738a3f79SFlorian Fainelli /* clear BHTD to enable branch history table */ 606738a3f79SFlorian Fainelli clear_c0_brcm_reset(BIT(16)); 607738a3f79SFlorian Fainelli 608738a3f79SFlorian Fainelli /* Flush and enable RAC */ 609738a3f79SFlorian Fainelli cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); 610ea4b3afeSJaedon Shin __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); 611738a3f79SFlorian Fainelli __raw_readl(cbr + BMIPS_RAC_CONFIG); 612738a3f79SFlorian Fainelli 613738a3f79SFlorian Fainelli cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); 614ea4b3afeSJaedon Shin __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG); 615738a3f79SFlorian Fainelli __raw_readl(cbr + BMIPS_RAC_CONFIG); 616738a3f79SFlorian Fainelli 617738a3f79SFlorian Fainelli cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); 618738a3f79SFlorian Fainelli __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE); 619738a3f79SFlorian Fainelli __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); 620738a3f79SFlorian Fainelli break; 621738a3f79SFlorian Fainelli 622738a3f79SFlorian Fainelli case CPU_BMIPS4380: 623738a3f79SFlorian Fainelli /* CBG workaround for early BMIPS4380 CPUs */ 624738a3f79SFlorian Fainelli switch (read_c0_prid()) { 625738a3f79SFlorian Fainelli case 0x2a040: 626738a3f79SFlorian Fainelli case 0x2a042: 627738a3f79SFlorian Fainelli case 0x2a044: 628738a3f79SFlorian Fainelli case 0x2a060: 629738a3f79SFlorian Fainelli cfg = __raw_readl(cbr + BMIPS_L2_CONFIG); 630738a3f79SFlorian Fainelli __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG); 631738a3f79SFlorian Fainelli __raw_readl(cbr + BMIPS_L2_CONFIG); 632738a3f79SFlorian Fainelli } 633738a3f79SFlorian Fainelli 634738a3f79SFlorian Fainelli /* clear BHTD to enable branch history table */ 635738a3f79SFlorian Fainelli clear_c0_brcm_config_0(BIT(21)); 636738a3f79SFlorian Fainelli 637738a3f79SFlorian Fainelli /* XI/ROTR enable */ 638738a3f79SFlorian Fainelli set_c0_brcm_config_0(BIT(23)); 639738a3f79SFlorian Fainelli set_c0_brcm_cmt_ctrl(BIT(15)); 640738a3f79SFlorian Fainelli break; 641738a3f79SFlorian Fainelli 642738a3f79SFlorian Fainelli case CPU_BMIPS5000: 643738a3f79SFlorian Fainelli /* enable RDHWR, BRDHWR */ 644738a3f79SFlorian Fainelli set_c0_brcm_config(BIT(17) | BIT(21)); 645738a3f79SFlorian Fainelli 646738a3f79SFlorian Fainelli /* Disable JTB */ 647738a3f79SFlorian Fainelli __asm__ __volatile__( 648738a3f79SFlorian Fainelli " .set noreorder\n" 649738a3f79SFlorian Fainelli " li $8, 0x5a455048\n" 650738a3f79SFlorian Fainelli " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */ 651738a3f79SFlorian Fainelli " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */ 652738a3f79SFlorian Fainelli " li $9, 0x00008000\n" 653738a3f79SFlorian Fainelli " or $8, $8, $9\n" 654738a3f79SFlorian Fainelli " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */ 655738a3f79SFlorian Fainelli " sync\n" 656738a3f79SFlorian Fainelli " li $8, 0x0\n" 657738a3f79SFlorian Fainelli " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */ 658738a3f79SFlorian Fainelli " .set reorder\n" 659738a3f79SFlorian Fainelli : : : "$8", "$9"); 660738a3f79SFlorian Fainelli 661738a3f79SFlorian Fainelli /* XI enable */ 662738a3f79SFlorian Fainelli set_c0_brcm_config(BIT(27)); 663738a3f79SFlorian Fainelli 664738a3f79SFlorian Fainelli /* enable MIPS32R2 ROR instruction for XI TLB handlers */ 665738a3f79SFlorian Fainelli __asm__ __volatile__( 666738a3f79SFlorian Fainelli " li $8, 0x5a455048\n" 667738a3f79SFlorian Fainelli " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */ 668738a3f79SFlorian Fainelli " nop; nop; nop\n" 669738a3f79SFlorian Fainelli " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */ 670738a3f79SFlorian Fainelli " lui $9, 0x0100\n" 671738a3f79SFlorian Fainelli " or $8, $9\n" 672738a3f79SFlorian Fainelli " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */ 673738a3f79SFlorian Fainelli : : : "$8", "$9"); 674738a3f79SFlorian Fainelli break; 675738a3f79SFlorian Fainelli } 676738a3f79SFlorian Fainelli } 677