1df0ac8a4SKevin Cernekee /* 2df0ac8a4SKevin Cernekee * This file is subject to the terms and conditions of the GNU General Public 3df0ac8a4SKevin Cernekee * License. See the file "COPYING" in the main directory of this archive 4df0ac8a4SKevin Cernekee * for more details. 5df0ac8a4SKevin Cernekee * 6df0ac8a4SKevin Cernekee * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) 7df0ac8a4SKevin Cernekee * 8df0ac8a4SKevin Cernekee * SMP support for BMIPS 9df0ac8a4SKevin Cernekee */ 10df0ac8a4SKevin Cernekee 11df0ac8a4SKevin Cernekee #include <linux/init.h> 12df0ac8a4SKevin Cernekee #include <linux/sched.h> 13df0ac8a4SKevin Cernekee #include <linux/mm.h> 14df0ac8a4SKevin Cernekee #include <linux/delay.h> 15df0ac8a4SKevin Cernekee #include <linux/smp.h> 16df0ac8a4SKevin Cernekee #include <linux/interrupt.h> 17df0ac8a4SKevin Cernekee #include <linux/spinlock.h> 18df0ac8a4SKevin Cernekee #include <linux/cpu.h> 19df0ac8a4SKevin Cernekee #include <linux/cpumask.h> 20df0ac8a4SKevin Cernekee #include <linux/reboot.h> 21df0ac8a4SKevin Cernekee #include <linux/io.h> 22df0ac8a4SKevin Cernekee #include <linux/compiler.h> 23df0ac8a4SKevin Cernekee #include <linux/linkage.h> 24df0ac8a4SKevin Cernekee #include <linux/bug.h> 25df0ac8a4SKevin Cernekee #include <linux/kernel.h> 26df0ac8a4SKevin Cernekee 27df0ac8a4SKevin Cernekee #include <asm/time.h> 28df0ac8a4SKevin Cernekee #include <asm/pgtable.h> 29df0ac8a4SKevin Cernekee #include <asm/processor.h> 30df0ac8a4SKevin Cernekee #include <asm/bootinfo.h> 31df0ac8a4SKevin Cernekee #include <asm/pmon.h> 32df0ac8a4SKevin Cernekee #include <asm/cacheflush.h> 33df0ac8a4SKevin Cernekee #include <asm/tlbflush.h> 34df0ac8a4SKevin Cernekee #include <asm/mipsregs.h> 35df0ac8a4SKevin Cernekee #include <asm/bmips.h> 36df0ac8a4SKevin Cernekee #include <asm/traps.h> 37df0ac8a4SKevin Cernekee #include <asm/barrier.h> 38df0ac8a4SKevin Cernekee 39df0ac8a4SKevin Cernekee static int __maybe_unused max_cpus = 1; 40df0ac8a4SKevin Cernekee 41df0ac8a4SKevin Cernekee /* these may be configured by the platform code */ 42df0ac8a4SKevin Cernekee int bmips_smp_enabled = 1; 43df0ac8a4SKevin Cernekee int bmips_cpu_offset; 44df0ac8a4SKevin Cernekee cpumask_t bmips_booted_mask; 45df0ac8a4SKevin Cernekee 46df0ac8a4SKevin Cernekee #ifdef CONFIG_SMP 47df0ac8a4SKevin Cernekee 48df0ac8a4SKevin Cernekee /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */ 49df0ac8a4SKevin Cernekee unsigned long bmips_smp_boot_sp; 50df0ac8a4SKevin Cernekee unsigned long bmips_smp_boot_gp; 51df0ac8a4SKevin Cernekee 526465460cSJonas Gorski static void bmips43xx_send_ipi_single(int cpu, unsigned int action); 536465460cSJonas Gorski static void bmips5000_send_ipi_single(int cpu, unsigned int action); 546465460cSJonas Gorski static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id); 556465460cSJonas Gorski static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id); 56df0ac8a4SKevin Cernekee 57df0ac8a4SKevin Cernekee /* SW interrupts 0,1 are used for interprocessor signaling */ 58df0ac8a4SKevin Cernekee #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) 59df0ac8a4SKevin Cernekee #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1) 60df0ac8a4SKevin Cernekee 61df0ac8a4SKevin Cernekee #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) 62df0ac8a4SKevin Cernekee #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 63df0ac8a4SKevin Cernekee #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 64df0ac8a4SKevin Cernekee #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) 65df0ac8a4SKevin Cernekee 66df0ac8a4SKevin Cernekee static void __init bmips_smp_setup(void) 67df0ac8a4SKevin Cernekee { 684df715aaSFlorian Fainelli int i, cpu = 1, boot_cpu = 0; 69fcfa66deSFlorian Fainelli int cpu_hw_intr; 70fcfa66deSFlorian Fainelli 716465460cSJonas Gorski switch (current_cpu_type()) { 726465460cSJonas Gorski case CPU_BMIPS4350: 736465460cSJonas Gorski case CPU_BMIPS4380: 74df0ac8a4SKevin Cernekee /* arbitration priority */ 75df0ac8a4SKevin Cernekee clear_c0_brcm_cmt_ctrl(0x30); 76df0ac8a4SKevin Cernekee 77df0ac8a4SKevin Cernekee /* NBK and weak order flags */ 78df0ac8a4SKevin Cernekee set_c0_brcm_config_0(0x30000); 79df0ac8a4SKevin Cernekee 804df715aaSFlorian Fainelli /* Find out if we are running on TP0 or TP1 */ 814df715aaSFlorian Fainelli boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 824df715aaSFlorian Fainelli 83df0ac8a4SKevin Cernekee /* 846465460cSJonas Gorski * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other 856465460cSJonas Gorski * thread 86df0ac8a4SKevin Cernekee * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 87df0ac8a4SKevin Cernekee * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 88df0ac8a4SKevin Cernekee */ 89fcfa66deSFlorian Fainelli if (boot_cpu == 0) 90fcfa66deSFlorian Fainelli cpu_hw_intr = 0x02; 91fcfa66deSFlorian Fainelli else 92fcfa66deSFlorian Fainelli cpu_hw_intr = 0x1d; 93fcfa66deSFlorian Fainelli 946465460cSJonas Gorski change_c0_brcm_cmt_intr(0xf8018000, 956465460cSJonas Gorski (cpu_hw_intr << 27) | (0x03 << 15)); 96df0ac8a4SKevin Cernekee 97df0ac8a4SKevin Cernekee /* single core, 2 threads (2 pipelines) */ 98df0ac8a4SKevin Cernekee max_cpus = 2; 996465460cSJonas Gorski 1006465460cSJonas Gorski break; 1016465460cSJonas Gorski case CPU_BMIPS5000: 102df0ac8a4SKevin Cernekee /* enable raceless SW interrupts */ 103df0ac8a4SKevin Cernekee set_c0_brcm_config(0x03 << 22); 104df0ac8a4SKevin Cernekee 105df0ac8a4SKevin Cernekee /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ 106df0ac8a4SKevin Cernekee change_c0_brcm_mode(0x1f << 27, 0x02 << 27); 107df0ac8a4SKevin Cernekee 108df0ac8a4SKevin Cernekee /* N cores, 2 threads per core */ 109df0ac8a4SKevin Cernekee max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; 110df0ac8a4SKevin Cernekee 111df0ac8a4SKevin Cernekee /* clear any pending SW interrupts */ 112df0ac8a4SKevin Cernekee for (i = 0; i < max_cpus; i++) { 113df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); 114df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); 115df0ac8a4SKevin Cernekee } 1166465460cSJonas Gorski 1176465460cSJonas Gorski break; 1186465460cSJonas Gorski default: 1196465460cSJonas Gorski max_cpus = 1; 1206465460cSJonas Gorski } 121df0ac8a4SKevin Cernekee 122df0ac8a4SKevin Cernekee if (!bmips_smp_enabled) 123df0ac8a4SKevin Cernekee max_cpus = 1; 124df0ac8a4SKevin Cernekee 125df0ac8a4SKevin Cernekee /* this can be overridden by the BSP */ 126df0ac8a4SKevin Cernekee if (!board_ebase_setup) 127df0ac8a4SKevin Cernekee board_ebase_setup = &bmips_ebase_setup; 128df0ac8a4SKevin Cernekee 1294df715aaSFlorian Fainelli __cpu_number_map[boot_cpu] = 0; 1304df715aaSFlorian Fainelli __cpu_logical_map[0] = boot_cpu; 1314df715aaSFlorian Fainelli 132df0ac8a4SKevin Cernekee for (i = 0; i < max_cpus; i++) { 1334df715aaSFlorian Fainelli if (i != boot_cpu) { 1344df715aaSFlorian Fainelli __cpu_number_map[i] = cpu; 1354df715aaSFlorian Fainelli __cpu_logical_map[cpu] = i; 1364df715aaSFlorian Fainelli cpu++; 1374df715aaSFlorian Fainelli } 138df0ac8a4SKevin Cernekee set_cpu_possible(i, 1); 139df0ac8a4SKevin Cernekee set_cpu_present(i, 1); 140df0ac8a4SKevin Cernekee } 141df0ac8a4SKevin Cernekee } 142df0ac8a4SKevin Cernekee 143df0ac8a4SKevin Cernekee /* 144df0ac8a4SKevin Cernekee * IPI IRQ setup - runs on CPU0 145df0ac8a4SKevin Cernekee */ 146df0ac8a4SKevin Cernekee static void bmips_prepare_cpus(unsigned int max_cpus) 147df0ac8a4SKevin Cernekee { 1486465460cSJonas Gorski irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id); 1496465460cSJonas Gorski 1506465460cSJonas Gorski switch (current_cpu_type()) { 1516465460cSJonas Gorski case CPU_BMIPS4350: 1526465460cSJonas Gorski case CPU_BMIPS4380: 1536465460cSJonas Gorski bmips_ipi_interrupt = bmips43xx_ipi_interrupt; 1546465460cSJonas Gorski break; 1556465460cSJonas Gorski case CPU_BMIPS5000: 1566465460cSJonas Gorski bmips_ipi_interrupt = bmips5000_ipi_interrupt; 1576465460cSJonas Gorski break; 1586465460cSJonas Gorski default: 1596465460cSJonas Gorski return; 1606465460cSJonas Gorski } 1616465460cSJonas Gorski 162df0ac8a4SKevin Cernekee if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 163df0ac8a4SKevin Cernekee "smp_ipi0", NULL)) 164f7777dccSRalf Baechle panic("Can't request IPI0 interrupt"); 165df0ac8a4SKevin Cernekee if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 166df0ac8a4SKevin Cernekee "smp_ipi1", NULL)) 167f7777dccSRalf Baechle panic("Can't request IPI1 interrupt"); 168df0ac8a4SKevin Cernekee } 169df0ac8a4SKevin Cernekee 170df0ac8a4SKevin Cernekee /* 171df0ac8a4SKevin Cernekee * Tell the hardware to boot CPUx - runs on CPU0 172df0ac8a4SKevin Cernekee */ 173df0ac8a4SKevin Cernekee static void bmips_boot_secondary(int cpu, struct task_struct *idle) 174df0ac8a4SKevin Cernekee { 175df0ac8a4SKevin Cernekee bmips_smp_boot_sp = __KSTK_TOS(idle); 176df0ac8a4SKevin Cernekee bmips_smp_boot_gp = (unsigned long)task_thread_info(idle); 177df0ac8a4SKevin Cernekee mb(); 178df0ac8a4SKevin Cernekee 179df0ac8a4SKevin Cernekee /* 180df0ac8a4SKevin Cernekee * Initial boot sequence for secondary CPU: 181df0ac8a4SKevin Cernekee * bmips_reset_nmi_vec @ a000_0000 -> 182df0ac8a4SKevin Cernekee * bmips_smp_entry -> 183df0ac8a4SKevin Cernekee * plat_wired_tlb_setup (cached function call; optional) -> 184df0ac8a4SKevin Cernekee * start_secondary (cached jump) 185df0ac8a4SKevin Cernekee * 186df0ac8a4SKevin Cernekee * Warm restart sequence: 187df0ac8a4SKevin Cernekee * play_dead WAIT loop -> 188df0ac8a4SKevin Cernekee * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC -> 189df0ac8a4SKevin Cernekee * eret to play_dead -> 190df0ac8a4SKevin Cernekee * bmips_secondary_reentry -> 191df0ac8a4SKevin Cernekee * start_secondary 192df0ac8a4SKevin Cernekee */ 193df0ac8a4SKevin Cernekee 194df0ac8a4SKevin Cernekee pr_info("SMP: Booting CPU%d...\n", cpu); 195df0ac8a4SKevin Cernekee 1966465460cSJonas Gorski if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { 1976465460cSJonas Gorski switch (current_cpu_type()) { 1986465460cSJonas Gorski case CPU_BMIPS4350: 1996465460cSJonas Gorski case CPU_BMIPS4380: 2006465460cSJonas Gorski bmips43xx_send_ipi_single(cpu, 0); 2016465460cSJonas Gorski break; 2026465460cSJonas Gorski case CPU_BMIPS5000: 2036465460cSJonas Gorski bmips5000_send_ipi_single(cpu, 0); 2046465460cSJonas Gorski break; 2056465460cSJonas Gorski } 2066465460cSJonas Gorski } 207df0ac8a4SKevin Cernekee else { 2086465460cSJonas Gorski switch (current_cpu_type()) { 2096465460cSJonas Gorski case CPU_BMIPS4350: 2106465460cSJonas Gorski case CPU_BMIPS4380: 2114df715aaSFlorian Fainelli /* Reset slave TP1 if booting from TP0 */ 212976f39b1SFlorian Fainelli if (cpu_logical_map(cpu) == 1) 213df0ac8a4SKevin Cernekee set_c0_brcm_cmt_ctrl(0x01); 2146465460cSJonas Gorski break; 2156465460cSJonas Gorski case CPU_BMIPS5000: 216df0ac8a4SKevin Cernekee if (cpu & 0x01) 217df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); 218df0ac8a4SKevin Cernekee else { 219df0ac8a4SKevin Cernekee /* 220df0ac8a4SKevin Cernekee * core N thread 0 was already booted; just 221df0ac8a4SKevin Cernekee * pulse the NMI line 222df0ac8a4SKevin Cernekee */ 223df0ac8a4SKevin Cernekee bmips_write_zscm_reg(0x210, 0xc0000000); 224df0ac8a4SKevin Cernekee udelay(10); 225df0ac8a4SKevin Cernekee bmips_write_zscm_reg(0x210, 0x00); 226df0ac8a4SKevin Cernekee } 2276465460cSJonas Gorski break; 2286465460cSJonas Gorski } 229df0ac8a4SKevin Cernekee cpumask_set_cpu(cpu, &bmips_booted_mask); 230df0ac8a4SKevin Cernekee } 231df0ac8a4SKevin Cernekee } 232df0ac8a4SKevin Cernekee 233df0ac8a4SKevin Cernekee /* 234df0ac8a4SKevin Cernekee * Early setup - runs on secondary CPU after cache probe 235df0ac8a4SKevin Cernekee */ 236df0ac8a4SKevin Cernekee static void bmips_init_secondary(void) 237df0ac8a4SKevin Cernekee { 238df0ac8a4SKevin Cernekee /* move NMI vector to kseg0, in case XKS01 is enabled */ 239df0ac8a4SKevin Cernekee 2406465460cSJonas Gorski void __iomem *cbr; 241df0ac8a4SKevin Cernekee unsigned long old_vec; 242ff5fadafSFlorian Fainelli unsigned long relo_vector; 243ff5fadafSFlorian Fainelli int boot_cpu; 244df0ac8a4SKevin Cernekee 2456465460cSJonas Gorski switch (current_cpu_type()) { 2466465460cSJonas Gorski case CPU_BMIPS4350: 2476465460cSJonas Gorski case CPU_BMIPS4380: 2486465460cSJonas Gorski cbr = BMIPS_GET_CBR(); 2496465460cSJonas Gorski 250ff5fadafSFlorian Fainelli boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 251ff5fadafSFlorian Fainelli relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 : 252ff5fadafSFlorian Fainelli BMIPS_RELO_VECTOR_CONTROL_1; 253ff5fadafSFlorian Fainelli 254ff5fadafSFlorian Fainelli old_vec = __raw_readl(cbr + relo_vector); 255ff5fadafSFlorian Fainelli __raw_writel(old_vec & ~0x20000000, cbr + relo_vector); 256df0ac8a4SKevin Cernekee 257df0ac8a4SKevin Cernekee clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); 2586465460cSJonas Gorski break; 2596465460cSJonas Gorski case CPU_BMIPS5000: 260df0ac8a4SKevin Cernekee write_c0_brcm_bootvec(read_c0_brcm_bootvec() & 261df0ac8a4SKevin Cernekee (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000)); 262df0ac8a4SKevin Cernekee 263df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); 2646465460cSJonas Gorski break; 2656465460cSJonas Gorski } 266df0ac8a4SKevin Cernekee } 267df0ac8a4SKevin Cernekee 268df0ac8a4SKevin Cernekee /* 269df0ac8a4SKevin Cernekee * Late setup - runs on secondary CPU before entering the idle loop 270df0ac8a4SKevin Cernekee */ 271df0ac8a4SKevin Cernekee static void bmips_smp_finish(void) 272df0ac8a4SKevin Cernekee { 273df0ac8a4SKevin Cernekee pr_info("SMP: CPU%d is running\n", smp_processor_id()); 274856ac3c6SYong Zhang 275856ac3c6SYong Zhang /* make sure there won't be a timer interrupt for a little while */ 276856ac3c6SYong Zhang write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 277856ac3c6SYong Zhang 278856ac3c6SYong Zhang irq_enable_hazard(); 279856ac3c6SYong Zhang set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE); 280856ac3c6SYong Zhang irq_enable_hazard(); 281df0ac8a4SKevin Cernekee } 282df0ac8a4SKevin Cernekee 283df0ac8a4SKevin Cernekee /* 284df0ac8a4SKevin Cernekee * Runs on CPU0 after all CPUs have been booted 285df0ac8a4SKevin Cernekee */ 286df0ac8a4SKevin Cernekee static void bmips_cpus_done(void) 287df0ac8a4SKevin Cernekee { 288df0ac8a4SKevin Cernekee } 289df0ac8a4SKevin Cernekee 290df0ac8a4SKevin Cernekee /* 291df0ac8a4SKevin Cernekee * BMIPS5000 raceless IPIs 292df0ac8a4SKevin Cernekee * 293df0ac8a4SKevin Cernekee * Each CPU has two inbound SW IRQs which are independent of all other CPUs. 294df0ac8a4SKevin Cernekee * IPI0 is used for SMP_RESCHEDULE_YOURSELF 295df0ac8a4SKevin Cernekee * IPI1 is used for SMP_CALL_FUNCTION 296df0ac8a4SKevin Cernekee */ 297df0ac8a4SKevin Cernekee 2986465460cSJonas Gorski static void bmips5000_send_ipi_single(int cpu, unsigned int action) 299df0ac8a4SKevin Cernekee { 300df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); 301df0ac8a4SKevin Cernekee } 302df0ac8a4SKevin Cernekee 3036465460cSJonas Gorski static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) 304df0ac8a4SKevin Cernekee { 305df0ac8a4SKevin Cernekee int action = irq - IPI0_IRQ; 306df0ac8a4SKevin Cernekee 307df0ac8a4SKevin Cernekee write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action)); 308df0ac8a4SKevin Cernekee 309df0ac8a4SKevin Cernekee if (action == 0) 310df0ac8a4SKevin Cernekee scheduler_ipi(); 311df0ac8a4SKevin Cernekee else 312df0ac8a4SKevin Cernekee smp_call_function_interrupt(); 313df0ac8a4SKevin Cernekee 314df0ac8a4SKevin Cernekee return IRQ_HANDLED; 315df0ac8a4SKevin Cernekee } 316df0ac8a4SKevin Cernekee 3176465460cSJonas Gorski static void bmips5000_send_ipi_mask(const struct cpumask *mask, 3186465460cSJonas Gorski unsigned int action) 3196465460cSJonas Gorski { 3206465460cSJonas Gorski unsigned int i; 3216465460cSJonas Gorski 3226465460cSJonas Gorski for_each_cpu(i, mask) 3236465460cSJonas Gorski bmips5000_send_ipi_single(i, action); 3246465460cSJonas Gorski } 325df0ac8a4SKevin Cernekee 326df0ac8a4SKevin Cernekee /* 327df0ac8a4SKevin Cernekee * BMIPS43xx racey IPIs 328df0ac8a4SKevin Cernekee * 329df0ac8a4SKevin Cernekee * We use one inbound SW IRQ for each CPU. 330df0ac8a4SKevin Cernekee * 331df0ac8a4SKevin Cernekee * A spinlock must be held in order to keep CPUx from accidentally clearing 332df0ac8a4SKevin Cernekee * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The 333df0ac8a4SKevin Cernekee * same spinlock is used to protect the action masks. 334df0ac8a4SKevin Cernekee */ 335df0ac8a4SKevin Cernekee 336df0ac8a4SKevin Cernekee static DEFINE_SPINLOCK(ipi_lock); 337df0ac8a4SKevin Cernekee static DEFINE_PER_CPU(int, ipi_action_mask); 338df0ac8a4SKevin Cernekee 3396465460cSJonas Gorski static void bmips43xx_send_ipi_single(int cpu, unsigned int action) 340df0ac8a4SKevin Cernekee { 341df0ac8a4SKevin Cernekee unsigned long flags; 342df0ac8a4SKevin Cernekee 343df0ac8a4SKevin Cernekee spin_lock_irqsave(&ipi_lock, flags); 344df0ac8a4SKevin Cernekee set_c0_cause(cpu ? C_SW1 : C_SW0); 345df0ac8a4SKevin Cernekee per_cpu(ipi_action_mask, cpu) |= action; 346df0ac8a4SKevin Cernekee irq_enable_hazard(); 347df0ac8a4SKevin Cernekee spin_unlock_irqrestore(&ipi_lock, flags); 348df0ac8a4SKevin Cernekee } 349df0ac8a4SKevin Cernekee 3506465460cSJonas Gorski static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) 351df0ac8a4SKevin Cernekee { 352df0ac8a4SKevin Cernekee unsigned long flags; 353df0ac8a4SKevin Cernekee int action, cpu = irq - IPI0_IRQ; 354df0ac8a4SKevin Cernekee 355df0ac8a4SKevin Cernekee spin_lock_irqsave(&ipi_lock, flags); 356df0ac8a4SKevin Cernekee action = __get_cpu_var(ipi_action_mask); 357df0ac8a4SKevin Cernekee per_cpu(ipi_action_mask, cpu) = 0; 358df0ac8a4SKevin Cernekee clear_c0_cause(cpu ? C_SW1 : C_SW0); 359df0ac8a4SKevin Cernekee spin_unlock_irqrestore(&ipi_lock, flags); 360df0ac8a4SKevin Cernekee 361df0ac8a4SKevin Cernekee if (action & SMP_RESCHEDULE_YOURSELF) 362df0ac8a4SKevin Cernekee scheduler_ipi(); 363df0ac8a4SKevin Cernekee if (action & SMP_CALL_FUNCTION) 364df0ac8a4SKevin Cernekee smp_call_function_interrupt(); 365df0ac8a4SKevin Cernekee 366df0ac8a4SKevin Cernekee return IRQ_HANDLED; 367df0ac8a4SKevin Cernekee } 368df0ac8a4SKevin Cernekee 3696465460cSJonas Gorski static void bmips43xx_send_ipi_mask(const struct cpumask *mask, 370df0ac8a4SKevin Cernekee unsigned int action) 371df0ac8a4SKevin Cernekee { 372df0ac8a4SKevin Cernekee unsigned int i; 373df0ac8a4SKevin Cernekee 374df0ac8a4SKevin Cernekee for_each_cpu(i, mask) 3756465460cSJonas Gorski bmips43xx_send_ipi_single(i, action); 376df0ac8a4SKevin Cernekee } 377df0ac8a4SKevin Cernekee 378df0ac8a4SKevin Cernekee #ifdef CONFIG_HOTPLUG_CPU 379df0ac8a4SKevin Cernekee 380df0ac8a4SKevin Cernekee static int bmips_cpu_disable(void) 381df0ac8a4SKevin Cernekee { 382df0ac8a4SKevin Cernekee unsigned int cpu = smp_processor_id(); 383df0ac8a4SKevin Cernekee 384df0ac8a4SKevin Cernekee if (cpu == 0) 385df0ac8a4SKevin Cernekee return -EBUSY; 386df0ac8a4SKevin Cernekee 387df0ac8a4SKevin Cernekee pr_info("SMP: CPU%d is offline\n", cpu); 388df0ac8a4SKevin Cernekee 3890b5f9c00SRusty Russell set_cpu_online(cpu, false); 390df0ac8a4SKevin Cernekee cpu_clear(cpu, cpu_callin_map); 391df0ac8a4SKevin Cernekee 392df0ac8a4SKevin Cernekee local_flush_tlb_all(); 393df0ac8a4SKevin Cernekee local_flush_icache_range(0, ~0); 394df0ac8a4SKevin Cernekee 395df0ac8a4SKevin Cernekee return 0; 396df0ac8a4SKevin Cernekee } 397df0ac8a4SKevin Cernekee 398df0ac8a4SKevin Cernekee static void bmips_cpu_die(unsigned int cpu) 399df0ac8a4SKevin Cernekee { 400df0ac8a4SKevin Cernekee } 401df0ac8a4SKevin Cernekee 402df0ac8a4SKevin Cernekee void __ref play_dead(void) 403df0ac8a4SKevin Cernekee { 404df0ac8a4SKevin Cernekee idle_task_exit(); 405df0ac8a4SKevin Cernekee 406df0ac8a4SKevin Cernekee /* flush data cache */ 407df0ac8a4SKevin Cernekee _dma_cache_wback_inv(0, ~0); 408df0ac8a4SKevin Cernekee 409df0ac8a4SKevin Cernekee /* 410df0ac8a4SKevin Cernekee * Wakeup is on SW0 or SW1; disable everything else 411df0ac8a4SKevin Cernekee * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux 412df0ac8a4SKevin Cernekee * IRQ handlers; this clears ST0_IE and returns immediately. 413df0ac8a4SKevin Cernekee */ 414df0ac8a4SKevin Cernekee clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1); 415df0ac8a4SKevin Cernekee change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV, 416df0ac8a4SKevin Cernekee IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV); 417df0ac8a4SKevin Cernekee irq_disable_hazard(); 418df0ac8a4SKevin Cernekee 419df0ac8a4SKevin Cernekee /* 420df0ac8a4SKevin Cernekee * wait for SW interrupt from bmips_boot_secondary(), then jump 421df0ac8a4SKevin Cernekee * back to start_secondary() 422df0ac8a4SKevin Cernekee */ 423df0ac8a4SKevin Cernekee __asm__ __volatile__( 424df0ac8a4SKevin Cernekee " wait\n" 425df0ac8a4SKevin Cernekee " j bmips_secondary_reentry\n" 426df0ac8a4SKevin Cernekee : : : "memory"); 427df0ac8a4SKevin Cernekee } 428df0ac8a4SKevin Cernekee 429df0ac8a4SKevin Cernekee #endif /* CONFIG_HOTPLUG_CPU */ 430df0ac8a4SKevin Cernekee 4316465460cSJonas Gorski struct plat_smp_ops bmips43xx_smp_ops = { 432df0ac8a4SKevin Cernekee .smp_setup = bmips_smp_setup, 433df0ac8a4SKevin Cernekee .prepare_cpus = bmips_prepare_cpus, 434df0ac8a4SKevin Cernekee .boot_secondary = bmips_boot_secondary, 435df0ac8a4SKevin Cernekee .smp_finish = bmips_smp_finish, 436df0ac8a4SKevin Cernekee .init_secondary = bmips_init_secondary, 437df0ac8a4SKevin Cernekee .cpus_done = bmips_cpus_done, 4386465460cSJonas Gorski .send_ipi_single = bmips43xx_send_ipi_single, 4396465460cSJonas Gorski .send_ipi_mask = bmips43xx_send_ipi_mask, 4406465460cSJonas Gorski #ifdef CONFIG_HOTPLUG_CPU 4416465460cSJonas Gorski .cpu_disable = bmips_cpu_disable, 4426465460cSJonas Gorski .cpu_die = bmips_cpu_die, 4436465460cSJonas Gorski #endif 4446465460cSJonas Gorski }; 4456465460cSJonas Gorski 4466465460cSJonas Gorski struct plat_smp_ops bmips5000_smp_ops = { 4476465460cSJonas Gorski .smp_setup = bmips_smp_setup, 4486465460cSJonas Gorski .prepare_cpus = bmips_prepare_cpus, 4496465460cSJonas Gorski .boot_secondary = bmips_boot_secondary, 4506465460cSJonas Gorski .smp_finish = bmips_smp_finish, 4516465460cSJonas Gorski .init_secondary = bmips_init_secondary, 4526465460cSJonas Gorski .cpus_done = bmips_cpus_done, 4536465460cSJonas Gorski .send_ipi_single = bmips5000_send_ipi_single, 4546465460cSJonas Gorski .send_ipi_mask = bmips5000_send_ipi_mask, 455df0ac8a4SKevin Cernekee #ifdef CONFIG_HOTPLUG_CPU 456df0ac8a4SKevin Cernekee .cpu_disable = bmips_cpu_disable, 457df0ac8a4SKevin Cernekee .cpu_die = bmips_cpu_die, 458df0ac8a4SKevin Cernekee #endif 459df0ac8a4SKevin Cernekee }; 460df0ac8a4SKevin Cernekee 461df0ac8a4SKevin Cernekee #endif /* CONFIG_SMP */ 462df0ac8a4SKevin Cernekee 463df0ac8a4SKevin Cernekee /*********************************************************************** 464df0ac8a4SKevin Cernekee * BMIPS vector relocation 465df0ac8a4SKevin Cernekee * This is primarily used for SMP boot, but it is applicable to some 466df0ac8a4SKevin Cernekee * UP BMIPS systems as well. 467df0ac8a4SKevin Cernekee ***********************************************************************/ 468df0ac8a4SKevin Cernekee 469078a55fcSPaul Gortmaker static void bmips_wr_vec(unsigned long dst, char *start, char *end) 470df0ac8a4SKevin Cernekee { 471df0ac8a4SKevin Cernekee memcpy((void *)dst, start, end - start); 472df0ac8a4SKevin Cernekee dma_cache_wback((unsigned long)start, end - start); 473df0ac8a4SKevin Cernekee local_flush_icache_range(dst, dst + (end - start)); 474df0ac8a4SKevin Cernekee instruction_hazard(); 475df0ac8a4SKevin Cernekee } 476df0ac8a4SKevin Cernekee 477078a55fcSPaul Gortmaker static inline void bmips_nmi_handler_setup(void) 478df0ac8a4SKevin Cernekee { 479df0ac8a4SKevin Cernekee bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec, 480df0ac8a4SKevin Cernekee &bmips_reset_nmi_vec_end); 481df0ac8a4SKevin Cernekee bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec, 482df0ac8a4SKevin Cernekee &bmips_smp_int_vec_end); 483df0ac8a4SKevin Cernekee } 484df0ac8a4SKevin Cernekee 485078a55fcSPaul Gortmaker void bmips_ebase_setup(void) 486df0ac8a4SKevin Cernekee { 487df0ac8a4SKevin Cernekee unsigned long new_ebase = ebase; 488df0ac8a4SKevin Cernekee void __iomem __maybe_unused *cbr; 489df0ac8a4SKevin Cernekee 490df0ac8a4SKevin Cernekee BUG_ON(ebase != CKSEG0); 491df0ac8a4SKevin Cernekee 4926465460cSJonas Gorski switch (current_cpu_type()) { 4936465460cSJonas Gorski case CPU_BMIPS4350: 494df0ac8a4SKevin Cernekee /* 495df0ac8a4SKevin Cernekee * BMIPS4350 cannot relocate the normal vectors, but it 496df0ac8a4SKevin Cernekee * can relocate the BEV=1 vectors. So CPU1 starts up at 497df0ac8a4SKevin Cernekee * the relocated BEV=1, IV=0 general exception vector @ 498df0ac8a4SKevin Cernekee * 0xa000_0380. 499df0ac8a4SKevin Cernekee * 500df0ac8a4SKevin Cernekee * set_uncached_handler() is used here because: 501df0ac8a4SKevin Cernekee * - CPU1 will run this from uncached space 502df0ac8a4SKevin Cernekee * - None of the cacheflush functions are set up yet 503df0ac8a4SKevin Cernekee */ 504df0ac8a4SKevin Cernekee set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, 505df0ac8a4SKevin Cernekee &bmips_smp_int_vec, 0x80); 506df0ac8a4SKevin Cernekee __sync(); 507df0ac8a4SKevin Cernekee return; 5086465460cSJonas Gorski case CPU_BMIPS4380: 509df0ac8a4SKevin Cernekee /* 510df0ac8a4SKevin Cernekee * 0x8000_0000: reset/NMI (initially in kseg1) 511df0ac8a4SKevin Cernekee * 0x8000_0400: normal vectors 512df0ac8a4SKevin Cernekee */ 513df0ac8a4SKevin Cernekee new_ebase = 0x80000400; 514df0ac8a4SKevin Cernekee cbr = BMIPS_GET_CBR(); 515df0ac8a4SKevin Cernekee __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0); 516df0ac8a4SKevin Cernekee __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1); 5176465460cSJonas Gorski break; 5186465460cSJonas Gorski case CPU_BMIPS5000: 519df0ac8a4SKevin Cernekee /* 520df0ac8a4SKevin Cernekee * 0x8000_0000: reset/NMI (initially in kseg1) 521df0ac8a4SKevin Cernekee * 0x8000_1000: normal vectors 522df0ac8a4SKevin Cernekee */ 523df0ac8a4SKevin Cernekee new_ebase = 0x80001000; 524df0ac8a4SKevin Cernekee write_c0_brcm_bootvec(0xa0088008); 525df0ac8a4SKevin Cernekee write_c0_ebase(new_ebase); 526df0ac8a4SKevin Cernekee if (max_cpus > 2) 527df0ac8a4SKevin Cernekee bmips_write_zscm_reg(0xa0, 0xa008a008); 5286465460cSJonas Gorski break; 5296465460cSJonas Gorski default: 530df0ac8a4SKevin Cernekee return; 5316465460cSJonas Gorski } 5326465460cSJonas Gorski 533df0ac8a4SKevin Cernekee board_nmi_handler_setup = &bmips_nmi_handler_setup; 534df0ac8a4SKevin Cernekee ebase = new_ebase; 535df0ac8a4SKevin Cernekee } 536df0ac8a4SKevin Cernekee 537df0ac8a4SKevin Cernekee asmlinkage void __weak plat_wired_tlb_setup(void) 538df0ac8a4SKevin Cernekee { 539df0ac8a4SKevin Cernekee /* 540df0ac8a4SKevin Cernekee * Called when starting/restarting a secondary CPU. 541df0ac8a4SKevin Cernekee * Kernel stacks and other important data might only be accessible 542df0ac8a4SKevin Cernekee * once the wired entries are present. 543df0ac8a4SKevin Cernekee */ 544df0ac8a4SKevin Cernekee } 545