1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle 7 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Copyright (C) 2000 MIPS Technologies, Inc. 11 * written by Carsten Langgaard, carstenl@mips.com 12 */ 13#include <asm/asm.h> 14#include <asm/cachectl.h> 15#include <asm/fpregdef.h> 16#include <asm/mipsregs.h> 17#include <asm/asm-offsets.h> 18#include <asm/pgtable-bits.h> 19#include <asm/regdef.h> 20#include <asm/stackframe.h> 21#include <asm/thread_info.h> 22 23#include <asm/asmmacro.h> 24 25/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ 26#undef fp 27 28/* 29 * Offset to the current process status flags, the first 32 bytes of the 30 * stack are not used. 31 */ 32#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS) 33 34#ifndef USE_ALTERNATE_RESUME_IMPL 35/* 36 * task_struct *resume(task_struct *prev, task_struct *next, 37 * struct thread_info *next_ti, s32 fp_save) 38 */ 39 .align 5 40 LEAF(resume) 41 mfc0 t1, CP0_STATUS 42 LONG_S t1, THREAD_STATUS(a0) 43 cpu_save_nonscratch a0 44 LONG_S ra, THREAD_REG31(a0) 45 46 /* 47 * Check whether we need to save any FP context. FP context is saved 48 * iff the process has used the context with the scalar FPU or the MSA 49 * ASE in the current time slice, as indicated by _TIF_USEDFPU and 50 * _TIF_USEDMSA respectively. switch_to will have set fp_save 51 * accordingly to an FP_SAVE_ enum value. 52 */ 53 beqz a3, 2f 54 55 /* 56 * We do. Clear the saved CU1 bit for prev, such that next time it is 57 * scheduled it will start in userland with the FPU disabled. If the 58 * task uses the FPU then it will be enabled again via the do_cpu trap. 59 * This allows us to lazily restore the FP context. 60 */ 61 PTR_L t3, TASK_THREAD_INFO(a0) 62 LONG_L t0, ST_OFF(t3) 63 li t1, ~ST0_CU1 64 and t0, t0, t1 65 LONG_S t0, ST_OFF(t3) 66 67 /* Check whether we're saving scalar or vector context. */ 68 bgtz a3, 1f 69 70 /* Save 128b MSA vector context + scalar FP control & status. */ 71 .set push 72 SET_HARDFLOAT 73 cfc1 t1, fcr31 74 msa_save_all a0 75 .set pop /* SET_HARDFLOAT */ 76 77 sw t1, THREAD_FCR31(a0) 78 b 2f 79 801: /* Save 32b/64b scalar FP context. */ 81 fpu_save_double a0 t0 t1 # c0_status passed in t0 82 # clobbers t1 832: 84 85#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 86 PTR_LA t8, __stack_chk_guard 87 LONG_L t9, TASK_STACK_CANARY(a1) 88 LONG_S t9, 0(t8) 89#endif 90 91 /* 92 * The order of restoring the registers takes care of the race 93 * updating $28, $29 and kernelsp without disabling ints. 94 */ 95 move $28, a2 96 cpu_restore_nonscratch a1 97 98 PTR_ADDU t0, $28, _THREAD_SIZE - 32 99 set_saved_sp t0, t1, t2 100 mfc0 t1, CP0_STATUS /* Do we really need this? */ 101 li a3, 0xff01 102 and t1, a3 103 LONG_L a2, THREAD_STATUS(a1) 104 nor a3, $0, a3 105 and a2, a3 106 or a2, t1 107 mtc0 a2, CP0_STATUS 108 move v0, a0 109 jr ra 110 END(resume) 111 112#endif /* USE_ALTERNATE_RESUME_IMPL */ 113 114/* 115 * Save a thread's fp context. 116 */ 117LEAF(_save_fp) 118#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ 119 defined(CONFIG_CPU_MIPS32_R6) 120 mfc0 t0, CP0_STATUS 121#endif 122 fpu_save_double a0 t0 t1 # clobbers t1 123 jr ra 124 END(_save_fp) 125 126/* 127 * Restore a thread's fp context. 128 */ 129LEAF(_restore_fp) 130#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ 131 defined(CONFIG_CPU_MIPS32_R6) 132 mfc0 t0, CP0_STATUS 133#endif 134 fpu_restore_double a0 t0 t1 # clobbers t1 135 jr ra 136 END(_restore_fp) 137 138#ifdef CONFIG_CPU_HAS_MSA 139 140/* 141 * Save a thread's MSA vector context. 142 */ 143LEAF(_save_msa) 144 msa_save_all a0 145 jr ra 146 END(_save_msa) 147 148/* 149 * Restore a thread's MSA vector context. 150 */ 151LEAF(_restore_msa) 152 msa_restore_all a0 153 jr ra 154 END(_restore_msa) 155 156LEAF(_init_msa_upper) 157 msa_init_all_upper 158 jr ra 159 END(_init_msa_upper) 160 161#endif 162 163/* 164 * Load the FPU with signalling NANS. This bit pattern we're using has 165 * the property that no matter whether considered as single or as double 166 * precision represents signaling NANS. 167 * 168 * The value to initialize fcr31 to comes in $a0. 169 */ 170 171 .set push 172 SET_HARDFLOAT 173 174LEAF(_init_fpu) 175 mfc0 t0, CP0_STATUS 176 li t1, ST0_CU1 177 or t0, t1 178 mtc0 t0, CP0_STATUS 179 enable_fpu_hazard 180 181 ctc1 a0, fcr31 182 183 li t1, -1 # SNaN 184 185#ifdef CONFIG_64BIT 186 sll t0, t0, 5 187 bgez t0, 1f # 16 / 32 register mode? 188 189 dmtc1 t1, $f1 190 dmtc1 t1, $f3 191 dmtc1 t1, $f5 192 dmtc1 t1, $f7 193 dmtc1 t1, $f9 194 dmtc1 t1, $f11 195 dmtc1 t1, $f13 196 dmtc1 t1, $f15 197 dmtc1 t1, $f17 198 dmtc1 t1, $f19 199 dmtc1 t1, $f21 200 dmtc1 t1, $f23 201 dmtc1 t1, $f25 202 dmtc1 t1, $f27 203 dmtc1 t1, $f29 204 dmtc1 t1, $f31 2051: 206#endif 207 208#ifdef CONFIG_CPU_MIPS32 209 mtc1 t1, $f0 210 mtc1 t1, $f1 211 mtc1 t1, $f2 212 mtc1 t1, $f3 213 mtc1 t1, $f4 214 mtc1 t1, $f5 215 mtc1 t1, $f6 216 mtc1 t1, $f7 217 mtc1 t1, $f8 218 mtc1 t1, $f9 219 mtc1 t1, $f10 220 mtc1 t1, $f11 221 mtc1 t1, $f12 222 mtc1 t1, $f13 223 mtc1 t1, $f14 224 mtc1 t1, $f15 225 mtc1 t1, $f16 226 mtc1 t1, $f17 227 mtc1 t1, $f18 228 mtc1 t1, $f19 229 mtc1 t1, $f20 230 mtc1 t1, $f21 231 mtc1 t1, $f22 232 mtc1 t1, $f23 233 mtc1 t1, $f24 234 mtc1 t1, $f25 235 mtc1 t1, $f26 236 mtc1 t1, $f27 237 mtc1 t1, $f28 238 mtc1 t1, $f29 239 mtc1 t1, $f30 240 mtc1 t1, $f31 241 242#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6) 243 .set push 244 .set MIPS_ISA_LEVEL_RAW 245 .set fp=64 246 sll t0, t0, 5 # is Status.FR set? 247 bgez t0, 1f # no: skip setting upper 32b 248 249 mthc1 t1, $f0 250 mthc1 t1, $f1 251 mthc1 t1, $f2 252 mthc1 t1, $f3 253 mthc1 t1, $f4 254 mthc1 t1, $f5 255 mthc1 t1, $f6 256 mthc1 t1, $f7 257 mthc1 t1, $f8 258 mthc1 t1, $f9 259 mthc1 t1, $f10 260 mthc1 t1, $f11 261 mthc1 t1, $f12 262 mthc1 t1, $f13 263 mthc1 t1, $f14 264 mthc1 t1, $f15 265 mthc1 t1, $f16 266 mthc1 t1, $f17 267 mthc1 t1, $f18 268 mthc1 t1, $f19 269 mthc1 t1, $f20 270 mthc1 t1, $f21 271 mthc1 t1, $f22 272 mthc1 t1, $f23 273 mthc1 t1, $f24 274 mthc1 t1, $f25 275 mthc1 t1, $f26 276 mthc1 t1, $f27 277 mthc1 t1, $f28 278 mthc1 t1, $f29 279 mthc1 t1, $f30 280 mthc1 t1, $f31 2811: .set pop 282#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */ 283#else 284 .set MIPS_ISA_ARCH_LEVEL_RAW 285 dmtc1 t1, $f0 286 dmtc1 t1, $f2 287 dmtc1 t1, $f4 288 dmtc1 t1, $f6 289 dmtc1 t1, $f8 290 dmtc1 t1, $f10 291 dmtc1 t1, $f12 292 dmtc1 t1, $f14 293 dmtc1 t1, $f16 294 dmtc1 t1, $f18 295 dmtc1 t1, $f20 296 dmtc1 t1, $f22 297 dmtc1 t1, $f24 298 dmtc1 t1, $f26 299 dmtc1 t1, $f28 300 dmtc1 t1, $f30 301#endif 302 jr ra 303 END(_init_fpu) 304 305 .set pop /* SET_HARDFLOAT */ 306