xref: /openbmc/linux/arch/mips/kernel/r4k_switch.S (revision e1f7c9ee) 
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
7 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 *    written by Carsten Langgaard, carstenl@mips.com
12 */
13#include <asm/asm.h>
14#include <asm/cachectl.h>
15#include <asm/fpregdef.h>
16#include <asm/mipsregs.h>
17#include <asm/asm-offsets.h>
18#include <asm/pgtable-bits.h>
19#include <asm/regdef.h>
20#include <asm/stackframe.h>
21#include <asm/thread_info.h>
22
23#include <asm/asmmacro.h>
24
25/*
26 * Offset to the current process status flags, the first 32 bytes of the
27 * stack are not used.
28 */
29#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
30
31#ifndef USE_ALTERNATE_RESUME_IMPL
32/*
33 * task_struct *resume(task_struct *prev, task_struct *next,
34 *		       struct thread_info *next_ti, s32 fp_save)
35 */
36	.align	5
37	LEAF(resume)
38	mfc0	t1, CP0_STATUS
39	LONG_S	t1, THREAD_STATUS(a0)
40	cpu_save_nonscratch a0
41	LONG_S	ra, THREAD_REG31(a0)
42
43	/*
44	 * Check whether we need to save any FP context. FP context is saved
45	 * iff the process has used the context with the scalar FPU or the MSA
46	 * ASE in the current time slice, as indicated by _TIF_USEDFPU and
47	 * _TIF_USEDMSA respectively. switch_to will have set fp_save
48	 * accordingly to an FP_SAVE_ enum value.
49	 */
50	beqz	a3, 2f
51
52	/*
53	 * We do. Clear the saved CU1 bit for prev, such that next time it is
54	 * scheduled it will start in userland with the FPU disabled. If the
55	 * task uses the FPU then it will be enabled again via the do_cpu trap.
56	 * This allows us to lazily restore the FP context.
57	 */
58	PTR_L	t3, TASK_THREAD_INFO(a0)
59	LONG_L	t0, ST_OFF(t3)
60	li	t1, ~ST0_CU1
61	and	t0, t0, t1
62	LONG_S	t0, ST_OFF(t3)
63
64	/* Check whether we're saving scalar or vector context. */
65	bgtz	a3, 1f
66
67	/* Save 128b MSA vector context + scalar FP control & status. */
68	cfc1	t1, fcr31
69	msa_save_all	a0
70	sw	t1, THREAD_FCR31(a0)
71	b	2f
72
731:	/* Save 32b/64b scalar FP context. */
74	fpu_save_double a0 t0 t1		# c0_status passed in t0
75						# clobbers t1
762:
77
78#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
79	PTR_LA	t8, __stack_chk_guard
80	LONG_L	t9, TASK_STACK_CANARY(a1)
81	LONG_S	t9, 0(t8)
82#endif
83
84	/*
85	 * The order of restoring the registers takes care of the race
86	 * updating $28, $29 and kernelsp without disabling ints.
87	 */
88	move	$28, a2
89	cpu_restore_nonscratch a1
90
91	PTR_ADDU	t0, $28, _THREAD_SIZE - 32
92	set_saved_sp	t0, t1, t2
93	mfc0	t1, CP0_STATUS		/* Do we really need this? */
94	li	a3, 0xff01
95	and	t1, a3
96	LONG_L	a2, THREAD_STATUS(a1)
97	nor	a3, $0, a3
98	and	a2, a3
99	or	a2, t1
100	mtc0	a2, CP0_STATUS
101	move	v0, a0
102	jr	ra
103	END(resume)
104
105#endif /* USE_ALTERNATE_RESUME_IMPL */
106
107/*
108 * Save a thread's fp context.
109 */
110LEAF(_save_fp)
111#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
112	mfc0	t0, CP0_STATUS
113#endif
114	fpu_save_double a0 t0 t1		# clobbers t1
115	jr	ra
116	END(_save_fp)
117
118/*
119 * Restore a thread's fp context.
120 */
121LEAF(_restore_fp)
122#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
123	mfc0	t0, CP0_STATUS
124#endif
125	fpu_restore_double a0 t0 t1		# clobbers t1
126	jr	ra
127	END(_restore_fp)
128
129#ifdef CONFIG_CPU_HAS_MSA
130
131/*
132 * Save a thread's MSA vector context.
133 */
134LEAF(_save_msa)
135	msa_save_all	a0
136	jr	ra
137	END(_save_msa)
138
139/*
140 * Restore a thread's MSA vector context.
141 */
142LEAF(_restore_msa)
143	msa_restore_all	a0
144	jr	ra
145	END(_restore_msa)
146
147LEAF(_init_msa_upper)
148	msa_init_all_upper
149	jr	ra
150	END(_init_msa_upper)
151
152#endif
153
154/*
155 * Load the FPU with signalling NANS.  This bit pattern we're using has
156 * the property that no matter whether considered as single or as double
157 * precision represents signaling NANS.
158 *
159 * We initialize fcr31 to rounding to nearest, no exceptions.
160 */
161
162#define FPU_DEFAULT  0x00000000
163
164LEAF(_init_fpu)
165	mfc0	t0, CP0_STATUS
166	li	t1, ST0_CU1
167	or	t0, t1
168	mtc0	t0, CP0_STATUS
169	enable_fpu_hazard
170
171	li	t1, FPU_DEFAULT
172	ctc1	t1, fcr31
173
174	li	t1, -1				# SNaN
175
176#ifdef CONFIG_64BIT
177	sll	t0, t0, 5
178	bgez	t0, 1f				# 16 / 32 register mode?
179
180	dmtc1	t1, $f1
181	dmtc1	t1, $f3
182	dmtc1	t1, $f5
183	dmtc1	t1, $f7
184	dmtc1	t1, $f9
185	dmtc1	t1, $f11
186	dmtc1	t1, $f13
187	dmtc1	t1, $f15
188	dmtc1	t1, $f17
189	dmtc1	t1, $f19
190	dmtc1	t1, $f21
191	dmtc1	t1, $f23
192	dmtc1	t1, $f25
193	dmtc1	t1, $f27
194	dmtc1	t1, $f29
195	dmtc1	t1, $f31
1961:
197#endif
198
199#ifdef CONFIG_CPU_MIPS32
200	mtc1	t1, $f0
201	mtc1	t1, $f1
202	mtc1	t1, $f2
203	mtc1	t1, $f3
204	mtc1	t1, $f4
205	mtc1	t1, $f5
206	mtc1	t1, $f6
207	mtc1	t1, $f7
208	mtc1	t1, $f8
209	mtc1	t1, $f9
210	mtc1	t1, $f10
211	mtc1	t1, $f11
212	mtc1	t1, $f12
213	mtc1	t1, $f13
214	mtc1	t1, $f14
215	mtc1	t1, $f15
216	mtc1	t1, $f16
217	mtc1	t1, $f17
218	mtc1	t1, $f18
219	mtc1	t1, $f19
220	mtc1	t1, $f20
221	mtc1	t1, $f21
222	mtc1	t1, $f22
223	mtc1	t1, $f23
224	mtc1	t1, $f24
225	mtc1	t1, $f25
226	mtc1	t1, $f26
227	mtc1	t1, $f27
228	mtc1	t1, $f28
229	mtc1	t1, $f29
230	mtc1	t1, $f30
231	mtc1	t1, $f31
232
233#ifdef CONFIG_CPU_MIPS32_R2
234	.set    push
235	.set    mips64r2
236	sll     t0, t0, 5			# is Status.FR set?
237	bgez    t0, 1f				# no: skip setting upper 32b
238
239	mthc1   t1, $f0
240	mthc1   t1, $f1
241	mthc1   t1, $f2
242	mthc1   t1, $f3
243	mthc1   t1, $f4
244	mthc1   t1, $f5
245	mthc1   t1, $f6
246	mthc1   t1, $f7
247	mthc1   t1, $f8
248	mthc1   t1, $f9
249	mthc1   t1, $f10
250	mthc1   t1, $f11
251	mthc1   t1, $f12
252	mthc1   t1, $f13
253	mthc1   t1, $f14
254	mthc1   t1, $f15
255	mthc1   t1, $f16
256	mthc1   t1, $f17
257	mthc1   t1, $f18
258	mthc1   t1, $f19
259	mthc1   t1, $f20
260	mthc1   t1, $f21
261	mthc1   t1, $f22
262	mthc1   t1, $f23
263	mthc1   t1, $f24
264	mthc1   t1, $f25
265	mthc1   t1, $f26
266	mthc1   t1, $f27
267	mthc1   t1, $f28
268	mthc1   t1, $f29
269	mthc1   t1, $f30
270	mthc1   t1, $f31
2711:	.set    pop
272#endif /* CONFIG_CPU_MIPS32_R2 */
273#else
274	.set	arch=r4000
275	dmtc1	t1, $f0
276	dmtc1	t1, $f2
277	dmtc1	t1, $f4
278	dmtc1	t1, $f6
279	dmtc1	t1, $f8
280	dmtc1	t1, $f10
281	dmtc1	t1, $f12
282	dmtc1	t1, $f14
283	dmtc1	t1, $f16
284	dmtc1	t1, $f18
285	dmtc1	t1, $f20
286	dmtc1	t1, $f22
287	dmtc1	t1, $f24
288	dmtc1	t1, $f26
289	dmtc1	t1, $f28
290	dmtc1	t1, $f30
291#endif
292	jr	ra
293	END(_init_fpu)
294