xref: /openbmc/linux/arch/mips/kernel/r4k_switch.S (revision 842ed298)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
7 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 *    written by Carsten Langgaard, carstenl@mips.com
12 */
13#include <asm/asm.h>
14#include <asm/cachectl.h>
15#include <asm/mipsregs.h>
16#include <asm/asm-offsets.h>
17#include <asm/regdef.h>
18#include <asm/stackframe.h>
19#include <asm/thread_info.h>
20
21#include <asm/asmmacro.h>
22
23/*
24 * task_struct *resume(task_struct *prev, task_struct *next,
25 *		       struct thread_info *next_ti)
26 */
27	.align	5
28	LEAF(resume)
29	mfc0	t1, CP0_STATUS
30	LONG_S	t1, THREAD_STATUS(a0)
31	cpu_save_nonscratch a0
32	LONG_S	ra, THREAD_REG31(a0)
33
34#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
35	PTR_LA	t8, __stack_chk_guard
36	LONG_L	t9, TASK_STACK_CANARY(a1)
37	LONG_S	t9, 0(t8)
38#endif
39
40	/*
41	 * The order of restoring the registers takes care of the race
42	 * updating $28, $29 and kernelsp without disabling ints.
43	 */
44	move	$28, a2
45	cpu_restore_nonscratch a1
46
47	PTR_ADDU	t0, $28, _THREAD_SIZE - 32
48	set_saved_sp	t0, t1, t2
49	mfc0	t1, CP0_STATUS		/* Do we really need this? */
50	li	a3, 0xff01
51	and	t1, a3
52	LONG_L	a2, THREAD_STATUS(a1)
53	nor	a3, $0, a3
54	and	a2, a3
55	or	a2, t1
56	mtc0	a2, CP0_STATUS
57	move	v0, a0
58	jr	ra
59	END(resume)
60