xref: /openbmc/linux/arch/mips/kernel/r4k_switch.S (revision 206a81c1) 
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
7 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 *    written by Carsten Langgaard, carstenl@mips.com
12 */
13#include <asm/asm.h>
14#include <asm/cachectl.h>
15#include <asm/fpregdef.h>
16#include <asm/mipsregs.h>
17#include <asm/asm-offsets.h>
18#include <asm/pgtable-bits.h>
19#include <asm/regdef.h>
20#include <asm/stackframe.h>
21#include <asm/thread_info.h>
22
23#include <asm/asmmacro.h>
24
25/*
26 * Offset to the current process status flags, the first 32 bytes of the
27 * stack are not used.
28 */
29#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
30
31#ifndef USE_ALTERNATE_RESUME_IMPL
32/*
33 * task_struct *resume(task_struct *prev, task_struct *next,
34 *		       struct thread_info *next_ti, s32 fp_save)
35 */
36	.align	5
37	LEAF(resume)
38	mfc0	t1, CP0_STATUS
39	LONG_S	t1, THREAD_STATUS(a0)
40	cpu_save_nonscratch a0
41	LONG_S	ra, THREAD_REG31(a0)
42
43	/*
44	 * Check whether we need to save any FP context. FP context is saved
45	 * iff the process has used the context with the scalar FPU or the MSA
46	 * ASE in the current time slice, as indicated by _TIF_USEDFPU and
47	 * _TIF_USEDMSA respectively. switch_to will have set fp_save
48	 * accordingly to an FP_SAVE_ enum value.
49	 */
50	beqz	a3, 2f
51
52	/*
53	 * We do. Clear the saved CU1 bit for prev, such that next time it is
54	 * scheduled it will start in userland with the FPU disabled. If the
55	 * task uses the FPU then it will be enabled again via the do_cpu trap.
56	 * This allows us to lazily restore the FP context.
57	 */
58	PTR_L	t3, TASK_THREAD_INFO(a0)
59	LONG_L	t0, ST_OFF(t3)
60	li	t1, ~ST0_CU1
61	and	t0, t0, t1
62	LONG_S	t0, ST_OFF(t3)
63
64	/* Check whether we're saving scalar or vector context. */
65	bgtz	a3, 1f
66
67	/* Save 128b MSA vector context. */
68	msa_save_all	a0
69	b	2f
70
711:	/* Save 32b/64b scalar FP context. */
72	fpu_save_double a0 t0 t1		# c0_status passed in t0
73						# clobbers t1
742:
75
76#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
77	PTR_LA	t8, __stack_chk_guard
78	LONG_L	t9, TASK_STACK_CANARY(a1)
79	LONG_S	t9, 0(t8)
80#endif
81
82	/*
83	 * The order of restoring the registers takes care of the race
84	 * updating $28, $29 and kernelsp without disabling ints.
85	 */
86	move	$28, a2
87	cpu_restore_nonscratch a1
88
89	PTR_ADDU	t0, $28, _THREAD_SIZE - 32
90	set_saved_sp	t0, t1, t2
91	mfc0	t1, CP0_STATUS		/* Do we really need this? */
92	li	a3, 0xff01
93	and	t1, a3
94	LONG_L	a2, THREAD_STATUS(a1)
95	nor	a3, $0, a3
96	and	a2, a3
97	or	a2, t1
98	mtc0	a2, CP0_STATUS
99	move	v0, a0
100	jr	ra
101	END(resume)
102
103#endif /* USE_ALTERNATE_RESUME_IMPL */
104
105/*
106 * Save a thread's fp context.
107 */
108LEAF(_save_fp)
109#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
110	mfc0	t0, CP0_STATUS
111#endif
112	fpu_save_double a0 t0 t1		# clobbers t1
113	jr	ra
114	END(_save_fp)
115
116/*
117 * Restore a thread's fp context.
118 */
119LEAF(_restore_fp)
120#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
121	mfc0	t0, CP0_STATUS
122#endif
123	fpu_restore_double a0 t0 t1		# clobbers t1
124	jr	ra
125	END(_restore_fp)
126
127#ifdef CONFIG_CPU_HAS_MSA
128
129/*
130 * Save a thread's MSA vector context.
131 */
132LEAF(_save_msa)
133	msa_save_all	a0
134	jr	ra
135	END(_save_msa)
136
137/*
138 * Restore a thread's MSA vector context.
139 */
140LEAF(_restore_msa)
141	msa_restore_all	a0
142	jr	ra
143	END(_restore_msa)
144
145#endif
146
147/*
148 * Load the FPU with signalling NANS.  This bit pattern we're using has
149 * the property that no matter whether considered as single or as double
150 * precision represents signaling NANS.
151 *
152 * We initialize fcr31 to rounding to nearest, no exceptions.
153 */
154
155#define FPU_DEFAULT  0x00000000
156
157LEAF(_init_fpu)
158	mfc0	t0, CP0_STATUS
159	li	t1, ST0_CU1
160	or	t0, t1
161	mtc0	t0, CP0_STATUS
162	enable_fpu_hazard
163
164	li	t1, FPU_DEFAULT
165	ctc1	t1, fcr31
166
167	li	t1, -1				# SNaN
168
169#ifdef CONFIG_64BIT
170	sll	t0, t0, 5
171	bgez	t0, 1f				# 16 / 32 register mode?
172
173	dmtc1	t1, $f1
174	dmtc1	t1, $f3
175	dmtc1	t1, $f5
176	dmtc1	t1, $f7
177	dmtc1	t1, $f9
178	dmtc1	t1, $f11
179	dmtc1	t1, $f13
180	dmtc1	t1, $f15
181	dmtc1	t1, $f17
182	dmtc1	t1, $f19
183	dmtc1	t1, $f21
184	dmtc1	t1, $f23
185	dmtc1	t1, $f25
186	dmtc1	t1, $f27
187	dmtc1	t1, $f29
188	dmtc1	t1, $f31
1891:
190#endif
191
192#ifdef CONFIG_CPU_MIPS32
193	mtc1	t1, $f0
194	mtc1	t1, $f1
195	mtc1	t1, $f2
196	mtc1	t1, $f3
197	mtc1	t1, $f4
198	mtc1	t1, $f5
199	mtc1	t1, $f6
200	mtc1	t1, $f7
201	mtc1	t1, $f8
202	mtc1	t1, $f9
203	mtc1	t1, $f10
204	mtc1	t1, $f11
205	mtc1	t1, $f12
206	mtc1	t1, $f13
207	mtc1	t1, $f14
208	mtc1	t1, $f15
209	mtc1	t1, $f16
210	mtc1	t1, $f17
211	mtc1	t1, $f18
212	mtc1	t1, $f19
213	mtc1	t1, $f20
214	mtc1	t1, $f21
215	mtc1	t1, $f22
216	mtc1	t1, $f23
217	mtc1	t1, $f24
218	mtc1	t1, $f25
219	mtc1	t1, $f26
220	mtc1	t1, $f27
221	mtc1	t1, $f28
222	mtc1	t1, $f29
223	mtc1	t1, $f30
224	mtc1	t1, $f31
225
226#ifdef CONFIG_CPU_MIPS32_R2
227	.set    push
228	.set    mips64r2
229	sll     t0, t0, 5			# is Status.FR set?
230	bgez    t0, 1f				# no: skip setting upper 32b
231
232	mthc1   t1, $f0
233	mthc1   t1, $f1
234	mthc1   t1, $f2
235	mthc1   t1, $f3
236	mthc1   t1, $f4
237	mthc1   t1, $f5
238	mthc1   t1, $f6
239	mthc1   t1, $f7
240	mthc1   t1, $f8
241	mthc1   t1, $f9
242	mthc1   t1, $f10
243	mthc1   t1, $f11
244	mthc1   t1, $f12
245	mthc1   t1, $f13
246	mthc1   t1, $f14
247	mthc1   t1, $f15
248	mthc1   t1, $f16
249	mthc1   t1, $f17
250	mthc1   t1, $f18
251	mthc1   t1, $f19
252	mthc1   t1, $f20
253	mthc1   t1, $f21
254	mthc1   t1, $f22
255	mthc1   t1, $f23
256	mthc1   t1, $f24
257	mthc1   t1, $f25
258	mthc1   t1, $f26
259	mthc1   t1, $f27
260	mthc1   t1, $f28
261	mthc1   t1, $f29
262	mthc1   t1, $f30
263	mthc1   t1, $f31
2641:	.set    pop
265#endif /* CONFIG_CPU_MIPS32_R2 */
266#else
267	.set	arch=r4000
268	dmtc1	t1, $f0
269	dmtc1	t1, $f2
270	dmtc1	t1, $f4
271	dmtc1	t1, $f6
272	dmtc1	t1, $f8
273	dmtc1	t1, $f10
274	dmtc1	t1, $f12
275	dmtc1	t1, $f14
276	dmtc1	t1, $f16
277	dmtc1	t1, $f18
278	dmtc1	t1, $f20
279	dmtc1	t1, $f22
280	dmtc1	t1, $f24
281	dmtc1	t1, $f26
282	dmtc1	t1, $f28
283	dmtc1	t1, $f30
284#endif
285	jr	ra
286	END(_init_fpu)
287