1/* 2 * r2300_switch.S: R2300 specific task switching code. 3 * 4 * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle 5 * Copyright (C) 1994, 1995, 1996 by Andreas Busse 6 * 7 * Multi-cpu abstraction and macros for easier reading: 8 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 9 * 10 * Further modifications to make this work: 11 * Copyright (c) 1998-2000 Harald Koerfgen 12 */ 13#include <asm/asm.h> 14#include <asm/cachectl.h> 15#include <asm/fpregdef.h> 16#include <asm/mipsregs.h> 17#include <asm/asm-offsets.h> 18#include <asm/regdef.h> 19#include <asm/stackframe.h> 20#include <asm/thread_info.h> 21 22#include <asm/asmmacro.h> 23 24 .set mips1 25 .align 5 26 27/* 28 * Offset to the current process status flags, the first 32 bytes of the 29 * stack are not used. 30 */ 31#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS) 32 33/* 34 * FPU context is saved iff the process has used it's FPU in the current 35 * time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user 36 * space STATUS register should be 0, so that a process *always* starts its 37 * userland with FPU disabled after each context switch. 38 * 39 * FPU will be enabled as soon as the process accesses FPU again, through 40 * do_cpu() trap. 41 */ 42 43/* 44 * task_struct *resume(task_struct *prev, task_struct *next, 45 * struct thread_info *next_ti, int usedfpu) 46 */ 47LEAF(resume) 48 mfc0 t1, CP0_STATUS 49 sw t1, THREAD_STATUS(a0) 50 cpu_save_nonscratch a0 51 sw ra, THREAD_REG31(a0) 52 53 beqz a3, 1f 54 55 PTR_L t3, TASK_THREAD_INFO(a0) 56 57 /* 58 * clear saved user stack CU1 bit 59 */ 60 lw t0, ST_OFF(t3) 61 li t1, ~ST0_CU1 62 and t0, t0, t1 63 sw t0, ST_OFF(t3) 64 65 fpu_save_single a0, t0 # clobbers t0 66 671: 68 /* 69 * The order of restoring the registers takes care of the race 70 * updating $28, $29 and kernelsp without disabling ints. 71 */ 72 move $28, a2 73 cpu_restore_nonscratch a1 74 75 addiu t1, $28, _THREAD_SIZE - 32 76 sw t1, kernelsp 77 78 mfc0 t1, CP0_STATUS /* Do we really need this? */ 79 li a3, 0xff01 80 and t1, a3 81 lw a2, THREAD_STATUS(a1) 82 nor a3, $0, a3 83 and a2, a3 84 or a2, t1 85 mtc0 a2, CP0_STATUS 86 move v0, a0 87 jr ra 88 END(resume) 89 90/* 91 * Save a thread's fp context. 92 */ 93LEAF(_save_fp) 94 fpu_save_single a0, t1 # clobbers t1 95 jr ra 96 END(_save_fp) 97 98/* 99 * Restore a thread's fp context. 100 */ 101LEAF(_restore_fp) 102 fpu_restore_single a0, t1 # clobbers t1 103 jr ra 104 END(_restore_fp) 105 106/* 107 * Load the FPU with signalling NANS. This bit pattern we're using has 108 * the property that no matter whether considered as single or as double 109 * precision represents signaling NANS. 110 * 111 * We initialize fcr31 to rounding to nearest, no exceptions. 112 */ 113 114#define FPU_DEFAULT 0x00000000 115 116LEAF(_init_fpu) 117 mfc0 t0, CP0_STATUS 118 li t1, ST0_CU1 119 or t0, t1 120 mtc0 t0, CP0_STATUS 121 122 li t1, FPU_DEFAULT 123 ctc1 t1, fcr31 124 125 li t0, -1 126 127 mtc1 t0, $f0 128 mtc1 t0, $f1 129 mtc1 t0, $f2 130 mtc1 t0, $f3 131 mtc1 t0, $f4 132 mtc1 t0, $f5 133 mtc1 t0, $f6 134 mtc1 t0, $f7 135 mtc1 t0, $f8 136 mtc1 t0, $f9 137 mtc1 t0, $f10 138 mtc1 t0, $f11 139 mtc1 t0, $f12 140 mtc1 t0, $f13 141 mtc1 t0, $f14 142 mtc1 t0, $f15 143 mtc1 t0, $f16 144 mtc1 t0, $f17 145 mtc1 t0, $f18 146 mtc1 t0, $f19 147 mtc1 t0, $f20 148 mtc1 t0, $f21 149 mtc1 t0, $f22 150 mtc1 t0, $f23 151 mtc1 t0, $f24 152 mtc1 t0, $f25 153 mtc1 t0, $f26 154 mtc1 t0, $f27 155 mtc1 t0, $f28 156 mtc1 t0, $f29 157 mtc1 t0, $f30 158 mtc1 t0, $f31 159 jr ra 160 END(_init_fpu) 161