1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1992 Ross Biro 7 * Copyright (C) Linus Torvalds 8 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle 9 * Copyright (C) 1996 David S. Miller 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 1999 MIPS Technologies, Inc. 12 * Copyright (C) 2000 Ulf Carlsson 13 * 14 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit 15 * binaries. 16 */ 17 #include <linux/compiler.h> 18 #include <linux/context_tracking.h> 19 #include <linux/elf.h> 20 #include <linux/kernel.h> 21 #include <linux/sched.h> 22 #include <linux/sched/task_stack.h> 23 #include <linux/mm.h> 24 #include <linux/errno.h> 25 #include <linux/ptrace.h> 26 #include <linux/regset.h> 27 #include <linux/smp.h> 28 #include <linux/security.h> 29 #include <linux/stddef.h> 30 #include <linux/tracehook.h> 31 #include <linux/audit.h> 32 #include <linux/seccomp.h> 33 #include <linux/ftrace.h> 34 35 #include <asm/byteorder.h> 36 #include <asm/cpu.h> 37 #include <asm/cpu-info.h> 38 #include <asm/dsp.h> 39 #include <asm/fpu.h> 40 #include <asm/mipsregs.h> 41 #include <asm/mipsmtregs.h> 42 #include <asm/pgtable.h> 43 #include <asm/page.h> 44 #include <asm/processor.h> 45 #include <asm/syscall.h> 46 #include <linux/uaccess.h> 47 #include <asm/bootinfo.h> 48 #include <asm/reg.h> 49 50 #define CREATE_TRACE_POINTS 51 #include <trace/events/syscalls.h> 52 53 static void init_fp_ctx(struct task_struct *target) 54 { 55 /* If FP has been used then the target already has context */ 56 if (tsk_used_math(target)) 57 return; 58 59 /* Begin with data registers set to all 1s... */ 60 memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr)); 61 62 /* FCSR has been preset by `mips_set_personality_nan'. */ 63 64 /* 65 * Record that the target has "used" math, such that the context 66 * just initialised, and any modifications made by the caller, 67 * aren't discarded. 68 */ 69 set_stopped_child_used_math(target); 70 } 71 72 /* 73 * Called by kernel/ptrace.c when detaching.. 74 * 75 * Make sure single step bits etc are not set. 76 */ 77 void ptrace_disable(struct task_struct *child) 78 { 79 /* Don't load the watchpoint registers for the ex-child. */ 80 clear_tsk_thread_flag(child, TIF_LOAD_WATCH); 81 } 82 83 /* 84 * Poke at FCSR according to its mask. Set the Cause bits even 85 * if a corresponding Enable bit is set. This will be noticed at 86 * the time the thread is switched to and SIGFPE thrown accordingly. 87 */ 88 static void ptrace_setfcr31(struct task_struct *child, u32 value) 89 { 90 u32 fcr31; 91 u32 mask; 92 93 fcr31 = child->thread.fpu.fcr31; 94 mask = boot_cpu_data.fpu_msk31; 95 child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask); 96 } 97 98 /* 99 * Read a general register set. We always use the 64-bit format, even 100 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel. 101 * Registers are sign extended to fill the available space. 102 */ 103 int ptrace_getregs(struct task_struct *child, struct user_pt_regs __user *data) 104 { 105 struct pt_regs *regs; 106 int i; 107 108 if (!access_ok(VERIFY_WRITE, data, 38 * 8)) 109 return -EIO; 110 111 regs = task_pt_regs(child); 112 113 for (i = 0; i < 32; i++) 114 __put_user((long)regs->regs[i], (__s64 __user *)&data->regs[i]); 115 __put_user((long)regs->lo, (__s64 __user *)&data->lo); 116 __put_user((long)regs->hi, (__s64 __user *)&data->hi); 117 __put_user((long)regs->cp0_epc, (__s64 __user *)&data->cp0_epc); 118 __put_user((long)regs->cp0_badvaddr, (__s64 __user *)&data->cp0_badvaddr); 119 __put_user((long)regs->cp0_status, (__s64 __user *)&data->cp0_status); 120 __put_user((long)regs->cp0_cause, (__s64 __user *)&data->cp0_cause); 121 122 return 0; 123 } 124 125 /* 126 * Write a general register set. As for PTRACE_GETREGS, we always use 127 * the 64-bit format. On a 32-bit kernel only the lower order half 128 * (according to endianness) will be used. 129 */ 130 int ptrace_setregs(struct task_struct *child, struct user_pt_regs __user *data) 131 { 132 struct pt_regs *regs; 133 int i; 134 135 if (!access_ok(VERIFY_READ, data, 38 * 8)) 136 return -EIO; 137 138 regs = task_pt_regs(child); 139 140 for (i = 0; i < 32; i++) 141 __get_user(regs->regs[i], (__s64 __user *)&data->regs[i]); 142 __get_user(regs->lo, (__s64 __user *)&data->lo); 143 __get_user(regs->hi, (__s64 __user *)&data->hi); 144 __get_user(regs->cp0_epc, (__s64 __user *)&data->cp0_epc); 145 146 /* badvaddr, status, and cause may not be written. */ 147 148 /* System call number may have been changed */ 149 mips_syscall_update_nr(child, regs); 150 151 return 0; 152 } 153 154 int ptrace_getfpregs(struct task_struct *child, __u32 __user *data) 155 { 156 int i; 157 158 if (!access_ok(VERIFY_WRITE, data, 33 * 8)) 159 return -EIO; 160 161 if (tsk_used_math(child)) { 162 union fpureg *fregs = get_fpu_regs(child); 163 for (i = 0; i < 32; i++) 164 __put_user(get_fpr64(&fregs[i], 0), 165 i + (__u64 __user *)data); 166 } else { 167 for (i = 0; i < 32; i++) 168 __put_user((__u64) -1, i + (__u64 __user *) data); 169 } 170 171 __put_user(child->thread.fpu.fcr31, data + 64); 172 __put_user(boot_cpu_data.fpu_id, data + 65); 173 174 return 0; 175 } 176 177 int ptrace_setfpregs(struct task_struct *child, __u32 __user *data) 178 { 179 union fpureg *fregs; 180 u64 fpr_val; 181 u32 value; 182 int i; 183 184 if (!access_ok(VERIFY_READ, data, 33 * 8)) 185 return -EIO; 186 187 init_fp_ctx(child); 188 fregs = get_fpu_regs(child); 189 190 for (i = 0; i < 32; i++) { 191 __get_user(fpr_val, i + (__u64 __user *)data); 192 set_fpr64(&fregs[i], 0, fpr_val); 193 } 194 195 __get_user(value, data + 64); 196 ptrace_setfcr31(child, value); 197 198 /* FIR may not be written. */ 199 200 return 0; 201 } 202 203 int ptrace_get_watch_regs(struct task_struct *child, 204 struct pt_watch_regs __user *addr) 205 { 206 enum pt_watch_style style; 207 int i; 208 209 if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0) 210 return -EIO; 211 if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs))) 212 return -EIO; 213 214 #ifdef CONFIG_32BIT 215 style = pt_watch_style_mips32; 216 #define WATCH_STYLE mips32 217 #else 218 style = pt_watch_style_mips64; 219 #define WATCH_STYLE mips64 220 #endif 221 222 __put_user(style, &addr->style); 223 __put_user(boot_cpu_data.watch_reg_use_cnt, 224 &addr->WATCH_STYLE.num_valid); 225 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) { 226 __put_user(child->thread.watch.mips3264.watchlo[i], 227 &addr->WATCH_STYLE.watchlo[i]); 228 __put_user(child->thread.watch.mips3264.watchhi[i] & 229 (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW), 230 &addr->WATCH_STYLE.watchhi[i]); 231 __put_user(boot_cpu_data.watch_reg_masks[i], 232 &addr->WATCH_STYLE.watch_masks[i]); 233 } 234 for (; i < 8; i++) { 235 __put_user(0, &addr->WATCH_STYLE.watchlo[i]); 236 __put_user(0, &addr->WATCH_STYLE.watchhi[i]); 237 __put_user(0, &addr->WATCH_STYLE.watch_masks[i]); 238 } 239 240 return 0; 241 } 242 243 int ptrace_set_watch_regs(struct task_struct *child, 244 struct pt_watch_regs __user *addr) 245 { 246 int i; 247 int watch_active = 0; 248 unsigned long lt[NUM_WATCH_REGS]; 249 u16 ht[NUM_WATCH_REGS]; 250 251 if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0) 252 return -EIO; 253 if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs))) 254 return -EIO; 255 /* Check the values. */ 256 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) { 257 __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]); 258 #ifdef CONFIG_32BIT 259 if (lt[i] & __UA_LIMIT) 260 return -EINVAL; 261 #else 262 if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) { 263 if (lt[i] & 0xffffffff80000000UL) 264 return -EINVAL; 265 } else { 266 if (lt[i] & __UA_LIMIT) 267 return -EINVAL; 268 } 269 #endif 270 __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]); 271 if (ht[i] & ~MIPS_WATCHHI_MASK) 272 return -EINVAL; 273 } 274 /* Install them. */ 275 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) { 276 if (lt[i] & MIPS_WATCHLO_IRW) 277 watch_active = 1; 278 child->thread.watch.mips3264.watchlo[i] = lt[i]; 279 /* Set the G bit. */ 280 child->thread.watch.mips3264.watchhi[i] = ht[i]; 281 } 282 283 if (watch_active) 284 set_tsk_thread_flag(child, TIF_LOAD_WATCH); 285 else 286 clear_tsk_thread_flag(child, TIF_LOAD_WATCH); 287 288 return 0; 289 } 290 291 /* regset get/set implementations */ 292 293 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32) 294 295 static int gpr32_get(struct task_struct *target, 296 const struct user_regset *regset, 297 unsigned int pos, unsigned int count, 298 void *kbuf, void __user *ubuf) 299 { 300 struct pt_regs *regs = task_pt_regs(target); 301 u32 uregs[ELF_NGREG] = {}; 302 303 mips_dump_regs32(uregs, regs); 304 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0, 305 sizeof(uregs)); 306 } 307 308 static int gpr32_set(struct task_struct *target, 309 const struct user_regset *regset, 310 unsigned int pos, unsigned int count, 311 const void *kbuf, const void __user *ubuf) 312 { 313 struct pt_regs *regs = task_pt_regs(target); 314 u32 uregs[ELF_NGREG]; 315 unsigned start, num_regs, i; 316 int err; 317 318 start = pos / sizeof(u32); 319 num_regs = count / sizeof(u32); 320 321 if (start + num_regs > ELF_NGREG) 322 return -EIO; 323 324 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0, 325 sizeof(uregs)); 326 if (err) 327 return err; 328 329 for (i = start; i < num_regs; i++) { 330 /* 331 * Cast all values to signed here so that if this is a 64-bit 332 * kernel, the supplied 32-bit values will be sign extended. 333 */ 334 switch (i) { 335 case MIPS32_EF_R1 ... MIPS32_EF_R25: 336 /* k0/k1 are ignored. */ 337 case MIPS32_EF_R28 ... MIPS32_EF_R31: 338 regs->regs[i - MIPS32_EF_R0] = (s32)uregs[i]; 339 break; 340 case MIPS32_EF_LO: 341 regs->lo = (s32)uregs[i]; 342 break; 343 case MIPS32_EF_HI: 344 regs->hi = (s32)uregs[i]; 345 break; 346 case MIPS32_EF_CP0_EPC: 347 regs->cp0_epc = (s32)uregs[i]; 348 break; 349 } 350 } 351 352 /* System call number may have been changed */ 353 mips_syscall_update_nr(target, regs); 354 355 return 0; 356 } 357 358 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */ 359 360 #ifdef CONFIG_64BIT 361 362 static int gpr64_get(struct task_struct *target, 363 const struct user_regset *regset, 364 unsigned int pos, unsigned int count, 365 void *kbuf, void __user *ubuf) 366 { 367 struct pt_regs *regs = task_pt_regs(target); 368 u64 uregs[ELF_NGREG] = {}; 369 370 mips_dump_regs64(uregs, regs); 371 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0, 372 sizeof(uregs)); 373 } 374 375 static int gpr64_set(struct task_struct *target, 376 const struct user_regset *regset, 377 unsigned int pos, unsigned int count, 378 const void *kbuf, const void __user *ubuf) 379 { 380 struct pt_regs *regs = task_pt_regs(target); 381 u64 uregs[ELF_NGREG]; 382 unsigned start, num_regs, i; 383 int err; 384 385 start = pos / sizeof(u64); 386 num_regs = count / sizeof(u64); 387 388 if (start + num_regs > ELF_NGREG) 389 return -EIO; 390 391 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0, 392 sizeof(uregs)); 393 if (err) 394 return err; 395 396 for (i = start; i < num_regs; i++) { 397 switch (i) { 398 case MIPS64_EF_R1 ... MIPS64_EF_R25: 399 /* k0/k1 are ignored. */ 400 case MIPS64_EF_R28 ... MIPS64_EF_R31: 401 regs->regs[i - MIPS64_EF_R0] = uregs[i]; 402 break; 403 case MIPS64_EF_LO: 404 regs->lo = uregs[i]; 405 break; 406 case MIPS64_EF_HI: 407 regs->hi = uregs[i]; 408 break; 409 case MIPS64_EF_CP0_EPC: 410 regs->cp0_epc = uregs[i]; 411 break; 412 } 413 } 414 415 /* System call number may have been changed */ 416 mips_syscall_update_nr(target, regs); 417 418 return 0; 419 } 420 421 #endif /* CONFIG_64BIT */ 422 423 /* 424 * Copy the floating-point context to the supplied NT_PRFPREG buffer, 425 * !CONFIG_CPU_HAS_MSA variant. FP context's general register slots 426 * correspond 1:1 to buffer slots. Only general registers are copied. 427 */ 428 static int fpr_get_fpa(struct task_struct *target, 429 unsigned int *pos, unsigned int *count, 430 void **kbuf, void __user **ubuf) 431 { 432 return user_regset_copyout(pos, count, kbuf, ubuf, 433 &target->thread.fpu, 434 0, NUM_FPU_REGS * sizeof(elf_fpreg_t)); 435 } 436 437 /* 438 * Copy the floating-point context to the supplied NT_PRFPREG buffer, 439 * CONFIG_CPU_HAS_MSA variant. Only lower 64 bits of FP context's 440 * general register slots are copied to buffer slots. Only general 441 * registers are copied. 442 */ 443 static int fpr_get_msa(struct task_struct *target, 444 unsigned int *pos, unsigned int *count, 445 void **kbuf, void __user **ubuf) 446 { 447 unsigned int i; 448 u64 fpr_val; 449 int err; 450 451 BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t)); 452 for (i = 0; i < NUM_FPU_REGS; i++) { 453 fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0); 454 err = user_regset_copyout(pos, count, kbuf, ubuf, 455 &fpr_val, i * sizeof(elf_fpreg_t), 456 (i + 1) * sizeof(elf_fpreg_t)); 457 if (err) 458 return err; 459 } 460 461 return 0; 462 } 463 464 /* 465 * Copy the floating-point context to the supplied NT_PRFPREG buffer. 466 * Choose the appropriate helper for general registers, and then copy 467 * the FCSR and FIR registers separately. 468 */ 469 static int fpr_get(struct task_struct *target, 470 const struct user_regset *regset, 471 unsigned int pos, unsigned int count, 472 void *kbuf, void __user *ubuf) 473 { 474 const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t); 475 const int fir_pos = fcr31_pos + sizeof(u32); 476 int err; 477 478 if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t)) 479 err = fpr_get_fpa(target, &pos, &count, &kbuf, &ubuf); 480 else 481 err = fpr_get_msa(target, &pos, &count, &kbuf, &ubuf); 482 if (err) 483 return err; 484 485 err = user_regset_copyout(&pos, &count, &kbuf, &ubuf, 486 &target->thread.fpu.fcr31, 487 fcr31_pos, fcr31_pos + sizeof(u32)); 488 if (err) 489 return err; 490 491 err = user_regset_copyout(&pos, &count, &kbuf, &ubuf, 492 &boot_cpu_data.fpu_id, 493 fir_pos, fir_pos + sizeof(u32)); 494 495 return err; 496 } 497 498 /* 499 * Copy the supplied NT_PRFPREG buffer to the floating-point context, 500 * !CONFIG_CPU_HAS_MSA variant. Buffer slots correspond 1:1 to FP 501 * context's general register slots. Only general registers are copied. 502 */ 503 static int fpr_set_fpa(struct task_struct *target, 504 unsigned int *pos, unsigned int *count, 505 const void **kbuf, const void __user **ubuf) 506 { 507 return user_regset_copyin(pos, count, kbuf, ubuf, 508 &target->thread.fpu, 509 0, NUM_FPU_REGS * sizeof(elf_fpreg_t)); 510 } 511 512 /* 513 * Copy the supplied NT_PRFPREG buffer to the floating-point context, 514 * CONFIG_CPU_HAS_MSA variant. Buffer slots are copied to lower 64 515 * bits only of FP context's general register slots. Only general 516 * registers are copied. 517 */ 518 static int fpr_set_msa(struct task_struct *target, 519 unsigned int *pos, unsigned int *count, 520 const void **kbuf, const void __user **ubuf) 521 { 522 unsigned int i; 523 u64 fpr_val; 524 int err; 525 526 BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t)); 527 for (i = 0; i < NUM_FPU_REGS && *count > 0; i++) { 528 err = user_regset_copyin(pos, count, kbuf, ubuf, 529 &fpr_val, i * sizeof(elf_fpreg_t), 530 (i + 1) * sizeof(elf_fpreg_t)); 531 if (err) 532 return err; 533 set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val); 534 } 535 536 return 0; 537 } 538 539 /* 540 * Copy the supplied NT_PRFPREG buffer to the floating-point context. 541 * Choose the appropriate helper for general registers, and then copy 542 * the FCSR register separately. Ignore the incoming FIR register 543 * contents though, as the register is read-only. 544 * 545 * We optimize for the case where `count % sizeof(elf_fpreg_t) == 0', 546 * which is supposed to have been guaranteed by the kernel before 547 * calling us, e.g. in `ptrace_regset'. We enforce that requirement, 548 * so that we can safely avoid preinitializing temporaries for 549 * partial register writes. 550 */ 551 static int fpr_set(struct task_struct *target, 552 const struct user_regset *regset, 553 unsigned int pos, unsigned int count, 554 const void *kbuf, const void __user *ubuf) 555 { 556 const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t); 557 const int fir_pos = fcr31_pos + sizeof(u32); 558 u32 fcr31; 559 int err; 560 561 BUG_ON(count % sizeof(elf_fpreg_t)); 562 563 if (pos + count > sizeof(elf_fpregset_t)) 564 return -EIO; 565 566 init_fp_ctx(target); 567 568 if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t)) 569 err = fpr_set_fpa(target, &pos, &count, &kbuf, &ubuf); 570 else 571 err = fpr_set_msa(target, &pos, &count, &kbuf, &ubuf); 572 if (err) 573 return err; 574 575 if (count > 0) { 576 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 577 &fcr31, 578 fcr31_pos, fcr31_pos + sizeof(u32)); 579 if (err) 580 return err; 581 582 ptrace_setfcr31(target, fcr31); 583 } 584 585 if (count > 0) 586 err = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 587 fir_pos, 588 fir_pos + sizeof(u32)); 589 590 return err; 591 } 592 593 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32) 594 595 /* 596 * Copy the DSP context to the supplied 32-bit NT_MIPS_DSP buffer. 597 */ 598 static int dsp32_get(struct task_struct *target, 599 const struct user_regset *regset, 600 unsigned int pos, unsigned int count, 601 void *kbuf, void __user *ubuf) 602 { 603 unsigned int start, num_regs, i; 604 u32 dspregs[NUM_DSP_REGS + 1]; 605 606 BUG_ON(count % sizeof(u32)); 607 608 if (!cpu_has_dsp) 609 return -EIO; 610 611 start = pos / sizeof(u32); 612 num_regs = count / sizeof(u32); 613 614 if (start + num_regs > NUM_DSP_REGS + 1) 615 return -EIO; 616 617 for (i = start; i < num_regs; i++) 618 switch (i) { 619 case 0 ... NUM_DSP_REGS - 1: 620 dspregs[i] = target->thread.dsp.dspr[i]; 621 break; 622 case NUM_DSP_REGS: 623 dspregs[i] = target->thread.dsp.dspcontrol; 624 break; 625 } 626 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, dspregs, 0, 627 sizeof(dspregs)); 628 } 629 630 /* 631 * Copy the supplied 32-bit NT_MIPS_DSP buffer to the DSP context. 632 */ 633 static int dsp32_set(struct task_struct *target, 634 const struct user_regset *regset, 635 unsigned int pos, unsigned int count, 636 const void *kbuf, const void __user *ubuf) 637 { 638 unsigned int start, num_regs, i; 639 u32 dspregs[NUM_DSP_REGS + 1]; 640 int err; 641 642 BUG_ON(count % sizeof(u32)); 643 644 if (!cpu_has_dsp) 645 return -EIO; 646 647 start = pos / sizeof(u32); 648 num_regs = count / sizeof(u32); 649 650 if (start + num_regs > NUM_DSP_REGS + 1) 651 return -EIO; 652 653 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, dspregs, 0, 654 sizeof(dspregs)); 655 if (err) 656 return err; 657 658 for (i = start; i < num_regs; i++) 659 switch (i) { 660 case 0 ... NUM_DSP_REGS - 1: 661 target->thread.dsp.dspr[i] = (s32)dspregs[i]; 662 break; 663 case NUM_DSP_REGS: 664 target->thread.dsp.dspcontrol = (s32)dspregs[i]; 665 break; 666 } 667 668 return 0; 669 } 670 671 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */ 672 673 #ifdef CONFIG_64BIT 674 675 /* 676 * Copy the DSP context to the supplied 64-bit NT_MIPS_DSP buffer. 677 */ 678 static int dsp64_get(struct task_struct *target, 679 const struct user_regset *regset, 680 unsigned int pos, unsigned int count, 681 void *kbuf, void __user *ubuf) 682 { 683 unsigned int start, num_regs, i; 684 u64 dspregs[NUM_DSP_REGS + 1]; 685 686 BUG_ON(count % sizeof(u64)); 687 688 if (!cpu_has_dsp) 689 return -EIO; 690 691 start = pos / sizeof(u64); 692 num_regs = count / sizeof(u64); 693 694 if (start + num_regs > NUM_DSP_REGS + 1) 695 return -EIO; 696 697 for (i = start; i < num_regs; i++) 698 switch (i) { 699 case 0 ... NUM_DSP_REGS - 1: 700 dspregs[i] = target->thread.dsp.dspr[i]; 701 break; 702 case NUM_DSP_REGS: 703 dspregs[i] = target->thread.dsp.dspcontrol; 704 break; 705 } 706 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, dspregs, 0, 707 sizeof(dspregs)); 708 } 709 710 /* 711 * Copy the supplied 64-bit NT_MIPS_DSP buffer to the DSP context. 712 */ 713 static int dsp64_set(struct task_struct *target, 714 const struct user_regset *regset, 715 unsigned int pos, unsigned int count, 716 const void *kbuf, const void __user *ubuf) 717 { 718 unsigned int start, num_regs, i; 719 u64 dspregs[NUM_DSP_REGS + 1]; 720 int err; 721 722 BUG_ON(count % sizeof(u64)); 723 724 if (!cpu_has_dsp) 725 return -EIO; 726 727 start = pos / sizeof(u64); 728 num_regs = count / sizeof(u64); 729 730 if (start + num_regs > NUM_DSP_REGS + 1) 731 return -EIO; 732 733 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, dspregs, 0, 734 sizeof(dspregs)); 735 if (err) 736 return err; 737 738 for (i = start; i < num_regs; i++) 739 switch (i) { 740 case 0 ... NUM_DSP_REGS - 1: 741 target->thread.dsp.dspr[i] = dspregs[i]; 742 break; 743 case NUM_DSP_REGS: 744 target->thread.dsp.dspcontrol = dspregs[i]; 745 break; 746 } 747 748 return 0; 749 } 750 751 #endif /* CONFIG_64BIT */ 752 753 /* 754 * Determine whether the DSP context is present. 755 */ 756 static int dsp_active(struct task_struct *target, 757 const struct user_regset *regset) 758 { 759 return cpu_has_dsp ? NUM_DSP_REGS + 1 : -ENODEV; 760 } 761 762 /* Copy the FP mode setting to the supplied NT_MIPS_FP_MODE buffer. */ 763 static int fp_mode_get(struct task_struct *target, 764 const struct user_regset *regset, 765 unsigned int pos, unsigned int count, 766 void *kbuf, void __user *ubuf) 767 { 768 int fp_mode; 769 770 fp_mode = mips_get_process_fp_mode(target); 771 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &fp_mode, 0, 772 sizeof(fp_mode)); 773 } 774 775 /* 776 * Copy the supplied NT_MIPS_FP_MODE buffer to the FP mode setting. 777 * 778 * We optimize for the case where `count % sizeof(int) == 0', which 779 * is supposed to have been guaranteed by the kernel before calling 780 * us, e.g. in `ptrace_regset'. We enforce that requirement, so 781 * that we can safely avoid preinitializing temporaries for partial 782 * mode writes. 783 */ 784 static int fp_mode_set(struct task_struct *target, 785 const struct user_regset *regset, 786 unsigned int pos, unsigned int count, 787 const void *kbuf, const void __user *ubuf) 788 { 789 int fp_mode; 790 int err; 791 792 BUG_ON(count % sizeof(int)); 793 794 if (pos + count > sizeof(fp_mode)) 795 return -EIO; 796 797 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fp_mode, 0, 798 sizeof(fp_mode)); 799 if (err) 800 return err; 801 802 if (count > 0) 803 err = mips_set_process_fp_mode(target, fp_mode); 804 805 return err; 806 } 807 808 enum mips_regset { 809 REGSET_GPR, 810 REGSET_FPR, 811 REGSET_DSP, 812 REGSET_FP_MODE, 813 }; 814 815 struct pt_regs_offset { 816 const char *name; 817 int offset; 818 }; 819 820 #define REG_OFFSET_NAME(reg, r) { \ 821 .name = #reg, \ 822 .offset = offsetof(struct pt_regs, r) \ 823 } 824 825 #define REG_OFFSET_END { \ 826 .name = NULL, \ 827 .offset = 0 \ 828 } 829 830 static const struct pt_regs_offset regoffset_table[] = { 831 REG_OFFSET_NAME(r0, regs[0]), 832 REG_OFFSET_NAME(r1, regs[1]), 833 REG_OFFSET_NAME(r2, regs[2]), 834 REG_OFFSET_NAME(r3, regs[3]), 835 REG_OFFSET_NAME(r4, regs[4]), 836 REG_OFFSET_NAME(r5, regs[5]), 837 REG_OFFSET_NAME(r6, regs[6]), 838 REG_OFFSET_NAME(r7, regs[7]), 839 REG_OFFSET_NAME(r8, regs[8]), 840 REG_OFFSET_NAME(r9, regs[9]), 841 REG_OFFSET_NAME(r10, regs[10]), 842 REG_OFFSET_NAME(r11, regs[11]), 843 REG_OFFSET_NAME(r12, regs[12]), 844 REG_OFFSET_NAME(r13, regs[13]), 845 REG_OFFSET_NAME(r14, regs[14]), 846 REG_OFFSET_NAME(r15, regs[15]), 847 REG_OFFSET_NAME(r16, regs[16]), 848 REG_OFFSET_NAME(r17, regs[17]), 849 REG_OFFSET_NAME(r18, regs[18]), 850 REG_OFFSET_NAME(r19, regs[19]), 851 REG_OFFSET_NAME(r20, regs[20]), 852 REG_OFFSET_NAME(r21, regs[21]), 853 REG_OFFSET_NAME(r22, regs[22]), 854 REG_OFFSET_NAME(r23, regs[23]), 855 REG_OFFSET_NAME(r24, regs[24]), 856 REG_OFFSET_NAME(r25, regs[25]), 857 REG_OFFSET_NAME(r26, regs[26]), 858 REG_OFFSET_NAME(r27, regs[27]), 859 REG_OFFSET_NAME(r28, regs[28]), 860 REG_OFFSET_NAME(r29, regs[29]), 861 REG_OFFSET_NAME(r30, regs[30]), 862 REG_OFFSET_NAME(r31, regs[31]), 863 REG_OFFSET_NAME(c0_status, cp0_status), 864 REG_OFFSET_NAME(hi, hi), 865 REG_OFFSET_NAME(lo, lo), 866 #ifdef CONFIG_CPU_HAS_SMARTMIPS 867 REG_OFFSET_NAME(acx, acx), 868 #endif 869 REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr), 870 REG_OFFSET_NAME(c0_cause, cp0_cause), 871 REG_OFFSET_NAME(c0_epc, cp0_epc), 872 #ifdef CONFIG_CPU_CAVIUM_OCTEON 873 REG_OFFSET_NAME(mpl0, mpl[0]), 874 REG_OFFSET_NAME(mpl1, mpl[1]), 875 REG_OFFSET_NAME(mpl2, mpl[2]), 876 REG_OFFSET_NAME(mtp0, mtp[0]), 877 REG_OFFSET_NAME(mtp1, mtp[1]), 878 REG_OFFSET_NAME(mtp2, mtp[2]), 879 #endif 880 REG_OFFSET_END, 881 }; 882 883 /** 884 * regs_query_register_offset() - query register offset from its name 885 * @name: the name of a register 886 * 887 * regs_query_register_offset() returns the offset of a register in struct 888 * pt_regs from its name. If the name is invalid, this returns -EINVAL; 889 */ 890 int regs_query_register_offset(const char *name) 891 { 892 const struct pt_regs_offset *roff; 893 for (roff = regoffset_table; roff->name != NULL; roff++) 894 if (!strcmp(roff->name, name)) 895 return roff->offset; 896 return -EINVAL; 897 } 898 899 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32) 900 901 static const struct user_regset mips_regsets[] = { 902 [REGSET_GPR] = { 903 .core_note_type = NT_PRSTATUS, 904 .n = ELF_NGREG, 905 .size = sizeof(unsigned int), 906 .align = sizeof(unsigned int), 907 .get = gpr32_get, 908 .set = gpr32_set, 909 }, 910 [REGSET_FPR] = { 911 .core_note_type = NT_PRFPREG, 912 .n = ELF_NFPREG, 913 .size = sizeof(elf_fpreg_t), 914 .align = sizeof(elf_fpreg_t), 915 .get = fpr_get, 916 .set = fpr_set, 917 }, 918 [REGSET_DSP] = { 919 .core_note_type = NT_MIPS_DSP, 920 .n = NUM_DSP_REGS + 1, 921 .size = sizeof(u32), 922 .align = sizeof(u32), 923 .get = dsp32_get, 924 .set = dsp32_set, 925 .active = dsp_active, 926 }, 927 [REGSET_FP_MODE] = { 928 .core_note_type = NT_MIPS_FP_MODE, 929 .n = 1, 930 .size = sizeof(int), 931 .align = sizeof(int), 932 .get = fp_mode_get, 933 .set = fp_mode_set, 934 }, 935 }; 936 937 static const struct user_regset_view user_mips_view = { 938 .name = "mips", 939 .e_machine = ELF_ARCH, 940 .ei_osabi = ELF_OSABI, 941 .regsets = mips_regsets, 942 .n = ARRAY_SIZE(mips_regsets), 943 }; 944 945 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */ 946 947 #ifdef CONFIG_64BIT 948 949 static const struct user_regset mips64_regsets[] = { 950 [REGSET_GPR] = { 951 .core_note_type = NT_PRSTATUS, 952 .n = ELF_NGREG, 953 .size = sizeof(unsigned long), 954 .align = sizeof(unsigned long), 955 .get = gpr64_get, 956 .set = gpr64_set, 957 }, 958 [REGSET_FPR] = { 959 .core_note_type = NT_PRFPREG, 960 .n = ELF_NFPREG, 961 .size = sizeof(elf_fpreg_t), 962 .align = sizeof(elf_fpreg_t), 963 .get = fpr_get, 964 .set = fpr_set, 965 }, 966 [REGSET_DSP] = { 967 .core_note_type = NT_MIPS_DSP, 968 .n = NUM_DSP_REGS + 1, 969 .size = sizeof(u64), 970 .align = sizeof(u64), 971 .get = dsp64_get, 972 .set = dsp64_set, 973 .active = dsp_active, 974 }, 975 [REGSET_FP_MODE] = { 976 .core_note_type = NT_MIPS_FP_MODE, 977 .n = 1, 978 .size = sizeof(int), 979 .align = sizeof(int), 980 .get = fp_mode_get, 981 .set = fp_mode_set, 982 }, 983 }; 984 985 static const struct user_regset_view user_mips64_view = { 986 .name = "mips64", 987 .e_machine = ELF_ARCH, 988 .ei_osabi = ELF_OSABI, 989 .regsets = mips64_regsets, 990 .n = ARRAY_SIZE(mips64_regsets), 991 }; 992 993 #ifdef CONFIG_MIPS32_N32 994 995 static const struct user_regset_view user_mipsn32_view = { 996 .name = "mipsn32", 997 .e_flags = EF_MIPS_ABI2, 998 .e_machine = ELF_ARCH, 999 .ei_osabi = ELF_OSABI, 1000 .regsets = mips64_regsets, 1001 .n = ARRAY_SIZE(mips64_regsets), 1002 }; 1003 1004 #endif /* CONFIG_MIPS32_N32 */ 1005 1006 #endif /* CONFIG_64BIT */ 1007 1008 const struct user_regset_view *task_user_regset_view(struct task_struct *task) 1009 { 1010 #ifdef CONFIG_32BIT 1011 return &user_mips_view; 1012 #else 1013 #ifdef CONFIG_MIPS32_O32 1014 if (test_tsk_thread_flag(task, TIF_32BIT_REGS)) 1015 return &user_mips_view; 1016 #endif 1017 #ifdef CONFIG_MIPS32_N32 1018 if (test_tsk_thread_flag(task, TIF_32BIT_ADDR)) 1019 return &user_mipsn32_view; 1020 #endif 1021 return &user_mips64_view; 1022 #endif 1023 } 1024 1025 long arch_ptrace(struct task_struct *child, long request, 1026 unsigned long addr, unsigned long data) 1027 { 1028 int ret; 1029 void __user *addrp = (void __user *) addr; 1030 void __user *datavp = (void __user *) data; 1031 unsigned long __user *datalp = (void __user *) data; 1032 1033 switch (request) { 1034 /* when I and D space are separate, these will need to be fixed. */ 1035 case PTRACE_PEEKTEXT: /* read word at location addr. */ 1036 case PTRACE_PEEKDATA: 1037 ret = generic_ptrace_peekdata(child, addr, data); 1038 break; 1039 1040 /* Read the word at location addr in the USER area. */ 1041 case PTRACE_PEEKUSR: { 1042 struct pt_regs *regs; 1043 union fpureg *fregs; 1044 unsigned long tmp = 0; 1045 1046 regs = task_pt_regs(child); 1047 ret = 0; /* Default return value. */ 1048 1049 switch (addr) { 1050 case 0 ... 31: 1051 tmp = regs->regs[addr]; 1052 break; 1053 case FPR_BASE ... FPR_BASE + 31: 1054 if (!tsk_used_math(child)) { 1055 /* FP not yet used */ 1056 tmp = -1; 1057 break; 1058 } 1059 fregs = get_fpu_regs(child); 1060 1061 #ifdef CONFIG_32BIT 1062 if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) { 1063 /* 1064 * The odd registers are actually the high 1065 * order bits of the values stored in the even 1066 * registers. 1067 */ 1068 tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE], 1069 addr & 1); 1070 break; 1071 } 1072 #endif 1073 tmp = get_fpr64(&fregs[addr - FPR_BASE], 0); 1074 break; 1075 case PC: 1076 tmp = regs->cp0_epc; 1077 break; 1078 case CAUSE: 1079 tmp = regs->cp0_cause; 1080 break; 1081 case BADVADDR: 1082 tmp = regs->cp0_badvaddr; 1083 break; 1084 case MMHI: 1085 tmp = regs->hi; 1086 break; 1087 case MMLO: 1088 tmp = regs->lo; 1089 break; 1090 #ifdef CONFIG_CPU_HAS_SMARTMIPS 1091 case ACX: 1092 tmp = regs->acx; 1093 break; 1094 #endif 1095 case FPC_CSR: 1096 tmp = child->thread.fpu.fcr31; 1097 break; 1098 case FPC_EIR: 1099 /* implementation / version register */ 1100 tmp = boot_cpu_data.fpu_id; 1101 break; 1102 case DSP_BASE ... DSP_BASE + 5: { 1103 dspreg_t *dregs; 1104 1105 if (!cpu_has_dsp) { 1106 tmp = 0; 1107 ret = -EIO; 1108 goto out; 1109 } 1110 dregs = __get_dsp_regs(child); 1111 tmp = dregs[addr - DSP_BASE]; 1112 break; 1113 } 1114 case DSP_CONTROL: 1115 if (!cpu_has_dsp) { 1116 tmp = 0; 1117 ret = -EIO; 1118 goto out; 1119 } 1120 tmp = child->thread.dsp.dspcontrol; 1121 break; 1122 default: 1123 tmp = 0; 1124 ret = -EIO; 1125 goto out; 1126 } 1127 ret = put_user(tmp, datalp); 1128 break; 1129 } 1130 1131 /* when I and D space are separate, this will have to be fixed. */ 1132 case PTRACE_POKETEXT: /* write the word at location addr. */ 1133 case PTRACE_POKEDATA: 1134 ret = generic_ptrace_pokedata(child, addr, data); 1135 break; 1136 1137 case PTRACE_POKEUSR: { 1138 struct pt_regs *regs; 1139 ret = 0; 1140 regs = task_pt_regs(child); 1141 1142 switch (addr) { 1143 case 0 ... 31: 1144 regs->regs[addr] = data; 1145 /* System call number may have been changed */ 1146 if (addr == 2) 1147 mips_syscall_update_nr(child, regs); 1148 else if (addr == 4 && 1149 mips_syscall_is_indirect(child, regs)) 1150 mips_syscall_update_nr(child, regs); 1151 break; 1152 case FPR_BASE ... FPR_BASE + 31: { 1153 union fpureg *fregs = get_fpu_regs(child); 1154 1155 init_fp_ctx(child); 1156 #ifdef CONFIG_32BIT 1157 if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) { 1158 /* 1159 * The odd registers are actually the high 1160 * order bits of the values stored in the even 1161 * registers. 1162 */ 1163 set_fpr32(&fregs[(addr & ~1) - FPR_BASE], 1164 addr & 1, data); 1165 break; 1166 } 1167 #endif 1168 set_fpr64(&fregs[addr - FPR_BASE], 0, data); 1169 break; 1170 } 1171 case PC: 1172 regs->cp0_epc = data; 1173 break; 1174 case MMHI: 1175 regs->hi = data; 1176 break; 1177 case MMLO: 1178 regs->lo = data; 1179 break; 1180 #ifdef CONFIG_CPU_HAS_SMARTMIPS 1181 case ACX: 1182 regs->acx = data; 1183 break; 1184 #endif 1185 case FPC_CSR: 1186 init_fp_ctx(child); 1187 ptrace_setfcr31(child, data); 1188 break; 1189 case DSP_BASE ... DSP_BASE + 5: { 1190 dspreg_t *dregs; 1191 1192 if (!cpu_has_dsp) { 1193 ret = -EIO; 1194 break; 1195 } 1196 1197 dregs = __get_dsp_regs(child); 1198 dregs[addr - DSP_BASE] = data; 1199 break; 1200 } 1201 case DSP_CONTROL: 1202 if (!cpu_has_dsp) { 1203 ret = -EIO; 1204 break; 1205 } 1206 child->thread.dsp.dspcontrol = data; 1207 break; 1208 default: 1209 /* The rest are not allowed. */ 1210 ret = -EIO; 1211 break; 1212 } 1213 break; 1214 } 1215 1216 case PTRACE_GETREGS: 1217 ret = ptrace_getregs(child, datavp); 1218 break; 1219 1220 case PTRACE_SETREGS: 1221 ret = ptrace_setregs(child, datavp); 1222 break; 1223 1224 case PTRACE_GETFPREGS: 1225 ret = ptrace_getfpregs(child, datavp); 1226 break; 1227 1228 case PTRACE_SETFPREGS: 1229 ret = ptrace_setfpregs(child, datavp); 1230 break; 1231 1232 case PTRACE_GET_THREAD_AREA: 1233 ret = put_user(task_thread_info(child)->tp_value, datalp); 1234 break; 1235 1236 case PTRACE_GET_WATCH_REGS: 1237 ret = ptrace_get_watch_regs(child, addrp); 1238 break; 1239 1240 case PTRACE_SET_WATCH_REGS: 1241 ret = ptrace_set_watch_regs(child, addrp); 1242 break; 1243 1244 default: 1245 ret = ptrace_request(child, request, addr, data); 1246 break; 1247 } 1248 out: 1249 return ret; 1250 } 1251 1252 /* 1253 * Notification of system call entry/exit 1254 * - triggered by current->work.syscall_trace 1255 */ 1256 asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall) 1257 { 1258 user_exit(); 1259 1260 current_thread_info()->syscall = syscall; 1261 1262 if (test_thread_flag(TIF_SYSCALL_TRACE)) { 1263 if (tracehook_report_syscall_entry(regs)) 1264 return -1; 1265 syscall = current_thread_info()->syscall; 1266 } 1267 1268 #ifdef CONFIG_SECCOMP 1269 if (unlikely(test_thread_flag(TIF_SECCOMP))) { 1270 int ret, i; 1271 struct seccomp_data sd; 1272 unsigned long args[6]; 1273 1274 sd.nr = syscall; 1275 sd.arch = syscall_get_arch(); 1276 syscall_get_arguments(current, regs, 0, 6, args); 1277 for (i = 0; i < 6; i++) 1278 sd.args[i] = args[i]; 1279 sd.instruction_pointer = KSTK_EIP(current); 1280 1281 ret = __secure_computing(&sd); 1282 if (ret == -1) 1283 return ret; 1284 syscall = current_thread_info()->syscall; 1285 } 1286 #endif 1287 1288 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) 1289 trace_sys_enter(regs, regs->regs[2]); 1290 1291 audit_syscall_entry(syscall, regs->regs[4], regs->regs[5], 1292 regs->regs[6], regs->regs[7]); 1293 1294 /* 1295 * Negative syscall numbers are mistaken for rejected syscalls, but 1296 * won't have had the return value set appropriately, so we do so now. 1297 */ 1298 if (syscall < 0) 1299 syscall_set_return_value(current, regs, -ENOSYS, 0); 1300 return syscall; 1301 } 1302 1303 /* 1304 * Notification of system call entry/exit 1305 * - triggered by current->work.syscall_trace 1306 */ 1307 asmlinkage void syscall_trace_leave(struct pt_regs *regs) 1308 { 1309 /* 1310 * We may come here right after calling schedule_user() 1311 * or do_notify_resume(), in which case we can be in RCU 1312 * user mode. 1313 */ 1314 user_exit(); 1315 1316 audit_syscall_exit(regs); 1317 1318 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) 1319 trace_sys_exit(regs, regs_return_value(regs)); 1320 1321 if (test_thread_flag(TIF_SYSCALL_TRACE)) 1322 tracehook_report_syscall_exit(regs, 0); 1323 1324 user_enter(); 1325 } 1326