1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others. 7 * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 * Copyright (C) 2004 Thiemo Seufer 10 * Copyright (C) 2013 Imagination Technologies Ltd. 11 */ 12 #include <linux/errno.h> 13 #include <linux/sched.h> 14 #include <linux/sched/debug.h> 15 #include <linux/sched/task.h> 16 #include <linux/sched/task_stack.h> 17 #include <linux/tick.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/export.h> 23 #include <linux/ptrace.h> 24 #include <linux/mman.h> 25 #include <linux/personality.h> 26 #include <linux/sys.h> 27 #include <linux/init.h> 28 #include <linux/completion.h> 29 #include <linux/kallsyms.h> 30 #include <linux/random.h> 31 #include <linux/prctl.h> 32 #include <linux/nmi.h> 33 #include <linux/cpu.h> 34 35 #include <asm/abi.h> 36 #include <asm/asm.h> 37 #include <asm/bootinfo.h> 38 #include <asm/cpu.h> 39 #include <asm/dsemul.h> 40 #include <asm/dsp.h> 41 #include <asm/fpu.h> 42 #include <asm/irq.h> 43 #include <asm/mips-cps.h> 44 #include <asm/msa.h> 45 #include <asm/mipsregs.h> 46 #include <asm/processor.h> 47 #include <asm/reg.h> 48 #include <linux/uaccess.h> 49 #include <asm/io.h> 50 #include <asm/elf.h> 51 #include <asm/isadep.h> 52 #include <asm/inst.h> 53 #include <asm/stacktrace.h> 54 #include <asm/irq_regs.h> 55 56 #ifdef CONFIG_HOTPLUG_CPU 57 void arch_cpu_idle_dead(void) 58 { 59 play_dead(); 60 } 61 #endif 62 63 asmlinkage void ret_from_fork(void); 64 asmlinkage void ret_from_kernel_thread(void); 65 66 void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) 67 { 68 unsigned long status; 69 70 /* New thread loses kernel privileges. */ 71 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK); 72 status |= KU_USER; 73 regs->cp0_status = status; 74 lose_fpu(0); 75 clear_thread_flag(TIF_MSA_CTX_LIVE); 76 clear_used_math(); 77 #ifdef CONFIG_MIPS_FP_SUPPORT 78 atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); 79 #endif 80 init_dsp(); 81 regs->cp0_epc = pc; 82 regs->regs[29] = sp; 83 } 84 85 void exit_thread(struct task_struct *tsk) 86 { 87 /* 88 * User threads may have allocated a delay slot emulation frame. 89 * If so, clean up that allocation. 90 */ 91 if (!(current->flags & PF_KTHREAD)) 92 dsemul_thread_cleanup(tsk); 93 } 94 95 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 96 { 97 /* 98 * Save any process state which is live in hardware registers to the 99 * parent context prior to duplication. This prevents the new child 100 * state becoming stale if the parent is preempted before copy_thread() 101 * gets a chance to save the parent's live hardware registers to the 102 * child context. 103 */ 104 preempt_disable(); 105 106 if (is_msa_enabled()) 107 save_msa(current); 108 else if (is_fpu_owner()) 109 _save_fp(current); 110 111 save_dsp(current); 112 113 preempt_enable(); 114 115 *dst = *src; 116 return 0; 117 } 118 119 /* 120 * Copy architecture-specific thread state 121 */ 122 int copy_thread_tls(unsigned long clone_flags, unsigned long usp, 123 unsigned long kthread_arg, struct task_struct *p, unsigned long tls) 124 { 125 struct thread_info *ti = task_thread_info(p); 126 struct pt_regs *childregs, *regs = current_pt_regs(); 127 unsigned long childksp; 128 129 childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32; 130 131 /* set up new TSS. */ 132 childregs = (struct pt_regs *) childksp - 1; 133 /* Put the stack after the struct pt_regs. */ 134 childksp = (unsigned long) childregs; 135 p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1); 136 if (unlikely(p->flags & PF_KTHREAD)) { 137 /* kernel thread */ 138 unsigned long status = p->thread.cp0_status; 139 memset(childregs, 0, sizeof(struct pt_regs)); 140 ti->addr_limit = KERNEL_DS; 141 p->thread.reg16 = usp; /* fn */ 142 p->thread.reg17 = kthread_arg; 143 p->thread.reg29 = childksp; 144 p->thread.reg31 = (unsigned long) ret_from_kernel_thread; 145 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 146 status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) | 147 ((status & (ST0_KUC | ST0_IEC)) << 2); 148 #else 149 status |= ST0_EXL; 150 #endif 151 childregs->cp0_status = status; 152 return 0; 153 } 154 155 /* user thread */ 156 *childregs = *regs; 157 childregs->regs[7] = 0; /* Clear error flag */ 158 childregs->regs[2] = 0; /* Child gets zero as return value */ 159 if (usp) 160 childregs->regs[29] = usp; 161 ti->addr_limit = USER_DS; 162 163 p->thread.reg29 = (unsigned long) childregs; 164 p->thread.reg31 = (unsigned long) ret_from_fork; 165 166 /* 167 * New tasks lose permission to use the fpu. This accelerates context 168 * switching for most programs since they don't use the fpu. 169 */ 170 childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); 171 172 clear_tsk_thread_flag(p, TIF_USEDFPU); 173 clear_tsk_thread_flag(p, TIF_USEDMSA); 174 clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE); 175 176 #ifdef CONFIG_MIPS_MT_FPAFF 177 clear_tsk_thread_flag(p, TIF_FPUBOUND); 178 #endif /* CONFIG_MIPS_MT_FPAFF */ 179 180 #ifdef CONFIG_MIPS_FP_SUPPORT 181 atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); 182 #endif 183 184 if (clone_flags & CLONE_SETTLS) 185 ti->tp_value = tls; 186 187 return 0; 188 } 189 190 #ifdef CONFIG_STACKPROTECTOR 191 #include <linux/stackprotector.h> 192 unsigned long __stack_chk_guard __read_mostly; 193 EXPORT_SYMBOL(__stack_chk_guard); 194 #endif 195 196 struct mips_frame_info { 197 void *func; 198 unsigned long func_size; 199 int frame_size; 200 int pc_offset; 201 }; 202 203 #define J_TARGET(pc,target) \ 204 (((unsigned long)(pc) & 0xf0000000) | ((target) << 2)) 205 206 static inline int is_ra_save_ins(union mips_instruction *ip, int *poff) 207 { 208 #ifdef CONFIG_CPU_MICROMIPS 209 /* 210 * swsp ra,offset 211 * swm16 reglist,offset(sp) 212 * swm32 reglist,offset(sp) 213 * sw32 ra,offset(sp) 214 * jradiussp - NOT SUPPORTED 215 * 216 * microMIPS is way more fun... 217 */ 218 if (mm_insn_16bit(ip->word >> 16)) { 219 switch (ip->mm16_r5_format.opcode) { 220 case mm_swsp16_op: 221 if (ip->mm16_r5_format.rt != 31) 222 return 0; 223 224 *poff = ip->mm16_r5_format.imm; 225 *poff = (*poff << 2) / sizeof(ulong); 226 return 1; 227 228 case mm_pool16c_op: 229 switch (ip->mm16_m_format.func) { 230 case mm_swm16_op: 231 *poff = ip->mm16_m_format.imm; 232 *poff += 1 + ip->mm16_m_format.rlist; 233 *poff = (*poff << 2) / sizeof(ulong); 234 return 1; 235 236 default: 237 return 0; 238 } 239 240 default: 241 return 0; 242 } 243 } 244 245 switch (ip->i_format.opcode) { 246 case mm_sw32_op: 247 if (ip->i_format.rs != 29) 248 return 0; 249 if (ip->i_format.rt != 31) 250 return 0; 251 252 *poff = ip->i_format.simmediate / sizeof(ulong); 253 return 1; 254 255 case mm_pool32b_op: 256 switch (ip->mm_m_format.func) { 257 case mm_swm32_func: 258 if (ip->mm_m_format.rd < 0x10) 259 return 0; 260 if (ip->mm_m_format.base != 29) 261 return 0; 262 263 *poff = ip->mm_m_format.simmediate; 264 *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32); 265 *poff /= sizeof(ulong); 266 return 1; 267 default: 268 return 0; 269 } 270 271 default: 272 return 0; 273 } 274 #else 275 /* sw / sd $ra, offset($sp) */ 276 if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) && 277 ip->i_format.rs == 29 && ip->i_format.rt == 31) { 278 *poff = ip->i_format.simmediate / sizeof(ulong); 279 return 1; 280 } 281 282 return 0; 283 #endif 284 } 285 286 static inline int is_jump_ins(union mips_instruction *ip) 287 { 288 #ifdef CONFIG_CPU_MICROMIPS 289 /* 290 * jr16,jrc,jalr16,jalr16 291 * jal 292 * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb 293 * jraddiusp - NOT SUPPORTED 294 * 295 * microMIPS is kind of more fun... 296 */ 297 if (mm_insn_16bit(ip->word >> 16)) { 298 if ((ip->mm16_r5_format.opcode == mm_pool16c_op && 299 (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op)) 300 return 1; 301 return 0; 302 } 303 304 if (ip->j_format.opcode == mm_j32_op) 305 return 1; 306 if (ip->j_format.opcode == mm_jal32_op) 307 return 1; 308 if (ip->r_format.opcode != mm_pool32a_op || 309 ip->r_format.func != mm_pool32axf_op) 310 return 0; 311 return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op; 312 #else 313 if (ip->j_format.opcode == j_op) 314 return 1; 315 if (ip->j_format.opcode == jal_op) 316 return 1; 317 if (ip->r_format.opcode != spec_op) 318 return 0; 319 return ip->r_format.func == jalr_op || ip->r_format.func == jr_op; 320 #endif 321 } 322 323 static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size) 324 { 325 #ifdef CONFIG_CPU_MICROMIPS 326 unsigned short tmp; 327 328 /* 329 * addiusp -imm 330 * addius5 sp,-imm 331 * addiu32 sp,sp,-imm 332 * jradiussp - NOT SUPPORTED 333 * 334 * microMIPS is not more fun... 335 */ 336 if (mm_insn_16bit(ip->word >> 16)) { 337 if (ip->mm16_r3_format.opcode == mm_pool16d_op && 338 ip->mm16_r3_format.simmediate & mm_addiusp_func) { 339 tmp = ip->mm_b0_format.simmediate >> 1; 340 tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100; 341 if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */ 342 tmp ^= 0x100; 343 *frame_size = -(signed short)(tmp << 2); 344 return 1; 345 } 346 if (ip->mm16_r5_format.opcode == mm_pool16d_op && 347 ip->mm16_r5_format.rt == 29) { 348 tmp = ip->mm16_r5_format.imm >> 1; 349 *frame_size = -(signed short)(tmp & 0xf); 350 return 1; 351 } 352 return 0; 353 } 354 355 if (ip->mm_i_format.opcode == mm_addiu32_op && 356 ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) { 357 *frame_size = -ip->i_format.simmediate; 358 return 1; 359 } 360 #else 361 /* addiu/daddiu sp,sp,-imm */ 362 if (ip->i_format.rs != 29 || ip->i_format.rt != 29) 363 return 0; 364 365 if (ip->i_format.opcode == addiu_op || 366 ip->i_format.opcode == daddiu_op) { 367 *frame_size = -ip->i_format.simmediate; 368 return 1; 369 } 370 #endif 371 return 0; 372 } 373 374 static int get_frame_info(struct mips_frame_info *info) 375 { 376 bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS); 377 union mips_instruction insn, *ip; 378 const unsigned int max_insns = 128; 379 unsigned int last_insn_size = 0; 380 unsigned int i; 381 bool saw_jump = false; 382 383 info->pc_offset = -1; 384 info->frame_size = 0; 385 386 ip = (void *)msk_isa16_mode((ulong)info->func); 387 if (!ip) 388 goto err; 389 390 for (i = 0; i < max_insns; i++) { 391 ip = (void *)ip + last_insn_size; 392 393 if (is_mmips && mm_insn_16bit(ip->halfword[0])) { 394 insn.word = ip->halfword[0] << 16; 395 last_insn_size = 2; 396 } else if (is_mmips) { 397 insn.word = ip->halfword[0] << 16 | ip->halfword[1]; 398 last_insn_size = 4; 399 } else { 400 insn.word = ip->word; 401 last_insn_size = 4; 402 } 403 404 if (!info->frame_size) { 405 is_sp_move_ins(&insn, &info->frame_size); 406 continue; 407 } else if (!saw_jump && is_jump_ins(ip)) { 408 /* 409 * If we see a jump instruction, we are finished 410 * with the frame save. 411 * 412 * Some functions can have a shortcut return at 413 * the beginning of the function, so don't start 414 * looking for jump instruction until we see the 415 * frame setup. 416 * 417 * The RA save instruction can get put into the 418 * delay slot of the jump instruction, so look 419 * at the next instruction, too. 420 */ 421 saw_jump = true; 422 continue; 423 } 424 if (info->pc_offset == -1 && 425 is_ra_save_ins(&insn, &info->pc_offset)) 426 break; 427 if (saw_jump) 428 break; 429 } 430 if (info->frame_size && info->pc_offset >= 0) /* nested */ 431 return 0; 432 if (info->pc_offset < 0) /* leaf */ 433 return 1; 434 /* prologue seems bogus... */ 435 err: 436 return -1; 437 } 438 439 static struct mips_frame_info schedule_mfi __read_mostly; 440 441 #ifdef CONFIG_KALLSYMS 442 static unsigned long get___schedule_addr(void) 443 { 444 return kallsyms_lookup_name("__schedule"); 445 } 446 #else 447 static unsigned long get___schedule_addr(void) 448 { 449 union mips_instruction *ip = (void *)schedule; 450 int max_insns = 8; 451 int i; 452 453 for (i = 0; i < max_insns; i++, ip++) { 454 if (ip->j_format.opcode == j_op) 455 return J_TARGET(ip, ip->j_format.target); 456 } 457 return 0; 458 } 459 #endif 460 461 static int __init frame_info_init(void) 462 { 463 unsigned long size = 0; 464 #ifdef CONFIG_KALLSYMS 465 unsigned long ofs; 466 #endif 467 unsigned long addr; 468 469 addr = get___schedule_addr(); 470 if (!addr) 471 addr = (unsigned long)schedule; 472 473 #ifdef CONFIG_KALLSYMS 474 kallsyms_lookup_size_offset(addr, &size, &ofs); 475 #endif 476 schedule_mfi.func = (void *)addr; 477 schedule_mfi.func_size = size; 478 479 get_frame_info(&schedule_mfi); 480 481 /* 482 * Without schedule() frame info, result given by 483 * thread_saved_pc() and get_wchan() are not reliable. 484 */ 485 if (schedule_mfi.pc_offset < 0) 486 printk("Can't analyze schedule() prologue at %p\n", schedule); 487 488 return 0; 489 } 490 491 arch_initcall(frame_info_init); 492 493 /* 494 * Return saved PC of a blocked thread. 495 */ 496 static unsigned long thread_saved_pc(struct task_struct *tsk) 497 { 498 struct thread_struct *t = &tsk->thread; 499 500 /* New born processes are a special case */ 501 if (t->reg31 == (unsigned long) ret_from_fork) 502 return t->reg31; 503 if (schedule_mfi.pc_offset < 0) 504 return 0; 505 return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset]; 506 } 507 508 509 #ifdef CONFIG_KALLSYMS 510 /* generic stack unwinding function */ 511 unsigned long notrace unwind_stack_by_address(unsigned long stack_page, 512 unsigned long *sp, 513 unsigned long pc, 514 unsigned long *ra) 515 { 516 unsigned long low, high, irq_stack_high; 517 struct mips_frame_info info; 518 unsigned long size, ofs; 519 struct pt_regs *regs; 520 int leaf; 521 522 if (!stack_page) 523 return 0; 524 525 /* 526 * IRQ stacks start at IRQ_STACK_START 527 * task stacks at THREAD_SIZE - 32 528 */ 529 low = stack_page; 530 if (!preemptible() && on_irq_stack(raw_smp_processor_id(), *sp)) { 531 high = stack_page + IRQ_STACK_START; 532 irq_stack_high = high; 533 } else { 534 high = stack_page + THREAD_SIZE - 32; 535 irq_stack_high = 0; 536 } 537 538 /* 539 * If we reached the top of the interrupt stack, start unwinding 540 * the interrupted task stack. 541 */ 542 if (unlikely(*sp == irq_stack_high)) { 543 unsigned long task_sp = *(unsigned long *)*sp; 544 545 /* 546 * Check that the pointer saved in the IRQ stack head points to 547 * something within the stack of the current task 548 */ 549 if (!object_is_on_stack((void *)task_sp)) 550 return 0; 551 552 /* 553 * Follow pointer to tasks kernel stack frame where interrupted 554 * state was saved. 555 */ 556 regs = (struct pt_regs *)task_sp; 557 pc = regs->cp0_epc; 558 if (!user_mode(regs) && __kernel_text_address(pc)) { 559 *sp = regs->regs[29]; 560 *ra = regs->regs[31]; 561 return pc; 562 } 563 return 0; 564 } 565 if (!kallsyms_lookup_size_offset(pc, &size, &ofs)) 566 return 0; 567 /* 568 * Return ra if an exception occurred at the first instruction 569 */ 570 if (unlikely(ofs == 0)) { 571 pc = *ra; 572 *ra = 0; 573 return pc; 574 } 575 576 info.func = (void *)(pc - ofs); 577 info.func_size = ofs; /* analyze from start to ofs */ 578 leaf = get_frame_info(&info); 579 if (leaf < 0) 580 return 0; 581 582 if (*sp < low || *sp + info.frame_size > high) 583 return 0; 584 585 if (leaf) 586 /* 587 * For some extreme cases, get_frame_info() can 588 * consider wrongly a nested function as a leaf 589 * one. In that cases avoid to return always the 590 * same value. 591 */ 592 pc = pc != *ra ? *ra : 0; 593 else 594 pc = ((unsigned long *)(*sp))[info.pc_offset]; 595 596 *sp += info.frame_size; 597 *ra = 0; 598 return __kernel_text_address(pc) ? pc : 0; 599 } 600 EXPORT_SYMBOL(unwind_stack_by_address); 601 602 /* used by show_backtrace() */ 603 unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, 604 unsigned long pc, unsigned long *ra) 605 { 606 unsigned long stack_page = 0; 607 int cpu; 608 609 for_each_possible_cpu(cpu) { 610 if (on_irq_stack(cpu, *sp)) { 611 stack_page = (unsigned long)irq_stack[cpu]; 612 break; 613 } 614 } 615 616 if (!stack_page) 617 stack_page = (unsigned long)task_stack_page(task); 618 619 return unwind_stack_by_address(stack_page, sp, pc, ra); 620 } 621 #endif 622 623 /* 624 * get_wchan - a maintenance nightmare^W^Wpain in the ass ... 625 */ 626 unsigned long get_wchan(struct task_struct *task) 627 { 628 unsigned long pc = 0; 629 #ifdef CONFIG_KALLSYMS 630 unsigned long sp; 631 unsigned long ra = 0; 632 #endif 633 634 if (!task || task == current || task->state == TASK_RUNNING) 635 goto out; 636 if (!task_stack_page(task)) 637 goto out; 638 639 pc = thread_saved_pc(task); 640 641 #ifdef CONFIG_KALLSYMS 642 sp = task->thread.reg29 + schedule_mfi.frame_size; 643 644 while (in_sched_functions(pc)) 645 pc = unwind_stack(task, &sp, pc, &ra); 646 #endif 647 648 out: 649 return pc; 650 } 651 652 unsigned long mips_stack_top(void) 653 { 654 unsigned long top = TASK_SIZE & PAGE_MASK; 655 656 if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT)) { 657 /* One page for branch delay slot "emulation" */ 658 top -= PAGE_SIZE; 659 } 660 661 /* Space for the VDSO, data page & GIC user page */ 662 top -= PAGE_ALIGN(current->thread.abi->vdso->size); 663 top -= PAGE_SIZE; 664 top -= mips_gic_present() ? PAGE_SIZE : 0; 665 666 /* Space for cache colour alignment */ 667 if (cpu_has_dc_aliases) 668 top -= shm_align_mask + 1; 669 670 /* Space to randomize the VDSO base */ 671 if (current->flags & PF_RANDOMIZE) 672 top -= VDSO_RANDOMIZE_SIZE; 673 674 return top; 675 } 676 677 /* 678 * Don't forget that the stack pointer must be aligned on a 8 bytes 679 * boundary for 32-bits ABI and 16 bytes for 64-bits ABI. 680 */ 681 unsigned long arch_align_stack(unsigned long sp) 682 { 683 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 684 sp -= get_random_int() & ~PAGE_MASK; 685 686 return sp & ALMASK; 687 } 688 689 static DEFINE_PER_CPU(call_single_data_t, backtrace_csd); 690 static struct cpumask backtrace_csd_busy; 691 692 static void handle_backtrace(void *info) 693 { 694 nmi_cpu_backtrace(get_irq_regs()); 695 cpumask_clear_cpu(smp_processor_id(), &backtrace_csd_busy); 696 } 697 698 static void raise_backtrace(cpumask_t *mask) 699 { 700 call_single_data_t *csd; 701 int cpu; 702 703 for_each_cpu(cpu, mask) { 704 /* 705 * If we previously sent an IPI to the target CPU & it hasn't 706 * cleared its bit in the busy cpumask then it didn't handle 707 * our previous IPI & it's not safe for us to reuse the 708 * call_single_data_t. 709 */ 710 if (cpumask_test_and_set_cpu(cpu, &backtrace_csd_busy)) { 711 pr_warn("Unable to send backtrace IPI to CPU%u - perhaps it hung?\n", 712 cpu); 713 continue; 714 } 715 716 csd = &per_cpu(backtrace_csd, cpu); 717 csd->func = handle_backtrace; 718 smp_call_function_single_async(cpu, csd); 719 } 720 } 721 722 void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) 723 { 724 nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace); 725 } 726 727 int mips_get_process_fp_mode(struct task_struct *task) 728 { 729 int value = 0; 730 731 if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS)) 732 value |= PR_FP_MODE_FR; 733 if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS)) 734 value |= PR_FP_MODE_FRE; 735 736 return value; 737 } 738 739 static long prepare_for_fp_mode_switch(void *unused) 740 { 741 /* 742 * This is icky, but we use this to simply ensure that all CPUs have 743 * context switched, regardless of whether they were previously running 744 * kernel or user code. This ensures that no CPU that a mode-switching 745 * program may execute on keeps its FPU enabled (& in the old mode) 746 * throughout the mode switch. 747 */ 748 return 0; 749 } 750 751 int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) 752 { 753 const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE; 754 struct task_struct *t; 755 struct cpumask process_cpus; 756 int cpu; 757 758 /* If nothing to change, return right away, successfully. */ 759 if (value == mips_get_process_fp_mode(task)) 760 return 0; 761 762 /* Only accept a mode change if 64-bit FP enabled for o32. */ 763 if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT)) 764 return -EOPNOTSUPP; 765 766 /* And only for o32 tasks. */ 767 if (IS_ENABLED(CONFIG_64BIT) && !test_thread_flag(TIF_32BIT_REGS)) 768 return -EOPNOTSUPP; 769 770 /* Check the value is valid */ 771 if (value & ~known_bits) 772 return -EOPNOTSUPP; 773 774 /* Setting FRE without FR is not supported. */ 775 if ((value & (PR_FP_MODE_FR | PR_FP_MODE_FRE)) == PR_FP_MODE_FRE) 776 return -EOPNOTSUPP; 777 778 /* Avoid inadvertently triggering emulation */ 779 if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu && 780 !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64)) 781 return -EOPNOTSUPP; 782 if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre) 783 return -EOPNOTSUPP; 784 785 /* FR = 0 not supported in MIPS R6 */ 786 if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6) 787 return -EOPNOTSUPP; 788 789 /* Indicate the new FP mode in each thread */ 790 for_each_thread(task, t) { 791 /* Update desired FP register width */ 792 if (value & PR_FP_MODE_FR) { 793 clear_tsk_thread_flag(t, TIF_32BIT_FPREGS); 794 } else { 795 set_tsk_thread_flag(t, TIF_32BIT_FPREGS); 796 clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE); 797 } 798 799 /* Update desired FP single layout */ 800 if (value & PR_FP_MODE_FRE) 801 set_tsk_thread_flag(t, TIF_HYBRID_FPREGS); 802 else 803 clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS); 804 } 805 806 /* 807 * We need to ensure that all threads in the process have switched mode 808 * before returning, in order to allow userland to not worry about 809 * races. We can do this by forcing all CPUs that any thread in the 810 * process may be running on to schedule something else - in this case 811 * prepare_for_fp_mode_switch(). 812 * 813 * We begin by generating a mask of all CPUs that any thread in the 814 * process may be running on. 815 */ 816 cpumask_clear(&process_cpus); 817 for_each_thread(task, t) 818 cpumask_set_cpu(task_cpu(t), &process_cpus); 819 820 /* 821 * Now we schedule prepare_for_fp_mode_switch() on each of those CPUs. 822 * 823 * The CPUs may have rescheduled already since we switched mode or 824 * generated the cpumask, but that doesn't matter. If the task in this 825 * process is scheduled out then our scheduling 826 * prepare_for_fp_mode_switch() will simply be redundant. If it's 827 * scheduled in then it will already have picked up the new FP mode 828 * whilst doing so. 829 */ 830 get_online_cpus(); 831 for_each_cpu_and(cpu, &process_cpus, cpu_online_mask) 832 work_on_cpu(cpu, prepare_for_fp_mode_switch, NULL); 833 put_online_cpus(); 834 835 return 0; 836 } 837 838 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32) 839 void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs) 840 { 841 unsigned int i; 842 843 for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) { 844 /* k0/k1 are copied as zero. */ 845 if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27) 846 uregs[i] = 0; 847 else 848 uregs[i] = regs->regs[i - MIPS32_EF_R0]; 849 } 850 851 uregs[MIPS32_EF_LO] = regs->lo; 852 uregs[MIPS32_EF_HI] = regs->hi; 853 uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc; 854 uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr; 855 uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status; 856 uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause; 857 } 858 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */ 859 860 #ifdef CONFIG_64BIT 861 void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs) 862 { 863 unsigned int i; 864 865 for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) { 866 /* k0/k1 are copied as zero. */ 867 if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27) 868 uregs[i] = 0; 869 else 870 uregs[i] = regs->regs[i - MIPS64_EF_R0]; 871 } 872 873 uregs[MIPS64_EF_LO] = regs->lo; 874 uregs[MIPS64_EF_HI] = regs->hi; 875 uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc; 876 uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr; 877 uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status; 878 uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause; 879 } 880 #endif /* CONFIG_64BIT */ 881