1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others. 7 * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 * Copyright (C) 2004 Thiemo Seufer 10 * Copyright (C) 2013 Imagination Technologies Ltd. 11 */ 12 #include <linux/errno.h> 13 #include <linux/sched.h> 14 #include <linux/tick.h> 15 #include <linux/kernel.h> 16 #include <linux/mm.h> 17 #include <linux/stddef.h> 18 #include <linux/unistd.h> 19 #include <linux/export.h> 20 #include <linux/ptrace.h> 21 #include <linux/mman.h> 22 #include <linux/personality.h> 23 #include <linux/sys.h> 24 #include <linux/init.h> 25 #include <linux/completion.h> 26 #include <linux/kallsyms.h> 27 #include <linux/random.h> 28 #include <linux/prctl.h> 29 30 #include <asm/asm.h> 31 #include <asm/bootinfo.h> 32 #include <asm/cpu.h> 33 #include <asm/dsemul.h> 34 #include <asm/dsp.h> 35 #include <asm/fpu.h> 36 #include <asm/irq.h> 37 #include <asm/msa.h> 38 #include <asm/pgtable.h> 39 #include <asm/mipsregs.h> 40 #include <asm/processor.h> 41 #include <asm/reg.h> 42 #include <linux/uaccess.h> 43 #include <asm/io.h> 44 #include <asm/elf.h> 45 #include <asm/isadep.h> 46 #include <asm/inst.h> 47 #include <asm/stacktrace.h> 48 #include <asm/irq_regs.h> 49 50 #ifdef CONFIG_HOTPLUG_CPU 51 void arch_cpu_idle_dead(void) 52 { 53 play_dead(); 54 } 55 #endif 56 57 asmlinkage void ret_from_fork(void); 58 asmlinkage void ret_from_kernel_thread(void); 59 60 void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) 61 { 62 unsigned long status; 63 64 /* New thread loses kernel privileges. */ 65 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK); 66 status |= KU_USER; 67 regs->cp0_status = status; 68 lose_fpu(0); 69 clear_thread_flag(TIF_MSA_CTX_LIVE); 70 clear_used_math(); 71 atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); 72 init_dsp(); 73 regs->cp0_epc = pc; 74 regs->regs[29] = sp; 75 } 76 77 void exit_thread(struct task_struct *tsk) 78 { 79 /* 80 * User threads may have allocated a delay slot emulation frame. 81 * If so, clean up that allocation. 82 */ 83 if (!(current->flags & PF_KTHREAD)) 84 dsemul_thread_cleanup(tsk); 85 } 86 87 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 88 { 89 /* 90 * Save any process state which is live in hardware registers to the 91 * parent context prior to duplication. This prevents the new child 92 * state becoming stale if the parent is preempted before copy_thread() 93 * gets a chance to save the parent's live hardware registers to the 94 * child context. 95 */ 96 preempt_disable(); 97 98 if (is_msa_enabled()) 99 save_msa(current); 100 else if (is_fpu_owner()) 101 _save_fp(current); 102 103 save_dsp(current); 104 105 preempt_enable(); 106 107 *dst = *src; 108 return 0; 109 } 110 111 /* 112 * Copy architecture-specific thread state 113 */ 114 int copy_thread(unsigned long clone_flags, unsigned long usp, 115 unsigned long kthread_arg, struct task_struct *p) 116 { 117 struct thread_info *ti = task_thread_info(p); 118 struct pt_regs *childregs, *regs = current_pt_regs(); 119 unsigned long childksp; 120 p->set_child_tid = p->clear_child_tid = NULL; 121 122 childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32; 123 124 /* set up new TSS. */ 125 childregs = (struct pt_regs *) childksp - 1; 126 /* Put the stack after the struct pt_regs. */ 127 childksp = (unsigned long) childregs; 128 p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1); 129 if (unlikely(p->flags & PF_KTHREAD)) { 130 /* kernel thread */ 131 unsigned long status = p->thread.cp0_status; 132 memset(childregs, 0, sizeof(struct pt_regs)); 133 ti->addr_limit = KERNEL_DS; 134 p->thread.reg16 = usp; /* fn */ 135 p->thread.reg17 = kthread_arg; 136 p->thread.reg29 = childksp; 137 p->thread.reg31 = (unsigned long) ret_from_kernel_thread; 138 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 139 status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) | 140 ((status & (ST0_KUC | ST0_IEC)) << 2); 141 #else 142 status |= ST0_EXL; 143 #endif 144 childregs->cp0_status = status; 145 return 0; 146 } 147 148 /* user thread */ 149 *childregs = *regs; 150 childregs->regs[7] = 0; /* Clear error flag */ 151 childregs->regs[2] = 0; /* Child gets zero as return value */ 152 if (usp) 153 childregs->regs[29] = usp; 154 ti->addr_limit = USER_DS; 155 156 p->thread.reg29 = (unsigned long) childregs; 157 p->thread.reg31 = (unsigned long) ret_from_fork; 158 159 /* 160 * New tasks lose permission to use the fpu. This accelerates context 161 * switching for most programs since they don't use the fpu. 162 */ 163 childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); 164 165 clear_tsk_thread_flag(p, TIF_USEDFPU); 166 clear_tsk_thread_flag(p, TIF_USEDMSA); 167 clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE); 168 169 #ifdef CONFIG_MIPS_MT_FPAFF 170 clear_tsk_thread_flag(p, TIF_FPUBOUND); 171 #endif /* CONFIG_MIPS_MT_FPAFF */ 172 173 atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); 174 175 if (clone_flags & CLONE_SETTLS) 176 ti->tp_value = regs->regs[7]; 177 178 return 0; 179 } 180 181 #ifdef CONFIG_CC_STACKPROTECTOR 182 #include <linux/stackprotector.h> 183 unsigned long __stack_chk_guard __read_mostly; 184 EXPORT_SYMBOL(__stack_chk_guard); 185 #endif 186 187 struct mips_frame_info { 188 void *func; 189 unsigned long func_size; 190 int frame_size; 191 int pc_offset; 192 }; 193 194 #define J_TARGET(pc,target) \ 195 (((unsigned long)(pc) & 0xf0000000) | ((target) << 2)) 196 197 static inline int is_ra_save_ins(union mips_instruction *ip, int *poff) 198 { 199 #ifdef CONFIG_CPU_MICROMIPS 200 /* 201 * swsp ra,offset 202 * swm16 reglist,offset(sp) 203 * swm32 reglist,offset(sp) 204 * sw32 ra,offset(sp) 205 * jradiussp - NOT SUPPORTED 206 * 207 * microMIPS is way more fun... 208 */ 209 if (mm_insn_16bit(ip->halfword[1])) { 210 switch (ip->mm16_r5_format.opcode) { 211 case mm_swsp16_op: 212 if (ip->mm16_r5_format.rt != 31) 213 return 0; 214 215 *poff = ip->mm16_r5_format.simmediate; 216 *poff = (*poff << 2) / sizeof(ulong); 217 return 1; 218 219 case mm_pool16c_op: 220 switch (ip->mm16_m_format.func) { 221 case mm_swm16_op: 222 *poff = ip->mm16_m_format.imm; 223 *poff += 1 + ip->mm16_m_format.rlist; 224 *poff = (*poff << 2) / sizeof(ulong); 225 return 1; 226 227 default: 228 return 0; 229 } 230 231 default: 232 return 0; 233 } 234 } 235 236 switch (ip->i_format.opcode) { 237 case mm_sw32_op: 238 if (ip->i_format.rs != 29) 239 return 0; 240 if (ip->i_format.rt != 31) 241 return 0; 242 243 *poff = ip->i_format.simmediate / sizeof(ulong); 244 return 1; 245 246 case mm_pool32b_op: 247 switch (ip->mm_m_format.func) { 248 case mm_swm32_func: 249 if (ip->mm_m_format.rd < 0x10) 250 return 0; 251 if (ip->mm_m_format.base != 29) 252 return 0; 253 254 *poff = ip->mm_m_format.simmediate; 255 *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32); 256 *poff /= sizeof(ulong); 257 return 1; 258 default: 259 return 0; 260 } 261 262 default: 263 return 0; 264 } 265 #else 266 /* sw / sd $ra, offset($sp) */ 267 if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) && 268 ip->i_format.rs == 29 && ip->i_format.rt == 31) { 269 *poff = ip->i_format.simmediate / sizeof(ulong); 270 return 1; 271 } 272 273 return 0; 274 #endif 275 } 276 277 static inline int is_jump_ins(union mips_instruction *ip) 278 { 279 #ifdef CONFIG_CPU_MICROMIPS 280 /* 281 * jr16,jrc,jalr16,jalr16 282 * jal 283 * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb 284 * jraddiusp - NOT SUPPORTED 285 * 286 * microMIPS is kind of more fun... 287 */ 288 if (mm_insn_16bit(ip->halfword[1])) { 289 if ((ip->mm16_r5_format.opcode == mm_pool16c_op && 290 (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op)) 291 return 1; 292 return 0; 293 } 294 295 if (ip->j_format.opcode == mm_j32_op) 296 return 1; 297 if (ip->j_format.opcode == mm_jal32_op) 298 return 1; 299 if (ip->r_format.opcode != mm_pool32a_op || 300 ip->r_format.func != mm_pool32axf_op) 301 return 0; 302 return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op; 303 #else 304 if (ip->j_format.opcode == j_op) 305 return 1; 306 if (ip->j_format.opcode == jal_op) 307 return 1; 308 if (ip->r_format.opcode != spec_op) 309 return 0; 310 return ip->r_format.func == jalr_op || ip->r_format.func == jr_op; 311 #endif 312 } 313 314 static inline int is_sp_move_ins(union mips_instruction *ip) 315 { 316 #ifdef CONFIG_CPU_MICROMIPS 317 /* 318 * addiusp -imm 319 * addius5 sp,-imm 320 * addiu32 sp,sp,-imm 321 * jradiussp - NOT SUPPORTED 322 * 323 * microMIPS is not more fun... 324 */ 325 if (mm_insn_16bit(ip->halfword[1])) { 326 return (ip->mm16_r3_format.opcode == mm_pool16d_op && 327 ip->mm16_r3_format.simmediate && mm_addiusp_func) || 328 (ip->mm16_r5_format.opcode == mm_pool16d_op && 329 ip->mm16_r5_format.rt == 29); 330 } 331 332 return ip->mm_i_format.opcode == mm_addiu32_op && 333 ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29; 334 #else 335 /* addiu/daddiu sp,sp,-imm */ 336 if (ip->i_format.rs != 29 || ip->i_format.rt != 29) 337 return 0; 338 if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op) 339 return 1; 340 #endif 341 return 0; 342 } 343 344 static int get_frame_info(struct mips_frame_info *info) 345 { 346 bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS); 347 union mips_instruction insn, *ip, *ip_end; 348 const unsigned int max_insns = 128; 349 unsigned int i; 350 351 info->pc_offset = -1; 352 info->frame_size = 0; 353 354 ip = (void *)msk_isa16_mode((ulong)info->func); 355 if (!ip) 356 goto err; 357 358 ip_end = (void *)ip + info->func_size; 359 360 for (i = 0; i < max_insns && ip < ip_end; i++, ip++) { 361 if (is_mmips && mm_insn_16bit(ip->halfword[0])) { 362 insn.halfword[0] = 0; 363 insn.halfword[1] = ip->halfword[0]; 364 } else if (is_mmips) { 365 insn.halfword[0] = ip->halfword[1]; 366 insn.halfword[1] = ip->halfword[0]; 367 } else { 368 insn.word = ip->word; 369 } 370 371 if (is_jump_ins(&insn)) 372 break; 373 374 if (!info->frame_size) { 375 if (is_sp_move_ins(&insn)) 376 { 377 #ifdef CONFIG_CPU_MICROMIPS 378 if (mm_insn_16bit(ip->halfword[0])) 379 { 380 unsigned short tmp; 381 382 if (ip->halfword[0] & mm_addiusp_func) 383 { 384 tmp = (((ip->halfword[0] >> 1) & 0x1ff) << 2); 385 info->frame_size = -(signed short)(tmp | ((tmp & 0x100) ? 0xfe00 : 0)); 386 } else { 387 tmp = (ip->halfword[0] >> 1); 388 info->frame_size = -(signed short)(tmp & 0xf); 389 } 390 ip = (void *) &ip->halfword[1]; 391 ip--; 392 } else 393 #endif 394 info->frame_size = - ip->i_format.simmediate; 395 } 396 continue; 397 } 398 if (info->pc_offset == -1 && 399 is_ra_save_ins(&insn, &info->pc_offset)) 400 break; 401 } 402 if (info->frame_size && info->pc_offset >= 0) /* nested */ 403 return 0; 404 if (info->pc_offset < 0) /* leaf */ 405 return 1; 406 /* prologue seems bogus... */ 407 err: 408 return -1; 409 } 410 411 static struct mips_frame_info schedule_mfi __read_mostly; 412 413 #ifdef CONFIG_KALLSYMS 414 static unsigned long get___schedule_addr(void) 415 { 416 return kallsyms_lookup_name("__schedule"); 417 } 418 #else 419 static unsigned long get___schedule_addr(void) 420 { 421 union mips_instruction *ip = (void *)schedule; 422 int max_insns = 8; 423 int i; 424 425 for (i = 0; i < max_insns; i++, ip++) { 426 if (ip->j_format.opcode == j_op) 427 return J_TARGET(ip, ip->j_format.target); 428 } 429 return 0; 430 } 431 #endif 432 433 static int __init frame_info_init(void) 434 { 435 unsigned long size = 0; 436 #ifdef CONFIG_KALLSYMS 437 unsigned long ofs; 438 #endif 439 unsigned long addr; 440 441 addr = get___schedule_addr(); 442 if (!addr) 443 addr = (unsigned long)schedule; 444 445 #ifdef CONFIG_KALLSYMS 446 kallsyms_lookup_size_offset(addr, &size, &ofs); 447 #endif 448 schedule_mfi.func = (void *)addr; 449 schedule_mfi.func_size = size; 450 451 get_frame_info(&schedule_mfi); 452 453 /* 454 * Without schedule() frame info, result given by 455 * thread_saved_pc() and get_wchan() are not reliable. 456 */ 457 if (schedule_mfi.pc_offset < 0) 458 printk("Can't analyze schedule() prologue at %p\n", schedule); 459 460 return 0; 461 } 462 463 arch_initcall(frame_info_init); 464 465 /* 466 * Return saved PC of a blocked thread. 467 */ 468 unsigned long thread_saved_pc(struct task_struct *tsk) 469 { 470 struct thread_struct *t = &tsk->thread; 471 472 /* New born processes are a special case */ 473 if (t->reg31 == (unsigned long) ret_from_fork) 474 return t->reg31; 475 if (schedule_mfi.pc_offset < 0) 476 return 0; 477 return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset]; 478 } 479 480 481 #ifdef CONFIG_KALLSYMS 482 /* generic stack unwinding function */ 483 unsigned long notrace unwind_stack_by_address(unsigned long stack_page, 484 unsigned long *sp, 485 unsigned long pc, 486 unsigned long *ra) 487 { 488 struct mips_frame_info info; 489 unsigned long size, ofs; 490 int leaf; 491 extern void ret_from_irq(void); 492 extern void ret_from_exception(void); 493 494 if (!stack_page) 495 return 0; 496 497 /* 498 * If we reached the bottom of interrupt context, 499 * return saved pc in pt_regs. 500 */ 501 if (pc == (unsigned long)ret_from_irq || 502 pc == (unsigned long)ret_from_exception) { 503 struct pt_regs *regs; 504 if (*sp >= stack_page && 505 *sp + sizeof(*regs) <= stack_page + THREAD_SIZE - 32) { 506 regs = (struct pt_regs *)*sp; 507 pc = regs->cp0_epc; 508 if (!user_mode(regs) && __kernel_text_address(pc)) { 509 *sp = regs->regs[29]; 510 *ra = regs->regs[31]; 511 return pc; 512 } 513 } 514 return 0; 515 } 516 if (!kallsyms_lookup_size_offset(pc, &size, &ofs)) 517 return 0; 518 /* 519 * Return ra if an exception occurred at the first instruction 520 */ 521 if (unlikely(ofs == 0)) { 522 pc = *ra; 523 *ra = 0; 524 return pc; 525 } 526 527 info.func = (void *)(pc - ofs); 528 info.func_size = ofs; /* analyze from start to ofs */ 529 leaf = get_frame_info(&info); 530 if (leaf < 0) 531 return 0; 532 533 if (*sp < stack_page || 534 *sp + info.frame_size > stack_page + THREAD_SIZE - 32) 535 return 0; 536 537 if (leaf) 538 /* 539 * For some extreme cases, get_frame_info() can 540 * consider wrongly a nested function as a leaf 541 * one. In that cases avoid to return always the 542 * same value. 543 */ 544 pc = pc != *ra ? *ra : 0; 545 else 546 pc = ((unsigned long *)(*sp))[info.pc_offset]; 547 548 *sp += info.frame_size; 549 *ra = 0; 550 return __kernel_text_address(pc) ? pc : 0; 551 } 552 EXPORT_SYMBOL(unwind_stack_by_address); 553 554 /* used by show_backtrace() */ 555 unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, 556 unsigned long pc, unsigned long *ra) 557 { 558 unsigned long stack_page = 0; 559 int cpu; 560 561 for_each_possible_cpu(cpu) { 562 if (on_irq_stack(cpu, *sp)) { 563 stack_page = (unsigned long)irq_stack[cpu]; 564 break; 565 } 566 } 567 568 if (!stack_page) 569 stack_page = (unsigned long)task_stack_page(task); 570 571 return unwind_stack_by_address(stack_page, sp, pc, ra); 572 } 573 #endif 574 575 /* 576 * get_wchan - a maintenance nightmare^W^Wpain in the ass ... 577 */ 578 unsigned long get_wchan(struct task_struct *task) 579 { 580 unsigned long pc = 0; 581 #ifdef CONFIG_KALLSYMS 582 unsigned long sp; 583 unsigned long ra = 0; 584 #endif 585 586 if (!task || task == current || task->state == TASK_RUNNING) 587 goto out; 588 if (!task_stack_page(task)) 589 goto out; 590 591 pc = thread_saved_pc(task); 592 593 #ifdef CONFIG_KALLSYMS 594 sp = task->thread.reg29 + schedule_mfi.frame_size; 595 596 while (in_sched_functions(pc)) 597 pc = unwind_stack(task, &sp, pc, &ra); 598 #endif 599 600 out: 601 return pc; 602 } 603 604 /* 605 * Don't forget that the stack pointer must be aligned on a 8 bytes 606 * boundary for 32-bits ABI and 16 bytes for 64-bits ABI. 607 */ 608 unsigned long arch_align_stack(unsigned long sp) 609 { 610 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) 611 sp -= get_random_int() & ~PAGE_MASK; 612 613 return sp & ALMASK; 614 } 615 616 static void arch_dump_stack(void *info) 617 { 618 struct pt_regs *regs; 619 620 regs = get_irq_regs(); 621 622 if (regs) 623 show_regs(regs); 624 625 dump_stack(); 626 } 627 628 void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) 629 { 630 long this_cpu = get_cpu(); 631 632 if (cpumask_test_cpu(this_cpu, mask) && !exclude_self) 633 dump_stack(); 634 635 smp_call_function_many(mask, arch_dump_stack, NULL, 1); 636 637 put_cpu(); 638 } 639 640 int mips_get_process_fp_mode(struct task_struct *task) 641 { 642 int value = 0; 643 644 if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS)) 645 value |= PR_FP_MODE_FR; 646 if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS)) 647 value |= PR_FP_MODE_FRE; 648 649 return value; 650 } 651 652 static void prepare_for_fp_mode_switch(void *info) 653 { 654 struct mm_struct *mm = info; 655 656 if (current->mm == mm) 657 lose_fpu(1); 658 } 659 660 int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) 661 { 662 const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE; 663 struct task_struct *t; 664 int max_users; 665 666 /* Check the value is valid */ 667 if (value & ~known_bits) 668 return -EOPNOTSUPP; 669 670 /* Avoid inadvertently triggering emulation */ 671 if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu && 672 !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64)) 673 return -EOPNOTSUPP; 674 if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre) 675 return -EOPNOTSUPP; 676 677 /* FR = 0 not supported in MIPS R6 */ 678 if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6) 679 return -EOPNOTSUPP; 680 681 /* Proceed with the mode switch */ 682 preempt_disable(); 683 684 /* Save FP & vector context, then disable FPU & MSA */ 685 if (task->signal == current->signal) 686 lose_fpu(1); 687 688 /* Prevent any threads from obtaining live FP context */ 689 atomic_set(&task->mm->context.fp_mode_switching, 1); 690 smp_mb__after_atomic(); 691 692 /* 693 * If there are multiple online CPUs then force any which are running 694 * threads in this process to lose their FPU context, which they can't 695 * regain until fp_mode_switching is cleared later. 696 */ 697 if (num_online_cpus() > 1) { 698 /* No need to send an IPI for the local CPU */ 699 max_users = (task->mm == current->mm) ? 1 : 0; 700 701 if (atomic_read(¤t->mm->mm_users) > max_users) 702 smp_call_function(prepare_for_fp_mode_switch, 703 (void *)current->mm, 1); 704 } 705 706 /* 707 * There are now no threads of the process with live FP context, so it 708 * is safe to proceed with the FP mode switch. 709 */ 710 for_each_thread(task, t) { 711 /* Update desired FP register width */ 712 if (value & PR_FP_MODE_FR) { 713 clear_tsk_thread_flag(t, TIF_32BIT_FPREGS); 714 } else { 715 set_tsk_thread_flag(t, TIF_32BIT_FPREGS); 716 clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE); 717 } 718 719 /* Update desired FP single layout */ 720 if (value & PR_FP_MODE_FRE) 721 set_tsk_thread_flag(t, TIF_HYBRID_FPREGS); 722 else 723 clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS); 724 } 725 726 /* Allow threads to use FP again */ 727 atomic_set(&task->mm->context.fp_mode_switching, 0); 728 preempt_enable(); 729 730 return 0; 731 } 732 733 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32) 734 void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs) 735 { 736 unsigned int i; 737 738 for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) { 739 /* k0/k1 are copied as zero. */ 740 if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27) 741 uregs[i] = 0; 742 else 743 uregs[i] = regs->regs[i - MIPS32_EF_R0]; 744 } 745 746 uregs[MIPS32_EF_LO] = regs->lo; 747 uregs[MIPS32_EF_HI] = regs->hi; 748 uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc; 749 uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr; 750 uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status; 751 uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause; 752 } 753 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */ 754 755 #ifdef CONFIG_64BIT 756 void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs) 757 { 758 unsigned int i; 759 760 for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) { 761 /* k0/k1 are copied as zero. */ 762 if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27) 763 uregs[i] = 0; 764 else 765 uregs[i] = regs->regs[i - MIPS64_EF_R0]; 766 } 767 768 uregs[MIPS64_EF_LO] = regs->lo; 769 uregs[MIPS64_EF_HI] = regs->hi; 770 uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc; 771 uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr; 772 uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status; 773 uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause; 774 } 775 #endif /* CONFIG_64BIT */ 776